PCIe signals layout considerations:

Characteristics of PCIe signals:

1) Diff pairs
TX & RX are differential lines. Each lane consists of one pair of TX and one pair of RX
2) AC coupled
a. TX lines are connected other end RX through AC coupling (via a Cap).
b. TX pairs usually route on top layer (due to AC coupling caps on TX traces )
3) Lane-to-lane de-skew
a. Trace length matching between data pairs is not required (Embedded clock simplifies
routing rules). Only the inter-pair (+/-) has to be matched
b. There is no length match requirement between transmit and receive pairs
4) Polarity inversion
5) On-chip equalization (de-emphasis)
6) On-chip terminations

Manufacturing probe point on Tx traces before AC coupling caps.

Interconnect Budget:
1)
2)
3)
4)

Signal Loss and jitter are key parameters

Target impedance not as critical
Maintain differential pair symmetry
Trace lengths: Manage trace lengths to minimize loss
a. Add-in / plug-in card traces (between Chip and connector): up to 3.5 max
b. System backplane card traces (between Chip and connector): up to 12 max
c. System backplane card traces (between Chip and chip): up to 15 max
5) To minimize loss and jitter, the most important considerations are to design to a target
impedance and to keep tolerances small. Thicker dielectrics and wider traces will minimize loss.
Microstrip differential traces produce greater impedance variation than stripline traces

Figure 1: As per Intel guidelines

Trace Geometry and Impedance:

1) Wide pair to pair spacing -> minimize crosstalk
a. But Close intra-pair spacing
2) Spacing should be same for interleaved (TX pair-RX pair-TX pair) / non-interleaved (TX pair-TX
pair-TX pair)
3) Example impedance targets:
b. Single-end Zo of 60 ohms 15%
c. Differential Impedance of ~100 ohms 20%
d.

Single-ended: 50 ohms +/- 15%

e.

Differential: 85 ohms nominal +/-15%

PCI Express link traces must maintain 100 differential / 60 single-ended impedance for 4-layer or 6-layer
boards; and 85 differential / 55 single-ended impedance for 8-layer or 10-layer boards.

Trace Symmetry & Matching:

1) There is no length match requirement between transmit and receive pairs.

2) Matching a pair (using small serpentine) should be added near the location where the mismatch
occurs.
3) An uncoupled section of trace routing into a pin or a ball should be 45 mils when using
multiple bends

Trace: Bends and small Serpentines

1) When a serpentine section is used to match one length to another, as shown above fig, the
length of each jog must be at least 15 mils (three times the 5 mil trace width). The maximum
distance between traces in a serpentine section should be less than two times the distance
between traces in a non-serpentine section.

1) 5 mils intra-pair space and 10 mils inter-pair space are allowed in the breakout region. A small
section of trace, up to 50 mils, does not necessarily require a reference plane. Length matching
should occur as close as possible to signal pins without introducing any tight bends.
2) The above Fig shows some techniques used in breakout areas. Side-by-side placement is
considered best. Adjacent with a small serpentine is acceptable. Diagonal routing and adjacent
placement with a bend are acceptable but not as good as the other techniques.

1) Routing over unbroken ground plane is preferred. If unbroken ground plane is not available,
route over unbroken voltage plane.
2) A signal pair should avoid discontinuities in the reference plane, such as splits and voids. When a
signal changes layers, the ground stitching vias should be placed close to the signal vias. A
minimum of 1 to 3 stitching vias per pair of signals is recommended. Never route a trace so that
it straddles a plane split

1) Signal vias affect the overall loss and jitter budgets. Each via pair may contribute 0.25 dB of loss
in some corner cases. Vias may limit the achievable maximum routing length.
2) A maximum of four via pairs can be used on a TX differential pair. A maximum of two via pairs
can be used on an RX differential pair. Vias should have a pad size of 25 mils or less, and a
finished hole size of 14 mils or less. Two vias must be placed as a symmetric pair in the same
location
3) Test points (which can be vias, pads or components) and probe pads should be placed
symmetrically in series. Stubs should not be introduced on differential pairs. Refer to above Fig
for illustrations of correct and incorrect placements
4) Probe pads (if required) to be placed near to the driver.????
5) Every effort should be made to avoid vias on the PCIe differential pairs since they can result in a
signal loss of up to 0.25 dB. When a via is unavoidable, its pad size should be less than 25 mils,
its hole size should be less than 14 mils, and its anti-pads should be 35 mils or smaller. No extra
vias should be added over and above those needed for IC pads or a connector. Vias in a
differential pair should always be at the same relative location and placed in a symmetrical
fashion along the differential pair as shown in below Figure.

Clock source termination should be near to the driver.

PCIe reference clocks to back plane is not required to match trace lengths

Figure 2: As per Intel guideline