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Proceedings of Asia-Pacific Microwave Conference 2010

Directional Couplers from 30 to 140 GHz in Silicon

Benjamin Laemmle 1 , Klaus Schmalz 2 , Christoph Scheytt 2 , Alexander Koelpin 1 , and Robert Weigel 1

Institute for Electronics Engineering,

University of Erlangen-Nuremberg, Cauerstr. 9, 91058 Erlangen, Germany
2 IHP Microelectronics GmbH,
Im Technologiepark 25, 15236 Frankfurt (Oder), Germany

AbstractIn this paper directional couplers with reduced size,

by lumped elements, inverted microstrip, and broadside coupled
lines at 61, 110, and 122 GHz center frequency and up to 156-GHz
bandwidth have been designed. The couplers show an isolation up
to 40 dB. Different SiGe BiCMOS technologies with 250-nm and
130-nm feature width and 5 to 7 metal layers have been used. The
measurement results have been compared to simulation results
and good agreement has been observed.
Index Termsmillimeter wave directional couplers, passive

In this paper different directional couplers have been designed and presented in two different process technologies.
Several branchline couplers have been designed and measured
and a broadside coupled-line coupler with more than 150 GHz
bandwidth is presented. The couplers are compared in area,
insertion loss, isolation, and susceptibility to process variation.
The passive structures have been simulated with SONNET
and very good agreement between simulation and measurement is observed.



The increase of operating frequencies in silicon integrated

circuits enables the integration of passive microwave elements
with reasonable size on chip [1]. The wavelength of millimeter110fF
wave signals is smaller than the die size enabling the use of dis- P1
tributed elements in complex integrated circuits and systems.
Transmission lines, Wilkinson power dividers, or matching
networks are already standard elements in millimeter-wave sil- P4
icon designs. Even complex structures like bandpass filters [2],
ratrace couplers, or Lange Couplers have been integrated and
presented. While for III-V based millimeter-wave integrated
circuits (MMIC) an isolating microwave substrate is available, Fig. 1. Schematic of a lumped elements (left) and reduced size (right)
this is not the case for silicon. Also silicon is often labeled as branchline couplers at 61 GHz. The inductors and capacitors reactance (left)
substrate, although this refers to a semiconductor substrate for is equal to the characteristic impedance of the respective lines (35 or 50 ).
fabrication of transistors. However, several metal layers exist
where a ground-plane and conductors for microwave structures
can be formed. With conductors on different metal layers even A. Reduced Size Branchline Couplers
3-D structures can be fabricated unlike to III-V based MMICs.
Two reduced size branchline couplers at 61 GHz and at
Integrated directional couplers have several applications 122 GHz have been designed in different technologies. The
for integrated receivers, transmitters, or other circuits. The standard branchline coupler includes four quarterwave lines
couplers can be designed as quadrature hybrid couplers with (or branches) and therefore consumes a large chiparea. A
equal signal split and 90 phase difference. The application is special technique enables the use of branches with shorter
quadrature signal generation in the LO [3] or signal path [4] physical length by the use of lines with a higher characteristic
of quadrature receivers, active IQ modulators [5], or reflection impedance and capacitors at the junctions. According to [9]
type modulators [6]. The coupler has to feature low and equal the electrical length of a quarterwave line can be calculated
insertion loss and stable phase difference for the coupled and with sin = Z0 /Z1,2 and the capacitors as C = cos /(Z0 ),
direct port.
where Z0 is the actual impedance (86 ) and Z1,2 is the
However, the use of the directive behavior of such couplers desired impedance (35 or 50 ) of the line. The schematic of
in silicon technology has not been in focus for a while. The the coupler is shown on the right side of Fig. 1, whereas the
design of reflectometers for different applications requires cou- layout of the coupler with the metal-insulator-metal (MIM)
plers with high isolation and therefore directivity whereas the capacitors is depicted in Fig. 2. The process variations of
properties listed above are of minor concern. Such directional these capacitors mainly determines the isolation of the coucouplers are used to divide the incident and reflected wave and pler. The effect on center frequency and phase difference
are part of integrated vector network analyzers for readout of between coupled and direct port is low. The size of the
coupler depends on the physical length of the lines, which is
integrated mm-wave sensors [7] or built-in test circuits [8].

Copyright 2010 IEICE


inversely proportional to the characteristic impedance of the

lines. In order to increase the impedance of the line, the unit
capacitance has to be decreased by increasing the height h
(on the uppermost metal layer) and decreasing the conductor
width. However, most designers and simulators assume the
full embedding of the upper metal in the dielectric substrate.
In this process however, the lack of planarization after the
last deposition of SiO2 and the subsequent deposition of
the passivation layer results in a layer stack as shown in
Fig. 2. With smaller conductor width w the capacitance of
the sidewalls to the ground plane is increasing, but with this
topology the electric field is penetrating the passivation layer
and the air. A proper simulation setup is therefore required,
which has been setup by dielectric bricks in SONNET . The
characteristic impedance is decreasing from 86 to 82 with
flat SiO2 layer in comparison to the actual layer stack.

and two capacitors with 1/C = Z0 . The circuit and their

parameters are shown in Fig. 1. The inductors are designed
with SONNET and show a good agreement with simulation.
The use of a SiGe BiCMOS technology results in a layer
stack where am epitaxial-grown silicon layer (required for
bipolar transistor formation) with higher substrate resistivity
is introduced between he silicon and the isolating SiO2 layers.
The deembedded measurement results of the lumped elements coupler are depicted in Fig. 4. This coupler shows higher
losses compared to the reduced size coupler. A chipmicrograph
is shown in Fig. 5.

Magnitude (dB)


Passivation r =5

SiO2 r =4.1



Si epi r =11.9 =5 S/m


Si bulk r =11.9 =2 S/m




MIM Capacitor


Fig. 2. Layer stack (left) and layout (right) of a reduced size branchline
coupler with MIM-capacitors.



Frequency (GHz)




Fig. 4. S-Parameter measurements of lumped elements branchline coupler.

The isolation is high although all inductors couple into the same substrate.

C. Inverted Microstrip Branchline Coupler

Inverted microstrip lines have been presented in this technology for a low noise amplifier at 122 GHz [10]. The ground
plane is formed on top of the silicon wafer and the conductor
placed directly below as shown in Fig. 6. This results in
lower ground losses due to the thicker ground metal, and
lower sensitivity to electromagnetic radiation fields due to the

Magnitude (dB)









Frequency (GHz)




Fig. 3. Deembedded S-Parameter measurements of the 61-GHz reduced

size branchline coupler. The measurement results of the coupler with the
highest isolation measured is shown, The variation of the capacitors result in
a degradation of the isolation to 30 dB at the center frequency, but has nearly
no influence on insertion loss and the phase difference.

B. Lumped Elements Branchline Coupler

Another option to improve the area requirements of branchline couplers is the use of lumped elements. A quarterwave
line with characteristic impedance Z0 can be synthesized
by a Pi-network consisting of an inductor with L = Z0

Fig. 5. Chipmicrograph of 61-GHz reduced size (left) and lumped elements

(right) branchline couplers. The size is nearly identical and both devices
possess the same pad-frame. Ground pads are shared between neighboring
couplers to reduce the footprint for a characterization. The branches of the
reduced size coupler (left) are bent to save chip area. It has to be ensured,
that the coupling between the bends and different branches is negligible. The
inductors and the MIM capacitors of the lumped elements couplers can be
easily identified. In the center of the coupler a dedicated ground return path
for each inductor is drawn. The couplers are fabricated in a 250-nm SiGe
BiCMOS technology with a 5-metal layer front-end from IHP.


shielding groundplane. However, the field of the line couples

to the conducting silicon substrate resulting in lower isolation.
An inverted microstrip coupler has been designed with
122 GHz center frequency in a 7-metal 130-nm BiCMOS
process from IHP. The required area is four times the one
of a reduced size coupler at the same frequency.

Magnitude (dB)





S21 meas

SiO2 r =4.1

S31 meas
S41 meas

Si epi r =11.9 =5 S/m

Si bulk r =11.9 =2 S/m

S11 meas

Fig. 6. Layer stack of inverted microstrip branchline coupler showing the

large ground plane on TopMetal2 and the conductor on TopMetal1. The
ground plane is connected to a metal grid throughout the chip to ensure
shielding of all structures. The distance h between conductor and ground
plane is nearly four times smaller than the distance to the silicon substrate,
therefore the unit capacitance to ground is much larger than to the substrate.


Frequency (GHz)



Fig. 8. Deembedded S-Parameter measurements of the inverted microstrip

branchline coupler from 90 to 140 GHz showing an isolation better than 20 dB
and equal signal split from 115 to 128 GHz. The optimum return loss is better
than -40 dB at 131 GHz.

SiO2 r =4.1


Deembedded measurement results from 90 to 140 GHz are

shown in Fig. 8. The coupler shows better than 20 dB isolation
from 115 to 128 GHz and a return loss below -40 dB at
131 GHz. The coupler has better performance in measurement
than in simulation.
D. Broadside Coupled-Line Directional Coupler

Si epi r =11.9 =5 S/m
Si bulk r =11.9 =2 S/m

Fig. 9.
Layer stack (left) and layout (right) of broadside coupled-line
directional couplers. The lower metal layer is directly below the upper
conductor and is not seen in the layout. The slit in the ground plane increases
the coupling of the structure.

Broadband directional couplers can be designed as coupledlines, in most cases drawn by parallel lines with a small
gap. However, higher coupling can be achieved by broadside
coupling in silicon technology. The vertical distance between
two conductors in the upper metal layers is in most cases in Fig. 10. All S-Parameters can be measured in this way
smaller than the permitted horizontal distance. Moreover, the except the transmission coefficient of the lower line. A THRU
size w of both coupled-lines can be arbitrarily chosen. The deembedding structure has also been placed on the chip.
width of the lower conductor should be made smaller than The connections on all three structures should be identical
the upper one, as the distance to the substrate is lower. The (but attached to different ports). This is unfortunately not
coupler can be further optimized for special applications by possible, as two ports lie on lower metal layers. This requires
introducing more asymmetries, e.g. a displacement of the a via and a connection on the lower layer (with nonidentical
lower conductor. The structure has been placed three times characteristic impedance). The magnitude of the transmission
to enable 4-Port S-Parameters with a 2-Port measurement of this connection is nearly identical but the phase is slightly
setup. On each structure different ports are connected to different. Simulations however show a difference in magnitude

the pads and the remaining ports are terminated on-chip. and phase of only 0.028 dB and up to 0.35 from 20 to
Fig. 11, have
The micrograph of the three connected structures is shown

Fig. 7. Chipmicrograph of the inverted microstrip (left) and reduced size

(right) branchline coupler at 122 GHz center frequency. The conductor of the
inverted microstrip coupler can not be seen as the ground plane is formed on
top of the metal stack. The structures have been fabricated in a 130-nm SiGe
BiCMOS process with 7-metal aluminum front-end from IHP.

Fig. 10. Chipmicrograph of a broadside coupled directional coupler. The

coupler has been placed three times to measure 4-Port S-Parameters with a
2-Port VNA. The connections should be identical to simplify deembedding,
but attached to different ports. The coupler has been fabricated in a 130-nm
7-metal layer SiGe BiCMOS process from IHP.


been performed from 20 to 115 GHz with an Agilent 8510XF

VNA and from 90 to 140 GHz with a Rohde & Schwarz
ZVB. The transmission coefficients at 110 GHz are 4.15 dB.
The coupler has a 3-dB bandwidth of 156 GHz with corner
frequencies at 32 GHz (measured) and 188 GHz (simulated).
The isolation is above 12 dB over the measured frequency
range even without optimizing the structure. The measured
phase difference between direct and coupled port is between
81 and 90 from 20 GHz to 140 GHz. Simulation results
of the S-parameters are also shown in Fig. 11. A very good
agreement can be observed in the total frequency range with
only a small step in the change of the measurement setup.
The return loss, however, shows a major step at 90 GHz,
presumably due to calibration. The broadside coupled-line di0

Magnitude (dB)


Coupler Type
Reduced Size
Reduced Size
Lumped Elements
Inverted Microstrip

S21 sim
S31 sim
S41 sim

Frequency (GHz)





S11 sim


The authors would like to thank Falk Korndorfer, Johannes

Borngraber, and Christian Wipf for measurement and chipmicrographs of the structures and IHP Microelectronics GmbH
for fabricating the chips.

S41 meas
S11 meas




S31 meas


(m2 )
180 x 205
125 x 115
180 x 205
225 x 250
95 x 160

In this paper five different couplers have been presented and

compared with different center frequencies and bandwidths
in different technologies. A reduced size branchline coupler
at 61 and 122 GHz, a lumped elements branchline coupler
at 61 GHz, a normal size branchline coupler realized with
inverted microstrip lines at 122 GHz, and a broadside coupledlines directional coupler have been designed and measured.
Further studies will concentrate on the optimization and the
behavior of broadside coupled directional couplers up to
325 GHz with improved directivity.

S21 meas



Fig. 11. S-Parameter measurements and simulated values of transmission parameters for the broadside coupled-line directional coupler. The S-Parameters
have been measured from 20 to 115 GHz and from 90 to 140 GHz with
two different frequency extenders and setups. The measurements are in good
agreement with the simulation results.

rectional coupler can be further optimized for either broadband

quadrature generation or for improved isolation. The coupling
ratio of the broadside coupled-line can be arbitrarily chosen.
A comparison of the designed couplers can be found in
Table I with the center frequency, the size, the transmission
parameters of the direct and coupled port and the isolation at
the center frequency.
The reduced size coupler possesses the highest isolation,
but only in a small frequency range. It has good insertion
loss, low area and is therefore the best choice for narrowband
applications. The broadside coupled-line topology shows lower
insertion loss, lower sensitivity to process parameters, higher
bandwidth, and lower area requirements compared to the other
presented couplers. The isolation and therefore the directivity
is lower than the reduced size coupler. The remaining couplers
show lower performance in terms of insertion loss and area

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