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264783929.doc
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VDD
VDD
RD
R1
K , Vt
+
R2
ID
+
VDS
VGS
3/26/2015
264783929.doc
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VDD
VDD
RD
R1 K , V
t
ID
VDD
I
+
R2
Q1
Q2
+
VGS2
VGS1
I
Vt
K
VGS
and since the DC gate voltage is:
R2
R
1
2
VG VDD
3/26/2015
264783929.doc
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VS VG VGS
R2
R1 R2
VDD
I
Vt
K
VGS 2 Vt 2 VGS 1 Vt 1
VDD I ref R Vt 1
3/26/2015
264783929.doc
VDD
VDD
ID
VS VGS 1 Vt 1
+
+
R2
RD
R1
(although to be practical, we
should make VS slightly
greater than this to allow for
some design margin).
VDS
VGS
-
4/5
+
V > VGS1-Vt1
-
R2
R1 R2
VG VDD
3/26/2015
264783929.doc
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VG VGS VS
I
Vt VGS 1 Vt 1
K
VD
VDD VG Vt
2
RD
VDD VD VDD VG Vt
ID
ID