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An Efficient Implementation of TPG using Gray Counter

S.VENKATLAKSHMI
M.E VLSI Design
Knowledge Institute of Technology
Salem, India
gvenkatlakshme@gmail.com

Abstract In digital circuits, the complexity and


density are increasing, while at the same time, more quality and
reliability are required. It increases the cost and makes the
validation of VLSI circuits more and more difficult. A new BuiltIn Self- Test (BIST) scheme is introduced to deal with the
increased switching activity in system on chip for low energy
testing that uses a gray counter within reasonable clock cycles. In
our approach, only a small part of the Circuit Under Test(CUT)
is active, the rest of the CUT is fed with low leakage input
patterns. Even the active part is fed by a gray counter which
make the overall power consumption extremely low. This method
save the test power and give a better fault coverage without an
increase in the test length. The experimental result provided the
high performance which is applied to ISCAS benchmarks
circuitry. The power required for test pattern generation is
analyzed using Xilinx ISE 12.1 Software.

Index Terms

Built-In Self- Test (BIST), Circuit Under


Test(CUT), Gray counter.

I.

INTRODUCTION

Built-In Self-Test (BIST) techniques can effectively


reduce the difficulty and complexity of VLSI testing, by
introducing on-chip test hardware into the Circuit-Under-Test
(CUT). In conventional BIST architectures, the linear
feedback shift register (LFSR) is commonly used in the test
pattern generators (TPGs) and output response analyzers. A
major drawback of these architectures is that the
pseudorandom patterns generated by the LFSR lead to
significantly high switching activities in the CUT, which can
cause excessive power dissipation. They can also damage the
circuit and reduce product yield and lifetime. The objective of
the BIST is to reduce power dissipation without affecting the
fault coverage.
Abu Issa Suggested a novel low-transition linear
feedback shift register (LFSR) that is based on some new
observations about the Output sequence of a conventional
LFSR. The proposed design, called bit-swapping LFSR (BSLFSR), is composed of an LFSR and a 2 1 multiplexer.
When used to generate test patterns for scan-based built-in
self-tests, it reduces the number of transitions that occur at the
scan-chain input during scan shift operation by 50% when
compared to those patterns produced by a conventional LFSR.
Hence, it reduces the overall switching activity in the circuit

N.VIJAYANANDAM

Assistant Professor
Knowledge Institute of Technology
Salem, India
nvece@kiot.ac.in

analyzed where delay can occur that reduced the speed of the
operation under test during test applications. The BS-LFSR is
combined with a scan-chain-ordering algorithm that orders the
cells in a way that reduces the average and peak power (scan
and capture) in the test cycle or while scanning out a response
to a signature analyzer. These techniques have a substantial
effect on average- and peak-power reductions with negligible
effect on fault coverage or test application time. Experimental
results on ISCAS89 benchmark circuits show up to 65% and
55% reductions in average and peak power, respectively[1].
Girard presented surveys about the available low
power testing techniques during testing. It also suggests some
advantages and disadvantages associated with every
technique. The System-On-Chip revolution challenges both
design and test engineers, especially in the area of power
dissipation. Generally, a circuit or system consumes more
power in test mode than in normal mode. This extra power
consumption can give rise to severe hazards in circuit
reliability[2].
Girard considers the problem of minimizing the
energy required to test a BIST combinational circuit without
modifying the stuck-at fault coverage and with no extra area
or delay overhead over the classical LFSR architectures. First,
is to analyze the impact of the polynomial and seed selection
of the LFSR used as TPG on the energy consumed by the
circuit. Second, is to propose a method to significantly
decrease the energy consumption of BIST sessions. For this
purpose, a heuristic method based on a simulated annealing
algorithm is used. Finally results are obtained with no loss of
stuck-at fault[3].
S. Gupta suggested a new built-in self-test (BIST)
test pattern generator (TPG) design, called low-transition
random TPG (LT-RTPG. An LT-RTPG is composed of a linear
feedback shift register (LFSR), a -input AND gate, and a T
flip-flop. When used to generate test patterns for test-per-scan
BIST, it decreases the number of transitions that occur during
scan shifting and, hence, decreases switching activity during
testing. Various properties of LT-RTPGs are identified and a
methodology for their design is presented. Experimental
results demonstrate that LT-RTPGs designed using the
proposed methodology decrease switching activity during
BIST by significant amounts while providing high fault
coverage[4].

Feng Liang proposed a method which generates


Multiple Single Input Change (MSIC) vectors in a pattern, i.e.,
each vector applied to a scan chain is an SIC vector. A
reconfigurable Johnson counter and a scalable SIC counter are
developed to generate a class of minimum transition
sequences. The proposed TPG is flexible to both the test-perclock and the test-per-scan schemes. Simulation results with
ISCAS benchmarks demonstrate that MSIC can save test
power and impose no more than 7.5% overhead for a scan
design. It also achieves the target fault coverage without
increasing the test length[5].
Hemalatha proposed a method which generates test
pattern without additional hardware. This architecture reduces
switching activity in the circuit-under-test (CUT) and
increases the clock frequency of the scanning process. An
auxiliary chain is utilized in this architecture to avoid the large
number of transitions to the CUT during the scan-in process.
The auxiliary chain shifts in the difference between
consecutive test vectors and only the required transitions
(referred to as trigger data) are applied to the CUT. Hence
Power requirements are substantially reduced[6].
Mehrdad Nourani described a low-transition test
pattern generator, called the Low-Transition Linear Feedback
Shift Register (LT-LFSR), is proposed to reduce the average
and peak power of a circuit during test by reducing the
transitions among patterns. Transitions are reduced in two
dimensions: 1) between consecutive patterns and 2) between
consecutive bits. The proposed architecture increases the
correlation among the patterns generated by LT-LFSR with
negligible impact on test length. The experimental results for
the ISCAS85 and 89 benchmarks confirm up to 77 percent
and 49 percent reduction in average and peak power,
respectively[7].
Praveen Kasunde the single input change patterns
generated by a counter and a gray code generator are
ExclusiveOR with the seed generated by the low power
linear feedback shift register [LPLFSR]. The proposed scheme
is evaluated by using a 4x4 Braun array multiplier. The
System-On-Chip (SOC) approach is adopted for
implementation on Altera Field Programmable Gate Arrays
(FPGAs) based SOC kits with Nios II soft-core processor.
From the implementation results, it is verified that the testing
power for the proposed method is reduced by a significant
percentage[8].
Wang proposed Test Pattern Generator (TPG) For
Built-In Self-Test (BIST), which can reduce switching activity
during test application. The proposed TPG, called dual-speed
LFSR (DSLFSR), consists of two linear feedback shift
registers (LFSRs), a slow LFSR and a normal-speed LFSR.
The slow LFSR is driven by a slow clock whose speed is 1th
that of the normal clock, which drives the normal-speed
LFSR. The use of DS-LFSR reduces the frequency of
transitions at the circuit inputs driven by the slow LFSR,
leading to a reduction in switching activity during test
application. A procedure is presented to design a DS-LFSR so
as to achieve high fault coverage by ensuring that patterns

generated by it are unique and uniformly distributed. A new


gain function and a method to compute its value for each
circuit input are proposed to select inputs to be driven by the
slow LFSR. Also, a procedure to increase the number of inputs
driven by the slow LFSR by combining compatible inputs is
presented to further decrease the switching activity. Finally,
DS-LFSRs are designed for the ISCAS85 and ISCAS89
benchmark circuits and shown to provide a 13% to 70%
reduction in the numbers of load-capacitance weighted
transitions with no loss of fault coverage and at very slight
area overheads[9].
II. OVERVIEW OF BIST
Basic BIST Architecture
Built- In Self-Test (BIST) has been proven to be one
of the most cost effective and widely used solutions for VLSI
circuit testing. BIST is basically same as off-line testing using
Automated Test Equipment (ATE) where the test pattern
generator and the test response analyzer are on-chip circuitry
(instead of equipment). As equipment are replaced by
circuitry, so it is obvious that compressed implementations of
test pattern generator and response analyzer are to be
designed. The basic architecture of BIST is shown in Figure 1.
ROM

TEST CONTROLLER

TPG

M
U
X

CUT

MISR

COMPARATOR

Faulty
/ Fault
free

Fig 1 BIST Architecture


A. Test Pattern Generator
There are different methods to generate a Test
patterns, they
are Stored patterns,Exhaustive patterns,
Pseudo-exhaustive
patterns,Pseudo-Random
Pattern
Generation,Pattern Generation by Counter. In this paper, test
patterns are generated by gray counter.
B. Input Multiplexer
Multiplexer (MUX) is a device that selects one of
several analog or digital input signals and forwards the
selected input into a single line. A multiplexer of 2n inputs has
n select lines, which are used to select which input line to send
to the output. This multiplexer is to allow normal inputs to the
circuit when it is operational and test inputs from the pattern
generator when BIST is executed. The control input of the
multiplexer is fed by a central test controller.

C. Output Response Compactor


Output response compactor performs loss
compression of the outputs of the CUT (here Benchmark
circuit is used to test). As in the case of off-line testing, in
BIST the output of the CUT is to be compared with the
expected response called golden signature. If CUT output does
not match the expected response, fault is detected otherwise
fault free. Similar to the situation for test pattern generator,
expected output responses cannot be stored explicitly in a
memory and compared with the responses of the CUT.

D- or JK-type flip-flops ) which is given to the Ex-OR gate


and Seed generator So-Sm-1 output is feed to EX-OR gate as
another input in first clock cycle then the final output X is
obtained .
Gray Counter Using D Flip-Flop
Gray counter is designed by using D Flip Flop. Here,
the last flip flop inverted output Q is given as the input to first
flip flop. Then the first flip flop output (Q) is given to the
second flip flop. By using n flip flop, we can generate a n-bit
gray counter.

D. Test Controller
the controller connects normal inputs to the CUT via
the multiplexer, thus making it ready for operation. Among the
modules discussed above, the most important one is hardware
test pattern generator (LFSR) as applied algorithm to test
VLSI circuits.
Block Diagram of Test Pattern Generator
Figure shows the block diagram of test pattern
generator. It consist of D Flip-Flop and seed generator.

DFF
G0

DFF
G1

DFF
Gm-1

DFF
G3

Figure shows the Schematic diagram of gray counter


using D Flip Flop. By using this gray counter, test patterns are
generated.
III RESULTS AND DISCUSSION
The test patterns are generated using LFSR and Gray
counter. Then the power report and simulation results are
described below.

DFF

Gray counter
EX
OR
gate

EX OR
gate

EX
OR
gate

EX
OR
gate

AT
E

GA
TE

m-

m-

Fig 2 Block diagram of test pattern generator


l

Block Diagram Description


The gray counter generate L unique gray code words
through circular shifting which stores the number of times a
particular event or process has occurred, often in relationship
to a clock signal. The output from the last stage is inverted and
fed back as input to the first stage. The register cycles through
a sequence of bit-patterns (It can be implemented easily using

(a)

(d)
Fig.3.a the simulation result of test pattern generation using LFSR
b. Power analysis report of LFSR c the simulation result of test
pattern generation using Gray counter. D. Power analysis report of
Gray counter

Figure (a) shows the simulation result of test pattern


generation using LFSR. In this, D Flip Flop output is ExORed with seed input and generate a test pattern.
Figure (b) shows Power analysis report of LFSR. The
power required to generate a test pattern using LFSR is 0.049

(b)

Figure(c) shows the simulation result of test pattern


generation using Gray counter. In this, last D- Flip Flop invert
output is given to the first flip flop input. Then this output of
the D-flip flop are Ex-ORed with Seed generator. Finally it
generates a test pattern.
Figure (d) shows Power analysis report of Gray counter.
The power required to generate a test pattern using Gray
counter is 0.011

IV CONCLUSION
Test patterns are generated by using gray counter. This
test pattern generator consists of n D flip-flops and n-1
exclusive-OR gates. Hence hardware overhead can be
controlled. The generated test patterns are applied to Circuit
Under Test and analyze the circuit with area and power
consumption. The power consumption is of the test pattern
generation were analyzed using Xilinx.

References
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(c)
[2]

[3]
[4]

[5]

[6]

[7]

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