UART

Introduction:
is the most widely used serial
asynchronous communication protocol.
Typically uart is connected between a
processor and a peripheral.
UART

To the processor, the uart appears as

an 8-bit read-write parallel port that
performs serial to parallel conversions
for the processor and
Vice- versa for the peripheral.

The UART core consists of a

transmitter, a receiver, a modem
interface, a baud generator, an
interrupt controller, and various
controls and status registers.
The transmitter and receiver perform
parallel-to serial and serial-to-parallel

conversions, respectively. Each has a

256-byte FIFO to buffer data flow.

The use of FIFO buffers increases the

overall transmission rate by allowing

slower processors to respond, and
reducing the amount of time wasted on
context switching.

Besides data transfer, they also

facilitate start/stop framing bits, check

various parity options, as well as detect
transmission errors.

UART HAS THREE MAIN BLOCKS:

1. TRANSMITTER
2. RECEIVER
3. REGISTER SET

TRANSMITTER:

W
r
i
t
e

M
e
m

Baud
clock

R
e
a
d

TX
Contro
l

Shift

State

Reg

Parity
generato

The main function of transmitter is to convert

the parallel data into serial data.
TRANSMITTER block has 5 sub-modules:
o TX FIFO.
o TX control state machine.
o Shift register.

o Parity generator.
o Baud clock generator.
o Data frame.

TX FIFO:

Process

W
r
i
t
e

M
e
m

Process

R
e
a
d

Tx_con
trol
state
Fifo_rd
_data[

The main function of transmit FIFO is to store the

processor data based on the processor data valid
signal.
1. System_clock:
This is used to generate the baud clk.
This is used only to operate the write-logic
of tx_FIFO.
2. System_reset_n:
It is an active low signal, when it is low,
initialises all outputs to 0.

 Sometimes it is operated on the

system_clk and some other modules it is
operated on the baud_clk.

3. Processor_valid:

When this signal is high the valid

data(8-bit) is written into FIFO.

4. Processor data [7:0]:

When the processor valid signal is

high then the
processor valid data
(8-bit) is written into tx_FIFO.
5. Tx_RDY_n:

It is an acknowledge to the processor that

the FIFO is ready to accept the data.

Based on the FIFO-Full signal, Tx_RDY_n

signal is generated.

If FIFO_Full is low then the Tx_RDY_n

signal is low and it acknowledges to the
processor that it is ready to take the data.
6. FIFO_Full:

 Based on the address lines of write logic

and read logic, this signal is generated.

When the LSB bits of wr_addr and

wr_addr are same and the MSB bit of
wr_addr and rd_addr are not equal, then
this signal goes high.

7. FIFO_Empty:

This signal is generated, when the

wr_addr and rd_addr are same then
this signal will go high.
Key points:

Processor-valid (single bit) and processor

data (8-bit) are the inputs to the
transmit-FIFO from the processor.
The processor-data (8-bit) is valid only
when the processor-valid is high.
System-clock and system reset-n are the
user defined inputs to the transmit-FIFO.
Transmit-FIFO
generates
acknowledgements to the processor.
These are Tx_RDY_n and Rx_RDY_n. They
are active low signals.
FIFO_Full

and FIFO_Empty specify the

status of the transmit-FIFO.

SHIFT-REGISTER:

Tx_contr
ol state
machine

Shif
t

1. Shift_reg_en: when this signal is high then the data

is loaded into shift register from the tx_FIFO.
2. Shift_reg_data [7:0]: This is the processor data

[7:0]
3. Shift_reg_out:

serially

to the peripheral.

It is a 1-bit signal, shifts data

Bit by bit.

Shift register shifts the processor data serially

if operated in single transfer mode.
Shift register reads the data from tx_FIFO and
shifts serially if operated in multi transfer
mode.
Shift register sends the data to the data

frame after the start bit is asserted.

Parity generator:

Tx_contro

Parity
genera

Data

Registe
r set

Parity bit is generated and sends to the

data frame. To generate the parity bit the
parity enable should be high.
If parity enable is high and based on stick
parity conditions the required parity bit is
generated.
If stick parity is low then based on the even
parity, parity bit is generated.
If stick parity is high and even parity is low
then parity bit is forced to 1 irrespective of
even parity conditions.
If stick parity is high and even parity is high

then parity bit is forced to 0 irrespective of

even parity conditions.

Parity
enable

Stick
parity

Even
parity

Parity bit

~^(data)

^(data)

Baud clock generator:

Baud
clock

It generates baud clock based on the system

clock and this clock is used to operate every
sub-module in the transmitter module.

Data frame:

Data
frame

TX control
state

UART frame:

Star
t bit

D0 D1

D2

D3

D4

D5

D6

D7

Parity Stop
bit
bit1

When there is nothing to be sent, the

serial line is high. The first low bit is the
start bit, which indicates the beginning
of a new frame.

Stop
bit2

 The next five to eight bits are data bits,

which convey the actual information to

be sent, least significant bit first.

The number of data bits per frame is

configurable. If enabled, a parity bit will

be sent on the serial line after the data
bits.

Finally, the serial line is held high again

for at least one bit to indicate the end of

a frame. This is called the stop bit, which
also returns the serial line to the idle
state.
START BIT: it indicates to the peripheral that my
valid data starts after this bit.
D0-D7: the data to be send to the peripheral.
Parity bit: It is generated by parity generator.
(Optional).
STOP_BIT1 and STOP_BIT2: Based on the
number of bits of data...the stop bits are
determined. These are the bits which indicate end
of the frame.
Data bits

Required parity bit(s)

5-bit

1-bit

6-bit

1.5 bits

7-bit/8-bit

2-bits

Transmitter Control State Machine:

The other modules of the UART transmitter are controlled
by this module.

1.

TRANSMITTER IDLE

4h0000

2.

SEND BREAK

4h0001

3.

Transmit error

4h0010

4.

Single_mode_transfer

4h0011

5.

Multi_mode_transfer

4h0100

6.

FIFO_read

4h0101

7.

Send start

4h0110

8.

Send_data_bits

4h0111

9.

Send_parity_bit

4h1000

10
.

Send_stop_bit1

4h1001

11
.

Send_stop_bit2

4h1010

TX control state machine:

Baud clk
Shift

TX
Contr
ol
RD control
logic of

FIFO_re
State
Data
Fifo_rd

Machi

Parity

STATE DIAGRAM
H

Transmitter IDLE

Send break

Send_parity_bit
Single
transfer mode

DMA_signalli
ng mode &
processor
valid & !

Send_stop_bit1

Transmit Error

Multi transfer Send_stop_bit2

mode

!
DMA_signalli
ng mode &

FIFO_read

FIFO_data

Send start

Send data