CA3240, CA3240A

Data Sheet

March 4, 2005

Dual, 4.5MHz, BiMOS Operational Amplifier

with MOSFET Input/Bipolar Output

Features

The CA3240A and CA3240 are dual versions of the popular

CA3140 series integrated circuit operational amplifiers. They
combine the advantages of MOS and bipolar transistors on
the same monolithic chip. The gate-protected MOSFET
(PMOS) input transistors provide high input impedance and
a wide common-mode input voltage range (typically to 0.5V
below the negative supply rail). The bipolar output
transistors allow a wide output voltage swing and provide a
high output current capability.

Internally Compensated

The CA3240A and CA3240 are compatible with the industry

standard 1458 operational amplifiers in similar packages.

Dual Version of CA3140

MOSFET Input Stage

- Very High Input Impedance (ZIN) 1.5T (Typ)
- Very Low Input Current (II) 10pA (Typ) at 15V
- Wide Common-Mode Input Voltage Range (VICR): Can
Be Swung 0.5V Below Negative Supply Voltage Rail
Directly Replaces Industry Type 741 in Most Applications
Pb-Free Available (RoHS Compliant)

Applications
Ground Referenced Single Amplifiers in Automobile and
Portable Instrumentation

Ordering Information
PART NUMBER

FN1050.6

TEMP.
RANGE (oC)

PACKAGE

PKG.
DWG. #

Sample and Hold Amplifiers

Long Duration Timers/Multivibrators (MicrosecondsMinutes-Hours)

CA3240AE

-40 to 85

8 Ld PDIP

E8.3

CA3240AEZ
(See Note)

-40 to 85

8 Ld PDIP
(Pb-free)

E8.3

CA3240E

-40 to 85

8 Ld PDIP

E8.3

Intrusion Alarm System

Active Filters

CA3240EZ
(See Note)

-40 to 85

8 Ld PDIP
(Pb-free)

E8.3

Comparators

Function Generators

Instrumentation Amplifiers

Power Supplies

Photocurrent Instrumentation

Pb-free PDIPs can be used for through hole wave solder processing only.
They are not intended for use in Reflow solder processing applications.
NOTE: Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin plate termination
finish, which are RoHS compliant and compatible with both SnPb and Pb-free
soldering operations. Intersil Pb-free products are MSL classified at Pb-free
peak reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.

Functional Diagram
2mA

4mA

V+

Pinout
CA3240, CA3240A (PDIP)
TOP VIEW

OUTPUT (A) 1
INV.
INPUT (A) 2
NON-INV. 3
INPUT (A)
V- 4

8 V+
7 OUTPUT
INV.
6 INPUT (B)
5 NON-INV.
INPUT (B)

BIAS CIRCUIT
CURRENT SOURCES
AND REGULATOR
200A

1.6mA

200A

2A

2mA

+
INPUT

A 10

A 10,000

A1

OUTPUT

C1
12pF

V-

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-352-6832 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2001-2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

CA3240, CA3240A
Absolute Maximum Ratings

Thermal Information

Supply Voltage (Between V+ and V-) . . . . . . . . . . . . . . . . . . . . 36V

Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +8V) to (V- -0.5V)
Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1mA
Output Short Circuit Duration (Note 1). . . . . . . . . . . . . . . . Indefinite

Thermal Resistance (Typical, Note 2)

Operating Conditions

*Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing
applications.

JA (oC/W)

8 Lead PDIP Package* . . . . . . . . . . . . . . . . . . . . . .

100
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC

Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC

Voltage Range . . . . . . . . . . . . . . . . . . . . . 4V to 36V or 2V to 18V

CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:
1. Short circuit may be applied to ground or to either supply. Temperatures and/or supply voltages must be limited to keep dissipation within maximum rating.
2. JA is measured with the component mounted on an evaluation PC board in free air.
For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified

Electrical Specifications

CA3240
PARAMETER

CA3240A

SYMBOL

MIN

TYP

MAX

MIN

TYP

MAX

UNITS

Input Offset Voltage

VIO

15

mV

Input Offset Current

IIO

0.5

30

0.5

20

pA

II

10

50

10

40

pA

Input Current
Large-Signal Voltage Gain
(See Figures 12, 27) (Note 3)

AOL

Common Mode Rejection

Ratio (See Figure 17)

20

100

20

100

kV/V

86

100

86

100

dB

32

320

32

320

V/V

70

90

70

90

dB

VICR

-15

-15.5 to
+12.5

11

-15

-15.5 to
+12.5

12

PSRR
(VIO/V)

100

150

100

150

V/V

76

80

76

80

dB

CMRR

Common Mode Input Voltage Range

(See Figure24)
Power Supply Rejection Ratio
(See Figure 19)
Maximum Output Voltage (Note 4)
(See Figures 23, 24)

VOM+

12

13

12

13

VOM-

-14

-14.4

-14

-14.4

Maximum Output Voltage (Note 5)

VOM-

0.4

0.13

0.4

0.13

Total Supply Current

(See Figure 15) For Both Amps

I+

12

12

mA

Total Device Dissipation

PD

240

360

240

360

mW

NOTES:
3. At VO = 26VP-P, +12V, -14V and RL = 2k.
4. At RL = 2k.
5. At V+ = 5V, V- = GND, ISINK = 200A.
For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified

Electrical Specifications

TYPICAL VALUES
PARAMETER

SYMBOL

TEST CONDITIONS

CA3240A CA3240

UNITS

Input Resistance

RI

1.5

1.5

Input Capacitance

CI

pF

Output Resistance

RO

Equivalent Wideband Input Noise Voltage

(See Figure 2)

eN

BW = 140kHz, RS = 1M

60

60

48

48

FN1050.6
March 4, 2005

CA3240, CA3240A
For Equipment Design, VSUPPLY = 15V, TA = 25oC, Unless Otherwise Specified (Continued)

Electrical Specifications

TYPICAL VALUES
PARAMETER

SYMBOL

Equivalent Input Noise Voltage

(See Figure 18)

eN

Short-Circuit Current to Opposite Supply

40

UNITS

40

nV/Hz

f = 10kHz, RS = 100

12

12

nV/Hz

Source

40

40

mA

IOM-

Sink

fT

Slew Rate (See Figure 14)

SR

Settling Time at 10VP-P (See Figure 25)

CA3240A CA3240

IOM+

Gain Bandwidth Product (See Figures 13, 27)

Transient Response (See Figure 1)

TEST CONDITIONS
f = 1kHz, RS = 100

tr

RL = 2k, CL = 100pF

Rise Time

11

11

mA

4.5

4.5

MHz

V/s

0.08

0.08

OS

RL = 2k, CL = 100pF

Overshoot

10

10

tS

AV = +1, RL = 2k, CL = 100pF,

Voltage Follower

To 1mV

4.5

4.5

Crosstalk (See Figure 22)

To 10mV

f = 1kHz

1.4

1.4

120

120

dB

For Equipment Design, at VSUPPLY = 15V, TA = -40 to 85oC, Unless Otherwise Specified

Electrical Specifications

TYPICAL VALUES
SYMBOL

CA3240A

CA3240

UNITS

Input Offset Voltage

PARAMETER

|VIO|

10

mV

Input Offset Current (Note 8)

|IIO|

32

32

pA

II

640

640

pA

AOL

63

63

kV/V

96

96

dB

32

32

V/V

90

90

dB

Input Current (Note 8)

Large Signal Voltage Gain (See Figures 12, 27), (Note 6)

Common Mode Rejection Ratio (See Figure 17)

Common Mode Input Voltage Range (See Figure 24)

Power Supply Rejection Ratio (See Figure 19)

Maximum Output Voltage (Note 7) (See Figures 23, 24)

Supply Current (See Figure 15) Total For Both Amps

Total Device Dissipation
Temperature Coefficient of Input Offset Voltage

CMRR

VICR

-15 to +12.3

-15 to +12.3

PSRR
(VIO/V)

150

150

V/V

76

76

dB

VOM+

12.4

12.4

VOM-

-14.2

-14.2

I+

8.4

8.4

mA

PD

252

252

mW

VIO/T

15

15

V/oC

NOTES:
6. At VO = 26VP-P, +12V, -14V and RL = 2k.
7. At RL = 2k.
8. At TA = 85oC.
For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified

Electrical Specifications

TYPICAL VALUES
PARAMETER

SYMBOL

CA3240A

CA3240

UNITS

Input Offset Voltage

|VIO|

mV

Input Offset Current

|IIO|

0.1

0.1

pA

II

pA

Input Resistance

RIN

Large Signal Voltage Gain (See Figures 12, 27)

AOL

100

100

kV/V

100

100

dB

Input Current

FN1050.6
March 4, 2005

CA3240, CA3240A
For Equipment Design, at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified (Continued)

Electrical Specifications

TYPICAL VALUES
PARAMETER
Common-Mode Rejection Ratio

Common-Mode Input Voltage Range (See Figure 24)

SYMBOL

CA3240A

CA3240

UNITS

CMRR

32

32

V/V

90

90

dB

-0.5

-0.5

2.6

2.6

31.6

31.6

V/V

90

90

dB

VOM+

VICR

Power Supply Rejection Ratio

PSRR

Maximum Output Voltage (See Figures 23, 24)

VOM-

0.3

0.3

Source

IOM+

20

20

mA

Sink

IOM-

mA

SR

V/s

Gain Bandwidth Product (See Figure 13)

fT

4.5

4.5

MHz

Supply Current (See Figure 15)

I+

mA

Device Dissipation

PD

20

20

mW

Maximum Output Current

Slew Rate (See Figure14)

Test Circuits and Waveforms

50mV/Div., 200ns/Div.
Top Trace: Input, Bottom Trace: Output

5V/Div., 1s/Div.
Top Trace: Input, Bottom Trace: Output

FIGURE 1A. SMALL SIGNAL RESPONSE

FIGURE 1B. LARGE SIGNAL RESPONSE

+15V
0.1F

10k

SIMULATED
LOAD

+
CA3240

100pF

2k

0.1F

-15V
2k

BW (-3dB) = 4.5MHz
SR = 9V/s

0.05F

FIGURE 1C. TEST CIRCUIT

FIGURE 1. SPLIT-SUPPLY VOLTAGE FOLLOWER TEST CIRCUIT AND ASSOCIATED WAVEFORMS

FN1050.6
March 4, 2005

CA3240, CA3240A
Test Circuits and Waveforms

(Continued)
+15V
0.01F
RS
+
1M

NOISE
VOLTAGE
OUTPUT

CA3240

30.1k
0.01F

-15V

1k

BW (-3dB) = 140kHz
TOTAL NOISE VOLTAGE
(REFERRED TO INPUT) = 48V (TYP)

FIGURE 2. TEST CIRCUIT AMPLIFIER (30dB GAIN) USED FOR WIDEBAND NOISE MEASUREMENT

Schematic Diagram (One Amplifier of Two)

BIAS CIRCUIT

INPUT STAGE

SECOND STAGE

OUTPUT STAGE

DYNAMIC CURRENT SINK

V+

D7

D1
Q2

Q1

R9
50

Q3

Q4
R11
20

Q7

Q17

R1
8K

Q20
D8

R10
Q19 1K

Q5

Q6

R13
15K

R12
12K

R14
20K

Q21
R8
1K

Q8

OUTPUT

Q18
D4

D3

D2

D5
INVERTING
INPUT

Q9 Q10

NON-INVERTING
INPUT +
R2
500
Q11
R4
500

C1
12pF
R3
500
Q13

Q14

Q15

D6

Q12
R5
500

Q16

R6
50

R7
30

V-

NOTES:
9. All resistance values are in ohms.

FN1050.6
March 4, 2005

CA3240, CA3240A
Application Information
Circuit Description

Input Circuit Considerations

The schematic diagram details one amplifier section of the

CA3240. It consists of a differential amplifier stage using PMOS
transistors (Q9 and Q10) with gate-to-source protection against
static discharge damage provided by zener diodes D3, D4, and
D5. Constant current bias is applied to the differential amplifier
from transistors Q2 and Q5 connected as a constant current
source. This assures a high common-mode rejection ratio. The
output of the differential amplifier is coupled to the base of gain
stage transistor Q13 by means of an NPN current mirror that
supplies the required differential-to-single-ended conversion.

As indicated by the typical VICR, this device will accept

inputs as low as 0.5V below V-. However, a series currentlimiting resistor is recommended to limit the maximum input
terminal current to less than 1mA to prevent damage to the
input protection circuitry.

The gain stage transistor Q13 has a high impedance active

load (Q3 and Q4) to provide maximum open-loop gain. The
collector of Q13 directly drives the base of the compound
emitter-follower output stage. Pulldown for the output stage is
provided by two independent circuits: (1) constant-currentconnected transistors Q14 and Q15 and (2) dynamic currentsink transistor Q16 and its associated circuitry. The level of
pulldown current is constant at about 1mA for Q15 and varies
from 0 to 18mA for Q16 depending on the magnitude of the
voltage between the output terminal and V+. The dynamic
current sink becomes active whenever the output terminal is
more negative than V+ by about 15V. When this condition
exists, transistors Q21 and Q16 are turned on causing Q16 to
sink current from the output terminal to V-. This current always
flows when the output is in the linear region, either from the
load resistor or from the emitter of Q18 if no load resistor is
present. The purpose of this dynamic sink is to permit the
output to go within 0.2V (VCE (sat)) of V- with a 2k load to
ground. When the load is returned to V+, it may be necessary
to supplement the 1mA of current from Q15 in order to turn on
the dynamic current sink (Q16). This may be accomplished by
placing a resistor (Approx. 2k) between the output and V-.

Moreover, some current-limiting resistance should be

provided between the inverting input and the output when
the CA3240 is used as a unity-gain voltage follower. This
resistance prevents the possibility of extremely large inputsignal transients from forcing a signal through the inputprotection network and directly driving the internal constantcurrent source which could result in positive feedback via the
output terminal. A 3.9k resistor is sufficient.
The typical input current is on the order of 10pA when the
inputs are centered at nominal device dissipation. As the
output supplies load current, device dissipation will increase,
raising the chip temperature and resulting in increased input
current. Figure 4 shows typical input-terminal current versus
ambient temperature for the CA3240.

LOAD
CA3240
RL

RS

Figure 3 shows some typical configurations. Note that a series

resistor, RL, is used in both cases to limit the drive available to
the driven device. Moreover, it is recommended that a series
diode and shunt diode be used at the thyristor input to prevent
large negative transient surges that can appear at the gate of
thyristors, from damaging the integrated circuit.

LOAD

120VAC
30V NO LOAD

Output Circuit Considerations

Figure 23 shows output current-sinking capabilities of the
CA3240 at various supply voltages. Output voltage swing to
the negative supply rail permits this device to operate both
power transistors and thyristors directly without the need for
level-shifting circuitry usually associated with the 741 series
of operational amplifiers.

+HV

V+

CA3240
RL

MT2

MT1

FIGURE 3. METHODS OF UTILIZING THE VCE (SAT) SINKING

CURRENT CAPABILITY OF THE CA3240 SERIES

FN1050.6
March 4, 2005

CA3240, CA3240A
Dual Level Detector (Window Comparator)

10K

INPUT CURRENT (pA)

VS = 15V

1K

100

10

-60

-40

-20

20
40
60
80
TEMPERATURE (oC)

100

120 140

FIGURE 4. INPUT CURRENT vs TEMPERATURE

It is well known that MOSFET devices can exhibit slight

changes in characteristics (for example, small changes in
input offset voltage) due to the application of large
differential input voltages that are sustained over long
periods at elevated temperatures.
Both applied voltage and temperature accelerate these
changes. The process is reversible and offset voltage shifts
of the opposite polarity reverse the offset. In typical linear
applications, where the differential voltage is small and
symmetrical, these incremental changes are of about the
same magnitude as those encountered in an operational
amplifier employing a bipolar transistor input stage.

Figure 6 illustrates a simple dual liquid level detector using

the CA3240E as the sensing amplifier. This circuit operates
on the principle that most liquids contain enough ions in
solution to sustain a small amount of current flow between
two electrodes submersed in the liquid. The current, induced
by an 0.5V potential applied between two halves of a PC
board grid, is converted to a voltage level by the CA3240E in
a circuit similar to that of the on/off touch switch shown in
Figure 5. The changes in voltage for both the upper and
lower level sensors are processed by the CA3140 to activate
an LED whenever the liquid level is above the upper sensor
or below the lower sensor.

Constant-Voltage/Constant-Current Power Supply

The constant-voltage/constant-current power supply shown
in Figure 7 uses the CA3240E as a voltage-error and
current-sensing amplifier. The CA3240E is ideal for this
application because its input common-mode voltage range
includes ground, allowing the supply to adjust from 20mV to
25V without requiring a negative supply voltage. Also, the
ground reference capability of the CA3240E allows it to
sense the voltage across the 1 current-sensing resistor in
the negative output lead of the power supply. The CA3086
transistor array functions as a reference for both constantvoltage and constant-current limiting. The 2N6385 power
Darlington is used as the pass element and may be required
to dissipate as much as 40W. Figure 8 shows the transient
response of the supply during a 100mA to 1A load transition.

Precision Differential Amplifier

Typical Applications
On/Off Touch Switch
The on/off touch switch shown in Figure 5 uses the
CA3240E to sense small currents flowing between two
contact points on a touch plate consisting of a PC board
metallization grid. When the on plate is touched, current
flows between the two halves of the grid causing a positive
shift in the output voltage (Terminal 7) of the CA3240E.
These positive transitions are fed into the CA3059, which is
used as a latching circuit and zero-crossing TRIAC driver.
When a positive pulse occurs at Terminal 7 of the CA3240E,
the TRIAC is turned on and held on by the CA3059 and its
associated positive feedback circuitry (51k resistor and
36k/42k voltage divider). When the positive pulse occurs
at Terminal 1 (CA3240E), the TRIAC is turned off and held
off in a similar manner. Note that power for the CA3240E is
supplied by the CA3059 internal power supply.

Figure 9 shows the CA3240E in the classical precision

differential amplifier circuit. The CA3240E is ideally suited for
biomedical applications because of its extremely high input
impedance. To insure patient safety, an extremely high
electrode series resistance is required to limit any current
that might result in patient discomfort in the event of a fault
condition. In this case, 10M resistors have been used to
limit the current to less than 2A without affecting the
performance of the circuit. Figure 10 shows a typical
electrocardiogram waveform obtained with this circuit.

The advantage of using the CA3240E in this circuit is that it

can sense the small currents associated with skin
conduction while allowing sufficiently high circuit impedance
to provide protection against electrical shock.

FN1050.6
March 4, 2005

CA3240, CA3240A

44M

10K (2W)
120V/220V
AC
60Hz/50Hz

+6V
+6V
ON

51K
8

1M
6
+6V

0.01F

5.1M

36K

1/2
CA3240

1M

3
2

0.01F

T2300B (NOTE 12)

CA3059

10

MT1

COMMON

7
1

1N914

1M

MT2

11

+
1/2
CA3240

40W
120V LIGHT

12K

13
1N914
42K

OFF

RS (NOTE 10)

+6V SOURCE

100F (16V)

44M

NOTE:
10.

At 220V operation, TRIAC should be T2300D, RS = 18K, 5W.

FIGURE 5. ON/OFF TOUCH SWITCH

12M
+15V

8
100K

+15V

- 1/2

2
+15V

0.1F

CA3240
+

1
3

240K
HIGH
LEVEL

33K
160K

(0.5V)

2
5
100K
6

+
1/2
CA3240

100K

+
CA3140

100K

8.2K

6
680

LED

LOW
LEVEL

0.1F

LED ON WHEN
LIQUID OUTSIDE
OF LIMITS

12M

FIGURE 6. DUAL LEVEL DETECTER

FN1050.6
March 4, 2005

CA3240, CA3240A
VO
IO

V+
2N6385

10K

DARLINGTON

75

1/2
CA3240E
+

3K

2
180K

+ 500
- F

4
100

1N914

2.7K

VI = 30V
+

100K
2000F
50V

0.056F

2.2K
82K
V+
10
2

5F
16V

11

100K

14
CA3086E

TRANSISTOR
ARRAY

100K
5

12

1/2
CA3240E

13

820

680K
50K

1K
4

6.2K

100K

CHASSIS GROUND
VO RANGE = 20mV TO 25V
LOAD REGULATION:
VOLTAGE <0.08%
CURRENT <0.05%

1
1W

OUTPUT HUM AND NOISE 150VRMS

(10MHz BANDWIDTH)
SINE REGULATION 0.1%/VO
IO RANGE = 10mA - 1.3A

FIGURE 7. CONSTANT-VOLTAGE/CONSTANT-CURRENT POWER SUPPLY

Top Trace: Output Voltage;

500mV/Div., 5s/Div.
Bottom Trace: Collector Of Load Switching Transistor
Load = 100mA to 1A; 5V/Div., 5s/Div.
FIGURE 8. TRANSIENT RESPONSE

FN1050.6
March 4, 2005

CA3240, CA3240A

+15V
0.1F

100K 1%

10M
+
1/2
CA3240

GAIN
CONTROL

2000pF

2000pF

+15V
1%
5.1K

100K 1%
100K

0.1F
OUTPUT

2
CA3140

3.9K
100K 1%

TWO COND.
SHIELDED
CABLE

6
5

5.1K
1%

2K
4
0.1F

2000pF

1/2
CA3240
+

-15V
7
FREQUENCY RESPONSE (-3dB) DC TO 1MHz
SLEW RATE = 1.5V/s
COMMON MODE REJ: 86dB
GAIN RANGE: 35dB TO 60dB

10M
4
0.1F
-15V

FIGURE 9. PRECISION DIFFERENTIAL AMPLIFIER

Vertical: 1.0mV/Div.
Amplifier Gain = 100X
Scope Sensitivity = 0.1V/Div.
Horizontal: >0.2s/Div. (Uncal)
FIGURE 10. TYPICAL ELECTROCARIOGRAM WAVEFORM

10

FN1050.6
March 4, 2005

CA3240, CA3240A

0.015F

100K
+15V
+15V

8
2

+15V

1/2
CA3240E

5.1K

C30809
PHOTO
DIODE

3
200K

1.3
K
5
13K
6

2K

+
1/2
CA3240E

2
7

2K

+
CA3140

OUTPUT

4
-15V

4
C30809
PHOTO
DIODE

-15V

200k

100K

0.015F

FIGURE 11. DIFFERENTIAL LIGHT DETECTOR

Differential Light Detector

In the circuit shown in Figure 11, the CA3240E converts the
current from two photo diodes to voltage, and applies 1V of
reverse bias to the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage (CA3140) so that
only the difference is amplified. In this manner, the circuit
can be used over a wide range of ambient light conditions
without circuit component adjustment. Also, when used with
a light source, the circuit will not be sensitive to changes in
light level as the source ages.

11

FN1050.6
March 4, 2005

CA3240, CA3240A

RL = 2k

125

GAIN BANDWIDTH PRODUCT (MHz)

OPEN LOOP VOLTAGE GAIN (dB)

Typical Performance Curves

TA = -40oC

100
25oC

75
85oC
50
25

RL = 2k
CL = 100pF

20
10

TA = -40oC
25oC
85oC

1
0

10

15

20

25

10
15
SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

FIGURE 12. OPEN LOOP VOLTAGE GAIN vs SUPPLY VOLTAGE

TOTAL SUPPLY CURRENT (mA)

FOR BOTH AMPS

RL = 2k
CL = 100pF

SLEW RATE (V/s)

15
25oC
TA = -40oC

10

85oC
5

RL =

25oC
TA = -40oC

85oC

7
6
5
4
3
2

10

15

20

25

COMMON MODE REJECTION RATIO (dB)

SUPPLY VOLTAGE: VS = 15V

TA = 25oC
25
20
15
10

100K

1M

FREQUENCY (Hz)

FIGURE 16. MAXIMUM OUTPUT VOLTAGE SWING vs

FREQUENCY

12

15

20

25

FIGURE 15. QUIESCENT SUPPLY CURRENT vs SUPPLY VOLTAGE

FIGURE 14. SLEW RATE vs SUPPLY VOLTAGE

0
10K

10

SUPPLY VOLTAGE (V)

SUPPLY VOLTAGE (V)

OUTPUT VOLTAGE (VP-P)

25

FIGURE 13. GAIN BANDWIDTH PRODUCT vs SUPPLY VOLTAGE

10

20

20

4M

120
100

SUPPLY VOLTAGE: VS = 15V

TA = 25oC

80
60
40
20
0
101

102

103

104

105

106

107

FREQUENCY (Hz)

FIGURE 17. COMMON MODE REJECTION RATIO vs

FREQUENCY

FN1050.6
March 4, 2005

CA3240, CA3240A

1000

(Continued)
POWER SUPPLY REJECTION RATIO (dB)

EQUIVALENT INPUT NOISE VOLTAGE (nV/Hz)

Typical Performance Curves

SUPPLY VOLTAGE: VS = 15V
TA = 25oC

RS = 100

100

10

101

102
103
FREQUENCY (Hz)

104

80

-PSRR
40

20

101

17.5
VS = 15V
ONE AMPLIFIER OPERATING

6
4
2
0
-5
0
5
10
OUTPUT VOLTAGE (V)

106

107

VS = 15V
RL =

12.5
10
7.5
5

-15

TA = 25oC
AMP A AMP B
AMP B AMP A
VS = 15V
VO = 5VRMS

120
110
100
90

101

102

FREQUENCY (Hz)

FIGURE 22. CROSSTALK vs FREQUENCY

13

103

-10

-5
0
5
10
OUTPUT VOLTAGE (V)

15

FIGURE 21. SUPPLY CURRENT vs OUTPUT VOLTAGE

OUTPUT STAGE TRANSISTOR (Q15, Q16)

CROSSTALK (dB)

105

TA = 25oC

15

15

1000
SATURATION VOLTAGE (mV)

-10

FIGURE 20. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE

80
0.1

104

2.5
-15

130

103

FIGURE 19. POWER SUPPLY REJECTION RATIO vs

FREQUENCY

140

102

FREQUENCY (Hz)

TA = 25oC

10

+PSRR

60

SUPPLY CURRENT (mA)

PER AMP (DOUBLE FOR BOTH)

OUTPUT SINK CURRENT (mA)

PER AMP

100

105

FIGURE 18. EQUIVALENT INPUT NOISE VOLTAGE vs

FREQUENCY

12

SUPPLY VOLTAGE: VS = 15V

TA = 25oC
POWER SUPPLY
REJECTION RATIO = VIO/ VS

V- = 0V
TA = 25oC

V+ = +5V

100

+15V
+30V

10

1.0
0.01

0.1

1.0

10

LOAD (SINKING) CURRENT (mA)

FIGURE 23. VOLTAGE ACROSS OUTPUT TRANSISTORS Q15

AND Q16 vs LOAD CURRENT
FN1050.6
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CA3240, CA3240A
Typical Performance Curves

(Continued)

INPUT AND OUTPUT VOLTAGE

REFERENCED TO TERMINAL V- (V)

INPUT AND OUTPUT VOLTAGE

REFERENCED TO TERMINAL V+(V)

RL =
0
OUTPUT VOLTAGE (+VO)
COMMON MODE VOLTAGE (+VICR)

-0.5
-1

TA = 25oC

-1.5

TA = 85oC

TA = 85oC

-2
-2.5
TA = 25oC

-3

TA = -40oC

TA = -40oC

10
15
SUPPLY VOLTAGE (V)

20

RL =
1.5
OUTPUT VOLTAGE (-VO)
COMMON MODE VOLTAGE (-VICR)

1.0
0.5

TA = -40oC TO 85oC
0
TA = 85oC

-0.5

TA = -40oC

-1.0

TA = 25oC

-1.5

25

10

15

20

25

SUPPLY VOLTAGE (V)

FIGURE 24A.

FIGURE 24B.

FIGURE 24. OUTPUT VOLTAGE SWING CAPABILITY AND COMMON MODE INPUT VOLTAGE RANGE vs SUPPLY VOLTAGE
SUPPLY VOLTAGE: VS = 15V
TA = 25oC, RL = 2k, CL = 100pF

+15V

INPUT VOLTAGE (V)

10

1mV

10mV

1mV
0.1F

10mV

+
10k

SIMULATED
LOAD

CA3240

2k

100pF

FOLLOWER

INVERTING

0.1F

-2

-15V

-4
1mV

-6
-8
-10
0.1

10mV
2

1mV

2k

10mV
8

1.0
TIME (s)

0.05F
10

FIGURE 25A. SETTLING TIME vs INPUT VOLTAGE

FIGURE 25B. TEST CIRCUIT (FOLLOWER)

5k
+15V
0.1F

5k

SIMULATED
LOAD

CA3240
200

+
100pF

2k

0.1F
4.99k

D1
1N914

-15V

5.11k

SETTLING POINT
D2
1N914

FIGURE 25C. TEST CIRCUIT (INVERTING)

FIGURE 25. INPUT VOLTAGE vs SETTLING TIME

14

FN1050.6
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CA3240, CA3240A
(Continued)

10K
OPEN LOOP VOLTAGE GAIN (dB)

INPUT CURRENT (pA)

VS = 15V

1K

100

10

1
-60

-40

-20

20

40

60

80

100

120

TEMPERATURE (oC)

FIGURE 26. INPUT CURRENT vs TEMPERATURE

140

-75

VS = 15V
TA = 25oC
100

PHASE

RL = 2k,
CL = 0pF

-90
-105
-120
-135

80
RL = 2k,
CL = 100pF
60

-150

GAIN

40

20
0
101

102

103

104

105

106

107

OPEN LOOP PHASE (DEGREES)

Typical Performance Curves

108

FREQUENCY (Hz)

FIGURE 27. OPEN LOOP VOLTAGE GAIN AND PHASE vs

FREQUENCY

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15

FN1050.6
March 4, 2005