Академический Документы
Профессиональный Документы
Культура Документы
GENERAL DESCRIPTION
APPLICATIONS
Multiphase desktop CPU supplies
Single-supply synchronous buck converters
The OD pin shuts off both the high-side and the low-side
MOSFETs to prevent rapid output capacitor discharge during
system shutdown.
The ADP3110 is specified over the commercial temperature
range of 0C to 85C and is available in an 8-lead SOIC_N
package.
D1
VCC
4
BST
ADP3110
CBST2
CBST1
IN 2
DRVH
RG
Q1
DELAY
RBST
TO
INDUCTOR
SW
7
CMP
VCC
6
CMP
CONTROL
LOGIC
DRVL
Q2
PGND
DELAY
OD 3
05514-001
1V
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
ADP3110
TABLE OF CONTENTS
Specifications..................................................................................... 3
Application Information...................................................................8
ESD Caution.................................................................................. 4
Bootstrap Circuit...........................................................................8
Timing Characteristics..................................................................... 6
MOSFET Selection........................................................................8
Low-Side Driver............................................................................ 7
REVISION HISTORY
6/05Revision 0: Initial Version
Rev. 0 | Page 2 of 12
ADP3110
SPECIFICATIONS
VCC = 12 V, BST = 4 V to 26 V, TA = 25C, unless otherwise noted.
Table 1. 1
Parameter
PWM INPUT
Input Voltage High 2
Input Voltage Low2
Input Current2
Hysteresis2
OD INPUT
Input Voltage High2
Input Voltage Low2
Input Current 2
Hysteresis2
Propagation Delay Times 3
HIGH-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times3
SW Pull Down Resistance
LOW-SIDE DRIVER
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Output Resistance, Unbiased
Transition Times
Propagation Delay Times3
Symbol
Min
Typ
Max
Unit
0.8
+1
V
V
A
mV
2.0
1
90
250
2.0
tpdlOD
See Figure 3
250
20
35
V
V
A
mV
ns
tpdhOD
See Figure 3
40
55
ns
BST to SW = 12 V
BST to SW = 12 V
BST to SW = 0 V
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
BST to SW = 12 V, CLOAD = 3 nF,see Figure 4
BST to SW = 12 V, CLOAD = 3 nF, see Figure 4
SW to PGND
3.8
1.4
10
40
30
45
25
10
4.4
1.8
k
ns
ns
ns
ns
k
VCC = PGND
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
CLOAD = 3 nF, see Figure 4
SW = 5 V
SW = PGND
3.4
1.4
10
40
20
15
30
190
150
1
90
RDRV + SW
trDRVH
tfDRVH
tpdhDRVH
tpdlDRVH
RSW PGND
RDRVL PGND
trDRVL
tfDRVL
tpdhDRVL
tpdlDRVL
Time-out Delay
SUPPLY
Supply Voltage Range2
Supply Current2
UVLO Voltage2
Hysteresis2
Conditions
VCC
ISYS
110
95
0.8
+1
4.15
BST = 12 V, IN = 0 V
VCC rising
2
1.5
350
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC) methods.
2
Specifications apply over the full operating temperature range TA = 0C to 85C.
3
For propagation delays, tpdh refers to the specified signal going high, and tpdl refers to it going low.
Rev. 0 | Page 3 of 12
55
45
65
35
4.0
1.8
50
30
35
40
13.2
5
3.0
k
ns
ns
ns
ns
ns
ns
V
mA
V
mV
ADP3110
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC
BST
BST to SW
SW
DC
<200 ns
DRVH
DC
<200 ns
DRVL
DC
<200 ns
IN, OD
JA, SOIC_N
2-Layer Board
4-Layer Board
Operating Ambient Temperature
Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
Soldering (10 sec)
Vapor Phase (60 sec)
Infrared (15 sec)
Rating
0.3 V to +15 V
0.3 V to VCC + 15 V
0.3 V to +15 V
5 V to +15 V
10 V to +25 V
SW 0.3 V to BST + 0.3 V
SW 2 V to BST + 0.3 V
0.3 V to VCC + 0.3 V
2 V to VCC + 0.3 V
0.3 V to 6.5 V
123C/W
90C/W
0C to 85C
0C to 150C
65C to +150C
300C
215C
260C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 4 of 12
ADP3110
BST 1
IN 2
ADP3110
DRVH
SW
OD 3
6 PGND
TOP VIEW
VCC 4 (Not to Scale) 5 DRVL
05514-002
Mnemonic
BST
IN
3
4
5
6
7
OD
VCC
DRVL
PGND
SW
DRVH
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between the BST and SW pins holds this
bootstrapped voltage for the high-side MOSFET as it is switched.
Logic Level PWM Input. This pin has primary control of the driver outputs. In normal operation, pulling this pin
low turns on the low-side driver; pulling it high turns on the high-side driver.
Output Disable. When low, this pin disables normal operation, forcing DRVH and DRVL low.
Input Supply. This pin should be bypassed to PGND with ~1 F ceramic capacitor.
Synchronous Rectifier Drive. Output drive for the lower (synchronous rectifier) MOSFET.
Power Ground. This pin should be closely connected to the source of the lower MOSFET.
Switch Node Connection. This pin is connected to the buck-switching node, close to the upper MOSFETs
source. It is the floating return for the upper MOSFET drive signal. It is also used to monitor the switched voltage
to prevent turn-on of the lower MOSFET until the voltage is below ~1 V.
Buck Drive. Output drive for the upper (buck) MOSFET.
Rev. 0 | Page 5 of 12
ADP3110
TIMING CHARACTERISTICS
OD
tpdlOD
tpdhOD
05514-003
90%
DRVH
OR
DRVL
10%
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH-SW
trDRVH
VTH
VTH
1V
Rev. 0 | Page 6 of 12
05514-004
tpdhDRVL
SW
ADP3110
THEORY OF OPERATION
The ADP3110 is a dual MOSFET driver optimized for driving
two N-channel MOSFETs in a synchronous buck converter
topology. A single PWM input signal is all that is required to
properly drive the high-side and the low-side MOSFETs. Each
driver is capable of driving a 3 nF load at speeds up to 500 kHz.
A more detailed description of the ADP3110 and its features
follows. Refer to Figure 1.
LOW-SIDE DRIVER
HIGH-SIDE DRIVER
The high-side driver is designed to drive a floating N-channel
MOSFET. The bias voltage for the high-side driver is developed
by an external bootstrap supply circuit, which is connected
between the BST and SW pins.
The bootstrap circuit comprises a diode, D1, and bootstrap
capacitor, CBST1. CBST2 and RBST are included to reduce the highside gate drive voltage and limit the switch node slew rate
(referred to as a Boot-Snap circuit, see the Application
Information section for more details). When the ADP3110 is
starting up the SW pin is at ground; therefore the bootstrap
capacitor charges up to VCC through D1. When the PWM
input goes high, the high-side driver begins to turn on the highside MOSFET, Q1, by pulling charge out of CBST1 and CBST2. As
Q1 turns on, the SW pin rises up to VIN, forcing the BST pin to
VIN + VC(BST), which is enough gate-to-source voltage to hold Q1
To prevent the overlap of the gate drives during the Q1 turn off
and the Q2 turn on, the overlap circuit monitors the voltage at
the SW pin. When the PWM input signal goes low, Q1 begins
to turn off (after propagation delay). Before Q2 can turn on, the
overlap protection circuit makes sure that SW has first gone
high and then waits for the voltage at the SW pin to fall from
VIN to 1 V. Once the voltage on the SW pin has fallen to 1 V, Q2
begins turn on. If the SW pin had not gone high first, then the
Q2 turn on is delayed by a fixed 150 ns. By waiting for the
voltage on the SW pin to reach 1 V or for the fixed delay time,
the overlap protection circuit ensures that Q1 is off before Q2
turns on, regardless of variations in temperature, supply voltage,
input pulse width, gate charge, and drive current. If SW does
not go below 1 V after 190 ns, DRVL turns on. This can occur if
the current flowing in the output inductor is negative and is
flowing through the high-side MOSFET body diode.
Rev. 0 | Page 7 of 12
ADP3110
APPLICATION INFORMATION
SUPPLY CAPACITOR SELECTION
For the supply input (VCC) of the ADP3110, a local bypass
capacitor is recommended to reduce the noise and to supply
some of the peak currents drawn. Use a 4.7 F, low ESR
capacitor. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size. Keep the
ceramic capacitor as close as possible to the ADP3110.
BOOTSTRAP CIRCUIT
The bootstrap circuit uses a charge storage capacitor (CBST1) and
a diode, as shown in Figure 1. These components can be
selected after the high-side MOSFET is chosen. The bootstrap
capacitor must have a voltage rating that is able to handle twice
the maximum supply voltage. A minimum 50 V rating is
recommended. The capacitor values are determined using the
following equations:
C BST 1 + C BST 2 = 10
C BST 1
C BST 1 + C BST 2
Q GATE
VGATE
VGATE
VCC V D
(1)
(2)
A small signal diode can be used for the bootstrap diode due to
the ample gate drive voltage supplied by VCC. The bootstrap
diode must have a minimum 15 V rating to withstand the
maximum supply voltage. The average forward current can be
estimated by
(5)
VCC VD
R BST
(6)
MOSFET SELECTION
When interfacing the ADP3110 to external MOSFETs, the
designer should be aware of a few considerations. These help to
make a more robust design that minimizes stresses on both the
driver and MOSFETs. These stresses include exceeding the
short-time duration voltage ratings on the driver pins as well as
the external MOSFET.
where:
QGATE is the total gate charge of the high-side MOSFET at VGATE.
VGATE is the desired gate drive voltage (usually in the range of
5 V to 10 V, 7 V being typical).
VD is the voltage drop across D1.
Q GATE
VCC V D
(3)
Q GATE
VGATE
C BST 1
(4)
Rev. 0 | Page 8 of 12
ADP3110
The MOSFET vendor should provide a maximum voltage slew
rate at drain current rating such that this can be designed
around. The next step is to determine the expected maximum
current in the MOSFET. This can be done by
(7)
Trace out the high current paths and use short, wide
(>20 mil) traces to make these connections.
Minimize trace inductance between the DRVH and DRVL
outputs and the MOSFET gates.
Connect the PGND pin of the ADP3110 as closely as
possible to the source of the lower MOSFET.
The VCC bypass capacitor should be located as closely as
possible to the VCC and PGND pins.
Use vias to other layers when possible to maximize thermal
conduction away from the IC.
CBST1
CBST2
RBST
D1
CVCC
05514-005
I MAX
D MAX
= I DC ( per phase ) + (VCC VOUT )
f MAX L OUT
Rev. 0 | Page 10 of 12
05514-006
ENABLE
POWER
GOOD
C211
1nF
FROM
CPU
VIN RTN
VIN
12V
C4
1F
D1
1N4148
+
C2
1FOR
RLDY
470k
RT
137k,
1%
CFB
22pF
R1
10
PWRGD
10
14
C23
1nF
RAMPADJ ILIMIT 15
CSREF 16
GND 19
COMP
CSSUM 17
SW4 20
FB
RT
SW3 21
FBRTN
DELAY
SW2 22
CPUID
13
SW1 23
VID0
12
PWM4 24
VID1
CSCOMP 18
PWM3 25
VID2
EN
PWM2 26
VID3
11
VCC 28
PWM1 27
VID4
U1
ADP3181
R2
357k,
1%
RLIM
150k,
1%
C22
1nF
CCS1
560pF
CCS2
1.5nF
RSW41
RSW21
RCS2
RCS1
35.7k 84.5k
RPH4
158k, 1%
RSW31
RSW11
RPH2
RPH3 158k,
RPH1
1% 158k,
158k,
1%
1%
CLDY
39nF
CA
RB
RA
1.21k 470pF 12.1k
470pF
CB
+
C1
2700F/16V/3.3A 2
SANYO MV-WX SERIES
C3
100F
L1
370nH
18A
C17
4.7F
D5
1N4148
C13
4.7F
D4
1N4148
C9
4.7F
D3
1N4148
C5
4.7F
D2
1N4148
DRVL 5
VCC
C16
6.8nF
PGND 6
DRVL 5
IN
OD
VCC
3
4
SW 7
BST
2
DRVH 8
U5
ADP3110
C20
12nF
DRVL 5
VCC
R6
2.2
PGND 6
SW 7
DRVH 8
OD
IN
BST
C14
6.8nF
U4
ADP3110
C16
12nF
DRVL 5
VCC
R5
2.2
PGND 6
SW 7
DRVH 8
OD
IN
2
3
BST
C10
6.8nF
C12
12nF
U3
ADP3110
R4
2.2
PGND 6
OD
SW 7
IN
DRVH 8
BST
C6
6.8nF
C8
12nF
U2
ADP3110
R3
2.2
Q15
NTD110N02
Q11
NTD110N02
Q7
NTD110N02
Q3
NTD110N02
Q16
NTD110N02
Q13
NTD60N02
C19
4.7F
Q12
NTD110N02
Q9
NTD60N02
C15
4.7F
Q8
NTD110N02
Q5
NTD60N02
C11
4.7F
Q4
NTD110N02
Q1
NTD60N02
C7
4.7F
L5
320nH/1.4m
L4
320nH/1.4m
L3
320nH/1.4m
RTH1
100k, 5%
NTC
C24
10F 18
MLCC IN
SOCKET
C31
560F/4V 8
L2
320nH/1.4m SANYO SEPC SERIES
5m EACH
VCC (CORE)
0.8375V 1.6V
95A TDC, 119A PK
ADP3110
ADP3110
OUTLINE DIMENSIONS
5.00 (0.1968)
4.80 (0.1890)
8
4.00 (0.1574)
3.80 (0.1497) 1
1.27 (0.0500)
BSC
0.25 (0.0098)
0.10 (0.0040)
6.20 (0.2440)
5.80 (0.2284)
1.75 (0.0688)
1.35 (0.0532)
0.51 (0.0201)
COPLANARITY
SEATING 0.31 (0.0122)
0.10
PLANE
0.50 (0.0196)
45
0.25 (0.0099)
8
0.25 (0.0098) 0 1.27 (0.0500)
0.40 (0.0157)
0.17 (0.0067)
ORDERING GUIDE
Model
ADP3110KRZ 1
ADP3110KRZ-RL1
1
Temperature Range
0C to 85C
0C to 85C
Package Description
Standard Small Outline Package [SOIC_N]
Standard Small Outline Package [SOIC_N]
Z = Pb-free part.
Rev. 0 | Page 11 of 12
Package Option
R-8
R-8
ADP3110
NOTES
Rev. 0 | Page 12 of 12