AKGEC/IAP/FM/01

AjayKumarGargEngineeringCollege, Ghaziabad
Department of CSE
Pre-University Test
Course:
M.Tech.
Session:
2014-15
Subject:
Computer Organization &Architecture
Max Marks: 100

Semester: I
Section:
Sub. Code: CS-12
Time: 3 hour

Note: All questions are compulsory. All questions carry equal marks.
Q1. Attempt any four parts:

(4X5=20)

(a) Explain the differences between the hardwired control unit and micro programmed
control unit. Is it possible to have a hardwired control associated with the control
memory?
(b) Write a program to evaluate the arithmetic statement:
X=(A-B+C*(D*E-F))/G+H*K
Using general register computer, accumulator type computer and stack organization
computer.
(c) Draw the block diagram for the hardware that implement the following statement:
x+yz: ARAR+BR
where AR and BR are two n-bit registers and x,y and z are control variables.
(d) Design a 4-bit combinational circuit decrementer using four full adder circuits.
(e) Describe all memory addressing scheme employed at ISA at design level
Q2. Attempt any two parts:

(4X5=20)

(a) Show step-by-step multiplication process using Booth algorithm. Assume 5-bit
registers that hold signed numbers.
(+5)x(+13)
(b) Derive an algorithm in flowchart form for adding and subtracting two fixed point
binary numbers when negative numbers are in signed-2s complement representation
(c) Give the IEEE 754 standard 32-bit floating pointing number format.
(d) What do you mean by high speed adders? Discuss design of high speed adders?
(e) Represent the following decimal number in IEEE 754 floating point format
-0.12 , +1.75
Q3. Attempt any two parts:
(2X10=20)
(a) What are the different types of mapping techniques used in the usage of cache
memory? Explain
(b) A digital computer has a memory unit of 64X16 and a cache memory of 1K words.
The cache uses direct mapping with a block size of 4 words. How many bits are there in
tag, index, block and word field of the address format.
(c) Differentiate between programmed I/O and interrupt-driven I/O.

Q4. Attempt any two parts:

(2X10=20)

(a) Just like MIPS rating is defined, we can also define something called the MFLOPS
rating which stands for Millions of Floating Point operations per Second. If Machine A
has a higher MIPS rating than that of Machine B, then does Machine A necessarily have a
higher MFLOPS rating in comparison to Machine B?
(b) Consider two different implementations, M1 and M2, of the same instruction set.
There are three classes of instructions (A, B, and C) in the instruction set. M1 has a clock
rate of 80 MHz andM2 has a clock rate of 100 MHz The average number of cycles for
each instruction class and their frequencies (for a typical program) are as follows:
Instruction Class

Machine M1
Cycles/

Machine M2
Cycles/Instruction
Class

Frequency

A
B
C

1
2
4

2
3
4

60%
30%
10%

1. Calculate the average CPI for each machine, M1, and M2.
2. Calculate the average MIPS ratings for each machine, M1 and M2.
(c) Describe SUN & Ni Law in detail.
Q5. Attempt any two parts:

(2X10=20)

(a) What is cache coherence problem? What is snooping cache? Discuss with example the
write through and write once protocols for cache consistency.
(b) What are the problems of multiprocessor architecture, why it must be resolved to get
max benefit for scaling the architecture.
(c) What are Static and Dynamic interconnection networks.