SPD-S

Apr.2003

SERVICE NOTES
TABLE OF CONTENTS
SPECIFICATIONS.............................................................2
LOCATION OF CONTROLS ..........................................4
LOCATION OF CONTROLS PARTS LIST ...................5
EXPLODED VIEW ............................................................6
EXPLODED VIEW PARTS LIST .....................................7
PARTS LIST........................................................................8
IDENTIFYING THE VERSION NUMBER ..................10
SAVING USER DATA & RELOADING SAVED
DATA................................................................................10
TEST MODE.....................................................................11

INITIALIZATION PROCEDURE .................................16

FORMATTING A COMPACTFLASH CARD.............17
RESTORING THE FACTORY SETTINGS ...................17
PROCEDURE FOR UPDATING THE SYSTEM
SOFTWARE......................................................................18
BLOCK DIAGRAM.........................................................20
CIRCUIT BOARD (MAIN) ............................................22
CIRCUIT DIAGRAM (MAIN).......................................26
CIRCUIT BOARD (PANEL) ..........................................42
CIRCUIT DIAGRAM (PANEL).....................................46

Copyright 2003 ROLAND CORPORATION

All rights reserved. No part of this publication may be reproduced in any form without the written permission
of ROLAND CORPORATION.

17058160E0

Printed in Japan (0800) (NB)

Apr.2003

SPECIFICATIONS

Dimensions
342 (W) x 282 (D) x 83 (H) mm
13-1/2 (W) x 11-1/8 (D) x 3-5/16 (H) inches

SPD-S: Sampling Pad

Pads

Weight
2.1 kg

Built-in Pads: 9

Maximum Polyphony

4 lbs 11 oz (excluding AC adaptor)

Accessories

8 voices

Owners Manual English (#03129712)

Sampling Mode

AC Adaptor ACI-120C (#00975767)

AC Adaptor ACI-230C (#01018312)

Fine/Standard/Long

AC Adaptor ACB-230E (#01458278)

AC Adaptor ACB-240A (#12449549)

Sampling Frequency

Sampling CD (#03129723)

44.1 kHz

Stand Holder Mounting Screw x 4 (#40563778)

Security Screw x 2 (#02126156)

Input Level

Hexagon Wrench (#********)

Line: -10 dBu

Mic: -50 dBu

Input Impedance

Slit Tape (#********)

Options
Pads (PD-120, PD-100, PD-80, PD-80R, PD-9, PD-7, PD-6, KD-7)

10 k ohm (LINE/MIC)

Expression Pedal (EV-5)

Foot Switch (BOSS FS-5U)

Output Level

Hi-Hat Control Pedal (FD-7)

PCS Connecting Cord Set (PCS-31)

Output: -10 dBu

Output Impedance
Output: 1 k ohm

All Purpose Clamp Set (APC-33)

The CompactFlash which can operate by SPD-S

CompactFlash Capacity: 16M/32M/64M/128M/256M/512M byte

Headphones: 47 ohm

Memory

0 dBu = 0.775 Vrms

Patches: 128
Waves: Internal: 399 (Pre-loaded Sound 181)
Card: 500

Maximum Sampling Time

12 min. approx. (Internal Memory, Long Mode)

Effects
Multi-Effects (30 types) + Ambience (System)

Display
16 characters, 1 line (backlit LCD)

Connectors
Output Jacks (L/Mono, R) (1/4 inch phone type)
Input Jacks (L/Mono, R) (1/4 inch phone type)
* LINE/MIC selectable
Headphones Jack (Stereo) (Stereo 1/4 inch phone type)
Trigger Input Jack (1/4 inch TRS phone type)
Expression Pedal (1/4 inch TRS phone type)
MIDI Connectors (IN, OUT)
Foot Switch Jack (1/4 inch TRS phone type)
CompactFlash Card Slot

Power Supply
DC 9 V: AC Adaptor

Current Draw
1,000 mA

In the interest of product improvement, the specifications and/or appearance of

this unit are subject to change without prior notice.

SPD-S

Apr.2003

LOCATION OF CONTROLS
fig.panel

20

13

14 15

5
8

16

10

17

12

7
11

18

12

19

SPD-S

LOCATION OF CONTROLS PARTS LIST

[Parts]
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

PART CODE
03341889
03129489
03230601
F3229136
03129756
03129545
03129512
02341634
03341890
03235345
02341712
02897334
12499175
01676512
22365714
40011312
02568867
02341645
03129556
02565056
03341901
03121678
03121689

PART NAME
PLAYING PLATE ASSY
R-KNOB
9M/M ROTARY POT.
12M/M ROTARY POT.
PANEL SHEET ASSY
TOP PANEL
RUBBER SWITCH
DC JACK
BOTTOM CASE ASSY
SLIDE SWITCH
6.5MM JACK (MONORAL)
6.5MM JACK (STEREO)
KEY TOP for POWER SW
POWER SWITCH
CORD HOOK
SCREW M3x8
MIDI CONNECTOR
6.5MM JACK (STEREO)
REAR PANEL
9M/M ROTARY POT.
CF COVER ASSY
COMPACTFLASH CONNECTOR
COMPACTFLASH EJECTOR

DESCRIPTION
for SC
for SC
EVUJFRFK1B14
RV112B-40E1-125A-A10K for SC
for SC
for SC
for SC
HTJ-020-05A
for SC
SSSF141300
HTJ-064-10I
HTJ-064-10D for SC
JSPUE0011A
SDKLA1-B
BINDING TAPTITE P BZC
HDC-052A-12
HTJ-064-04A
for SC
RK09K12A0D0K
for SC
ICM-MA2H-SS52-R21A
ICM-MAE-R21

QTY
1
2
1
1
1
1
1
1
1
1
4
3
1
1
1
1
1
1
1
2
1
1
1

Apr.2003

EXPLODED VIEW
fig.bunkai-e

3
c
c
5
2

4
c

c
d

11
12
6

c
d

13

15

d
10

14
16
* Apply SHIELD SHEET using a
double-side tape on the reverse side

20
18
21

17

22

19

23

SPD-S

EXPLODED VIEW PARTS LIST

[Parts]
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

PART CODE
22365714
01344967
03341890
********
12499175
03129745
03341901
03341901
03341901
********
03129756
********
03129512
03341889
03341889
03341889
03129756
********
03129489
03341889
03341889
03341889
03341889

PART NAME
CORD HOOK
FOOT
BOTTOM CASE ASSY
REAR HOLDER
KEY TOP for POWER SW
MAIN BOARD ASSY
CF COVER ASSY
CF COVER ASSY
CF COVER ASSY
SHIELD SHEET
PANEL SHEET ASSY
WIRING 1
RUBBER SWITCH
PLAYING PLATE ASSY
PLAYING PLATE ASSY
PLAYING PLATE ASSY
PANEL SHEET ASSY
WIRING 2
R-KNOB
PLAYING PLATE ASSY
PLAYING PLATE ASSY
PLAYING PLATE ASSY
PLAYING PLATE ASSY

DESCRIPTION

(INC. PCB SPACER CBS-19K)

(INC. SENSOR ASSY)
(INC. TOP CASE)
(INC. VOLUME BOARD)
12 PIN
for SC
(INC. EDGE SHEET SENSOR for PAD 1-3)
(INC. HEAD SHEET SENSOR for PAD 4-9)
(INC. CUSHION)
(INC. PLAYING PLATE)

QTY
1
4
1
1
1
1
1
1
1
1
1
1
1
3
2
1
1
1
2
1
1
1
1

PART NAME
SCREW 4x16
SCREW 4x12
SCREW 3x8
SCREW 3x6
SCREW 3x8
SECURITY SCREW

DESCRIPTION
BINDING TAPTITE P NI
BINDING TAPTITE P BZC
BINDING TAPTITE P ZC
BINDING TAPTITE B ZC
BINDING TAPTITE P BZC
HEX CAP SCREW M3x10 TAPTITE P NI

QTY
4
11
16
9
1
2

(INC. BOTTOM CASE)

JSPUE0011A
(INC. CF ESCUTCHEON)
(INC. CF COVER)
(INC. CF HOLDER)
(INC. PANEL BOARD)
40 PIN

[Screws]
NO.
a
b
c
d
e
f

PART CODE
40562967
40012501
40011278
40011056
40011312
02126156

Apr.2003

PARTS LIST
fig.part1e

SAFETY PRECAUTIONS:
The parts marked
have
safety-related characteristics. Use
only listed parts for replacement.

CONSIDERATION ON PARTS ORDRING

When ordering any parts listed in the parts list, please specify the following items in the order sheet.
QTY
PART NUMBER
DESCRIPTION
MODEL NUMBER
Ex.
10
22575241
Sharp Key
C-20/50
15
2247017300
Knob (orange)
DAC-15D
Failure to completely fill the above items with correct number and description will result in delayed or even
undelivered replacement.

NOTE: The parts marked # are new. (initial parts)

CASING
#
#
#
#
#
#
#
#
#
#

#
#
#
#
#

QTY
1

03341889
PLAYING PLATE ASSY
for SC
NOTE : PLAYING PLATE ASSY INCLUDES TOP PANEL
********
EDGE SHEET SENSOR
for PAD 1-3
********
HEAD SHEET SENSOR
for PAD 4-9
********
CUSHON
********
PCB SPACER
CBS-19K
********
PLAYING PLATE
********
SENSOR ASSY
********
TOP CASE
03129545
TOP PANEL

1
1
1
1
1
2
1
1

03341890
BOTTOM CASE ASSY
for SC
NOTE : BOTTOM CASE ASSY INCLUDES THE FOLLOWING PARTS
********
BOTTOM CASE
22365714
CORD HOOK
01344967
FOOT
03129556
REAR PANEL

03341901
CF COVER ASSY
NOTE : CF COVER ASSY INCLUDES THE FOLLOWING PARTS
********
CF COVER
********
CF ESCUTCHEON
********
CF HOLDER

1
1
^4
1

1
1
1

KNOB, BUTTON
#
03129489
12499175

R-KNOB
JSPUE0011A

for SC
KEY TOP for POWER SW

JACK, EXT TERMINAL

#
03129512
01676512
#
03235345

RUBBER SWITCH
PUSH SWITCH SDKLA1-B
SLIDE SWITCH SSSF141300

for SC
POWER SWITCH
SLIDE SWITCH

SW3
SW2

1
1
1

HTJ-064-04A
HTJ-064-10D for SC
HTJ-064-10I
HTJ-020-05A
HDC-052A-12

6.5MM JACK (STEREO)

6.5MM JACK (STEREO)
6.5MM JACK (MONORAL)
DC JACK
MIDI CONNECTOR

JK9
JK4,JK7,JK8
JK2,JK3,JK5,JK6
JK10
JK1

1
3
4
1
1

PWB ASSY
#
03129745
#
03129756

MAIN BOARD ASSY

PANEL SHEET ASSY

for SC
for SC

POTENTIOMETER
02565056
#
03230601
#
F3229136

RK09K12A0D0K
EVUJFRFK1B14
RV112B-40E1-125A-A10K for SC

9M/M ROTARY POT.

9M/M ROTARY POT.
12M/M ROTARY POT.

VR1,VR2
VR4
VR3

2
1
1

CONNECTOR
#
03121678
#
03121689

COMPACTFLASH CONNECTOR
COMPACTFLASH EJECTOR

ICM-MA2H-SS52-R21A
ICM-MAE-R21

CN9
CN9

1
1

2
1

SWITCH
02341645
02897334
02341712
02341634
02568867

1
1

SPD-S

WIRIING, CABLE
********
#
#
********

WIRING 1
WIRING 2

40 PIN
12 PIN

1
1

40011056
40011278
40011312
40012501
40562967

SCREW M3x6
SCREW M3x8
SCREW M3x8
SCREW M4x12
SCREW M4x16

BINDING TAPTITE B ZC
BINDING TAPTITE P ZC
BINDING TAPTITE P BZC
BINDING TAPTITE P BZC
BINDING TAPTITE P NI

9
16
1
11
4

PACKING
#

03341878

PACKING SET

for SC

SCREW

MISCELLANEOUS
22365714
01344967
#
********

CORD HOOK
FOOT
SHIELD SHEET

ACCESSORIES (Standard)
03129701
#
#
03129712
#
03343323
00905756
00905767
01018312
01458278
12449549
#
03129723
#
40563778
02126156
#
********
#
********
40232334

OWNERS MANUAL
OWNERS MANUAL
LEAFLET
AC ADAPTOR ACI-100C
AC ADAPTOR ACI-120C
AC ADAPTOR ACI-230C
AC ADAPTOR ACB-230E
AC ADAPTOR ACB-240(A)
CD-ROM
STAND HOLDER MOUNTING SCREW
SECURITY SCREW
HEXAGON WRENCH
SLIT TAPE
WARRANTY CARD

1
4
1

JAPANESE
ENGLISH
JAPANESE/ENGLISH

SAMPLING CD for SC
HEX CAP SCREW M5x12 BZC
HEX CAP SCREW M3x10 TAPTITE P NI
4MM
(JAPAN ONLY)

1
1
1
1
1
1
1
1
1
4
2
1
1
1

Apr.2003

IDENTIFYING THE VERSION

NUMBER
1.

Hold down the [ALL SOUND OFF] and [CARD] buttons and turn on the
power to the unit.

2.

Press the [<]/[>] buttons to sequence through the display of the

following items.

SAVING USER DATA &

RELOADING SAVED DATA
Required equipment

MIDI sequencer

MIDI cable

CPU Version, Build Number

fig.ver-1

CPU1.00 BLD0018

BULK DUMP
Settings for SPD-S setups and patches can be saved to an external MIDI device,
such as a sequencer.

CPU Release Date

fig.ver-2

Operate the external sequencer for recording ordinary performance data and
then take the following steps for the SPD-S.

CPU DATE 12/16/02

CPU Release Time

See the operation manual of the external MIDI device for details on it.

fig.ver-3

CPU TIME 13:25:25

EXT ROM Version, Build Number

1.

Connect an external MIDI sequencer (as a saving destination) to the MIDI

OUT connector on the SPD-S using a MIDI cable.

fig.dump-e

fig.ver-4

PRG1.01 BLD0044
MIDI IN

MIDI OUT

EXT ROM Release Date

fig.ver-5

PRG DATE 04/10/03

EXT ROM Release Time

fig.ver-6

External Seqencer

PRG TIME 08:39:14

SPD-S

Factory Data Version, Build Number

fig.ver-7

PRE 1.17 BLD012

3.

Turn off the power to quit.

2.

Set the SPD-S to the patch mode or to the wave mode.

3.

Press [SETUP] button to access Setup Edit.

4.

Press the PAGE buttons to select BULK DUMP, then press [ENTER]
button.

5.

Press [+] button to select ALL.

6.

Start recording on the external sequencer.

7.

Press [>] button to display bulk dump, sure?

Press [ENTER] button to execute bulk dumping.

During transmission, now sending is displayed.

After the transmission is finished, a complete! indication appears and the
SPD-S returns to the Dump screen in Step 2.
To cancel the transmission midstream, press [EXIT] button.

8.

10

Stop the external sequencer to stop recording.

SPD-S

Retrieving Saved Data Back to

the SPD-S
Retrieves the settings saved to sequencers and other external MIDI devices to
the SPD-S.

1.

Connect the MIDI IN connector on the SPD-S to the MIDI OUT connector
of an external sequencer using a MIDI cable.

2.

Press [PATCH] button to enter patch mode.

Bulk data cannot be retrieved in any mode other than patch mode.

3.

6.

To quit Test mode:

Turn off the power to the unit.

In each tested item, the screen initially shows the test type for a set length of
time, the display switches to the actual test screen.

The BelTreeD sound is played when OK is returned and the procedure

advances to the subsequent test. When a test results NG, the FlexMtl sound
is played.

Test Mode Procedure

Transfer the settings data from the external sequencer to the SPD-S.
The transferred settings are restored.

Executing Test mode deletes the User data; be sure to back up the data stored
in the unit beforehand.
fig.audio

TEST MODE
Required items

Expression Pedal (EV-5 etc.)

Foot switch x3 (FS-5U etc.)

PAD (With a RIM switch function) x2 (PD-7, PD-9, CY-12 etc.)

Y cable (PCS-31) x2

Stereo jack plug Cable x1

Mono jack plug Cable x2

MIDI cable

CompactFlash (Formatting using the SPD-S)

Monitor Speaker

Headphone

Basic Test Mode Operations

1.

d
Rolan

or

1.

2.

Using a Y cable, connect two foot switches to the FOOT SW jack.

Use a stereo cable to connect a pad with a rim switch to the TRIG IN jack.
Alternatively, use a Y cable to connect one foot switch to the TRIG IN
jack (plug in the Y cables red connector).

Press [>] button (the LED flashes as a prompt).

Hold down [SHIFT] button and press the [>] button.

white

Make sure that the polarity is set properly here (set the foot switches to
open when the pedal is pressed; this should be the reverse of the TRIG IN
switch).

Proceeding with series of test:

To advance to the next test forcefully even when the result is NG or

while running a test:

red

Pad with
a rim switch

Some of tests automatically advance to the next when the result is OK.

2.

Y cable

Stereo jack
plug cable

Make sure that the polarity is set properly here (set the foot switches to
short (close) when the pedal is pressed).
3.

Connect an expression pedal to the EXP PEDAL jack.

4.

Insert a CompactFlash card in the unit for tests.

Use a CompactFlash card formatted on the SPD-S.
If updating of the factory data is required in 0. Factory Data Update,
use a CompactFlash card containing the factory data.

3.

To return to the previous test:

Press the [<] button.

4.

To return to the previous test forcefully:

Hold down [SHIFT] button and press the [<] button.

5.

To repeat the current test:

Press [EXIT] button.

11

Apr.2003

Entering Test Mode

2. Device Test

1.

Insert the CompactFlash card in the card slot.

fig.test2-1

2.

Hold down both [PHRASEMAKER] and [CARD] buttons and turn on the
power.

3.

Continue to hold down the buttons until [PATCH] and [EFFECTS]

buttons light.

4.

Release [PHRASEMAKER] and [CARD] buttons.

5.

Press [EXIT] button.

6.

Press [ENTER] button.

2.Device Test
1.

When the test results OK, the - symbol changes to o; if the test
results NG (fail), the symbol changes to a charactor to represent the
error type.

fig.test2-2

DEV [------]
fig.test2-3

Test Items
0. Factory Data Load

DEV [ooSoWC] NG!

Checked Items

When the CompactFlash contains factory data, the instrument compares its
version with the version contained internally, and if the CompactFlash
contains a newer version, the unit automatically switches to Update mode.

I: CPU Internal: Checksum Comparison

If the data stored in the instrument is the later version, this mode is skipped.

S: SDRAM: Write/Read

fig.test0-1

M: MR3 Chip: Write/Read

New Factory Data

1.

Press the [ENTER] button to begin loading.

fig.test0-2

P: Program ROM: Checksum Comparison

N: NAND Flash: Write/Read/Format

C: CompactFlash: Format (Write/Read Check)

2.

Press the [>] button to show which tests failed.

If multiple tests fail, use the [<] and [>] buttons to navigate (the [<] and
[>] buttons flash as a prompt).

[ENTER] to Update

fig.test2-4

CPU Internal NG!

Loading.
fig.test0-3

Now Loading...

fig.test2-5

Program ROM NG!

When loading fails (in this case, press [EXIT] button to return to the previous
screen).
fig.test0-4

Load Failed!

3.

If all tests result OK, the process automatically advances to the

subsequent test.

fig.test2-6

DEV [oooooo] OK!

2.

When loading completes normally, the process automatically advances to

the subsequent test.

fig.test0-5

Load Completed!

3. MIDI Test
fig.test3-1

3.MIDI Test

1. Version Test
1.

fig.test1-1

Use a MIDI cable to connect SPD-Ss MIDI IN and MIDI OUT.

1.Version Test
Before Connecting
1.

Confirm the version number.

fig.test3-2

fig.test1-2

MIDI OUT-x-IN

CPU1.00 PRG1.01

Connected
2.

Press the [>] button to advance to the subsequent test.

fig.test3-3

MIDI OUT---IN OK
2.

12

If the test results OK, the process automatically advances to the

subsequent test.

SPD-S
4. Switch/LED Test

5. Effects Control Knob Test

fig.test4-1

fig.test5-1

4.SW/LED Test

5.CtrlKnob Test

fig.test4-2

1.

(22)

Turn the [EFFECTS CONTROL] knob completely to the left

(counterclockwise), and confirm that the value is 0 when the knob is
fully turned.

fig.test5-2

KNOB (108)
The number of switches that have not been checked is indicated in
parentheses.

The following screen appears when the knob is turned fully to the left.
At this time, confirm that the CowbMmbo sound is played.
fig.test5-3

1.

Using a Y cable, connect two foot switches to the FOOT SW jack.

2.

Use a stereo cable to connect a PD-7 to the TRIG IN jack.

KNOB

Alternatively, use a Y cable to connect one foot switch to the TRIG IN

jack (plug in the Y cables red connector).
3.

2.

Press the panel switches individually to comfirm that the name of the
switch being pressed appears in the display and that the corresponding
sound is played.
If the switch includes an LED, also confirm that the LED turns off when
the switch is pressed.

For pad switches, press (grasp) the rim section.

The test doesn't result OK when two or more panel switches are pressed
simultaneously.
The test also doesn't result OK when the foot switches (or a foot switch and
pad switch) are pressed simultaneously.

Turn the [EFFECTS CONTROL] knob completely to the right.

At this time, confirm that the BelTreeD sound is played.

3.

If the test results in OK, the process automatically advances to the

subsequent test.

fig.test5-4

KNOB (127) OK!

6. Expression Pedal Test

fig.test6-1

fig.test4-3

6.Exp.Pedal Test

(14) ALLSOUNDOFF
4.

(0)

1.

Connect an expression pedal to the EXP PEDAL jack.

The PAD LEDs turn off with each press of the [+] button.

2.

Confirm that the value is 0 when the pedal heel is pressed down fully.

Confirm that all of the PAD LEDs go off.

fig.test6-2

fig.test4-4

PEDAL (108)

(0) + (PAD1 LED)

The following screen appears in the display when the pedal heel is
pressed down fully.

Switches

At this time, confirm that the CowbMmbo sound is played.

fig.test6-2

fig.test4-5

[PATCH]
[RESAMPLE]
[EFFECTS]
[EDIT]
[PHRASEMAKER]
[FOOTSW1]

[WAVE]
[EXIT]
[ALLSOUNDOFF]
[LEFT/<]
[FUNC]
[FOOTSW2]

[PLAY/STOP]
[ENTER]
[CARD]
[RIGHT/>]
[SHIFT]
[TRIGINSW]

[SAMPLE]

PEDAL

(0)

[SETUP]
[-]

[+]

3.

Press the pedal toe down completely.

At this time, confirm that the BelTreeD sound is played.

5.

If all of the switches pass their tests, the process automatically advances
to the subsequent test.

fig.test4-6

(0)

OK!

4.

If the test results in OK, the process automatically advances to the

subsequent test.

fig.test6-3

PEDAL (127) OK!

13

Apr.2003
7. LCD Test

8. Trigger Test

fig.test7-1

fig.test8-1

7.LCD Test
1.

Hold down the [INC/+] button and confirm that the LCD contrast
changes gradually.

8.Trigger Test
1.

Using a Y cable, connect two pads to the TRIG IN jack.

Holding down the [INC/+] button and pressing the [DEC/-] button
causes the contrast to change more rapidly.
When the contrast is at the maximum level, the screen shown below
appears.

To disable the trigger while connecting or disconnecting the cable, hold down
the [FUNC] button; the trigger is ignored while this button is pressed.

At this time, confirm that the Agogo Hi sound is played.

fig.test7-2
fig.test8-2

Hit "Softly"
2.

Hold down the [DEC/-] button and confirm that the LCD contrast
changes gradually.

fig.test8-3

123456789AB Soft

Holding down the [DEC/-] button and pressing the [INC/+] button
causes the contrast to change more rapidly.
When the contrast is at the minimum level, the screen shown below
appears.

2.

The test automatically checks whether or not the sheet sensor is turned
on while the pad is not being touched.

At this time, confirm that the Agogo Lo sound is played.

fig.test7-3

If no pad has a sheet sensor on, nothing appears in the display, and the
procedure advances to the subsequent test.

______________________
3.

Press the [ENTER] button and confirm that the entire LCD is lit (the
[ENTER] button flashes as a prompt).

Sheet Sensor Check

Do not touch the pads while the check is in progress.

At this time, confirm that the Shaker sound is played.

fig.test7-2

If there is a pad with its sheet sensor on, the pads number is displayed,
the pad LED flashes, and the test result is NG.
fig.test8-4

4.

oo3oo67oo Sheet

Press the [ENTER] button and confirm that the entire LCD goes dark (the
[ENTER] button flashes as a prompt).
At this time, confirm that the Maracas sound is played.

fig.test7-4

3.

Check response to weak hits by striking a lightly and individually.

Confirm that the corresponding number disappears and that the
corresponding sound is played.
The LED for each corresponding pad flashes and then goes off.

fig.test8-5

5.

Pressing the [ENTER] button cycles through the contrast check, all LCD on,
and all LCD off tests.

___456789AB Soft

If all tests result in OK, press the [>] button to advance to the
subsequent test.
The procedure does not advance unless all of the above tests are
completed.

The test does not result OK when two or more pads are struck
simultaneously.
A minimum interval of 0.1 seconds is required between each stroke of the
pads.

When a pad is struck hard, the corresponding number in LCD doesnt go off
and no sound is played although the pad LED lights, and the test doesnt
result OK.
4.

If all pads are OK, the process automatically advances to the

subsequent test.

fig.test8-6

Hit "Hard"!
fig.test8-7

123456789AB Hard

14

SPD-S
5.

Check response to strong hits by striking a pad hard and individually.

b.

Velocity Check
Strike each pad with a stick; when a pad is struck, the pad number and
velocity value (1--127) is displayed, and the corresponding LED flashes
and then goes off.

Confirm that the corresponding number disappears and that the

corresponding sound is played.
The LED for each corresponding pad flashes and then goes off.

fig.test8-13

fig.test8-8

___456789AB Hard

) Velo( )

Strike [Pad5].
fig.test8-14

(Pad5) Velo(115)

When a pad is struck lightly, the corresponding number in LCD doesnt go off
and no sound is played although the pad LED lights, and the test doesnt
result OK.

The weak and strong checks can be switched by pressing the [ENTER] button.

When a pad has faulty sheet sensors that does not turn on, there is no response
from the pad when it is struck.

Press the [ALLSOUNDOFF] button to return to the Sheet Sensor Check.

Correspondence Between the Pads and

Sounds

Press the [EXIT] button to return to the beginning of the Trigger Test.

fig.test8-9

[1: Claves 2 ]
[4: Bongo Hi ]
[7: 808Kik 1 ]
[A(Trig1): 909Claps ]

[2: CowbMmbo ]
[5: Conga Hi ]
[8: eSnr ]
[B(Trig2): SpokTom1 ]

[3: Agogo Hi ]
[6: Xstick 3 ]
[9: AcuHH cl ]

9. Audio Input Test

fig.test9-1

9.Audio In Test
6.

If all pads are OK, the process automatically advances to the

subsequent test.

fig.test8-10

[___________] OK!

1.

Set the [VOLUME] knob to minimum, and turn the [INPUT LEVEL] knob
on the rear panel to the maximum setting.

2.

Use two mono cables to connect the INPUT L/MONO and R to the
OUTPUT L/MONO and R.

fig.test9-2

Set Volumes MIN

Advanced Test Mode

To enter Advanced Test mode, press the [ALLSOUNDOFF] button during the
Trigger Test.
This mode, you may check the causes of failure in the above test.

3.

Press the [ENTER] button.

fig.test9-3

[MIC] <- [LINE]

a.

Sheet Sensor Check

If a pads sheet sensor turns on when the pad is pressed with the hand,
the corresponding number disappear, and the pads LED goes off.

fig.test9-4

Release the pads to return them to their original state.

fig.test8-11

(Level Meter Display)

123456789 Sheet
Above level meter is displayed, and a 100-Hz signal is output at -50 dBu.
The [START/STOP] button flashes.

Hand-press [Pad3].
fig.test8-12

4.

Set the [LINE/MIC] switch to MIC and turn up [VOLUME] knob.

If the signal level is correct when [VOLUME] knob is turned right fully,
the process automatically advances to the subsequent test.

12_456789 Sheet

The level meter is displayed in the LCD.

Release [Pad3].

fig.test9-4

fig.test8-11

123456789 Sheet
Press the [ALLSOUNDOFF] button to advance to the Velocity Check.

(Level Meter Display)

5.

The LCD shows following display, then it returns to the level meter.

fig.test9-5

[MIC] -> [LINE]

A 100-Hz signal is output at -10 dBu.
[START/STOP] button lights, and [SAMPLE] button flashes.

15

Apr.2003
6.

Set [LINE/MIC] to LINE.

If the signal level is correct, the signal automatically switches to 10 kHz,
and the same test runs.
The [START/STOP] and [SAMPLE] buttons light, and the [RESAMPLE]
button flashes.

11. Completing Test Mode

1.

If all of the tests in Test mode result in OK, shutdown for the card is
executed.

fig.test11-1

shutdown..

If the tests result is OK, the process automatically advances to the

subsequent test.

fig.test11-2

shutdown.. OK!
In this test, signal status is normal when six squares are displayed for both the
left and right channels in the LCD.

When the following is displayed, turn off the power to the unit.
fig.test11-3

At this time, the [WAVE] button lights.

10. Sound Test

Test Completed!
2.

Not All Passed

10.Sound Test
1.

Confirm that no sound is being played ([ENTER] LED flashes as a

prompt).

fig.test10-2

SOUND
2.

If any of the tests fails, the following is displayed.

fig.test11-4

fig.test10-1

Press [ENTER] button, and confirm that a sine wave is output from both
the left and right channels of OUTPUT and PHONES (the [EDIT] button
lights).

INITIALIZATION PROCEDURE
Resets the SPD-Ss settings to initial values, or delete all the data stored in the
SPD-S.

fig.test10-3

<<L SOUND R>>

3.

Press the [EDIT] button, and confirm that the output is muted (the mute
circuits activate).

If you execute INIT/DELETE to delete patches and waves from the internal
memory, the SPD-S will produce no sound.

1.

Set the SPD-S to the patch mode or to the wave mode.

2.

Press [SETUP] button to access Setup Edit.

3.

Press the PAGE buttons to select INIT/DELETE, then press [ENTER]

button.

At this time, the sound is output at a very low level; this does not indicate any
malfunction (the [ENTER] LED lights as a prompt).

4.

Press [+] button to select ALL.

fig.test10-4

5.

Press [>] button to display delete all, sure?

6.

Press [ENTER] button to start initialization or deletion.

7.

During execution, now processing? is indicated.

<<L MUTE R>>

4.

Press [ENTER] button, and confirm that a sine wave is output only from
the left channel of OUTPUT and PHONES (the [ENTER] LED lights as a
prompt).

After the execution, a complete! indication appears, and the SPD-S

returns to the patch mode.

fig.test10-5

<<L SOUND
5.

Press [ENTER] button, and confirm that a sine wave is output only from
the right channel of OUTPUT and PHONES (the [ENTER] LED lights as a
prompt).

fig.test10-6

SOUND R>>
6.

Press [ENTER] button, and confirm that no sound is being output (the
[ENTER] LED lights as a prompt).

fig.test10-7

SOUND
*

7.

16

Press [ENTER] button to cycle through Steps 3--6.

If the tests result OK, press [>].

Do not power the SPD-S off during execution.

SPD-S

FORMATTING A
COMPACTFLASH CARD

RESTORING THE FACTORY

SETTINGS

1.

The accompanying CD contains audio signals for sampling on the SPD-S and
digital data for restoring the SPD-S to its factory settings.

To insert a CompactFlash card, carefully open the card slot cover (lefthand side of the SPD-S).

Restoring Patches and Waves to the Factory Settings

fig.cf-1
MEMORY CARD slot

Once you execute this operation, you will lose all the patches and waves stored
in the internal memory.
Back up such data beforehand if needed.

Required items
CompactFla

sh

2.

Select patch mode or wave mode.

3.

Press [SHIFT] and [SETUP] buttons (CARD UTIL).

A computer with a CD-ROM drive

A card reader that supports CompactFlash cards

The accompanying CD-ROM (P/No.03129723)

CompactFlash (Formatted using the SPD-S)

Procedure
1.

Connect the card reader to the computer to ensure that it can be used.

If no CompactFlash card has been inserted, no card! is indicated and the

SPD-S returns to the original mode.
For connecting the card reader to the computer and using them, see their
respective operation manuals.
4.

Press the PAGE buttons to select CARD FORMAT, then press [ENTER]
button.
2.

Load the accompanying CD into the CD-ROM drive.

3.

Insert the CompactFlash card into the card reader.

4.

Copy the FCTRY folder on the accompanying CD to the ROLAND

folder on the CompactFlash card.

When the CompactFlash card is unformatted, only CARD FORMAT is

displayed.
5.

A [>] to format. indication appears. Press [>] button.

6.

A format, sure? indication is displayed. Press [ENTER] button to start

formatting.
While formatting is in progress, now processing.. is displayed. Then,
the SPD-S returns to the original mode.

If the ROLAND folder on the CompactFlash card already has a

FCTRY folder, delete the FCTRY folder before copying.
5.

Eject the CompactFlash card to which the copying was done in Step 4
from the card reader.
Then, make sure that the SPD-S is powered off and insert it into the card
slot of the SPD-S.

6.

While holding down [PATCH], [WAVE], and [CARD] button ON the

SPD-S.

After powering it on, hold down the three buttons until [ENTER] to Load
appears.

7.

[ENTER] to Load appears. Release the three buttons. Next, press

[ENTER].
Data transfer from the CompactFlash card to the SPD-S begins.
It takes a few minutes until it is complete.

During the data transfer, do not eject the CompactFlash card from the card slot
and do not switch off power to the SPD-S. Doing so could not only destroy the
data, but also cause problems for the SPD-S.

8.

Load Completed! appears, and the data transfer is complete.

Now, eject the CompactFlash card, power the SPD-S off, then power it on
again.

17

Apr.2003

PROCEDURE FOR UPDATING

THE SYSTEM SOFTWARE

5.

When the update is completed normally, the [START/STOP], [SAMPLE],

and [RESAMPLE] LEDs light up.

fig.up-3

Update Complate

The system can be updated using CompactFlash or MIDI.

Instructions for Updating Using

CompactFlash
Required items

A computer with a CD-ROM drive

A card reader that supports CompactFlash cards

UPDATE CD-ROM for CF Card (P/No.17041324)

CompactFlash (Formatted using the SPD-S)

1. Preparation
Prepares a CompactFlash card containing the updated system file.

1.

If an error occurs during the procedure, all of the LEDs light up, and an
error message is displayed.
fig.up-4

Update ERROR 15
6.

Turn off the power to end the procedure.

Updating Using MIDI

Required items

A MIDI sequencer that can play back SMF data

UPDATE CD-ROM for SMF (#17041324)

MIDI Cable

Insert the CompactFlash in a card reader connected to a computer.

1. Preparation
For instructions on connecting the computer and card reader, refer to the
service notes for formatting a CompactFlash.

The following sixteen files are required for the updater SMF; confirmed that
they are present.
p00001.mid, p00002.mid, p00003.mid, p00004.mid

2.

p00005.mid, p00006.mid, p00007.mid, p00008.mid

Place the updated program in the CompactFlashs root (the top level).
This completes preparation of the updater CompactFlash.

2. Update Procedure

p00009.mid, p00010.mid, p00011.mid, p00012.mid

p00013.mid, p00014.mid, p00015.mid, p00016.mid

2. Update Procedure

1.

Hold down the [EFFECTS] and [ENTER] buttons and turn on the power
to the unit.

1.

Use a MIDI cable to connect the MIDI OUT connector of a sequencer

capable of playing back SMFs and the MIDI IN connector on the SPD-S.

2.

The [PATCH] and [PHRASEMAKER] buttons flash.

2.

Hold down the [WAVE] and [ENTER] buttons and turn on the power to
the unit.

3.

The [SETUP] and [EDIT] buttons flash.

fig.up-1

Card Updater

fig.up-5

MIDI Updater

To cancel the update at this point, turn off the power to the SPD-S.

3.

Press the [PATCH] and [PHRASEMAKER] buttons simultaneously.

4.

The update begins.

The process is divided into sixteen steps, and in each step, the

4.

To cancel the update at this point, turn off the power to the SPD-S

Press the [SETUP] and [EDIT] buttons simultaneously.

fig.up-6

Please Send

[START/STOP] -> [SAMPLE] -> [RESAMPLE]

LEDs light in sequence.

fig.up-2

Update: **/16

5.

Play back p00001.mid through p00016.mid in sequence.

6.

The update begins, and with each file, the

[START/STOP] -> [SAMPLE] -> [RESAMPLE]

*

The ** indicates the step number currently being processed (01--16).

LEDs light in sequence.
fig.up-2

Update: **/16
*

18

The ** indicates the file currently being executed (01--16).

SPD-S
7.

When the update is completed normally, the [START/STOP], [SAMPLE],

and [RESAMPLE] LEDs light up.

fig.up-3

Update Complate
If an error occurs during the procedure, all of the LEDs light up, and an
error message is displayed.
fig.up-4

Update ERROR 15
8.

Turn off the power to end the procedure.

19

SPD-S

Apr.2003

BLOCK DIAGRAM
fig.block

A +9
RIPPLE
FILTER

D +5
120
2
5

IN

14
12
15

PC410

D +5

2.2k

D +3 . 3

100k

D +3 . 3

NJM2360AM

2
4

D +5

10k

XRESET

HD74LS05FP

MIDI_IN
MIDI_OUT

3
2
220

ComapctFlash

for Program

for Patch,Wave Storage

16Mbit

8Mbit

D +5

GND

CD

NJM78L05UA

XRESET

4
5
0.1

Others Par ts
@40

DC-DC

CPU
V850E/MA1

DC IN
16bit

P1
P2
MXPAD
2

REGULATOR

P O W E R SW

RIM[1..10]

D +3 . 3

F S R Only
1

OUT

NJM2360AM

ANI[0..7]

PAD 1

NOR FLASH

for Cache/Work/Delay Line

VCC

NC

HD74LS05FP

30
40
50
60

HD74LS05FP

SDRAM

RESET IC
S-80927CLMC-G6X-T2

Others Par ts
@40

RT1P141C

D +3 . 3
2

A -9

220
24
22
25

D +3 . 3
DC-DC

D +5

MIDI
OUT

D +3 . 3

5
3
100

D +3 . 3

16bit

2
1
3

ACI or ACB
9V/1000mA

16bit

BUS BUFFERS

RIM1

UPD70F3107AGJ- UEN (SPD-S 1.01)

D +3 . 3

PAD 2
F S R Only

RIM2

16bit
D +3 . 3

D +3 . 3

PAD 3

8 b it

D +5

D +3 . 3

D +3 . 3

F S R Only
1

13

12

14 ANI2

D +3 . 3

w. FSR

12
1

ANI3

11.2896MHz(256fs)

RIM6

INPUT
L E V EL

8bit

LINE/MIC

4
fx=5MHz

BA10324AF

D +3 . 3

BA10324AF
2

ANI4

AD/DA
CODEC

RIM7

D +3 . 3

ANI5

MAIN BOARD

D +3 . 3

RIM9

D +3 . 3

10

10

VD

D +3 . 3

M5218AFP

RIM10
9
2

A +9
16

BA10324AF
D +3

XCOM
C
B
A

VDD

CD4053BCSJ

5
4
2
3
7
8
1

VEE

2
3
1

ANI6
8

M5218AFP

ANI7

XPDN

M5218AFP
A +9

3
6
5

LRCK
MCLK
BCLK
DEM1
DEMO
PDN

VCOM

LINE -10dBu
MIC -50dBu

6
5

M5218AFP

2
4
1

LINE IN
R
A

P H ONES
LEVEL
1

2
12

M5218AFP

2
3
1

P H ONES

1
15

16

14

6
22

M5218AFP

0.1

PHONES +15dBu

M5216FP

+
M5216FP

1/50

P1
P2
1

ROUT
10
11
12
7
6
13

14
9
10
11

LOUT
SDTO

D +3 . 3

R?
10k

D +3 . 3

EXP PEDAL

15

FOOT
SW
(1/2)

YCOM

14

D +3

ZCOM

VSS
INH

13
12

0Z
0Y
0X
1Z
1Y
1X

22

MXPAD

SW Matr ix
( RU B B E R )

PANEL SHEET
(PANEL BOARD)

D +5

12

LCD
16x1 Charactor

RT1N141C

11

BA10324AF

5
2
12
3
1
13

LINE IN
L(MONO)
A

RCM2122M-1A
/RCM2122M-A

2
4
1

M5218AFP

OUTPUT
L
(MONO)

LED Matrix

6
22

7
1

13

RIN

2
4
1

10

8
6

2
3
1

TRIG IN
(1/2)

SDTI

M5218AFP

23

2
3

3
LIN

VSS

M5218AFP

w.FSR

12

13

RIM8

VA

PAD9

+
M5218AFP

M5218AFP

24bit/512fs/GD=15.4

w.FSR

1
-

w. FSR

PAD8

clk=50MHz

13
11

BA10324AF

PAD7

RIM5

w. FSR

PAD6

128Mbit

D +3 . 3

11

ANI1

V850E GA

21

RIM4

21

10

LINE +4dBu
-

+
M5218AFP

23

PAD5

DSP

11

BA10324AF

Gate Array

for Preset,User Wave

System Parameter

13

w. FSR

NAND FLASH

21

ANI0

RIM3

23

D +3 . 3

BCK
MCK
LRCK
XP-LRCK

PAD4

LRCK0
LRCK1
MCK
BCK
SYI

2
4
1

OUTPUT
R
A

BA10324AF

V O LUME
D +3 . 3

20

2
2

E F FECTS
CONTROL

+
BA10324AF

PANEL SHEET
(VOLUME BOARD)

21

SPD-S

Apr.2003

CIRCUIT BOARD (MAIN)

fig.main-comp-slk

View from components side

22

23

SPD-S

Apr.2003

CIRCUIT BOARD (MAIN)

fig.main-foil-ptn

View from foil side

24

25

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 1/8)

fig.main1-c

IC2
UPD70F3107AGJ-UEN
UPD70F3107AGJ-UEN (SPD-S 1.00)
UPD703106AGJ-066-UEN (SPD-S)

RA1
47

RIM[1..10]

50
51
52
53
54
55
56
65
66
67

RIM1
RIM2
RIM3
RIM4
RIM5
RIM6
RIM7
RIM8
RIM9
RIM10

IP122/P36
IP121/P35
RXD2/IP120/P34
TXD2/IP133/P33
SCK2/IP132/P32
SI2/IP131/P31
SO2/IP130/P30
SCK1/P45
RXD1/SI1/P44
TXD1/SO1/P43

SW1A
D +3. 3
SSSS222-01-A
NIU
11
SI0
13
12 R256
10k
69
MIDI_IN
70 RXD0/SIO/P41
MIDI_OUT(SO0)
TXD0/SO0/P40
68

SCK0

RA5
47

RA8
47

R1 100k
R2 NIU

RA11
22

SCK0/P42

D +3 . 3
R257
10
71
C5
SLP@M
10/16

C6
0.1
72

ANI[0..7]

RA12
22

AVDD/AVREF

AVSS

CPU - V850E/MA1

ADTRG/IP123/P37

D
ANI7
ANI6
ANI5
ANI4
ANI3
ANI2
ANI1
ANI0

73
74
75
76
77
78
79
80

XDMARQ3

19
20
21
22
23
24
25
26

XDMARQ1
XDMARQ0
XPDN
'LCDCONT

R259 R246
10k
10k

D
AMUTE
CF_RESETZ
XDMAAK1
XDMAAK0
1
SS3
2
SS2
3
SS1
4
SS0

29
30
31
32
33
34
35
36
60

8
7
6
5
C16
22p

62

1
D

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

49

'CF_R/XB

83
84
85
86
87
88
89
90
91
92
93
94
95
96
97

FL_R/XB
FL_VPP
XFL_WP
CF_XATA/IDE
XCF_OEGAT E
CF_RESET
CF_XON/OFF
GA_CLK
XWAIT
XBCYST
XWAIT_EN
XWE
XRD
UDQM
LDQM/XLWR

100
101
102
103
104
105
106
107
108
109
110
111
114
115

61
C19
SLP@M
10/16

C20
0.1
64

22

59

SW1B
SSSS222-01-A
NIU

C21
100p

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

C17
NIU

CVDD

CVSS
RESET

5
6
7
8

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

134
124
112
98
81
37
47
27
8

R23
10k

5
6
7

EEP_SDA
EEP_SCK

VCC

SDA
SCL
WP

19
20
32
31
30
29
28
27
24
23
22
21

XSD_CS
XSD_RAS
XSD_CAS
XWE

18
17
16
15

UDQM
LDQM/XLWR

36
14

SD_CKE
SD_CLK

34
35

C1
NIU
VSS

BA
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

CS
RAS
CAS
WE
UDQM
LDQM

VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ

CKE
CLK

4
XFL_WP
CF_XATA/IDE 3
XCF_OEGAT E2
CF_RESET 1
8
GA_CLK
7
6
XBCYST
XWAIT_EN 5
4
XWE
3
XRD
2
UDQM
LDQM/XLWR 1
XDSP_CS
XCF_CS
XNF_CS
XGA_CS
XSD_CS
XFL_CS
XSD_RAS
XSD_CAS
SD_CLK
SD_CKE
EEP_SCK
EEP_SDA

8
7
6
5
4
3
2
1
4
3
2
1

9
10
11
12
13
14
15
16
5
6
7
8

R7
NIU
R8
NIU

C345
NIU

A22
A21

RA16
10k

BA2
BA1
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

RA17
10k

R11
R12 NIU
NIU
R13
R15 NIU
NIU

(B)
(A)
(B)
(A)

20
21
35
22
34
33
32
31
30
29
26
25
24
23

XSD_CS
XSD_RAS
XSD_CAS
XWE

19
18
17
16

UDQM
LDQM/XLWR

39
15

SD_CKE
SD_CLK

37
38

36
40

BA0(A13)
BA1(A12)
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
CS
RAS
CAS
WE
DQMU
DQML

CKE
CLK

SDRAM
64/128Mb

NC
NC

XDMARQ3
XDMARQ1
XDMARQ0
XDMAAK[0..1]

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

RA10
22

1
25

A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

D +3 . 3

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

C13
SLP@M
10/16
XRESET

26
50
C7 C8 C9 C10 C11 C12
1
1
1
1
1
1

NC
NC

47
26
XFL_CS
LDQM/XLWR11
28
XRD
14
XFL_WP
15
FL_R/XB
12
R4
0

(B)
(A)
IC3
IC5

16Mbit
NIU
NIU
Mounting
NIU

DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

64Mbit
NIU
0
NIU
Mounting

A-1/DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0

FLASH
8Mb

R10
10k D +3. 3

4
10
41
47

53
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2

16
17
48
1
2
3
4
5
6
7
8
18
19
20
21
22
23
24
25

D +3 . 3

7
13
38
44

C14
100p

A23
A22

XDMARQ3
XDMARQ1
XDMARQ0

XDMAAK1
XDMAAK0

RA4
10k

IC3
GLT5160L16 -7TC

D +3 . 3

C22 C23 C24 C25 C26 C27 C28 C29 C30

0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1

49
48
46
45
43
42
40
39
12
11
9
8
6
5
3
2

RA7
22

C31
SLP@M
10/16

VSSQ
VSSQ

NC/RFU
NC

D +3 . 3

RA3
10k
D

VSS
VSS

RA30
D +3. 3
10k
5
6
7
8
9
10
D
11
12
13 RA13
14 10k
15
16

D +3 . 3

IC1
HN58X2408FPI
NIU

D
A20
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1

D +3. 3

A2
A1
A0

37
33

R24
0
XRESET

3
2
1

SDRAM
VSSQ
16Mb VSSQ

XDSP_CS
XCF_CS
XNF_CS
'XCF_SC
XCF_DETECT
XGA_CS
XSD_CS
XFL_CS
XSD_RAS
XSD_CAS
SD_CLK
SD_CKE
EEP_SCK
EEP_SDA
FZ_VPP

X1

4
3
2
1

18
57
58

X2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

XRESET

9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16

D +3. 3
9
10
11
12
13 RA2
14 10k
15
16
9
10
11
12
13 RA6
14 10k
15
16
9
10
11
12
13 RA9
14 10k
15
16

8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1

D +3 . 3
VPP/MODE2
MODE1
MODE0

D +3 . 3

D +3 . 3

21
23

PCS7/CS7
PCS6/CS6/RAS6
PCS5/CS5/IORD
PCS4/CS4/RAS4
RA15
PCS3/CS3/RAS3
22
PCS2/CS2/IOWR
PCS1/CS1/RAS1
PCS0/CS0
R19 47 PCD3/UBE/SDRAS
R20 47 PCD2/LBE/SDCAS
PCD1/SDCLK
R21 47
PCD0/SDCKE
R22 47
R5 NIU
PAH9/A25
R6 NIU
PAH8/A24

8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1

C18
22p
63

XFZ_RST

DMAAK3/PBD3
DMAAK2/PBD2
DMAAK1/PBD1
DMAAK0/PBD0
TO01/P13
IP011/P12
RA46
TIO10/IP010/P11 47
PWM1/P10
CKSEL

P52/TO03
P51/IP031
P50/IP030/TI030
PCM5/SELFREF
PCM4/REFRQ
PCM3/HLDRQ
PCM2/HLDAK
R9
47 PCM1/CLKO/BUSCL
PCM0/WAIT
PCT7/BCYST
R244 47
PCT6/OE
PCT5/WE
PCT4/RD
RA14
PCT1/UCS/UW/UDQ
22
PCT0/LCS/LW/LDQ

D
2

X1
SD3@
5MHz

R255
NIU

DRQ3/IP103/P07
DRQ2/IP102/P06
DRQ1/IP101/P05
DRQ0/IP100/P04
TO00/P03
IP001/P02
TIO00/IP000/P01 R17 100
PWM0/P00
R18 1.5k

C325 R245 D +3. 3

33p 10k

C15
1

Trigger Section

P77/ANI7
P76/ANI6
P75/ANI5
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0

144
1
2
3
4
5
6
7
10
11
12
13
14
15
16
17

A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

9
28
48
38
82
99
113
125
135

RING/XRIM
MXPAD

PDL15/D15
D14/PDL14
D13/PDL13
D12/PDL12
D11/PDL11
D10/PDL10
D9/PDL9
D8/PDL8
D7/PDL7
D6/PDL6
D5/PDL5
D4/PDL4
D3/PDL3
D2/PDL2
D1/PDL1
D0/PDL0

A23
A22
A21
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

LDQM/XLWR
XRD
XGA_CS
XNF_CS
XCF_CS
XDSP_CS
GA_CLK
XWAIT_EN
XWAIT

BYTE
CE
WE
OE
WP
RY/BY
RP

VPP
VCC

45
43
41
39
36
34
32
30
44
42
40
38
35
33
31
29

9
10

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

GA&DSP Section

A[1..11]
D[0..15]
CF_XATA/IDE
XCF_OEGATE
XCF_CS
XRD
LDQM/XLWR
XBCYST

D +3 . 3
D

D +3 . 3
2

PAH7/A23
PAH6/A22
PAH5/A21
PAH4/A20
PAH3/A19
PAH2/A18
PAH1/A17
PAH0/A16
PAL15/A15
PAL14/A14
PAL13/A13
PAL12/A12
PAL11/A11
PAL10/A10
PAL9/A9
PAL8/A8
PAL7/A7
PAL6/A6
PAL5/A5
PAL4/A4
PAL3/A3
PAL2/A2
PAL1/A1
PAL0/A0

9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16
9
10
11
12
13
14
15
16

16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9

TC3/IP113/P27
TC2/IP112/P26
TC1/IP111/P25
TC0/IP110/P24
TO02/P23
IP021/P22
TIO20/IP020/P21
NMI/P20

8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1

D[0..15]
A13

13
37

'CF_R/XB
'XCF_SC
Q1
RN2421
1 FL_VPP

CF_XON/OFF
CF_RESET
CF_RESETZ
XCF_DETECT
CF I/F Section

P[1..2]

116
117
118
119
120
121
122
123
126
127
128
129
130
131
132
133
136
137
138
139
140
141
142
143

A[0..9]

D[0..15]

1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8

39
40
41
42
43
44
45
46

SD4
SD3
SD2
SD1
SD0
P2
P1

(Trial)
(1Lot-1.99Lot)
(2Lot-)

A[0..9]

GND
GND

IC4
LH28F800BJE-PBTL90@
(LH28F160BJE)
(LH28F320BFE)

27
46
D
C2
C4
0.1
0.1
C3
SLP@M
10/16

XPDN
AMUTE

R3
10k

Audio Section

MIDI_IN
MIDI_OUT(SO0)

128Mbit
0
NIU
NIU
Mounting

Jack Section

SS[0..3]
SS3
SS2
SS1
SS0

SD[0..4]

SD4
SD3
SD2
SD1
SD0
'LCDCONT
CN Section

D +3 . 3
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS

IC5
(M2V64S40DTP-7)
(TC59SM716AFT-8 0)
NIU

1
14
27
3
49
9
43
12
46
6
52
28
41
54
D

CPU FLASH WRITER

7
6
5
4
3
2
1

7
6
5
4
3
2
1

CN1
B7B-PH-K-S
NIU

D +3. 3
FZ_VPP

XFZ_RST
SCK0
SI0
MIDI_OUT(SO0)
D

C322
WLP@M
NIU
D

Under Development Only

*SW1 SSSS222-01-A
*CN1 IL-S-7P-S2T2-EF
*C322 100u
*R255 10k
*C17 0.1u
*R1,R24 Pattern cut

26

27

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 2/8)

fig.main2-c

A[0..9]

D +3. 3

C32
SLP@M
C34 10/16
0.1
C36
0.1
C38
0.1
C40
0.1

D[0..15]

8
7
6
5

100
100
100

MCK
BCK
LRCK

102
103
104
C326
22p

GA_CLK

32
GA_CLK
110
111

XWAIT_EN
XWAIT
RA20
100

CPU Section

WAIT-CA
WAIT-CB-XP-WAIT

CPU-WCK
PHAI

PLL-SEND
PLL-RTRN
PLL-LOCK
S2
D+5V I/F
S1

ENC-A
ENC-B

LD6
LD5
LD4
LD3
LD2
LD1
LD0

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

123
122
121
120
119
118
117
116

XLS3
XLS2
XLS1
XLS0

4
3
2
1

5
6
7
8

105
115
114
113
112

TEST
NC
NC
NC

7SEG-D7
7SEG-D6
7SEG-D5
7SEG-D4
7SEG-D3
7SEG-D2
7SEG-D1
7SEG-D0
7SEG-COM4
7SEG-COM3
7SEG-COM2
7SEG-COM1
7SEG-COM0

RA22
100
XRESET

33
XRESET

LCD-D7
D+5V I/F LCD-D6
LCD-D5
LCD-D4
LCD-D3
LCD-D2
LCD-D1
LCD-D0
R51
NIU LCD-E
R52
100 LCD-RW
R53
100 LCD-RS
RESET-CTRL
LCD-POWER-UD

RESET

WAIT-OUT
CD-DETECT

R54
0
C48
100p
D

54

D +5

C256
0.1

42
43

D +5

IC6
LC24085B-SD1

41
40
39
50
51
53
25
42

XDMARQ3
XRD
XDSP_CS
LDQM/XLWR

1
47
48

5XCF_WAIT 4

41
57
38
40
39

XRESET
2
'XCF_WAIT
IC37
SN74AHCT1G08DCKR

R43

C42
0.1

R49
100

D
LDG

97
106
107
143
60
61
62
63
64
65
66
67
68
69
70
58
59

8
7
6
5
4
3
2
1

125
129

18
37
73
90
109
126
144

RA21
100
9
10
11
12
13
14
15
16

XNF_RE
XNF_WE

7
17
16
19
9
8
18

LD6
LD5
LD4
LD3
LD2
LD1
LD0
LDG

NAND
FLASH
128Mb

R/B
ALE
CLE
WP
CE
RE
WE

XLS[0..3]
XLS3
XLS2
XLS1
XLS0

D +3. 3
VCC
VCC
GND
VSS
VSS

IC13
TC58128AFT

12
37
C68
SLP@M
10/16

6
36
13
D
C254 C67
0.1
0.1

LD[0..6]

LDG
LCD[0..7]

LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
LE
R/XW
RS
CN Section

'XCF_WAIT
XCF_DETECT

XTO

R44
15

SYI
6

XTI
INT1
INT0
DRQ
RD
CS
WR
RST
DRST

C45
18p

X2
SD3@
11.2896MHz
(256fs)

CF I/F Section

R46
1M

C46
18p

IC7
TC220C120AF-006(MR3)

D +5
D

C43
SLP@M
10/16

NF_R/XB
NF_ALE
NF_CLE
XNF_WP
XNF_CE

48
47
46
45
40
39
38
35
34
33
28
27
26
25
24
23
22

1
3

OSC
OSCSEL

100

D +3. 3

C41
3900p

R258 100

DIV
DIVS1
DIVS0

D R37
27k

16
17
18
19
20

PLLVAA
PLLRO
PLLLP
PLLAGS
PLLAGD

LRCK0
AD1
DA1
AD0
AD2
DA0

R48
0
C47
100p

R50
10k
LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
LE
R/XW
RS

RA47
10k

XGA_WAIT
XCF_DETECT

D +3. 3
C324
0.1

L46

+
D +3. 3

C58
SLP@M
10/16

XGA_WAIT

9
8
7
6
5
4
3
2

XWAIT_EN
GA_CLK

1
11

C51 C52 C53 C54 C55 C56 C57

0.1 0.1 0.1 0.1 0.1 0.1 0.1

D7
D6
D5
D4
D3
D2
D1
D0
OE
CK

10

C50
0.1

TESTT
TESTS
TESTB
TESTP
PLLBP

1
19
36
55
72
91
108
127

C49
SLP@M
10/16

VDD

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

D +5

VDD
VDD
VDD
VDD
VDD
VDD
VDD

78
32
77
13
10

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

124

AR-SYNC-WCK
WCK-IN
INT-OUT

72

CTYPE

MCK
BCK
LRCK1

1
2
3
4
5
10
D +3 . 3 11
14
15
20
R55
21
1.5k

I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1

16
15
14
13
12
11
10
9

138

MR3

CD7
CD6
CD5
CD4
CD3
CD2
CD1
CD0

D
76

44
43
42
41
32
31
30
29

1
2
3
4
5
6
7
8

XRD
XDSP_CS
LDQM/XLWR

CPU-WR
CPU-RD
CPU-CS
XP-CS-IN
SM-CS-IN
CD-CS

C327
33p

46
45
44
49
56
51
50
52
53

C257
0.1
D

20

XDSP_CS

SPRX-SD
SPRX-BCK
SPRX-LRCK
XP-LRCK
XP-CLK
XP-SCK
XP-WCK
XP-SD-AR-TRG
XP-WR-AR-TRG

55
9
8

512fs

VCC

27
28
29
30
31
128

LDQM/XLWR
XRD
XGA_CS

DMA-ACK2
DMA-ACK1
DMA-ACK0

SDTO
SDTI

92
93

74
75
69

DA3
AD3
DA2

Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0

12
13
14
15
16
17
18
19

XSFT_WAIT

C316
0.1
4

2
IC54
SN74AHC1G08DCKR
D
XWAIT

GND

XDMAAK1 (AD)
XDMAAK0 (DA)

XTAL
EXTAL

62
68
67
58
70
57

137
136
135

DMA-REQ2
DMA-REQ1
DMA-REQ0

101
100
99
98

XDMAAK[0..1]

XNF_CS
XCF_CS

DAOUT1
ADIN1
DAOUT0
ADIN0

1
2
3
4
134
133
132

(AD)
(DA)

XDMARQ1
XDMARQ0

65
60
63

MCK
BCK
LRCK

RA19
10k
(DSP)

NF_D7
NF_D6
NF_D5
NF_D4
NF_D3
NF_D2
NF_D1
NF_D0

27
28
29
30
34
35
36
37

D7
D6
D5
D4
D3
D2
D1
D0

CA4
CA3
CA2
CA1
CA0

R28
R30
R32

86
88
94
95
89
87
85
84

44
45
46
47
48

NF_D7
NF_D6
NF_D5
NF_D4
NF_D3
NF_D2
NF_D1
NF_D0

SM-D7
SM-D6
SM-D5
SM-D4
SM-D3
SM-D2
SM-D1
SM-D0

A4
A3
A2
A1
A0

NF_R/XB
NF_CLE
XNF_CE
NF_ALE
XNF_RE
XNF_WE
XNF_WP

SDTO
Audio Section

V850E GA

96
76
82
77
78
79
80
81
83

LRCK
MCK
BCK

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

D +3. 3

XDMARQ3

7
14
15
23
24
33
38
49
56
59
64
73
79

SDTI

2
4
11
12
21
22
26
31
43
52
54
61
66
71
80

15
14
13
12
11
10
9
8
7
6
5
4
142
141
140
139

R25 RA18
10k 10k
D +3. 3

D +3 . 3
SW
PROTECT
R/B
CLE
CE
ALE
RE
WE
WP

D
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

2
3
34
35
71
74
75

VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD

NC
NC
NC
NC
NC
NC
NC

5
6
7
8

A13

A19
A18
A9
A8
A7
A6
A5
A4
A3
A2
A1

4
3
2
1

A13

131
A13 130
A9 26
A8 25
A7 24
A6 23
A5 22
A4 21
A3 20
A2 17
A1 16

C33
0.1
C35
0.1
C37
0.1
C39
0.1

IC39
74LV574PW
D
XGA_WAIT

28

29

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 3/8)

fig.main3-c

D +3 . 3

L36

1
19

DIR
OE

10

XCF_G1

A1
A2
A3
A4
A5
A6
A7
A8

VCC

2
3
4
5
6
7
8
9

A10
A9
A8
A7
A6
A5
A4
A3

18
17
16
15
14
13
12
11

1
2
3
4
5
6
7
8

L37

'CF_R/XB
'XCF_SC

1
19

XCF_G1

A8
A7
A6
A5
A4
A3
A2
A1
DIR
OE

10

CF_XON/OFF
CF_RESET
CF_RESETZ
XCF_DETECT

9
8
7
6
5
4
3
2

VCC

A2
A1

CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3

IC40
D SN74LV245APWR
C261
0.1
D
B8
B7
B6
B5
B4
B3
B2
B1

11
12
13
14
15
16
17
18

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

CF_A2
CF_A1
CF_A0
4
3
2
1

'XCF_WAIT
'XCF_SC
'CF_R/XB

XCF_DETECT
'XCF_WAIT
D +3 . 3

XCF_CS

XCF_CS

1
19

D +3 . 3

R265
22

CF_XATA/IDE
XCF_OEGATE

XRD

DIR
OE

10

XCF_G1

VCC

LDQM/XLWR

A8
A7
A6
A5
A4
A3
A2
A1

CF_R/XB 4
XCF_SC 3
XCF_WAIT 2
XCF_DASP 1

D +C F
5
6
RA37
7
10k
8

XCF_REG 8
XCF_IOWR 7
XCF_WE 6
XCF_IORD 5
XCF_CE2 4
XCF_CE1 3
2
1

D +C F
9
10
11
12
13 RA39
14 10k
15
16

CF Accsess Chart

C275
0.1
D

20

L38

B8
B7
B6
B5
B4
B3
B2
B1

11
12
13
14
15
16
17
18

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

XCF_REG
XCF_IOWR
XCF_WE
XCF_IORD
XCF_CE2
XCF_CE1

PC Card ATA
Memory Mode
Attribute Memory Area (w. external Wait)
Attribute Memory Area (w. internal Wait)
Common Memory Area (w. external Wait)
Common Memory Area (w. internal Wait)

CF_XATA/IDE
0
0
0
0

A13
0
1
0
1

A12
0
0
0
0

A11
0
0
1
1

RA38
22

GND

9
8
7
6
5
4
3
2

A11

IC45
D SN74LV245APWR

C277
100p
C279
100p
C281
100p
C284
100p
C286
100p

XCF_OE

3 2

C283
0.1

IC46A
SN74LVC2G02DCTR

C276
100p
C278
100p
C280
100p
C282
100p
C285
100p
C287
100p

XCF_CE2
XCF_CE1
XCF_OE
XCF_WE
XCF_IORD
XCF_IOWR
XCF_REG
CF_R/XB
XCF_DASP
XCF_SC
XCF_WAIT

CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0

8
10
11
12
14
15
16
17
18
19
20

XCF_CE2
XCF_CE1
XCF_OE
XCF_WE
XCF_IORD
XCF_IOWR
XCF_REG
CF_R/XB
XCF_DASP
XCF_SC
XCF_WAIT

32
7
9
36
34
35
44
37
45
46
42
39

IC46B
SN74LVC2G02DCTR

CF_A10
CF_A9
CF_A8
CF_A7
CF_A6
CF_A5
CF_A4
CF_A3
CF_A2
CF_A1
CF_A0
D

CF_R/XB
XCF_SC
XCF_WAIT

GA&DSP Section

D +3 . 3
5
6
RA36
7
8
10k

C262
100p
C264
100p
C266
100p
C268
100p
C270
100p
C272
100p

IC42
D SN74LV245APWR

'CF_R/XB
'XCF_SC
'XCF_WAIT

CPU Section

C263
100p
C265
100p
C267
100p
C269
100p
C271
100p

RA35
22

GND

CF_XATA/IDE
XCF_OEGAT E
XCF_CS
XRD
LDQM/XLWR
XBCYST

D
D
IC46C
SN74LVC2G02DCTR

14
14

IC50B
SN74LV02APWR

R266
47

20
DIR
OE

10
D +3 . 3

14

D +3 . 3
D +3. 3

D +3. 3

9
11

9
10

LDQM/XLWR 8
D

IC50C
SN74LV02APWR

1313
Q

9 12

11
12

IC50D
SN74LV02APWR

CK
Q

R267
100

IC48B
SN74LV74APWR

IC51D
SN74LV32APWR
XCF_G1

CF_AB/XBA
XCF_G2

11
12
13
14
15
16
17
18

8
7
6
5
4
3
2
1

9
8
7
6
5
4
3
2
1
19

A8
A7
A6
A5
A4
A3
A2
A1
DIR
OE

CF_D10
CF_D9
CF_D2
CF_D8
CF_D1
CF_D0
CF_D7
CF_D15

CF_D10
CF_D9
CF_D2
CF_D8
CF_D1
CF_D0
CF_D7
CF_D15

8
7
6
5
4
3
2
1

D +C F
9
10
11
12
13 RA42
14 10k
15
16

RA41
22

11
12
13
14
15
16
17
18

8
7
6
5
4
3
2
1

9
10
11
12
13
14
15
16

R247
100k
5

IC51A
SN74LV32APWR

CF_D14
CF_D6
CF_D13
CF_D5
CF_D12
CF_D4
CF_D11
CF_D3

CF_D14
CF_D6
CF_D13
CF_D5
CF_D12
CF_D4
CF_D11
CF_D3

8
7
6
5
4
3
2
1

D +C F
9
10
11
12
13 RA45
14 10k
15
16

XCD225

XCF_DETECT

XCD126

IC51B
C309
SN74LV32APWR
22p

C310
22p

24
33
40
43

IC52
D SN74LV245APWR

D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0

CD2
CD1
WP/IOIS16/IOIS16
VS1
VS2
INPACK

D +C F

RA44
22

13
38
Q29
D +3 . 3
XP132A1275SR
3
D1
2 S3
D2
1 S2
S1
D4
D3
R251
100k
CF_XON/OFF

C328
0.1

D +C F
5
6
8
7

CF_RESET
C312
SLP@M
10/16

R252
100k

L41
FBM-11-201209-601A20T

30

R249
R248 220
100k R250
220

C308
0.1
D

31
30
29
28
27
49
48
47
6
5
4
3
2
23
22
21

D +3. 3

B8
B7
B6
B5
B4
B3
B2
B1

CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0

XCF_G1 3

IC49
D SN74LV245APWR

20
9
10
11
12
13
14
15
16

9
10
11
12
13
14
15
16

G1

XBCYST

11

XCF_CS

13

IC51E
SN74LV32APWR
7

D IC51C
SN74LV32APWR

12

PR

10

C311
0.1

8
7
6
5
4
3
2
1

VCC

D14
D6
D13
D5
D12
D4
D11
D3

B8
B7
B6
B5
B4
B3
B2
B1

L40

RA43
47

GND

IC50E
SN74LV02APWR
D

1
19

CF_AB/XBA
XCF_G2

IC48A
SN74LV74APWR

A8
A7
A6
A5
A4
A3
A2
A1

XBCYST

D IC50A
SN74LV02APWR

10

9
8
7
6
5
4
3
2

10

9
10
11
12
13
14
15
16

CF_D15
CF_D14
CF_D13
CF_D12
CF_D11
CF_D10
CF_D9
CF_D8
CF_D7
CF_D6
CF_D5
CF_D4
CF_D3
CF_D2
CF_D1
CF_D0

D +C F
5

CK
R

XRD

8
7
6
5
4
3
2
1

C292
0.1
D

C288
100p
C290
100p
C293
100p
C297
100p
C299
100p
C301
100p
C303
100p
C305
100p

CF_RESETZ
1
3

4
3

PR

2
5

D10
D9
D2
D8
D1
D0
D7
D15

VCC

GND

D +3 . 3

D +3 . 3

XCF_CS

C307
0.1

L39

RA40
47

GND

VCC

D +3 . 3

IC48C
D
SN74LV74APWR

C289
100p
C291
100p
C296
100p
C298
100p
C300
100p
C302
100p
C304
100p
C306
100p

XCF_OEGATE

D +3 . 3

CE2/CE2/CS1
CE1/CE1/CS0
OE/OE/ATASEL
WE
IORD
IOWR
REG
RDYBSY/IREQ/INTRQ
BVD2/SPKR/DASP
BVD1/STSCHG/PDIAG
WAIT/WAIT/IORDY
CSEL

CF_D[0..15]

D +3. 3

C295
0.1

A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0

CompactFlash

CF_XATA/IDE
XCF_OEGAT E
XCF_CS
XRD
LDQM/XLWR
XBCYST

16
15
14
13
12
11
10
9
RA31
22

20

D +3 . 3

B1
B2
B3
B4
B5
B6
B7
B8

GND

D[0..15]

CF_A[0..10]

C259
0.1
D

20

A[1..11]

D
IC55
SN74AHC1G125DCKR

C313
SLP@M
10/16

1
50

D
41
'CF_RESET
C314 C315
0.1
0.1
C321
NIU

VCC
VCC

GND
GND

CNGND2
CNGND1

70
60

RESET/RESET/RESET
CN9
ICM-MA2H-SS52-R21A

D
D
R268 R269
NIU
NIU

31

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 4/8)

fig.main4-c

DA48
DAN202U

R70
4.7k
A

13

C78
10p

R78
220

C81
WLP@M
100/16

+
IC16B
M5218AFP
D +3. 3

C79
10p
7

VR1B
RK09K12A@
10kAx2

C77
WLP@M
100/16

R76
390

C332
100p

+
IC17B
M5218AFP

32

SW2C
SSSF141300

R71
NIU
43
41

R72
10k
42
A

SW2D
SSSF141300

R77
220k
33
31

A -9
DA4
DAP202U
C82
WLP@M
100/16

R79
470

IN_R
C333
0.1

SW2E
SSSF141300

10

20

R264
10

C76
WLP@M
100/16

R69
470

A +9
3

D
R263
10

DA3
DAN202U

R80
4.7k

IN_L

LINE -8.32dBu (+1.68dB)

MIC -8.31dBu (+41.69dB)

R75
47k

C331
100p

12

SW2A
SSSF141300

3
+
IC17A
M5218AFP

12

C80
WLP@M
100/16

R74
47k

C330
100p

VR1A
RK09K12A@
10kAx2

D
R73
47k

INPUT
VR
23

LINE/MIC -2.30dBu (+6.02dB)

C73
10p

DA49
DAP202U
3

3
+
IC16A
M5218AFP

D +3. 3
3

C75
WLP@M
100/16

C329
100p

R67
220k
13
11

R66
390

R68
220

C71
WLP@M
100/16

R65
47k

20

C72
10p

22

C74
WLP@M
100/16

R64
47k

R81
NIU
23
21

10

R63
47k

R82
10k
22
A

SW2B
SSSF141300

+4.89dBu (+6.02dB)

16

ROUT

SDTI

SDTO

LRCK
MCLK
BCLK
DEM1
DEMO
PDN

VCOM

IC20
AK4552VT
D

C92
1000p

14

C95
0.1

C101
WLP@M
100/16

R101
4.7k

C100
NIU

R105
27k

SDTO
C96
WLP@M
2.2/50

GA&DSP Section

C102
1000p

R92
4.7k

Q2
RN1441

C87
100p
1

PHONES_L

+
R93
100k

IC18A
M5216FP

R88
RCT20@J
47 (1/2W)

C88
WLP@M
NIU

PHONES +15dBu Max

(+10.10dB)

13
A R95
10k

C98
WLP@M
100/16

C99
WLP@M
100/16

IC19B
M5218AFP

R260
1k

23

R98
10k

3
VR2A
RK09K12A@
10kAx2

C93
1000p

C336
A 100p
R102
8.2k

PHONES
VR

IC19A
M5218AFP

R97
10k

LIN

R94
27k

22

4
VA

DAC -1.13dBu typ.

CODEC

C335
100p

R96
22k
6

C337
100p

10
11
12
7
6
13

LRCK
MCK
BCK

LOUT

C90
WLP@M
100/16

VR2B
RK09K12A@
10kAx2

C103
1000p

R261
1k

1
Q3
RN1441

R103
4.7k
A

SDTI

15

R90
4.7k

C89
WLP@M
100/16

R84
22k

12

C91
WLP@M
100/16

C334
A 100p
R91
8.2k

A R83
10k

R87
10k

C94
100p
7

R99
RCT20@J
47 (1/2W)

C97
WLP@M
NIU

PHONES_R

+
IC18B
M5216FP

R104
100k

A
A

20

D +3. 3
2

VSS

ADC -0.64dBu typ.

RIN

R86
10k

C86
WLP@M
100/16
D

VD

C85
0.1

10

C84 R85
0.1
NIU

C83
WLP@M
100/16

R109
470

R110
27k

R111
27k

C106
SLP@M
10/16

1
R112
10k

Q4
RN1441

Q5
2SA1037KR

R114
27k

Q6
2SC3052

OUT_L
R108
10k

R113
10k

XPDN
AMUTE

R107
470

RETURN_L

C105
WLP@M
100/16
A

CPU Section

SEND_L

R106
470
3

C104
WLP@M
100/16

DA7
DA204U
2

ADP V

C107
WLP@M
100/16

R115
27k

R117
470

RETURN_R

OUT_R
3

SEND_R

R116
470

A -9

R118
10k

Q7
RN1441

Jack Section

CN Section

A -9

32

IC17C
M5218AFP

A
C114
0.1

A -9

IC16C
M5218AFP

A
C115
0.1

A -9

C111
0.1

MUTE

C112
0.1

IC19C
M5218AFP

A
C116
0.1

A -9

+
IC18C
M5216FP

A +9

C110
0.1

A
C113
WLP@M
100/16

C109
0.1

A +9

C108
WLP@M
100/16

A +9

A +9

A +9

A
C117
0.1

D C348
NIU

D C349
NIU

A -9

33

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 5/8)

fig.main5-c

'RIM[1..9]

C131
0.01

DA16
DA204U

'PAD6
C145
1000p

R151
100k

C144
0.01

10

DA17
DA204U

C142
0.47

R148
NIU

D
D +3. 3
3

IC21C
BA10324AF

DA20
DAN202U

D
DA22
DA204U
2

R153
68k
1
R158
120k

C147
10p
13

'PAD7
C152
1000p

R159
100k

C151
0.01

12

14

4
11
+
IC25C
M5218AFP

A -9

13
C149
0.047

D +3 . 3
3

DA25
DAP202U
NIU
3

C135
0.1

C136
WLP@M
100/16

D
C138
0.1

D
C139
WLP@M
100/16

A -9

A -9

6 RIM4
4

IC23B
D SN74LV14APWR

12 RIM5

D +3 . 3

D +3. 3

C153
0.1

D
10 RIM6

IC26E
SN74LV14APWR

C155
0.047

R163
NIU

IC23A
D SN74LV14APWR

IC26F
SN74LV14APWR

11

3
1

D
C137
0.1

DA26
DA204U
R161
68k

A +9

+
IC24C
M5218AFP

IC23C
SN74LV14APWR

DA24
D DAN202U
NIU

R160
12k
R162
390k

A +9

IC21D
BA10324AF

A -9

A +9

ANI3
R156
NIU

A -9

C134
0.1

C148
0.47

D
C127
0.1

IC23D
SN74LV14APWR

D
2

11

D +3 . 3
3

8 RIM3

R155
NIU

2
DA23
DA204U

9
DA19
DAP202U
NIU
3

C146
0.047

+
IC22E
BA10324AF

C150
0.22

R157
NIU

R152
12k
R154
390k

10 RIM2

C140
0.047

D
C126
0.1

IC23E
SN74LV14APWR

C132
0.047

DA18
D DAN202U
NIU

DA21
DAP202U
NIU
3

C141
10p

R150
120k

ANI2

C143
0.22

R149
NIU

R147
NIU

R144
12k
R146
390k

IC21E
BA10324AF

R145
68k

RA26
EXB2HVJV@
1k
R136
1k
R137
100k
R139
1k
R140
1k

D
2

DA13
D DAN202U
NIU

IC23F
SN74LV14APWR

11

RA48
10k

IC21B
BA10324AF

DA14
DAP202U
NIU
3

R143
100k

R138
NIU

D +3 . 3
3

14

C133
1000p

C129
0.47

C125
0.047

C123
0.1

C154
0.1
IC26G
SN74LV14APWR
D

'PAD5

DA15
DA204U

C122
0.1

12 RIM1

C128
10p

ANI1

13

R142
120k

R135
NIU

C130
0.22

16
15
14
13
12
11
10
9

14

R132
12k
R134
390k

D
1
2
3
4
5
6
7
8

R133
68k

D
8
7
6
5
16
15
14
13
12
11
10
9

DA10
DAN202U

DA12
DA204U

'RIM1 1
'RIM2 2
'RIM3 3
4
'RIM4 1
'RIM5 2
'RIM6 3
'RIM7 4
'RIM8 5
'RIM9 6
7
8
RING
'P1
'P2

D +3. 3
3

D
2

R141
NIU

A +9

R128
100k

IC21A
BA10324AF

A +9
R124 R125 R126 R127
100k 5.6k 5.6k 270k

RA49
10k

C346
0.1
DA11
DAP202U
NIU
3

R123
NIU

C121
0.01

C119
0.47

R131
100k

DA9
DA204U

C124
1000p

1 RING/XRIM
Q8
RT1P141C

D +3. 3

9
10
11
12
13
14
15
16

C118
10p

R130
120k

D +3. 3

ANI0

C120
0.22

D +3. 3

R129
NIU
'PAD4

C347
RA25
+
EXB2HVJV@0.1 D 3. 3
100k

R122
NIU

R119
12k
R121
390k

CN Section

R120
68k

8
7
6
5
4
3
2
1

'CTRLVR

DA8
DA204U

'PAD[4..9]

IC23G
SN74LV14APWR
D

ANI4
D

DA28
DAN202U

DA32
DA204U

1
C163
10p

+
IC25B
M5218AFP

C172
0.22

R184
120k

C170
10p
9

TIP
RING
'PEDAL

C175
NIU

R185
100k

C173
0.01

R183
NIU

10

DA37
DA204U

R180
NIU

C171
0.47

R181
NIU

IC27
CD4053BCSJ
5
PEDAL 3
2
CTRLVR 1
12
13
9
10
11
6

IC22C
BA10324AF

D
DA41
DA204U
2

3
1

C180
0.22

R196
120k

C178
10p
13

C182
NIU

R197
100k

C181
0.01

12

RING
D

R191
NIU

DA42
DA204U

14

C179
0.47

R193
NIU

15
14

1
R182
NIU

IC24B
M5218AFP

C176
NIU
R192
0
D

R194
NIU

R179
100

C338
100p

R195
NIU

R187
12k
R190
390k

YCOM

C339
100p

ANI6

D +3. 3
3
DA38
DAN202U

7
R188
NIU

DA39
DAP202U
3

ANI7

RIM[1..10]
P[1..2]

MXPAD

D
7
IC22B
BA10324AF

C341
100p

3
C185
0.1

DA45
DA204U

R202
100

RING/XRIM

Q10
RT1N141C

2
6

ANI[0..7]

3
C184
0.1

'CTRLVR

1
5

DA44
DAP202U
3

CPU Section
C183
1000p

D +3 . 3
3

DA43
D DAN202U

A -9

A +9

C340
100p

R201
1k

P1
C177
1000p

D +3 . 3
2

R186
100

R198
10k

R199
100k

DA40
DA204U

2 RIM10

IC26A
SN74LV14APWR

P2
IC22D
BA10324AF

D +3. 3

D +3 . 3
2

4 RIM9

IC26B
SN74LV14APWR

1
C174
1000p

D +3 . 3
3

DA36
DAP202U
NIU
3

DA35
D DAN202U
NIU

R189
68k

C
B
A
INH

ZCOM

XCOM

Jack Section

0Z
1Z
0Y
1Y
0X
1X

C169
0.1
D

C168
0.047

1
'P1
'P2

A +9

R176
12k
R178
390k

VDD

VSS

2
R177
68k

IC24A
M5218AFP

DA34
DA204U

R172
NIU

C166
0.01

C164
0.47

R175
100k

DA33
DA204U

C167
1000p

6 RIM8

IC26C
SN74LV14APWR

C162
0.047

R174
120k

5
ANI5

C165
0.22

8 RIM7

IC26D
SN74LV14APWR

R171
NIU

R173
NIU

R168
12k
R170
390k

D +3 . 3
3

DA31
DAP202U
NIU
3

DA30
D DAN202U
NIU

2
R169
68k

9
C161
0.047

D +3. 3
3

IC25A
M5218AFP

'PAD9

16

C159
0.01

DA29
DAP202U
NIU
3

VEE

R167
100k

R164
NIU

C160
1000p

C157
0.47

'PAD8

DA27
DA204U

C156
10p

R166
120k

C158
0.22

R165
NIU

1
IC22A
BA10324AF

34

35

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 6/8)

fig.main6-c

LINE IN
L(MONO)
L2

MIDI IN/OUT

DA46
DAN202U
2

2
4

R204
120

D +5

C186
1000p

R203
2.2k

L4

1
5

L6

LINE -10dBu
MIC -50dBu

LINE IN
R

D
L7
D +5

R207
220

L8

JK2
HTJ-064-10I

IC28
PC410KT

R205
100
R206
220

L5

L3
NIU

MIDI_IN

2
4
1

IN_R
Q11
RT1P141C
1
2

R208
0

C189
1000p

XRESET
C191
100p

IC29A
SN74LS05NSR

30
40
50
60

23
25
22
24
21
29
20
13
15
12
14
11
19
10

C188
0.1

D +5

IN
OUT

JK1
HDC-052A-12

OUT
IN

2
4
1

IN_L

D +5

L9
NIU
A

JK3
HTJ-064-10I
A

D
R209
10k
4

12

13

PHONES

L10

MIDI_OUT(SO0)

2
3
1

PHONES_L
IC29B
IC29F
SN74LS05NSR SN74LS05NSR
D +5
IC29E
10
SN74LS05NSR
IC29C
6
SN74LS05NSR
IC29D
8
SN74LS05NSR

C192
1000p

L11
NIU

JK4
HTJ-064-10D

14

11

CPU Section

C194
0.1

PHONES +15dBu

C343
0.1

D IC29G
SN74LS05NSR
L12

TRIGGER INPUT
L13
L14
2
3
1

TIP
RING

C196
NIU

C197
NIU

D +3. 3

2
3
1

'PEDAL

L20
NIU

C201
NIU

2
4
1

OUT_L
C199
1000p

L17
NIU
A

JK5
HTJ-064-10I
A

LINE +4dBu

OUTPUT
R

'P1
'P2
Trigger Section
L25
NIU

2
4
1

OUT_R

L23
L24

36

L16
Q13
RT1N141C

L21

JK9
HTJ-064-04A

C205
NIU

C206
NIU

OUTPUT
L(MONO)

C202
NIU

FOOT SW
5
4
2
3
7
8
1

R210
4.7k
1

L18
L19

EXP PEDAL

C344
0.1

D +3. 3

C195
1000p

Q12
RT1P141C

JK8
HTJ-064-10D

C198
0.1

JK7
HTJ-064-10D

L15
NIU

PHONES_R

Audio Section

C203
1000p

L22
NIU
A

JK6
HTJ-064-10I
A

37

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 7/8)

fig.main7-c

RA27
100

SS2

IC53B
SN74AHCT08PWR
1
3
2

5
6
7
8

D
D
D
D
C207
C208
1000p
1000p
C209
C210
1000p
1000p

C223
NIU

20
VCC

OE
DIR

GND

B8
B7
B6
B5
B4
B3
B2
B1

R211
10k
R212
100

11
12
13
14
15
16
17
18

4
3
2
1

RA28
10k

D +3. 3
L48

5SD4
5SD3
5SD2
5SD1
5SD0

5
6
7
8

A +9

SEND_L
SEND_R

Audio Section

D
D
C226
C227
C228
1000p
1000p
1000p
C229
C230
1000p
1000p

D
C342
D 0.1

'PAD[4..9]

12
11
10
9
8
7
6
5
4
3
2
1

D +5

D +3. 3

5SS3
5SS2
5SS1
5SS0
5SD4
5SD3
5SD2
5SD1
5SD0
'LS0
'LS1
'LS2
'LS3
'LDG
'LD0
'LD1
'LD2
'LD3
'LD4
'LD5
'LD6
LCDCONT
RS
R/XW
LE
LCD0
LCD1
LCD2
LCD3
LCD4
LCD5
LCD6
LCD7

PANEL BOARD
C253
C225
0.1 C224 0.1
C252
SLP@M
SLP@M
10/16
10/16

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

R214
100
D

C231
1000p
D

4
3
2
1

L28
L29
L30
L31

D
Q15
DTB113ZK

'LS0
'LS1
'LS2
'LS3

XLS1

'RIM3

Q16
DTB113ZK

'RIM2

'RIM1

D
Q17
DTB113ZK

D
D
D
C233
C234
1000p
1000p
C235
C236
1000p
1000p

XLS2

'RIM5

Q18
DTB113ZK

'RIM4

XLS3

'RIM6
Trigger Section

'RIM9
'LDG
'LD0
'LD1
'LD2
'LD3
'LD4
'LD5
'LD6

R215
R216
R218
R217
R219
R220
R221
R222

56
27
27
27
39
39
39
39

'RIM7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D

4
3
2
1

PIEZO ASSY
(PAD7-9)

1
2
3
4
5
6
7
8

RIM SENSOR
(PAD1-3)

CN11
SLP8R-5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

RIM SENSOR
(PAD4-9)

CN12
SLP16R-5

2
D

3
1

LDG

LD6
LD5
LD4
LD3
LD2
LD1
LD0
LDG

LD[0..6]

'RIM8

PIEZO ASSY
(PAD4-6)

CN7
04FE-BT-VK-N
1
2
3
4
5
6
7
8

'RIM[1..9]

4
3
2
1
CN8
04FE-BT-VK-N

4
3
2
1

'PAD9
'PAD8
'PAD7

C232
0.1

XLS[0..3]
XLS0

D
D +3. 3

PANEL BOARD

CN10
12FE-BT-VK-N

'PAD6
'PAD5
'PAD4

L27

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
CN5
52045-4045

R213
3.3k

A -9

'CTRLVR

LCDCONT
CPU Section

12
11
10
9
8
7
6
5
4
3
2
1

RETURN_L
RETURN_R

RA29
100

D +5

'LCDCONT

D
D
D
D
D
D
D
D
D
D
C212
C213
C214
C215
C216
C217
100p
NIU
220p
220p
220p
220p
C218
C219
C220
C221
C222
100p
220p
220p
220p
220p

D +5

A8
A7
A6
A5
A4
A3
A2
A1

IC31
SN74LV245APWR
NIU

Q14
2SC3052
1

5
6
7
8

D +3. 3

10

19
1

GA&DSP Section
IC53E
SN74AHCT08PWR
D

IC53D
SN74AHCT08PWR

SD4
SD3
SD2
SD1
SD0

LCD7
LCD6
LCD5
LCD4
LCD3
LCD2
LCD1
LCD0
LE
R/XW
RS

LE
R/XW
RS

C211
0.1

IC53C
SN74AHCT08PWR
12
11
SS0 13

SD[0..4]

LCD[0..7]

D +5

IC53A
SN74AHCT08PWR
9
8
SS1 10

9
8
7
6
5
4
3
2

5SS3
5SS2
5SS1
5SS0

14

SS3

4
3
2
1

L26
FBM-11-201209-601A20T

L35
FBM-11-201209-601A20T

D +5
4

4
3
2
1

SS[0..3]

Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C RT1N141C

38

39

SPD-S

Apr.2003

CIRCUIT DIAGRAM (MAIN 8/8)

fig.main8-c

ACI,ACB Adaptor
(9V/1000mA)

ADP V

D1
SS5819
1

JK10
HTJ-020-05A

C237
WLP@M
220/16

C241
0.1

D +5

IC32
NJM78L05UA
IN

C238
0.1

OUT

COM

SW3A
L32
SDKLA1-B
EXCELDR35V
2
1

D+5V

C240
WLP@M
220/16

C239
0.1

2
1
3

DA47
DAN202U
NIU

D
D

20

VCC
VIN-

R226
RCT25@J
0.18

GND

C318
WLP@M
220/16
D

ES

C317
WLP@M
220/16

D2
SB07-03C

CT

R227
RCT03@F
3.3k

C242
WLP@M
220/16
D

'C
C244
0.1
'D

999 2
3

VDD
VSS

OUT
NC

XRESET

999
+

D
R228
RCT03@F
2k

C323
NIU

3
C246
150p

D IC33
NJM2360AM

R243
NIU
'B

'A

C245
0.1

+
R242
NIU

999

IPK

IC34
D +3. 3 S-80927CLMC-G6X-T2

D+3.3V

D
999

ADP V

A +9

A+9V

2
IC36
TC7S08F
NIU

SW4
EVQ11A05R
NIU
2
1

Q28
2SC3265Y
3
2

C255
NIU

CS

L43
D +3. 3
LA-DR080-150
15uH (7.8*6.4)

999

CD

L33
LA-DR080-150
15uH (7.8*6.4)

CD

3
Q27
2SA1706T

L42
LA-DR080-150
15uH (7.8*6.4)

R223
100

R224
270

ADP V

32

10

SW3B
SDKLA1-B

999
B
999
C
999
D

*Only under development

1

R229
1k

C247
WLP@M
220/16

C248
WLP@M
220/16
A

R231
2
R232
NIU
R233
NIU

ADP V

L44
LA-DR080-331
330uH (8*5)

C319
WLP@M
220/16

CD

CS

IPK
ES

VCC
VIN-

GND

CT

L34
LA-DR080-331
330uH (8*5)
3

2
5
3

D3
SB07-03C

R236
3.3k

R237
22k

IC35
NJM2360AM
A

C250 C251
150p NIU

A-9V
L45
LA-DR080-331
330uH (8*5)

C320
WLP@M
220/16

C249
WLP@M
220/16
A

R262
1k
A

A
A -9

40

41

SPD-S

Apr.2003

CIRCUIT BOARD (PANEL)

fig.panel-comp-ptn

View from components side

42

43

SPD-S

Apr.2003

CIRCUIT BOARD (PANEL)

fig.panel-foil-ptn

View from foil side

44

45

SPD-S

Apr.2003

CIRCUIT DIAGRAM (PANEL)

fig.panel-c

'5SD4
'5SD3
'5SD2
'5SD1
'5SD0
'5SS3

12
22
SW6A

11
21

DA3
DAP202U

11
21

DA4
DAP202U

1
3

DA5
DAP202U

EDIT

SETUP

12
22
SW7A

12
22
SW8A

SW5A
12
22

11
21

11
21

<
12
22
SW9A

D +5(P)

11
21

12
22
SW10A

C1
0.1

1
D + 3.3(P)

2
SW15

2
SW12

>
SW14A
11
21

12
22

2
SW13

D(P)

- /INC

+ /DEC

DA10
DAP202U

ENTER

11
21

12
22
SW18A

12
22

11
21

12
22
SW17A

11
21

SW11A

C2
RV2-V@M-R
10/16
*SMD

DA9
DAP202U

RCM2122M-A
LCD1

SW19A

D + 3.3(P)

''LS0
2

LED1
19-21SDRC/A2
D + 3.3(V)

TR2

A + 9(V)
CN3
12FE-ST-VK-N

23
VR3B
RV112B-40E1@
SPD-S9-10k
21

22

A(V)

PAD9

FS1

LED4
19-21SDRC/A2

LED5
19-21UYOC/A2

PATCH

FS2

LED6
19-21UYOC/A2

LED15
19-21UYOC/A2

<

CARD

LED10
19-21SDRC/A2

PAD8

LED11
19-21SDRC/A2

LED19
19-21SDRC/A2

RESAMPLE

PAD7

LED13
19-21UYOC/A2

WAVE

LED35
19-21UYOC/A2

EDIT

LED8
19-21SYGC/E1

START /
STOP
2

LED21
19-21UYOC/A2

>

D + 3.3(P)

D + 3.3(P)
LCD
BACKLIGHT
MODULE

'SEND_L
2
'SEND_R

LED16
19-21SDRC/A2

''CTRLVR

PAD6

LED17
19-21SDRC/A2

PAD5

LED18
19-21SDRC/A2

LED12
19-21SDRC/A2

SAMPLING

PAD4

LED20
19-21UYOC/A2

EFFECTS

LED14
19-21UYOC/A2

LED33
19-21UYOC/A2

SETUP

ENTER

R4
56

R5
56

*IF=20mA
@VF=2.2V

R1
56

R2
56

''LS3

C6
NIU
7 'RETURN_L

5
+
R11 IC1B
M5218AFP
4.7k

LED28
19-21SDRC/A2

PAD3

''LD6
''LD5
''LD4
''LD3
''LD2
''LD1
''LD0
''LDG

LED29
19-21SDRC/A2

PAD2

LED30
19-21SDRC/A2

PAD1

LED31
19-21SDRC/A2

MARK

LED32
19-21SDRC/A2

PHRASE
MAKER
R15
RPC05T@J
NIU

3
1

A(V)
C5
RV2-V@M-R
100/16
*SMD

LED34B
BLB-6519I-YG

LED34A
BLB-6519I-YG

D(P)

D(P)

10 VR3C
RV112B-40E1@
20 SPD-S9-10k

A(V)

A(V)

VOLUME

D + 3.3(V)
3

LINE +4.89dBu Max

(0dB)

A + 9(V)

13

12

11

C12
47p

A(V)

C7
NIU
1 'RETURN_R

+
R14 IC1A
M5218AFP
4.7k

VR4A
EVUF2J@
PCKS1-10kB

C8
0.1

C10
NIU

'SEND_R
VR3A
RV112B-40E1@
SPD-S9-10k

''CTRLVR

R13
NIU

D(V)

CONTROL

+
IC1C
M5218AFP

A(V)
4

A(V) R12
NIU

C9
0.1

A(V)
A - 9(V)

46

LED3
19-21SDRC/A2

''LS2

R10
NIU

C11
47p

LED9
19-21SDRC/A2

'RETURN_R

A - 9(V)

'SEND_L

TR1

''LS1

'RETURN_L

D(V)

A(V) R9
NIU

LED2
19-21SDRC/A2

to MAIN BOARD

6
4

1
2
3
4
5
6
7
8
9
10
11
12

1
2
3
4
5
6
7
8
9
10
11
12

*SMD
C4
RV2-V@M-R
100/16

VOLUME BOARD

CN2
52043-1410

16x1 Character LCD

12
22

D(P)

DA8
DAP202U

PHRASE
MAKER
11
21

DA7
DAP202U

C3
NIU

PANEL BOARD

SHIFT

'5SS0
DA6
DAP202U

CN1
52044-4045

12
22
SW16A

D + 5(P)

11
21

FUNC

CARD

ALL SND
OFF

1
2
3
4
5
6
7
8
9
10
11
12
13
14

'5SS1

1
2
3
4
5
6
7
8
9
10
11
12
13
14

EFFECTS
2

11
21

PATCH

SW4A
12
22

11
21

DA2
DAP202U

EXIT

DA1
DAP202U

SW3A
12
22

11
21
1

'5SS2

SW2A
12
22

11
21

RESAMPLE

SW1A
12
22

11
21

SAMPLING

START /
STOP

WAVE

'LCD7
'LCD6
'LCD5
'LCD4
'LCD3
'LCD2
'LCD1
'LCD0
'LE
'R/XW
'RS
'LCDCONT

to MAIN BOARD

'5SS3
'5SS2
'5SS1
'5SS0
'5SD4
'5SD3
'5SD2
'5SD1
'5SD0
''LS0
''LS1
''LS2
''LS3
''LDG
''LD0
''LD1
''LD2
''LD3
''LD4
''LD5
''LD6
'LCDCONT
'RS
'R/XW
'LE
'LCD0
'LCD1
'LCD2
'LCD3
'LCD4
'LCD5
'LCD6
'LCD7

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

10
VR4B
20 EVUF2J@
PCKS1-10kB
D(V)

47

Apr.2003

48