Академический Документы
Профессиональный Документы
Культура Документы
Amplifier Applications
Radhakrishnan Sithanandam and M. Jagadesh Kumar, Senior Member, IEEE
Department of Electrical Engineering
Indian Institute of Technology Delhi
New Delhi, India 110016
E-mail: radhakrishnansj@gmail.com; mamidala@ieee.org
Conference Proceedings: 23rd VLSI Design - 9th Embedded Systems, January 2010. Copyright © 2010 IEEE. All rights Reserved.
Fig. 2. Process steps to fabricate HSG LDMOS.
Fig. 2 shows the proposed fabrication procedure of
HSG gate LDMOS. This process is similar to the
method proposed by Xing et al [7]. The fabrication
process begins with an SOI wafer with an n-silicon
layer with a doping of 2×1016 cm-3. The first 0.3 µm
long p+ poly gate is formed on a 25 nm thermally
grown gate oxide using standard photolithography as
shown in Fig. 2 (a). Subsequently, a 50 nm low
temperature oxide (LTO) and over that n+ poly is
Fig. 1. Cross sectional view of (a) conventional deposited. Using blanket reactive ion etching (RIE),
LDMOS (b) HSG LDMOS. the polysilicon layer is etched leaving a sidewall
polysilicon layer as shown in Fig. 2(b) which will now
act as the second gate of 0.7 μm length. Now, we
Table.1. Device parameters used in deposit 100 nm LTO and over that p+ poly is deposited
simulation. and etched back to form 0.4 µm long third gate as
shown in Fig. 2 (c). A chemical-mechanical polishing
Gate length, 0.3 µm, 0.7 µm and 0.4 (CMP) process will planarize the gate as shown in Fig.
(LG1, LG2 and LG3) µm 2(d). Once the gate is defined, rest of the fabrication
process is similar to the conventional LDMOS
Gate oxide thickness, 25 nm, 50 nm and 150 fabrication. After metallization process, source, drain
(tox1, tox2 and tox3) nm and gate contacts are formed and all the three gates
shorted resulting in the final HSG LDMOS structure
Channel length, L 0.5 µm
shown in Fig. 1(b).
Buried oxide thickness 400 nm
Silicon thickness 1 µm 3. Simulation results and discussion
Drift region length 2.3 µm We have created the conventional and proposed
Source/Drain doping 1×1019 cm-3 device structure in ATLAS, a two dimensional device
simulator. The design of the LDMOS is done
Drift region doping 2×1016 cm-3 according to RESURF principle [8]. The effect of
Channel doping 1×1017 cm-3 hetero-material stepped gate on breakdown voltage,
DC characteristics, gate charge transients and
Threshold voltage ≈1.85 V switching characteristics are discussed below.
Fig. 3. Breakdown voltage of conventional and
Fig. 5. Output characteristics of conventional
HSG LDMOS.
and HSG LDMOS.
Fig. 4. Electric field distribution along the Fig. 6. On-resistance of conventional and HSG
surface of conventional and HSG LDMOS at a LDMOS.
drain voltage of 40 V.
3.2. DC Characteristics
3.1. Breakdown Voltage
The output characteristics of the HSG LDMOS and the
Breakdown voltage of LDMOS is the drain voltage at conventional LDMOS are shown in Fig. 5, it can be
which the off state current rises abruptly with the observed that the proposed device has higher drain
increase in drain voltage (we have taken this drain current than the conventional device. The reduced gate
current as 1 pA/µm). The breakdown voltage oxide at the source end improves the channel charge
characteristics of the HSG LDMOS and the density thereby increasing the drain current. The
conventional device are shown in Fig. 3. It can be seen improvement in drain current is approximately 60% at
that the proposed device exhibits an enhanced VGS = 4 V and VDS = 20 V. Due to the improved drain
breakdown voltage by about 29% compared to the current, specific on-resistance also decreases as shown
conventional LDMOS. in Fig. 6. The improvement in on-resistance is 32% at
The stepped gate in the drift region enhances RESURF VGS = 6 V. Here, the specific on-resistance is
and introduces additional electric field peaks as shown calculated as the ratio of drain current by drain voltage
in Fig. 4. These additional peaks reduce the main per unit area at the gate potential of 6 V. Furthermore,
electric field peak from 7.1 ×105 V/cm to 4 ×105 V/cm the HSG LDMOS shows 13% enhancement in peak
and also smear the electric field uniformly resulting in transconductance than the conventional device as
improved breakdown voltage. shown in Fig. 7. This improvement is again due to the
improved channel charge density.
Fig. 7. Transconductance of conventional and Fig. 9. Switching characteristics of
HSG LDMOS. conventional and HSG LDMOS in an inverter
configuration.
5. References
[1] M. M. De Souza, G.Cao, E. M. S. Narayanan, F.
Youming, S. K. Manhas, J. Luo and N. Moguilnaia,
"Progress in Silicon RF Power MOS Technologies-
Current and Future Trends.(Invited)," in Fourth IEEE
International Caracas Conference on Devices,Circuits
and Systems, Aruba, 2002, pp. D047-1-D047-7.
[2] J. G. Fiorenza and J. A del Alamo, "Experimental
Comparison of RF Power LDMOSFETs on Thin Film
SOI and Bulk Silicon," IEEE Transactions on Electron
devices, vol. 49, no. 4, pp. 687-692, Apr. 2002.
[3] T. Khan, V. Khemka, and R. Zhu, "Incremental
FRESURF LDMOSFET structure for enhanced voltage
blocking capability on 0.13um, SOI based technology,"
in 20th International Symposium on Power
Semiconductor Devices and IC's, Oralando, 2008, pp.
279-182
[4] S. Linder, Power Semiconductors, 1st ed. Lausanne,
Switzerland: EPFL Press, 2006
[5] M. M. De Souza, "Design for Reliability: The RF Power
LDMOSFET," IEEE Transactions on Device and
Material Reliability, vol. 7, no. 1, pp. 162-174, Mar.
2007.
[6] ATLAS user's manual : Device simulation software. Santa
Clara, CA: Silvaco International, 2007.
[7] H. Xing, Y. Dora, A. Chini, S. Heikman, S. Keller and U.
K. Mishra, "High Breakdown Voltage AlGaN-GaN
HEMTs Achieved by Multiple Field Plates," IEEE
Electron Device Letters, vol. 25, no. 4, pp. 161-163, Apr.
2004.
[8] J. A. Appeles and H. M. J. Vaes, "High Voltage Thin
Layer Devices (RESURF Devices)," in IEDM Tech
Digest, 1979, pp. 238-241.