Академический Документы
Профессиональный Документы
Культура Документы
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Table of Contents
Chapter 1
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Syntax Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mentor Graphics Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
23
24
Chapter 2
QVL Monitors Basics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Use Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Specifying Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiate QVL Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instance Templates Directory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile QVL Monitor Libraries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Compile and Simulate the DUT with the QVL Monitor . . . . . . . . . . . . . . . . . . . . . . . . . .
Verify and Troubleshoot the QVL Monitor Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Review and Debug Simulation QVL Monitor Results . . . . . . . . . . . . . . . . . . . . . . . . . . . .
QVL Monitor Coverage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Run Formal Verification with QVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity on the Bi-Directional/Tri-State Buffer Signals . . . . . . . . . . . . . . . . . . . . . . . .
25
25
26
28
28
32
33
34
35
36
39
39
Chapter 3
Advanced Microcontroller Bus Architecture (AMBA) . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
APB Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Master Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AHB Target Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
41
41
41
41
42
42
43
43
44
45
46
50
51
51
52
52
52
53
54
55
60
61
Table of Contents
61
62
62
62
63
63
64
65
65
Chapter 4
AMBA 3 Advanced Peripheral Bus (APB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AMBA 3 APB Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
67
67
67
67
67
68
69
69
71
71
Chapter 5
AMBA AXI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
AMBA AXI Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Chapter 6
Double Data Rate SDRAM (DDR SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
103
103
103
103
103
104
104
105
105
107
108
Table of Contents
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data interface and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
113
119
132
133
134
134
134
134
135
135
135
136
139
145
154
165
167
Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V1.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR-II SDRAMs Stacking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V2.0 Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Extended Mode Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization Sequence Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
169
169
169
169
169
170
170
171
173
174
176
178
187
189
190
190
190
190
191
191
192
196
201
204
221
222
Table of Contents
Chapter 8
Gigabit Ethernet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gigabit Media Independent Interface (GMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Gigabit Media Independent Interface (RGMII). . . . . . . . . . . . . . . . . . . . . . . . . .
Media Independent Interface (MII) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reduced Media Independent Interface (RMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Media Independent Interface (XGMII). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40/100 Gigabit Media Independent Interface (XLGMII/CGMII) . . . . . . . . . . . . . . . . . . .
1000BASE-X Ten bit Interface (TBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . .
Reduced Ten bit Interface (RTBI) between PCS and PMA . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Attachment Unit Interface (XAUI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
XAUI Limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 Gigabit Sixteen Bit Interface (XSBI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
40G/100G Attachment Unit Interface (XLAUI, CAUI). . . . . . . . . . . . . . . . . . . . . . . . . . .
40G or 100G Auto Negotiation Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Control Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
223
223
224
224
224
224
225
225
225
226
226
226
227
227
227
228
228
229
229
229
230
238
249
249
250
251
251
252
252
253
253
254
255
255
256
256
285
287
Chapter 9
High-Definition Multimedia Interface (HDMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
289
289
289
289
290
291
292
Table of Contents
295
296
297
303
307
Chapter 10
I2C (Inter-IC) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Monitor Instantiation Examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I2C Master/Slave Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Assertion Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Master Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Slave Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
309
309
310
310
311
313
313
313
314
314
315
318
319
320
320
321
321
Chapter 11
Low Pin Count (LPC). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
323
323
323
323
323
324
325
326
329
329
Chapter 12
Open Core Protocol (OCP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Transfers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Response Signaling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tags. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Threads and Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
331
331
331
331
331
331
331
332
332
332
Table of Contents
Data buses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sideband Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OCP Disconnect Proposal Revision 0.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 Users. . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Modification is Required for OCP 2.1 and 2.2 Users . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
332
332
332
333
333
333
334
338
340
350
352
352
354
356
395
397
Chapter 13
Peripheral Component Interconnect (PCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initiator (Master) Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Top-level Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
399
399
399
399
400
402
402
403
404
407
412
414
414
Chapter 14
PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Standard Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PIPE Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters (PIPE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
415
415
415
415
418
418
418
421
423
424
427
429
431
433
435
Table of Contents
438
442
442
458
466
487
493
504
505
613
615
616
617
619
Chapter 15
Serial Attached SCSI (SAS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unsupported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connecting Clocks in Serial Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Recovery Module. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMP, SSP and STP Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
623
623
623
623
624
624
626
630
630
635
635
637
638
639
640
640
642
642
647
659
662
663
664
Chapter 16
SERIAL ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
671
671
671
671
672
673
676
Table of Contents
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SAPIS Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Link Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transport Layer Normal and Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor FAQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
680
683
683
686
688
700
707
708
711
714
Chapter 17
Serial Parallel Interface (SPI) Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SPI Monitor Instantiation Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
719
719
719
719
719
720
721
721
722
Chapter 18
System Packet Interface Level 4 Phase 2 (SPI4-2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receive Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Transmit Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
723
723
723
724
724
724
728
730
734
741
741
743
743
743
747
749
749
750
751
753
759
760
10
Table of Contents
Chapter 19
Universal Serial Bus 2.0 (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supported Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Monitor Instantiated on the Host or Hub . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Placement and Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 (Standard) Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Connectivity Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Instantiation Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 Standard Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 UTMI Monitor Checks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
USB 2.0 ULPI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
761
761
761
762
763
763
764
764
765
767
768
768
769
770
770
772
774
779
781
781
782
783
788
790
790
804
824
846
849
Appendix 20
QVL Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Defines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Global Defines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Defines Common to All Assertions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
851
851
851
852
11
List of Examples
Example 2-1. Verilog AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-2. VHDL AHB Master Monitor Template . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Example 2-3. Binding an Assertion Module to the DUT in SVA . . . . . . . . . . . . . . . . . . . . . 31
Example 2-4. Verilog Simulator Argument Sample File. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Example 3-1. AHB Master Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Example 3-2. AHB Target Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Example 3-3. APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Example 4-1. AMBA 3 APB Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Example 5-1. AMBA AXI Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . 79
Example 5-2. AMBA AXI Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . 81
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 113
Example 6-2. Two DDR SDRAM Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Example 6-3. DDR SDRAM Monitor Instantiated in the Controller . . . . . . . . . . . . . . . . . . 116
Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing Parameter Values
117
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 145
Example 6-6. Two DDR SDRAM 2.0 Monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Example 6-7. DDR SDRAM 2.0 Monitor Instantiated in the Controller . . . . . . . . . . . . . . . 149
Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing Values
Configured Through Input Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Example 7-1. DDR-II SDRAM 1.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Example 7-2. DDR-II SDRAM 1.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Example 7-3. DDR-II SDRAM 2.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Example 7-4. DDR-II SDRAM 2.0 Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . 249
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation . . . . . . . . . . . . . . . . 250
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation . . . . . . . . . . . . . . . . . . 251
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation . . . . . . . . . . . . . . . . . 251
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 252
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation. . . . . . . . . . 252
Example 8-7. 1000BASE-X TBI Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-8. Reduced Ten bit Interface Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . 254
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . 255
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . 255
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation . . . . . . . . . . . 256
Example 9-1. HDMI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Example 10-1. I2C Master Monitor Instantiation for a Master Only Design . . . . . . . . . . . . 314
12
List of Examples
Example 10-2. I2C Slave Monitor Instantiation for a Slave Only Design . . . . . . . . . . . . . .
Example 10-3. I2C Master/Slave Monitor Instantiation for a Master/Slave Design. . . . . . .
Example 11-1. LPC Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-1. OCP Monitor Instantiation for Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 12-2. OCP Monitor Instantiation for Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 13-1. PCI Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-1. PCI Express Monitor Instantiation Example 1 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-2. PCI Express Monitor Instantiation Example 2 . . . . . . . . . . . . . . . . . . . . . . .
Example 14-3. PCI Express Gen2 Monitor Instantiation Example 3 . . . . . . . . . . . . . . . . . .
Example 14-4. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-5. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 14-6. PIPE Monitor Instantiation Example 3 (9Bit Mode). . . . . . . . . . . . . . . . . . .
Example 14-7. PIPE Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-1. SAS Monitor Within an SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-2. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-3. SAS Monitor Within a SAS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-4. SAS Monitor Within an Expander Device . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 15-5. Clock Recovery Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-1. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-2. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-3. SATA Monitor Instantiation for Example 3 . . . . . . . . . . . . . . . . . . . . . . . . .
Example 16-4. SATA Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 17-1. SPI Monitor Master Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-1. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-2. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-3. SPI4-2 Receive Monitor Instantiation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-4. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-5. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 18-6. SPI4-2 Transmit Monitor Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-1. USB Monitor on the Downstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-2. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-3. USB Monitor to Track an 8-bit UTM Interface . . . . . . . . . . . . . . . . . . . . . .
Example 19-4. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Example 19-5. USB Monitor to Track an 4-bit ULP Interface . . . . . . . . . . . . . . . . . . . . . . .
Example 19-6. USB Monitor on the Upstream Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
314
314
325
352
354
403
427
428
429
438
439
440
441
636
637
638
639
642
680
681
682
682
721
731
732
733
749
751
752
768
769
779
780
788
789
13
List of Figures
Figure 2-1. RTL Signals and Tri-State Buffer (I/O Structure) . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-1. AHB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-2. APB-Based System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-3. AHB Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-4. AHB Target Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 3-5. APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4-1. AMBA 3 APB Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-1. AMBA AXI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5-2. AMBA AXI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-1. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-2. DDR SDRAM Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-3. Stacking DDR SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-4. Stacking DDR SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-5. DDR SDRAM System Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 6-6. DDR SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-1. DDR-II SDRAM 1.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-3. Stacking DDR-II SDRAMs by Data Width . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-4. Stacking DDR-II SDRAMs by Address Width . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-6. DDR-II SDRAM 2.0 Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-1. Gigabit Ethernet Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8-2. Gigabit Ethernet Monitor Pin-Out Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-1. HDMI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9-2. HDMI Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1. I2C System Topology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-2. I2C Monitor Connectivity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3. I2C Master Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4. I2C Slave Monitor Pins Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-5. I2C Master/Slave Monitor Pins Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-1. LPC Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 11-2. LPC Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-1. OCP Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-2. OCP Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 12-3. OCP Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-1. PCI Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 13-2. PCI Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-1. PCI Express Gen1 Monitor Implementation . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-2. PCI Express Gen2 Monitor Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 14-3. PCI Express Monitor Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14
40
42
42
43
52
62
67
74
75
105
106
108
108
136
137
171
171
173
173
192
193
230
231
290
291
309
310
311
311
311
323
324
338
340
341
399
400
419
420
421
List of Figures
430
430
431
625
626
627
640
641
664
673
674
720
720
724
725
743
744
764
765
770
781
15
List of Tables
Table 1-1. Conventions for Command Line Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-1. AHB Master Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-2. AMBA AHB Master Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-3. AMBA AHB Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-4. AMBA AHB Master Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-5. AMBA AHB Master Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-6. AHB Target Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-7. AMBA AHB Target Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-8. AMBA AHB Target Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-9. AMBA AHB Target Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-10. AMBA AHB Target Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-11. APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-12. AMBA APB Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-13. AMBA APB Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-14. AMBA APB Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 3-15. AMBA APB Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-1. AMBA 3 APB Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-2. AMBA 3 APB Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-3. AMBA 3 APB Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-4. AMBA 3 APB Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 4-5. AMBA 3 APB Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-1. AMBA AXI Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-2. AMBA AXI Monitor Parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-3. AMBA AXI Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-4. AMBA AXI Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 5-5. AMBA AXI Protocol Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-1. DDR SDRAM Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-2. DDR SDRAM Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-3. JEDEC Mode Burst Length Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-4. JEDEC Mode CAS Latency Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-5. JEDEC Standard Compliant Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-6. DDR SDRAM Monitor Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-7. DDR SDRAM Monitor Checks for Each Bank . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-8. Calculate Minimum Delay From a Read/Write . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-9. DDR SDRAM Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank . . . . . . . . . .
Table 6-11. DDR SDRAM Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank . . . . . . . . . . . . . .
Table 6-13. DDR SDRAM 2.0 Monitor Pin-Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 6-14. DDR SDRAM 2.0 Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Questa Verification Library Monitors Data Book, v2010.2
23
43
44
46
50
51
52
53
55
60
61
62
63
64
65
65
68
68
69
71
71
75
77
82
99
102
106
108
112
112
113
119
123
131
132
132
133
133
137
140
16
List of Tables
144
144
145
154
158
165
165
166
167
167
172
174
176
178
181
187
188
189
189
194
196
201
204
212
221
221
222
222
232
232
233
233
234
234
234
235
235
236
236
237
238
238
239
240
241
17
List of Tables
18
242
242
243
244
245
246
247
258
261
263
265
268
269
272
273
275
280
282
283
285
287
291
292
296
297
297
298
300
303
303
304
305
307
308
312
313
315
318
319
320
320
321
321
324
324
List of Tables
326
329
329
341
350
356
395
397
400
402
404
407
412
414
414
421
424
431
435
442
449
458
466
487
491
493
497
498
501
503
504
506
506
530
538
567
567
572
573
573
574
574
589
601
613
19
List of Tables
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express Monitor . . . .
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express Monitor . .
Table 14-33. Physical Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-34. Data Link Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-35. Transaction Layer Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 14-36. Physical Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . . .
Table 14-37. Data Link Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . . .
Table 14-38. Transaction Layer Corner Cases PCI Express Monitor Gen2 . . . . . . . . . . . . .
Table 14-39. Physical Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . . .
Table 14-40. Data Link Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . . . .
Table 14-41. Transaction Layer Statistics PCI Express Monitor Gen2 . . . . . . . . . . . . . . . .
Table 15-1. SAS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-2. SAS Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-3. SAS Monitor (dynamic timer values) Parameters . . . . . . . . . . . . . . . . . . . . . . .
Table 15-4. Clock Recovery Module Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-5. SAS Monitor Physical Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-6. SAS Monitor Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-7. SMP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-8. SSP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-9. STP Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-10. SAS Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-11. SAS Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 15-12. Bit Order for TX and RX Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins . . . . . . . . . . . . . . . . . .
Table 16-2. SAPIS Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces . . . . . . . . . . . . . .
Table 16-4. SATA Monitor Parameters - SAPIS Interface . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-5. Power on Sequence Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-6. Phy Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-7. Link Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-8. Transport Layer Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-9. SAPIS Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-10. Link Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-11. Link Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-12. Transport Layer Normal Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 16-13. Transport Layer Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-1. SPI Monitor Pins Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-2. SPI Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 17-3. SPI Master Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-1. SPI4-2 Receive Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-2. SPI4-2 Receive Monitor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-3. SPI4-2 Receive Checks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-4. SPI4-2 Receive Monitor Corner Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-5. SPI4-2 Receive Monitor Statistics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 18-6. SPI4-2 Transmit Monitor Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
613
614
615
615
615
616
617
617
617
618
618
628
630
633
641
642
647
659
660
661
662
663
665
674
675
676
678
683
686
688
700
707
708
709
711
711
720
721
722
725
728
734
741
741
744
List of Tables
747
753
759
760
765
767
770
774
781
783
790
804
812
824
835
846
849
21
List of Tables
22
Chapter 1
Introduction
Syntax Conventions
This manual uses the following command usage line syntax conventions.
Table 1-1. Conventions for Command Line Syntax
Convention
Example
Usage
Boldface
[ ]
EXIt [-Discard]
Italic
DOFile filename
{ }
[-var req_signal]
-var {req_signal}
[std_option]
23
Introduction
Mentor Graphics Support
{arg1 arg2}
{[var1][var2][var3]}
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24
Chapter 2
QVL Monitors Basics
The Questa Verification Library Monitors (QVL monitors) is a set of monitors that validate
specific industry-standard interface protocols and verify specific interface behaviors.
The QVL monitors are supported by the 0-In Formal Verification tool suite. In addition, the
QVL monitors are licensed for the Questa product.
Interface protocol monitors are modules that include QVL assertion checkers. A monitor
performs its verification functions using checkers embedded in the monitor itself. The monitor
is, in essence, a compound checker. QVL monitors are instantiated directly by identifying the
connections to the monitor inputs.
QVL monitors are SystemVerilog components that are wired to probe your design during
simulation and do the following as simulation progresses:
They accumulate and maintain cover point data relevant to the protocol.
A QVL monitor can be configured to act as a formal constraint. Here, specific protocol rules are
turned into constraints (with the SystemVerilog assume construct) that constrain the formal
engines to restrict analysis to states that do not violate the monitors interface protocol.
25
Specify settings using the standard +define options in the simulation argument file or at
the command line.
QVL_COVER_ON
If neither of these constants is defined, then the QVL checkers are not activated. The
instantiations of these checkers has no influence on the verification performed.
Following is an example of using global defines:
vlog +define+QVL_ASSERT_ON+QVL_COVER_ON ...
26
By default, final coverage information is displayed for monitors, but not for checkers. To
change this behavior, specify one or both of the following global defines:
QVL_CW_FINAL_COVER
QVL_MW_FINAL_COVER_OFF
X/Z Checks
Assertion checkers can produce indeterminate results if a checker port value contains an X or Z
bit when the checker samples the port. (Note that a checker does not necessarily sample every
port at every active clock edge.) To assure determinate results, QVL monitors have special
assertions for X/Z checks (see Global Defines on page 851).
27
By default, QVL assertion checker logic includes logic implementing assertion checks for X
and Z bits in the values of checker ports when they are sampled. To exclude all X/Z checking
logic, specify the following global variable:
QVL_XCHECK_OFF
Adds one resolution unit of delay (that is, Verilog #1) to all QVL
input signals. Default: zero delay.
28
29
Specify the QVL instance in the testbench or design under test (DUT). To make the
monitor visible only during simulation, use the following:
o
Specify the QVL instance as a separate module, then use SVA bind to wire the monitor
signals to your DUT (see Example 2-3 on page 31 and SystemVerilog Bind on
page 32). SystemVerilog declares that by default, each file is a separate compilation
unit.
When bind is specified outside the module file that the program instance is being bound
to, the elaboration process does not recognize the dependency to the bound module and
the bind is not elaborated with the bound module. Therefore, you must use the -cuname
option to name the compilation unit. Then, specify the compilation unit name to vsim to
enable the bind statements to be elaborated, as shown in the following example:
vlog assertion_module.sv bind.v -cuname bind_cu
vsim top bind_cu
Specify the QVL instance in a PSL vunit, and then bind the vunit to the target module to
connect the signals from the target module to the monitor instance. Refer to the Questa
SV/AFV Users Manual, Chapter 18: Verification with Assertions and Cover Directives
for detailed information. This manual is available on the Mentor Graphics SupportNet.
Specify the QVL instance in a separate module, and connect the DUT to the instances
ports using one of the following methods:
o
clk
reset_n
wr_en
max
=
=
=
=
TB.DUT.clk;
TB.DUT.reset_n;
TB_DUT.wr_en;
TB.DUT.wr_hold_max;
Whenever a signal spy command is used, the ModelSim library and package must be
specified as follows:
library modelsim_lib;
use modelsim_lib.util.all;
30
This replaces the instances module keyword with the interface keyword.
Add the QVL instance to a ANSI port declaration. and use hierarchical port
references to wire the port signals to your DUT. For example:
module cpu_top (
qvl_pci_monitor pci_mon_if,
. . .
assign pci_mon_if.pci_ad_en_n
assign pci_mon_if.pci_cbe_en_n
= AD_enb;
= 1'b0;
Note that whenever a QVL monitor is instantiated in a VHDL design, the QVL library and the
QVL packages must be specified as follows:
library qvl_lib;
use qvl_lib.qvl_chechers.all;
use qvl_lib.qvl_monitors.all;
Exclude the QVL components from code coverage by adding source code pragmas (coverage
off/coverage on) around the QVL component instantiations as described in the Questa SV/AFV
Users Manual, chapter 16: Coverage.
Example 2-3. Binding an Assertion Module to the DUT in SVA
module assertion_module (clk, reset_n, wr_en, wr_hold_max);
input
clk;
input
reset_n;
input
wr_en;
input [2:0] wr_hold_max;
wire
qvl_clk
= clk;
wire
qvl_reset_n
= reset_n;
wire
qvl_wr_en
= wr_en;
wire [2:0] qvl_max
= wr_hold_max;
// include define file to allow use of QVL defines
include "std_qvl_defines.h"
qvl_change_timer #(
.severity_level(QVL_ERROR),
.property_type(QVL_ASSERT),
.msg("QVL_VIOLATION : "),
.coverage_level(QVL_COVER_ALL),
.width(1),
.min_check(1),
.max_check(1))
qvl_change_timer_instance(
31
SystemVerilog Bind
Many users prefer to instantiate assertions without modifying their RTL. A common way to
define or instantiate assertions into a separate module is to define your assertions in a separate
assertion module and use SystemVerilog bind to wire the assertion (monitor) signals to your
design module:
1. Create a separate assertion module.
2. Instantiate assertions in assertion module.
Note: When using a signal or port from the targeted design module, the signal and port
names must be added to the assertion module port list. Use the same signal and port
name as the design module, so implicit port instantiation can be used with the
SystemVerilog bind.
3. Create the SystemVerilog bind instance to connect the assertion module to the target
module.
32
To compile a protected (read-only) QVL library to be shared by your project team, add the
-novopt option to the vlog and vcom commands. Users can then compile simulation
environments both with, and without, vopt. Typically, questasim_dir is the same as the install
directory of the Questa executables. However, it can be the install directory of a later Questa
release (for example, if you are frozen into a particular Questa release, but want to use
features/enhancements of the later QVL release).
Caution
Starting with QVL 2009.1, QVL was decoupled from Questa releases. From this release
onward, QVL directs vlog to print the QVL version. However, when using QVL with
vlog version 6.5c (or earlier), you must specify +define+QVL_VERSION_PRINT_OFF
as a vlog argument to prevent a vlog error.
Run your vsim simulation command and the monitor is run in simulation in a similar way to
other SVA assertions.
Verilog
Add the QVL Verilog arguments to your Verilog compilation arguments. Example 2-4 shows a
sample simulator argument file that references the QVL checkers and the AMBA monitor. The
checkers are located in a single directory (qvl_src/qvl_checkers), but each monitor directory
must be specified separately (for example, qvl_src/qvl_monitors/amba,
qvl_src/qvl_monitors/axi, etc.). For example,
vlog <compile_arguments> -f filelist.qvl
In the QVL Monitors sections of the arguments filelist (see Example 2-4), update the -y and
+incdir options to refer to the appropriate monitor directories. By default, all QVL checkers are
specified through the -y option.
33
Once the design and testbench are compiled, your vsim simulation command needs no
modifications. Run your vsim simulation command and the QVL components run in simulation
similar to other SVA assertions.
Example 2-4. Verilog Simulator Argument Sample File
// Command line switches
// `DEFINES
+define+QVL_ASSERT_ON
+define+QVL_COVER_ON
//+define+QVL_SV_COVERGROUP_OFF
//+define+QVL_CW_FINAL_COVER
//+define+QVL_MW_FINAL_COVER_OFF
//
//
//
//
//
// File extensions
+libext+.v
+libext+.sv
// Include directories
// -- QVL checkers
+incdir+<questasim_install_dir>/qvl_src/qvl_checkers
// -- QVL monitors
+incdir+<questasim_install_dir>/qvl_src/qvl_monitors/amba
//
//
-y
//
-y
Library directories
-- QVL checkers
<questasim_install_dir>/qvl_src/qvl_checkers
-- QVL monitors
<questasim_install_dir>/qvl_src/qvl_monitors/amba
34
3. View all connections to the monitor in the simulation waveforms for the monitor
instance. Check that the monitor signals are not unknown.
4. Recheck the monitor coverage. Verify that the protocol transactions exercised in
simulation are consistent with the transactions recorded by the monitor.
If you are still having setup problems, please send the following to support@mentor.com:
Waveforms that trace the monitor instance with debug access enabled. Use the
+acc vopt argument to enable debug command access to monitor objects (see View
and Debug QVL Monitor Protocol Violations on page 35).
35
Note that in order to run vsim with the -novopt option and with precompiled libraries, the
libraries must have been compiled with the -novopt option or a user must have write privileges
to the compiled libraries. If the library was not compiled with the -novopt option and the user
does not have write privileges to the compiled libraries, then vsim generates the vcom-19
(Failed to access library) error.
Following is an example for disabling QuestaSim optimizations during vopt for all instances of
a QVL monitor:
vopt +acc+qvl_amba_axi_monitor ...
Following is an example for disabling QuestaSim optimizations during vsim for all instances of
a QVL monitor:
vsim -voptargs="+acc+qvl_amba_axi_monitor" ...
Following is an example for disabling QuestaSim optimizations for the entire simulation
environment (note that it is not recommended to disable all optimizations):
vsim -novopt ...
36
For Verilog designs using $finish, the simulation might exit before the coverage report
command executes. Add vsim commands that prevent simulation exit and resume vsim
command execution. For example,
set NoQuitOnFinish 1;
onbreak {resume};
run -all;
coverage report -details -file -coverage.rpt -r /*
Refer to the Questa SV/AFV Reference Manual for information on the coverage command.
37
The cover groups for the qvl_fifo checker type are defined in the following file:
questasim_dir/qvl_src/qvl_checkers/qvl_fifo_cover.svh
This file shows the Simultaneous Enqueues and Dequeues cover point is defined in the
fifo_cornercases cover group and has the name C3:
covergroup fifo_cornercases @ (posedge clock);
. . .
C3 : coverpoint
(!($stable(simultaneous_enq_deq, @ (posedge clock))))
iff (enable_coverpoint){
bins Simultaneous_Enqueues_and_Dequeues = {1};
type_option.comment = "Simultaneous Enqueues and Dequeues";
}
endgroup : fifo_cornercases
For this example, assume the logic driving the FIFO cannot produce a simultaneous
enqueue/dequeue. So, the fifo_cornercases.C3 cover point for fifo_valid always has coverage
0% and the maximum possible coverage for the fifo_cornercases cover group is 75% (i.e., at
most 3 out of 4 cover points can be hit).
The following code in tb disables the Simultaneous Enqueues and Dequeues cover point
(qvl_fifo_chx is the instance in the qvl_fifo module used to configure an internal version of the
checker):
initial begin
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.goal = 0;
dut.fifo_valid.qvl_fifo_chx.fifo_cornercases.C3.type_option.weight = 0;
38
Setting the cover point weight to 0 removes the cover point from the calculation of the coverage
for the parent cover group, so fifo_cornercases can attain 100% coverage. Setting the cover
point goal to 0 makes the % of goal measure for the cover point 100% (instead of 0%).
You should not disable all the cover points for a particular cover group. In this case, the weights
of all the cover groups cover points are 0. The calculation for cover group coverage divides by
the total weight of the cover points (in this case 0), which results in a NaN value for the
coverage.
The following example compiles a SystemVerilog bind module with the DUT using 2-step
compilation:
0in -cmd analyze -vhdl DUT.vhdl -work work
0in -cmd analyze \
assertion_module.v bind.sv -cuname bind_cu -work work -qvl
0in -cmd csl -d DUT -cuname bind_cu -work work -qvl
<sig_name>_out/<sig_name>_out_n
39
<sig_name>_out_en/<sig_name>_out_en_n
<sig_name>_in/<sig_name>_in_n
These signals are connected to the tri-state I/O structure on the final chip. To connect to the such
interfaces, the QVL monitors are also designed with split signals (see Figure 2-1 on page 40).
Following is the typical structure and the naming convention:
<sig_name>_out_en Output enable; output signal from the RTL, Active High.
<sig_name>_out_en_n Output enable; output signal from the RTL, Active Low.
Monitor
<sig_name>_out
<sig_name>_out_en
<sig_name>_in
Tri-State Buffer
<sig_name>_out
<sig_name>
RTL
<sig_name>_out_en
<sig_name>_in
40
Chapter 3
Advanced Microcontroller Bus Architecture
(AMBA)
Introduction
The Advanced Microcontroller Bus Architecture (AMBA), from ARM Limited, is an on-chip
communications standard for designing high-performance embedded microcontrollers. There
are three distinct buses defined within the AMBA specification: Advanced High-performance
Bus, Advanced System Bus, and Advanced Peripheral Bus.
QVL monitors are available for the following:
AHB monitors are compatible with AHB-Lite, and they also can be used in multilayer
interconnection schemes.
Reference Documentation
This version of the QVL AMBA monitor is modeled from the requirements provided in the
following documents:
AMBA Specification, Rev 2.0, May 13, 1999, Issue A, ARM IHI0011A.
AHB Monitors
The Advanced High-performance bus (AHB) protocol defines communication between master
and target devices. A typical AHB system design contains the following components: master,
target, arbiter, and decoder. QVL monitors are available for the AHB master and AHB target
components.
Examples of AHB masters are: high-performance ARM processors, DMA bus masters, and so
on. Examples of AHB targets are: high-bandwidth memory interfaces, high-bandwidth on-chip
41
RAMs, and so on. The APB bridge is also a target on the AHB bus. Figure 3-1 illustrates a
block diagram of an AHB-based system.
Figure 3-1. AHB-Based System Implementation
AHB Master
AHB Target
AHB
Bridge
AHB Bus
AHB Target
AHB Master
APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with the AHB system bus. The devices on
the APB bus are lower bandwidth peripheral devices such as UARTs, Timers, parallel I/O ports,
etc. Figure 3-2 illustrates a block diagram of an AHB-based system.
Figure 3-2. APB-Based System Implementation
Device 2
Device 1
Bridge
APB Bus
AHB Bus
Device 3
The APB monitor can be instantiated in the
bridge to specify targets and constraints while
searching the bridge. The AHB interface must
be constrained to do this search.
Device 4
The APB monitor can be instantiated in
the peripheral devices to run formal
analysis on these designs.
42
Monitor Connectivity
Connect the AHB master monitor pins to internal signals as specified in the pin-out Table 3-1
and illustrated in Figure 3-3. Note that hbusreqx and hlockx are not part of the AHB master
monitor because these signals are not used by the monitor.
Figure 3-3. AHB Master Monitor Pins Diagram
hresetn
hclk
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hwdata[DATA_BUS_WIDTH 1:0]
hrdata[DATA_BUS_WIDTH 1:0]
hready
hresp[1:0]
hprot[3:0]
hgrantx
AMBA
AHB Master
Monitor
Description
haddr[31:0]
hburst[2:0]
hclk
hgrantx
hprot[3:0]
hrdata[DATA_BUS_WIDTH 1:0]
Read data bus. Transfers data from target to master via a read
operation.
43
Description
hready
hresetn
Active low bus reset signal. Resets the system and the bus.
hresp[1:0]
Encoding for the response from the target indicating the status
of the current transfer.
hsize[2:0]
htrans[1:0]
hwdata[DATA_BUS_WIDTH 1:0]
Write data bus. Transfers data from master to target via a write
operation.
hwrite
Encoding for the type of transfer: HIGH for write transfers and
LOW for read transfers.
Monitor Parameters
The parameters shown in Table 3-2 configure the corresponding AHB master monitor.
Table 3-2. AMBA AHB Master Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
DATA_BUS_WIDTH
32
3.
CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE
4.
Over_Constraints_Mode 0
5.
DISABLE_CHKS_ON_IDLE
Note:
For the Over_Constraints_Mode set to 1, the AMBA AHB master monitor has the following
additional constraints:
44
Note that if using the AHB master monitor with an AHB-Lite master, then the user is required
to tie the hgrantx signal to high (1'b1) and the hresp[1] signal to low (1'b0).
45
Monitor Checks
Table 3-3 shows the checks performed by an AHB master monitor.
Table 3-3. AMBA AHB Master Checks
46
Check ID
Violation
Description
AHB_M1
AHB_M2
AHB_M3
AHB_M4
AHB_M5
AHB_M6_address
AHB_M6_control
AHB_M7
AHB_M8
Violation
Description
AHB_M9
AHB_M10
AHB_M11
AHB_M12
AHB_M13
AHB_M14
47
48
Check ID
Violation
Description
AHB_M15
AHB_M16
AHB_M17
AHB_M18
AHB_M19
AHB_M20
Violation
Description
AHB_M21
AHB_M22
AHB_M23
AHB_M24_hgrantx,
AHB_M24_hready,
AHB_M24_hresp,
AHB_M24_htrans,
AHB_M24_hwrite,
AHB_M24_hsize,
AHB_M24_hburst,
AHB_M24_hprot
AHB_M25_haddr
AHB_M26
AHB_M27
AHB_MX
49
50
Corner Case
Description
Read Transfers
Write Transfers
IDLE Transfers
BUSY Transfers
OKAY Responses
ERROR Responses
RETRY Responses
SPLIT Responses
Monitor Statistics
Table 3-5 shows the statistics maintained by the AHB master monitor.
Table 3-5. AMBA AHB Master Monitor Statistics
Statistic
Description
Total Transfers
51
Monitor Connectivity
Connect the AHB target monitor pins to internal signals as specified in the pin-out Table 3-6
and illustrated in Figure 3-4.
Note that the AHB target monitor does not support locked transfers.
Figure 3-4. AHB Target Monitor Pins Diagram
hresetn
hclk
hselx
haddr[31:0]
hwrite
htrans[1:0]
hsize[2:0]
hburst[2:0]
hwdata[DATA_BUS_WIDTH 1:0]
hrdata[DATA_BUS_WIDTH 1:0]
hready_in
hready_out
hresp[1:0]
hmaster[3:0]
hmastlock
hsplitx[NUMBER_OF_MASTERS 1:0]
AMBA
AHB Target
Monitor
52
Pin
Description
haddr[31:0]
hburst[2:0]
hclk
Description
hmaster[3:0]
hmastlock
hrdata[DATA_BUS_WIDTH 1:0]
Read data bus. Transfers data from target to master via a read
operation.
hready_in
hready_out
hresetn
Active low bus reset signal. Resets the system and the bus.
hresp[1:0]
hselx
hsize[2:0]
hsplitx[NUMBER_OF_MASTERS 1:0]
htrans[1:0]
hwdata[DATA_BUS_WIDTH 1:0]
hwrite
Monitor Parameters
The parameters shown in Table 3-7 configure the corresponding AHB target monitor.
Table 3-7. AMBA AHB Target Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
DATA_BUS_WIDTH
32
3.
NUMBER_OF_MASTERS
16
4.
CANCEL_FOLLOWING_
TRANSFER_ON_ERROR_
RESPONSE
53
Default Description
5.
Over_Constraints_Mode
6.
DISABLE_CHKS_ON_IDLE
Note:
For the Over_constraints_Mode set to 1, the AMBA AHB target monitor has the following
additional constraints:
54
Note that if using the AHB target monitor with an AHB-Lite target, then the user must tie the
hresp[1] signal to low (1'b0).
Monitor Checks
Table 3-8 shows the checks performed by an AHB target monitor.
Table 3-8. AMBA AHB Target Checks
Check ID
Violation
Description
AHB_T1
AHB_T2
AHB_T3
AHB_T4
AHB_T5
AHB_T6
55
56
Check ID
Violation
Description
AHB_T7
AHB_T8
AHB_T9
AHB_T10
AHB_T11
AHB_T12
AHB_T13
AHB_T14
Violation
Description
AHB_T15
AHB_T16
AHB_T17
AHB_T18
AHB_T19
AHB_T20
AHB_T21
57
58
Check ID
Violation
Description
AHB_T22
AHB_T23
AHB_T24
AHB_T25
AHB_T26
Violation
Description
AHB_T27
AHB_T28
AHB_T29_hselx,
AHB_T29_hwrite,
AHB_T29_htrans,
AHB_T29_hsize,
AHB_T29_hburst,
AHB_T29_hmaster,
AHB_T29_hmastlock,
AHB_T29_hready_in,
AHB_T29_hready_out,
AHB_T29_hresp,
AHB_T29_hsplitx
AHB_T30_haddr
AHB_T31
AHB_T32
AHB_T33
AHB_T34
AHB_T35
AHB_T36
AHB_T37
AHB_TX
59
Description
Read Transfers
Write Transfers
IDLE Transfers
BUSY Transfers
OKAY Responses
ERROR Responses
RETRY Responses
SPLIT Responses
60
Monitor Statistics
Table 3-10 shows the statistics maintained by the AHB target monitor.
Table 3-10. AMBA AHB Target Monitor Statistics
Statistic
Description
Total Transfers
61
APB Monitor
AMBA Advanced Peripheral Bus (APB) is for low power peripherals. AMBA APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. APB can be used in conjunction with the AHB system bus.
Monitor Connectivity
Connect the APB monitor pins to internal signals as specified in the pin-out Table 3-11 and
illustrated in Figure 3-5.
Figure 3-5. APB Monitor Pins Diagram
pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]
AMBA
APB Monitor
62
Pin
Description
paddr
pclk
APB clock.
penable
prdata
presetn
pselx
pwdata
pwrite
Encoding for the type of transfer: HIGH for write transfers and LOW
for read transfers.
Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.
Monitor Parameters
The parameters shown in Table 3-12 configure the corresponding APB monitor.
Table 3-12. AMBA APB Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode
2.
ADD_BUS_WIDTH
32
3.
DATA_BUS_WIDTH
32
Width of PRDATA and PWDATA buses. The default (32bits) is the maximum width supported by the APB
interface.
0,
24,
16
63
Monitor Checks
Table 3-13 shows the checks performed by the APB monitor.
Table 3-13. AMBA APB Checks
64
Check ID
Violation
Description
APB_01
APB_02
APB_03
APB_04
APB_06
APB_07
APB_08
APB_09_pselx
APB_09_penable
APB_09_pwrite
APB_10
APB_11
APB_12_paddr
APB_12_pwrite
Description
Read Transfers
Write Transfers
Back-to-back Transfers
Monitor Statistics
Table 3-15 shows the statistics maintained by the APB monitor.
Table 3-15. AMBA APB Monitor Statistics
Statistic
Description
Total Transfers
65
66
Chapter 4
AMBA 3 Advanced Peripheral Bus (APB)
Introduction
AMBA 3 Advanced Peripheral Bus (APB) is for low power peripherals. AMBA 3 APB is
optimized for minimal power consumption and reduced interface complexity to support
peripheral functions. AMBA 3 APB can be used in conjunction with the AHB and the AXI
system bus.
Reference Documentation
This version of the AMBA 3 APB monitor is modeled from the requirements provided in the
following document:
Monitor Connectivity
Connect the AMBA 3 APB monitor pins as specified in the pin out Table 4-1 and illustrated in
Figure 4-1.
Figure 4-1. AMBA 3 APB Monitor Pins Diagram
pclk
presetn
paddr[ADD_BUS_WIDTH 1:0]
pwrite
pselx
penable
pwdata[DATA_BUS_WIDTH 1:0]
prdata[DATA_BUS_WIDTH 1:0]
pready
pslverr
AMBA 3
APB Monitor
67
Description
paddr
pclk
penable
prdata
presetn
pselx
pwdata
pwrite
Encoding for the type of transfer: HIGH for write transfers and LOW for read
transfers.
pready
pslverr
Note that the pwdata and prdata buses can be implemented together as a single bidirectional
bus with tri-state capability. Under this configuration, connect the single data bus to both the
pwdata and prdata inputs of the interface monitor.
Monitor Parameters
The parameters shown in Table 4-2 configure the AMBA 3 APB monitor.
Table 4-2. AMBA 3 APB Monitor Parameter
Order Parameter
Default Description
1.
Constraints_Mode
2.
ADD_BUS_WIDTH
32
3.
DATA_BUS_WIDTH
32
4.
INTERFACE_TYPE
68
Default Description
5.
SLAVE_COUNT
6.
RECOMMENDED_CHECKS_OFF
Monitor Checks
Table 4-3 shows the checks performed by the AMBA 3 APB monitor.
Table 4-3. AMBA 3 APB Monitor Checks
Check ID
Violation
AMBA3_APB_01
The bus should advance to SETUP When the bus is in the IDLE state, it can
state or remain in IDLE state, but advance to the SETUP state or remain in the
went to ACCESS state.
IDLE state. Advancing to ACCESS state
causes this check to fire.
Description
69
70
Check ID
Violation
Description
AMBA3_APB_02
AMBA3_APB_03
AMBA3_APB_04
AMBA3_APB_UNKN
AMBA3_APB_06
AMBA3_APB_07
AMBA3_APB_08
AMBA3_APB_09_pselx
AMBA3_APB_09_penable
AMBA3_APB_09_pwrite
AMBA3_APB_09_pready
AMBA3_APB_09_pslverr
AMBA3_APB_10
AMBA3_APB_11
AMBA3_APB_12_paddr
Violation
Description
AMBA3_APB_12_pwrite
AMBA3_APB_13
AMBA3_APB_14
AMBA3_APB_15
Description
Read Transfers
Write Transfers
Monitor Statistics
Table 4-5 shows the statistics maintained by the AMBA 3 APB monitor.
Table 4-5. AMBA 3 APB Protocol Statistics
Statistic
Description
Total Transfers
71
72
Statistic
Description
Transfer Failures
Number of transactions that got pslverr asserted during the access phase.
Chapter 5
AMBA AXI
Introduction
The AXI is the latest generation AMBA interface, targeted at high-performance, high-frequency
system designs and includes a number of features that make it suitable for a high-speed
submicron interconnect. The QVL AMBA AXI monitor is designed for checking the AXI
interface.
Reference Documentation
This version of the AMBA AXI monitor is modeled from the requirements provided in the
following document:
Supported Features
Channel Handshake
Channel handshake.
Channel dependencies.
Addressing options
Atomic Accesses
Exclusive accesses.
Locked transactions.
Response Signaling
73
AMBA AXI
Monitor Placement and Instantiation
Completions
Data buses
Write strobes.
Unaligned transfers.
Unsupported Features
The monitor will assume the data as-is and will not perform endianness conversion.
AXI Monitor
INTERFACE_TYPE=0
AXI Monitor
INTERFACE_TYPE=1
AXI Interconnect
Refer to Table 5-2 on page 77, the INTERFACE_TYPE parameter, for descriptions on
monitor instantiations A, B, C, and D.
74
AMBA AXI
Monitor Connectivity
Monitor Connectivity
Connect the AMBA AXI monitor pins as specified in the pin out Table 5-1 and illustrated in
Figure 5-2.
bid[3:0]
bresp[1:0]
bvalid
bready
READ CHANNEL
WRITE RESP.
aclk
areset_n
reset_n
rvalid
rready
AMBA AXI
Monitor
csysreq
csysack
cactive
wid
wdata
wstrb
wlast
wvalid
wready
L.P. I.
awid[3:0]
awaddr
awlen
awsize[2:0]
awburst[1:0]
awlock[1:0]
awcache[3:0]
awprot[2:0]
awvalid
awready
rid[3:0]
rdata
rresp[1:0]
rlast
WRITE CHANNEL
arid[3:0]
araddr
arlen
arsize[2:0]
arburst[1:0]
arlock[1:0]
arcache[3:0]
arprot[2:0]
arvalid
arready
GLOBAL
Description
aclk
Global clock signal (all signals are sampled on the rising edge of global clock).
araddr
arburst[1:0]
75
AMBA AXI
Monitor Connectivity
76
Port
Description
arcache[3:0]
areset_n
arid
arlen
arlock[1:0]
arprot[2:0]
arready
arsize[2:0]
arvalid
awaddr
awburst[1:0]
awcache[3:0]
awid
awlen
awlock[1:0]
awprot[2:0]
awready
awsize[2:0]
awvalid
bid
bready
bresp[1:0]
bvalid
cactive
Clock active (peripheral device requires clock signal). Connect it to 1'b1 for normal
operation.
csysack
csysreq
rdata
reset_n
Synchronous reset signal (This active low signal is not part of standard AXI I/F).
rid
rlast
rready
AMBA AXI
Monitor Connectivity
Description
rresp[1:0]
rvalid
wdata
Write data (write data bus - 8-, 16-, 32-, .... 1024-bits).
wid
wlast
wready
wstrb
Write strobe (write data strobe - 1 bit for each 8-bits of write data bus).
wvalid
Note that the widths of data buses and transaction IDs are implementation specific. Refer to the
Monitor Parameters section below for the appropriate parameter that defines the widths of these
signals.
Monitor Parameters
The parameters shown in Table 5-2 configure the AMBA AXI monitor.
Table 5-2. AMBA AXI Monitor Parameter
Order Parameter
Default Description
1.
Constraints_Mode
2.
INTERFACE_TYPE
3.
WRITE_DATA_BUS_WIDTH
32
4.
READ_DATA_BUS_WIDTH
32
5.
TRAN_ID_WIDTH
6.
READ_REORDER_DEPTH
77
AMBA AXI
Monitor Connectivity
78
Order Parameter
Default Description
7.
READ_INTERLEAVING_DEPTH
8.
WRITE_INTERLEAVING_DEPTH
9.
EXCLUSIVE_ACCESS_ENABLE
10.
LPI_ENABLE
11.
MAX_OUTSTANDING_READ_
ADDR
16
12.
MAX_OUTSTANDING_WRITE_
ADDR
16
13.
CHECK_WRITE_DATA_
FOLLOWS_ADDR_ENABLE
14.
ENABLE_RESERVED_VALUE_
CHECKING
15.
ENABLE_RECOMMENDATION_
CHECKING
16.
LENGTH_WIDTH
17.
ADDR_WIDTH
32
18.
MAX_UNIQUE_EXCLUSIVE_
ACCESS
16
19.
EXCLUSIVE_READ_RESPONSE_
CHECKING_ENABLE
AMBA AXI
Monitor Connectivity
Default Description
20.
DATA_X_Z_CHECK_ENABLE
21.
ALLOW_SLAVE_ERROR_
RESPONSE_AGAINST_
EXCLUSIVE_ACCESS
22.
MAX_OUTSTANDING_WRITE_
DATA
23.
ENABLE_AWLEN_CHECK_
AGAINST_COMPLETED_DATA_
BEFORE_ADDRESS
79
AMBA AXI
Monitor Connectivity
0,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
1,
/* ENABLE_RESERVED_VALUE_CHECKING */
1,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);
80
AMBA AXI
Monitor Connectivity
Example 2
Example 5-2 instantiates an AMBA AXI monitor on an AMBA AXI slave interface with read
and write channels having different widths of 8-bits and 32-bits, respectively, and the width of
all the IDs is 4 and a maximum of 16 outstanding read and 16 outstanding write addresses. The
read reorder depth is taken as 8 and therefore, is the write data interleaving depth. Exclusive
access support and low power interface support are enabled. Checks pertaining to reserved
values and recommendations are disabled.
Example 5-2. AMBA AXI Monitor Instantiation for Example 2
qvl_amba_axi_monitor #(
1,
/* Constraints_Mode */
1,
/* INTERFACE_TYPE */
32,
/* WRITE_DATA_BUS_WIDTH */
8,
/* READ_DATA_BUS_WIDTH */
4,
/* TRAN_ID_WIDTH */
8,
/* READ_REORDER_DEPTH */
8,
/* READ_INTERLEAVING_DEPTH */
8,
/* WRITE_INTERLEAVING_DEPTH */
1,
/* EXCLUSIVE_ACCESS_ENABLE */
1,
/* LPI_ENABLE */
16,
/* MAX_OUTSTANDING_READ_ADDR */
16,
/* MAX_OUTSTANDING_WRITE_ADDR */
1,
/* CHECK_WRITE_DATA_FOLLOWS_ADDR_ENABLE */
0,
/* ENABLE_RESERVED_VALUE_CHECKING */
0,
/* ENABLE_RECCOMENDATION_CHECKING */
4,
/* LENGTH_WIDTH */
32
/* ADDR_WIDTH */
)
AMBA_AXI_MONITOR
(.aclk(aclk),
.areset_n(areset_n),
.reset_n(!reset),
.arvalid(arvalid),
.araddr(araddr),
.arlen(arlen),
.arsize(arsize),
.arburst(arburst),
.arlock(arlock),
.arcache(arcache),
.arprot(arprot),
.arid(arid),
.arready(arready),
.awvalid(awvalid),
.awaddr(awaddr),
.awlen(awlen),
.awsize(awsize),
.awburst(awburst),
.awlock(awlock),
.awcache(awcache),
.awprot(awprot),
.awid(awid),
.awready(awready),
.wvalid(wvalid),
81
AMBA AXI
Monitor Checks
.wlast(wlast),
.wdata(wdata),
.wstrb(wstrb),
.wid(wid),
.wready(wready),
.rvalid(rvalid),
.rlast(rlast),
.rdata(rdata),
.rresp(rresp),
.rid(rid),
.rready(rready),
.bvalid(bvalid),
.bresp(bresp),
.bid(bid),
.bready(bready),
.cactive(cactive),
.csysreq(csysreq),
.csysack(csysack)
);
Monitor Checks
Table 5-3 shows the general checks performed by the AMBA AXI monitor.
Table 5-3. AMBA AXI Monitor Checks
82
Check ID
Violation
Description
AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_READ_
SEQUENCE
AMBA_AXI_ADDR_ACROSS_
4K_WITHIN_LOCKED_WRITE_
SEQUENCE
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_ADDR_FOR_
READ_BURST_ACROSS_4K_
BOUNDARY
AMBA_AXI_ADDR_FOR_
WRITE_BURST_ACROSS_4K_
BOUNDARY
AMBA_AXI_ARADDR_UNKN
AMBA_AXI_ARBURST_UNKN
AMBA_AXI_ARCACHE_UNKN
AMBA_AXI_ARID_CHANGED_
WITHIN_LOCKED_READ_
SEQUENCE
AMBA_AXI_ARID_UNKN
ARID signal should not be X Checks that ARID is both known (not X)
or Z.
and driven (not Z). This check is active
only when ARVALID is high.
AMBA_AXI_ARLEN_UNKN
ARLEN signal should not be Checks that ARLEN is both known (not X)
X or Z.
and driven (not Z). This check is active
only when ARVALID is high.
AMBA_AXI_ARLOCK_UNKN
AMBA_AXI_ARPROT_
ARCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE
It is recommended that a
master should not change
ARPROT or ARCACHE
during a sequence of locked
accesses.
83
AMBA AXI
Monitor Checks
84
Check ID
Violation
Description
AMBA_AXI_ARPROT_UNKN
AMBA_AXI_ARREADY_UNKN
AMBA_AXI_ARSIZE_UNKN
AMBA_AXI_ARVALID_
DEASSERTED_BEFORE_
ARREADY
AMBA_AXI_ARVALID_UNKN
ARVALID signal should not Checks that ARVALID is both known (not
be X or Z.
X) and driven (not Z).
AMBA_AXI_AWADDR_UNKN
AWADDR signal should not Checks that AWADDR is both known (not
be X or Z.
X) and driven (not Z). This check is active
only when AWVALID is high.
AMBA_AXI_AWBURST_UNKN
AMBA_AXI_AWCACHE_UNKN
AMBA_AXI_AWID_CHANGED_
WITHIN_LOCKED_WRITE_
SEQUENCE
AMBA_AXI_AWID_UNKN
AMBA_AXI_AWLEN_
MISMATCHED_WITH_
ACTUAL_LENGTH_OF_WRITE_
DATA_BURST
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_AWLEN_UNKN
AMBA_AXI_AWLOCK_UNKN
AMBA_AXI_AWPROT_
AWCACHE_CHANGED_
WITHIN_LOCKED_SEQUENCE
It is recommended that a
master should not change
AWPROT or AWCACHE
during a sequence of locked
accesses.
AMBA_AXI_AWPROT_UNKN
AMBA_AXI_AWREADY_UNKN
AMBA_AXI_AWSIZE_UNKN
AMBA_AXI_AWVALID_
DEASSERTED_BEFORE_
AWREADY
AMBA_AXI_AWVALID_UNKN
AMBA_AXI_BID_CHANGED_
BEFORE_BREADY
AMBA_AXI_BID_UNKN
AMBA_AXI_BREADY_UNKN
85
AMBA AXI
Monitor Checks
86
Check ID
Violation
Description
AMBA_AXI_BRESP_UNKN
AMBA_AXI_BVALID_
DEASSERTED_BEFORE_
BREADY
AMBA_AXI_BVALID_UNKN
AMBA_AXI_CACTIVE_UNKN
AMBA_AXI_CSYSACK_
ASSERTION_VIOLATION
AMBA_AXI_CSYSACK_
DEASSERTION_VIOLATION
To request that the peripheral enter a lowpower state, the system clock controller
drives the CSYSREQ signal low. Only
then the peripheral can drive the
CSYSACK signal low to acknowledge the
entry to low-power state. This check fires
if this relationship is violated. This check
is active only when LPI_ENABLE is set to
1.
AMBA_AXI_CSYSACK_UNKN
AMBA_AXI_CSYSREQ_
ASSERTION_VIOLATION
Once de-asserted,
CSYSREQ should not be
asserted before CSYSACK
acknowledged the request
for entry into the low-power
state.
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_CSYSREQ_
DEASSERTION_VIOLATION
AMBA_AXI_CSYSREQ_UNKN
CSYSREQ signal should not Checks that CSYSREQ is both known (not
be X or Z.
X) and driven (not Z). This check is active
only when the parameter LPI_ENABLE is
set to 1.
AMBA_AXI_DATA_ISSUED_
EXCEEDS_MAX_ALLOWED_
OUTSTANDING_DATA_
BEFORE_ADDRESS
AMBA_AXI_DECODE_ERROR_
RESPONSE_BY_SLAVE
AMBA_AXI_EX_WRITE_
BEFORE_EX_READ_RESPONSE
AMBA_AXI_EXCLUSIVE_
ACCESS_ADDRESS_
VIOLATION
87
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_EXCLUSIVE_
ACCESS_WHILE_EXCLUSIVE_
ACCESS_NOT_SUPPORTED
Exclusive access may not be This check fires if the exclusive access is
tried by a master as the
tried by a master as the exclusive access
exclusive access
functionality is set.
functionality is configured to
be not supported by setting
EXCLUSIVE_ACCESS_
ENABLE to 0
AMBA_AXI_EXCLUSIVE_
READ_ACCESS_CACHEABLE
AMBA_AXI_EXCLUSIVE_
READ_RESPONSE_MISMATCH
88
AMBA_AXI_EXCLUSIVE_
READ_SIZE_EXCEEDS_128
AMBA_AXI_EXCLUSIVE_
READ_SIZE_NON_POWER_
OF_2
AMBA_AXI_EXCLUSIVE_
WRITE_ACCESS_CACHEABLE
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_EXCLUSIVE_
WRITE_SIZE_NON_POWER_
OF_2
AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_READ_
BURST
AMBA_AXI_ILLEGAL_
LENGTH_WRAPPING_WRITE_
BURST
AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_READ
AMBA_AXI_ILLEGAL_
RESPONSE_EXCLUSIVE_
WRITE
AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_READ
An EXOKAY response
should not be returned for a
normal (nonexclusive) read
operation.
89
AMBA AXI
Monitor Checks
90
Check ID
Violation
Description
AMBA_AXI_ILLEGAL_
RESPONSE_NORMAL_WRITE
An EXOKAY response
should not be returned for a
normal (nonexclusive) write
operation.
AMBA_AXI_INCORRECT_
LOW_POWER_SIGNAL_LEVEL
Any of the low power signal For low power interface disabled, the three
is not tied HIGH for disabled low power interface signals must be tied to
low power configuration.
HIGH. This check fires when any of the
low power interface signals is not sampled
HIGH.
AMBA_AXI_LOCKED_READ_
BEFORE_COMPLETION_OF_
PREVIOUS_READS
AMBA_AXI_LOCKED_READ_
BEFORE_COMPLETION_OF_
PREVIOUS_WRITES
AMBA_AXI_LOCKED_WRITE_
BEFORE_COMPLETION_OF_
PREVIOUS_READS
AMBA_AXI_LOCKED_WRITE_
BEFORE_COMPLETION_OF_
PREVIOUS_WRITES
AMBA_AXI_NUMBER_OF_
LOCKED_READ_ACCESSES_
EXCEEDS_2
AMBA AXI
Monitor Checks
Violation
AMBA_AXI_NUMBER_OF_
LOCKED_WRITE_ACCESSES_
EXCEEDS_2
AMBA_AXI_PARAM_READ_
DATA_BUS_WIDTH
READ_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.
AMBA_AXI_PARAM_WRITE_
DATA_BUS_WIDTH
WRITE_DATA_BUS_
WIDTH parameter should
be one of 8, 16, 32, 64, 128,
256, 512, or 1024.
AMBA_AXI_READ_ADDR_
BEFORE_COMPLETION_OF_
UNLOCK_TRANSACTION
AMBA_AXI_READ_ADDR_
CNTRL_CHANGED_BEFORE_
ARREADY
AMBA_AXI_READ_
ALLOCATE_WHEN_NON_
CACHEABLE
AMBA_AXI_READ_BURST_
LENGTH_VIOLATION
Description
91
AMBA AXI
Monitor Checks
92
Check ID
Violation
Description
AMBA_AXI_READ_BURST_
SIZE_VIOLATION
AMBA_AXI_READ_DATA_
BEFORE_ADDRESS
AMBA_AXI_READ_DATA_
RESP_CHANGED_BEFORE_
RREADY
AMBA_AXI_READ_DATA_
UNKN
AMBA_AXI_READ_
INTERLEAVE_DEPTH_
VIOLATION
AMBA_AXI_READ_REORDER_
DEPTH_VIOLATION
AMBA_AXI_RESERVED_
ARLOCK_ENCODING
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_RESERVED_
AWLOCK_ENCODING
AMBA_AXI_RESERVED_
READ_BURST_TYPE
AMBA_AXI_RESERVED_
WRITE_BURST_TYPE
AMBA_AXI_RID_CHANGED_
BEFORE_RREADY
AMBA_AXI_RID_UNKN
AMBA_AXI_RLAST_
CHANGED_BEFORE_RREADY
AMBA_AXI_RLAST_UNKN
93
AMBA AXI
Monitor Checks
94
Check ID
Violation
Description
AMBA_AXI_RLAST_
VIOLATION
AMBA_AXI_RREADY_UNKN
AMBA_AXI_RRESP_UNKN
AMBA_AXI_RVALID_
DEASSERTED_BEFORE_
RREADY
AMBA_AXI_RVALID_UNKN
AMBA_AXI_SIMULTANEOUS_
LOCK_WRITE_AND_LOCK_
READ_ACCESS
AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
READ_BURST
Starting address of a
wrapping read burst should
be aligned to the size of the
transfer.
AMBA_AXI_UNALIGNED_
ADDR_FOR_WRAPPING_
WRITE_BURST
Starting address of a
wrapping write burst should
be aligned to the size of the
transfer.
AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
READ
AMBA_AXI_UNALIGNED_
ADDRESS_FOR_EXCLUSIVE_
WRITE
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
READS
AMBA_AXI_UNLOCKED_
READ_WHILE_
OUTSTANDING_LOCKED_
WRITES
AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
READS
AMBA_AXI_UNLOCKED_
WRITE_WHILE_
OUTSTANDING_LOCKED_
WRITES
95
AMBA AXI
Monitor Checks
96
Check ID
Violation
Description
AMBA_AXI_UNLOCKING_
TRANSACTION_WITH_AN_
EXCLUSIVE_ACCESS
AMBA_AXI_VALID_HIGH_ON_
FIRST_CLOCK
AMBA_AXI_WID_CHANGED_
BEFORE_WREADY
AMBA_AXI_WID_UNKN
AMBA_AXI_WLAST_
CHANGED_BEFORE_WREADY
AMBA_AXI_WLAST_
ASSERTED_DURING_DATA_
PHASE_OTHER_THAN_LAST
AMBA_AXI_WLAST_UNKN
AMBA_AXI_WREADY_UNKN
AMBA AXI
Monitor Checks
Violation
Description
AMBA_AXI_WRITE_ADDR_
BEFORE_COMPLETION_OF_
UNLOCK_TRANSACTION
AMBA_AXI_WRITE_ADDR_
CNTRL_CHANGED_BEFORE_
AWREADY
Once AWVALID is
asserted, the write
address/control signals
{awaddr, awlen, awsize,
awburst, awlock, awcache,
awprot, awid} should not
change until AWREADY is
asserted.
AMBA_AXI_WRITE_ADDRESS_
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED
AMBA_AXI_WRITE_
ALLOCATE_WHEN_
NON_CACHEABLE
AMBA_AXI_WRITE_BURST_
SIZE_VIOLATION
AMBA_AXI_WRITE_DATA_
BEFORE_ADDRESS
97
AMBA AXI
Monitor Checks
98
Check ID
Violation
Description
AMBA_AXI_WRITE_DATA_
PHASE_WHILE_MAXIMUM_
OUTSTANDING_WRITES_
ALREADY_REACHED
AMBA_AXI_WRITE_DATA_
REORDER_DEPTH_VIOLATION
AMBA_AXI_WRITE_DATA_
STROBE_CHANGED_BEFORE_
WREADY
AMBA_AXI_WRITE_DATA_
UNKN
AMBA_AXI_WRITE_
INTERLEAVE_DEPTH_
VIOLATION
AMBA_AXI_WRITE_RESP_
CHANGED_BEFORE_BREADY
AMBA_AXI_WRITE_
RESPONSE_VALID_
WITHOUT_DATA
AMBA AXI
Monitor Corner Cases
Violation
Description
AMBA_AXI_WRITE_
RESPONSE_WITHOUT_ADDR
Write response should not be This check fires whenever a write response
sent before the
is detected for which the corresponding
corresponding address is
address has not been already received.
completed.
This check is active only if the
CHECK_WRITE_DATA_FOLLOWS_
ADDR_ENABLE parameter is set to 1.
AMBA_AXI_WRITE_
RESPONSE_WITHOUT_DATA
AMBA_AXI_WRITE_STROBE_
ON_INVALID_BYTE_LANES
AMBA_AXI_WSTRB_UNKN
AMBA_AXI_WVALID_
DEASSERTED_BEFORE_
WREADY
AMBA_AXI_WVALID_UNKN
Description
99
AMBA AXI
Monitor Corner Cases
Description
Cacheable write-through read allocate Number of cacheable write-through read allocatable read
reads
accesses.
Cacheable write-through read and
write allocatable reads
Normal nonsecure data write accesses Number of normal nonsecure data write accesses. This relates
to protection levels specified by AWPROT[2:0].
100
AMBA AXI
Monitor Corner Cases
Description
Privileged nonsecure instruction write Number of privileged secure instruction write accesses. This
access
relates to protection levels specified by AWPROT[2:0].
Privileged secure data read accesses
Read addresses
Write addresses
101
AMBA AXI
Monitor Statistics
Description
Monitor Statistics
Table 5-5 shows the statistics maintained by the AMBA AXI monitor.
Table 5-5. AMBA AXI Protocol Statistics
Statistic
Description
Locked write sequences exceeding two accesses Number of times more than two write transactions were
performed within a locked write sequence.
102
Chapter 6
Double Data Rate SDRAM (DDR SDRAM)
Introduction
The QVL Double Data Rate SDRAM (DDR SDRAM) monitor provides a method of debugging
DDR SDRAM system designs by checking that the operation of the design is compliant with
the JEDEC standard. This monitor can also be configured for custom requirements. The
monitor can be used to guarantee that your controller design cannot perform an illegal operation
to the memory subsystem.
The DDR SDRAM monitor tracks all operations to the DDR SDRAM subsystem for a single
row of DDR SDRAMs. To check multiple memory rows, the user can instantiate multiple
instances of the DDR SDRAM monitor. Each DDR SDRAM monitor instance checks
operations on a virtual four-bank DDR SDRAM by monitoring the states of each bank, and by
setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR SDRAM monitor instance determines illegal command sequences by comparing
bank-state against command issues. Checks for illegal commands and cycle-based timing
problems can be used as search targets. Use formal analysis to find legal stimulus sequences
(that is, corner-case behavior) that direct your controller design to violate legal DDR SDRAM
memory subsystem operations.
V1.0 Monitor
Reference Documentation
This DDR SDRAM monitor is modeled from the requirements provided in the following
documents:
Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM,
2M32DDR-07.p65-Rev. 9/01.
Burst lengths 2, 4, 8, 16, 32, 64, 128 and Full Page Mode (FPM).
103
Full Page mode burst and CAS Latency of 4 in NON JEDEC mode.
DLL enable/disable.
Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.
104
Address
address
pipe
Control
control
DDR SDRAM
Memory
Application
Interface
Controller
DDR SDRAM
Memory
data
in/out
Data
Monitor Connectivity
Connect the DDR SDRAM monitor pins to internal signals of the target design as specified in
the pin-out Table 6-1 and illustrated in Figure 6-2. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.
105
clock
clock_n
reset
areset
CKE[CS_CKE_WIDTH - 1:0]
CS_n[CS_CKE_WIDTH - 1:0]
RAS_n
CAS_n
WE_n
BA[1:0]
A[ADDR_WIDTH - 1:0]
DM[DM_WIDTH - 1:0]
DQ[DATA_WIDTH - 1:0]
DQS
mode_register
extended_mode_register
DDR SDRAM
Monitor
106
Pin
Description
A[ADDR_WIDTH 1:0]
Address.
areset
BA[1:0]
Bank address.
CAS_n
CKE[CS_CKE_WIDTH - 1:0]
clock
clock_n
CS_n[CS_CKE_WIDTH - 1:0]
DM[DM_WIDTH - 1:0]
DQ[DATA_WIDTH - 1:0]
Data lines.
DQS
Data strobe.
Description
extended_mode_register[ADDR_WIDTH 1:0]
mode_register[ADDR_WIDTH +1:0]
RAS_n
reset
WE_n
Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM monitor only supports tdqss
values equal to the clock period. This means that the DQS signal edges should be in line with
the clock signal for formal analysis. The monitor supports tdqss values from 75% to 125% of
the total clock period.
If the memory controller supports n DDR SDRAMs stacked by data width (for a total
data width of n x width and memory size mem), then connect only one instance of the
monitor to track the controller. Set the CS_CKE_WIDTH parameter to the width of the
CS_n and CKE pins.
If the memory controller supports n DDR SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller. The CS_n and CKE pins of each monitor are connected
to the appropriate bits of the controllers chip select and clock enable pins.
Use the above scheme also when stacking by both data width and address width.
107
DDR SDRAM
Memory Controller
DDR SDRAM
Monitor
Address
...
DDR SDRAM
Memory #1
DDR SDRAM
Memory #2
...
DDR SDRAM
Memory #n
DDR SDRAM
Memory Controller
DDR SDRAM
Memory #1
Address
DDR SDRAM
Memory #2
...
...
DDR SDRAM
Monitor
Address
...
DDR SDRAM
Monitor
DDR SDRAM
Monitor
Address
DDR SDRAM
Memory #n
Monitor Parameters
The parameters shown in Table 6-2 configure the corresponding DDR SDRAM monitor. The
override parameters set timing parameters for the monitor. Refer to Table 6-5 for the JEDEC
standard compliant values of the parameters, which are used as default values.
Table 6-2. DDR SDRAM Monitor Parameters
Order
Parameter
Default Description
1.
Constraints_Mode
108
Parameter
Default Description
2.
CONTROLLER_SIDE
3.
CS_CKE_WIDTH
4.
ADDR_WIDTH
12
5.
DM_WIDTH
6.
DATA_WIDTH
7.
DLL_TRACKING_ENABLE
8.
TRC_OVERRIDE
9.
TRAS_OVERRIDE
10.
TRP_OVERRIDE
11.
TRCD_OVERRIDE
12.
TRRD_OVERRIDE
13.
TMRD_OVERRIDE
109
Parameter
Default Description
14.
TRFC_OVERRIDE
15.
TXSNR_OVERRIDE
16.
TXSRD_OVERRIDE
17.
TWR_OVERRIDE
18.
TWTR_OVERRIDE
19.
AUTOPRECHARGE_ENABLE_
ADDRESS_BIT
10
20.
COL_ADDRESS_WIDTH
21.
READ_BEFORE_WRITE_
CHECK_ENABLE
22.
CON_AUTO_PRECHARGE
23.
ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK
110
Parameter
Default Description
24.
BYPASS_INIT
25.
NON_JEDEC
26.
DATA_CHECK_ENABLE
111
JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-3.
Table 6-3. JEDEC Mode Burst Length Configuration
A[2:0]
BURST LENGTH
000
RSVD
001
010
011
100
16
101
32
110
64
111
128
CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-4.
Table 6-4. JEDEC Mode CAS Latency Configuration
A[6:4]
CAS LATENCY
000
RSVD
001
1.0
010
2.0
011
3.0
100
0.5
101
1.5
110
2.5
111
RSVD
When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do the following:
112
TRC_OVERRIDE
TRAS_OVERRIDE
TRP_OVERRIDE
TRCD_OVERRIDE
TRRD_OVERRIDE
TMRD_OVERRIDE
TRFC_OVERRIDE
10
TXSNR_OVERRIDE
10
TXSRD_OVERRIDE
200
TWR_OVERRIDE
TWTR_OVERRIDE
Instantiation Examples
Example 1
Example 6-1 instantiates a JEDEC standard compliant DDR SDRAM monitor on the DDR
SDRAM controller side for unconstraint search with CS_CKE_WIDTH of 1, ADDR_WIDTH of 12,
DM_WIDTH of 1, DATA_WIDTH of 8, 8th bit of Address line as Auto precharge enable, Lower 8
Column Address lines are to be used for Full Page Mode burst, and DLL_TRACKING_ENABLE set
to 1.
Note that all timing parameters are the default values specified by JEDEC. The monitor is in
normal mode of operation, which enables the monitor to track the initialization sequence.
Example 6-1. DDR SDRAM Monitor Instantiated in the Controller
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */
0,
1,
1,
12,
1,
113
Example 2
Example 6-2 instantiates two DDR SDRAM monitors for a JEDEC standard DDR SDRAM
controller design. The example has the following characteristics:
The controller design interfaces two stacked DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.
CS_CKE_WIDTH
ADDR_WIDTH
DM_WIDTH
of 12.
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* CS_CKE_WIDTH */
/* ADDR_WIDTH */
/* DM_WIDTH */
/* DATA_WIDTH */
DDR_SDRAM_MONITOR0 (
.clock
(clock),
114
0,
1,
2,
12,
2,
16)
Example 3
Example 6-3 instantiates a DDR SDRAM monitor for a Micron 64 Mb compatible controller
design. The example has the following characteristics:
The controller design interfaces a DDR SDRAM having 32-bit DATA_WIDTH and 11-bit
ADDR_WIDTH.
1-bit CS_CKE_WIDTH.
DM_WIDTH
115
TRAS
7
TXSNR
10
TRP
3
TXSRD
200
TRCD
3
TWR
2
TRRD
2
TWTR
1
TMRD
2
FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* CS_CKE_WIDTH */
1,
/* ADDR_WIDTH */
12,
/* DM_WIDTH */
1,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
/* TXSNR_OVERRIDE */
10,
/* TXSRD_OVERRIDE */
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
116
The monitor is instantiated with BYPASS_INIT = 1 and the internal signals are connected to
the monitor ports mode_register and extended_mode_register.
Example 4
Example 6-4 on page 117 instantiates a DDR SDRAM monitor to check a controller with NON
JEDEC timing parameter values. The example has the following characteristics:
The controller design interfaces a DDR SDRAM having 32-bit DATA_WIDTH and 11-bit
ADDR_WIDTH.
1-bit CS_CKE_WIDTH.
DM_WIDTH
The timing parameters are set to NON JEDEC values. Therefore, the NON_JEDEC
parameter is 1. The NON JEDEC timing parameter values are as follows
TRC
12
TRFC
16
TRAS
9
TXSNR
14
TRP
4
TXSRD
300
TRCD
4
TWR
3
TRRD
5
TWTR
1
TMRD
3
Example 6-4. DDR SDRAM Monitor Instantiated with NON JEDEC Timing
Parameter Values
qvl_ddr_sdram_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
0,
1,
117
The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
118
Monitor Checks
Table 6-6 shows the checks performed by a DDR SDRAM monitor.
Table 6-6. DDR SDRAM Monitor Checks
Check ID
Violation
Description
DDR_SDRAM_ADDRESS
DDR_SDRAM_BA
Bank address bus, BA, has a X Bank address bus, BA, should have a
or Z value.
valid value when read/write/read with
auto precharge/write with auto
precharge/bank activation/single bank
precharge command is issued.
DDR_SDRAM_BYPASS_INIT
BYPASS_INIT should be
either 1 or 0.
DDR_SDRAM_CAS_n
DDR_SDRAM_CKE
DDR_SDRAM_Constraint_Mode
Constraints_Mode should be
either 1 or 0.
DDR_SDRAM_CONTROLLER_
SIDE
DDR_SDRAM_CS_CKE_WIDTH
DDR_SDRAM_CS_n
DDR_SDRAM_DATA_WIDTH
DDR_SDRAM_DLL_TRACKING_
ENABLE
DLL_TRACKING_ENABLE
should be either 1 or 0.
DDR_SDRAM_DM
119
Violation
Description
DDR_SDRAM_DM_WIDTH
DDR_SDRAM_incorrect_
command_before_mode_reg_set
DDR_SDRAM_invalid_burst_
length
DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set
DDR_SDRAM_invalid_cas_latency
DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set
120
Violation
Description
DDR_SDRAM_invalid_operating_
mode
DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs
DDR_SDRAM_RAS_n
DDR_SDRAM_TMRD
DDR_SDRAM_TRAS
TRAS value should not be less This check is applicable only when the
than the minimum limit of 6.
NON_JEDEC parameter is set to 0.
The value of the TRAS timing
parameter should not be specified to
be less than 6.
DDR_SDRAM_TRC
DDR_SDRAM_TRCD
121
Violation
Description
DDR_SDRAM_TRFC
DDR_SDRAM_TRP
DDR_SDRAM_TRRD
DDR_SDRAM_TWR
DDR_SDRAM_TXSNR
DDR_SDRAM_TXSRD
DDR_SDRAM_violates_tRRD
An activate command is
issued too quickly after the
prior activate command.
DDR_SDRAM_WE_n
122
Table 6-7 shows the checks for each bank performed by a DDR SDRAM monitor.
Table 6-7. DDR SDRAM Monitor Checks for Each Bank
Check ID
Violation
Description
DDR_SDRAM_ADDRESS
DDR_SDRAM_BA
DDR_SDRAM_bad_data
DDR_SDRAM_CAS_n
DDR_SDRAM_CKE
DDR_SDRAM_con_auto_
precharge_min_delay_violation
123
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
124
Check ID
Violation
Description
DDR_SDRAM_Constraints_Mode
Constraints_Mode should be
either 1 or 0.
DDR_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE should be
either 1 or 0.
The value of
CONTROLLER_SIDE parameter
value should be either 1 or 0.
DDR_SDRAM_CS_CKE_WIDTH
DDR_SDRAM_CS_n
DDR_SDRAM_DATA_WIDTH
DDR_SDRAM_DLL_
TRACKING_ENABLE
DLL_TRACKING_ENABLE
should be either 1 or 0.
DDR_SDRAM_DM
DDR_SDRAM_DM_WIDTH
DDR_SDRAM_illegal_command_
active
DDR_SDRAM_illegal_command_
aref
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_illegal_command_
emrs
DDR_SDRAM_illegal_command_
idle
DDR_SDRAM_illegal_command_
mrs
DDR_SDRAM_illegal_command_
pall
125
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
126
Check ID
Violation
Description
DDR_SDRAM_illegal_command_
pre
DDR_SDRAM_illegal_command_
read
DDR_SDRAM_illegal_command_
reada
DDR_SDRAM_illegal_command_
write
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_illegal_command_
writea
DDR_SDRAM_incorrect_
command_before_mode_reg_set
DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set
DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set
DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs
DDR_SDRAM_invalid_self_ref
_or_power_down_exit
127
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
128
Check ID
Violation
Description
DDR_SDRAM_no_auto_ refresh
DDR_SDRAM_no_dll_ reset
DDR_SDRAM_RAS_n
DDR_SDRAM_read_before_write
DDR_SDRAM_TMRD
DDR_SDRAM_TRAS
DDR_SDRAM_TRC
TRC value should not be less than The value of the TRC timing
the minimum limit of 9.
parameter should not be specified
as less than 9.
DDR_SDRAM_TRCD
DDR_SDRAM_TRFC
DDR_SDRAM_TRP
DDR_SDRAM_TRRD
DDR_SDRAM_TWR
DDR_SDRAM_TXSNR
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_TXSRD
DDR_SDRAM_violates_CKE_
signal_P
DDR_SDRAM_violates_CKE_
signal_N * (see the note at the end
of this table)
DDR_SDRAM_violates_tDLL
DDR_SDRAM_violates_tMRD
DDR_SDRAM_violates_tRAS
DDR_SDRAM_violates_tRC
DDR_SDRAM_violates_CKE_
signal_N
129
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
130
Check ID
Violation
Description
DDR_SDRAM_violates_tRCD
DDR_SDRAM_violates_tRFC
DDR_SDRAM_violates_tRP
DDR_SDRAM_violates_tRRD
DDR_SDRAM_violates_tXSNR
DDR_SDRAM_violates_tXSRD
Table 6-7. DDR SDRAM Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_WE_n
DDR_SDRAM_why_precharge_
an_idle_bank
A PRECHARGE command is
issued while the bank is already
in a precharged state.
The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-8.
Table 6-8. Calculate Minimum Delay From a Read/Write
From Command
To Command
Write with AP
Read or Read AP
(BL/2) + tWR +1
Write or Write AP
BL/2
Precharge or Active
Read or Read AP
BL/2
Write or Write AP
CL + (BL/2)
Precharge or Active
Read with AP
BL = burst length
CL = CAS latency rounded up to next integer
131
Description
Read Commands
Write Commands
Precharge Commands
NOP Commands
Deselect Commands
Number of times the chip select signal (CS_n) of the DDR SDRAM
is de-asserted.
Table 6-10 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank
132
Corner Case
Description
Read Commands
Write Commands
Table 6-10. DDR SDRAM Monitor Corner Cases Maintained for Each Bank
Corner Case
Description
Number of times a read operation was issued to a page that was already
opened for read in the bank.
Number of times a read operation was issued to a page that was already
opened for write in the bank.
Number of times a write operation was issued to a page that was already
opened for read in the bank.
Number of times a write operation was issued to a page that was already
opened for write in the bank.
Precharge Commands
Monitor Statistics
Table 6-11 shows the corner cases captured by the DDR SDRAM monitor for the protocol.
Table 6-11. DDR SDRAM Monitor Statistics
Statistic
Description
Active Commands
Table 6-12 shows the corner cases captured by the DDR SDRAM monitor for each DDR
SDRAM bank.
Table 6-12. DDR SDRAM Monitor Statistics Maintained for Each Bank
Statistic
Description
Active Commands
133
V2.0 Monitor
Reference Documentation
This DDR SDRAM 2.0 monitor is modeled from the requirements provided in the following
document:
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79C, (Revision
of JESD79B) JEDEC Solid State Technology Association, March 2003.
JEDEC Standard, Double Data Rate (DDR) SDRAM Specification, JESD79, (Release
2) JEDEC Solid State Technology Association, May 2002.
Micron, DOUBLE DATA RATE (DDR) SDRAM, 64Mb: x32 DDR SDRAM, 2M32DDR07.p65-Rev. 9/01.
JEDEC Standard, Double Data Rate (DDR) Specification, JESD79E, JEDEC Solid
State Technology Association, May 2005.
Burst lengths 2, 4, 8, 16, 32, 64, 128, and Full Page Mode (FPM).
The DDR SDRAM 2.0 monitor does not support the following:
Full Page Mode burst and CAS latency of 4 in NON JEDEC mode.
134
DLL enable/disable.
The DDR SDRAM 2.0 monitor does not support the following:
Data strobes (LDQS, UDQS) for lower and upper data bytes in x16 configuration.
Write data masks LDM and UDM for lower and upper data bytes in x16 mode.
Normal mode.
By default (i.e., BYPASS_INIT = 0), the monitor tracks the initialization sequence and
validates the requirements described in the specification during the initialization
sequence. For example, the monitor fires if it does not detect at least two auto refresh
commands between a reset and an active command. In this mode, the monitor tracks the
MRS and EMRS commands and configures itself accordingly. The monitor ports
mode_register and extended_mode_register can be left unconnected.
135
Address
address
pipe
Control
control
DDR SDRAM
Memory
Application
Interface
Controller
DDR SDRAM
Monitor
Data
data
in/out
DDR SDRAM Memory Controller
Monitor Connectivity
Connect the DDR SDRAM 2.0 monitor pins to internal signals of the target design as specified
in the pin-out Table 6-13 and illustrated in Figure 6-6. The clock, reset, and asynchronous reset
should be available inside the target design. The remaining signals can be attached to the
outbound control and address signals of the target design.
136
DDR SDRAM
Monitor
TRAS
TRC
TRCD
TRFC
TRP
TRRD
TWR
TWRT
TXSNR
TXSRD
Description
A[ADDR_WIDTH 1:0]
Address.
areset
BA[1:0]
Bank address.
137
138
Pin
Description
CAS_n
CKE
clock
clock_n
CS_n
DM
DQ[DATA_WIDTH - 1:0]
Data lines.
DQS
Data strobe.
extended_mode_register
[ADDR_WIDTH 1:0]
LDM
LDQS
mode_register[ADDR_WIDTH +1:0]
RAS_n
reset
TCLK
TMRD
TRAS
TRC
TRCD
Description
TRFC
TRP
TRRD
TWR
TWRT
TXSNR
TXSRD
UDM
UDQS
WE_n
Note that the timing value between a WRITE command and the first DQS latching transition is
called the tdqss value. For formal analysis, the DDR SDRAM 2.0 monitor only supports
tdqss values equal to the clock period. This means that the DQS signal edges should be in line
with the clock signal for formal analysis. The monitor supports tdqss values from 75% to
125% of the total clock period.
Monitor Parameters
The parameters shown in Table 6-14 configure the corresponding DDR SDRAM 2.0 monitor.
The override parameters set timing parameters for the monitor.
139
Refer to Table 6-17 on page 145 for the JEDEC standard compliant values of the parameters
that are used as default values.
Table 6-14. DDR SDRAM 2.0 Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
CONTROLLER_SIDE
3.
ADDR_WIDTH
12
4.
DATA_WIDTH
5.
DLL_TRACKING_ENABLE
6.
TRC_OVERRIDE
7.
TRAS_OVERRIDE
8.
TRP_OVERRIDE
9.
TRCD_OVERRIDE
140
Default Description
10.
TRRD_OVERRIDE
11.
TMRD_OVERRIDE
12.
TRFC_OVERRIDE
13.
TXSNR_OVERRIDE
14.
TXSRD_OVERRIDE
15.
TWR_OVERRIDE
16.
TWTR_OVERRIDE
141
Default Description
17.
AUTOPRECHARGE_ENABLE_
ADDRESS_BIT
10
18.
COL_ADDRESS_WIDTH
19.
READ_BEFORE_WRITE_
CHECK_ENABLE
20.
CON_AUTO_PRECHARGE
21.
ENABLE_WHY_PRECHARGE_
AN_IDLE_BANK
22.
BYPASS_INIT
23.
NON_JEDEC
24.
USE_PORTS_TO_CONFIGURE
25.
DATA_CHECK_ENABLE
142
Default Description
26.
TCLK_OVERRIDE
27.
CLOCK_CHANGE_TRACKING_ 0
ENABLE
28.
TCLK_CHECK_ENABLE
29.
CLOCK_FREQUENCY_RANGE_ 0
CHECK_ENABLE
30.
CLOCK_PERIOD_MAX
10
31.
CLOCK_PERIOD_MIN
143
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.
JEDEC Mode
Full Page mode burst can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the Burst Length configuration is as shown in Table 6-15.
Table 6-15. JEDEC Mode Burst Length Configuration
A[2:0]
BURST LENGTH
000
RSVD
001
010
011
100
16
101
32
110
64
111
128
CAS latency of 4 can be configured only in JEDEC mode (that is, when NON_JEDEC = 0).
When NON_JEDEC =1, the CAS Latency configuration is as shown in Table 6-16.
Table 6-16. JEDEC Mode CAS Latency Configuration
144
A[6:4]
CAS LATENCY
000
RSVD
001
1.0
010
2.0
011
3.0
100
0.5
101
1.5
110
2.5
111
RSVD
When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do the following:
Table 6-17. JEDEC Compliant Min. Timing for DDR SDRAM Speed Grade 266
Timing Parameter
TRC
TRAS
TRP
TRCD
TRRD
TMRD
TRFC
TXSNR
TXSRD
200
TWR
TWTR
Instantiation Examples
Example 1
Example 6-5 instantiates a JEDEC standard compliant DDR SDRAM 2.0 monitor on the DDR
SDRAM controller side for unconstraint search with ADDR_WIDTH of 12, DATA_WIDTH of 8,
8th bit of Address line as Auto precharge enable, Lower 8 Column Address lines are to be used
for Full Page Mode burst, and DLL_TRACKING_ENABLE set to 1. Note that all timing parameters
are the default values specified by JEDEC. The monitor is in normal mode of operation, which
enables the monitor to track the initialization sequence.
Example 6-5. DDR SDRAM 2.0 Monitor Instantiated in the Controller
qvl_ddr_sdram_2_0_monitor
145
Example 2
Example 6-6 instantiates two DDR SDRAM 2.0 monitors for a JEDEC standard DDR SDRAM
controller design. The example shows the following:
The controller design interfaces two DDR SDRAMs, each having 16 bits of
DATA_WIDTH to form a 32-bit data bus.
146
ADDR_WIDTH
DM_WIDTH
of 12.
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[1:0]),
.CS_n
(chip_select_4_n[1:0]),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(1'b0),
.DQ
(data_bus_32[15:0]),
.DQS
(1'b0),
.mode_register (),
.extended_mode_register (),
.LDQS (data_strobe),
.LDM (data_mask_4[0]),
.UDQS (data_strobe),
.UDM (data_mask_4[1]),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
.TRRD(32'b0),
.TWR(32'b0),
.TWTR(32'b0),
.TMRD(32'b0),
.TRFC(32'b0),
.TXSNR(32'b0),
.TXSRD(32'b0),
.TCLK(32'b0) );
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */ 0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
16)
DDR_SDRAM_MONITOR1 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable_4[3:2]),
147
Example 3
Example 6-7 instantiates a DDR SDRAM 2.0 monitor for a Micron 64 Mb compatible
controller design. The example has the following characteristics:
The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.
DM_WIDTH
148
of 1.
TRAS
7
TXSNR
10
TRP
3
TXSRD
200
TRCD
3
TWR
2
TRRD
2
TWTR
1
TMRD
2
FPM mode is supported. FPM size is 256 and the number of address lines required to
burst up to 256 is 8. Therefore, the COL_ADDRESS_WIDTH is set to 8.
qvl_ddr_sdram__2_0_monitor
#( /* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
1,
/* ADDR_WIDTH */
12,
/* DATA_WIDTH */
8,
/* DLL_TRACKING_ENABLE */
1,
/* TRC_OVERRIDE */
10,
/* TRAS_OVERRIDE */
7,
/* TRP_OVERRIDE */
3,
/* TRCD_OVERRIDE */
3,
/* TRRD_OVERRIDE */
2,
/* TMRD_OVERRIDE */
2,
/* TRFC_OVERRIDE */
11,
/* TXSNR_OVERRIDE */
10,
/* TXSRD_OVERRIDE */
200,
/* TWR_OVERRIDE */
2,
/* TWTR_OVERRIDE */
1,
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
/* COL_ADDRESS_WIDTH */
8,
/* READ_BEFORE_WRITE_CHECK_ENABLE */
1,
/* CON_AUTO_PRECHARGE */
0,
/* ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
/* BYPASS_INIT*/
1)
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
.UDM (1'b0),
.TRC(32'b0),
.TRAS(32'b0),
.TRP(32'b0),
.TRCD(32'b0),
149
The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
Example 4
Example 6-8 on page 150 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through parameters. The example has the following
characteristics:
The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.
DM_WIDTH of 1
The timing parameters are set to NON JEDEC values through the parameters. Therefore, the
NON_JEDEC parameter is 1 and USE_PORTS_TO_CONFIGURE parameter is 0. The NON JEDEC
timing parameter values are as follows:
TRC
12
TRFC
15
TRAS
8
TXSNR
13
TRP
4
TXSRD
250
TRCD
4
TWR
3
TRRD
4
TWTR
2
TMRD
4
Example 6-8. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Parameters
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* ADDR_WIDTH */
/* DATA_WIDTH */
150
0,
1,
12,
8,
151
The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.
Example 5
Example 6-9 on page 152 instantiates a DDR SDRAM 2.0 monitor to check the controller with
NON JEDEC timing values configured through input ports. The example has the following
characteristics:
The controller design interfaces a DDR SDRAM having 8-bit DATA_WIDTH and 12-bit
ADDR_WIDTH.
DM_WIDTH
of 1.
The timing parameters are set to NON JEDEC values through the input ports. Therefore,
the NON_JEDEC parameter is 1 and the USE_PORTS_TO_CONFIGURE parameter is 1. The
NON JEDEC timing parameter values are as follow:
TRC
12
TRFC
15
TRAS
8
TXSNR
13
TRP
4
TXSRD
250
TRCD
4
TWR
3
TRRD
4
TWTR
2
TMRD
4
Example 6-9. DDR SDRAM 2.0 Monitor Instantiated with NON JEDEC Timing
Values Configured Through Input Ports
qvl_ddr_sdram_2_0_monitor
#( /* Constraints_Mode */
/* CONTROLLER_SIDE */
/* ADDR_WIDTH */
152
0,
1,
12,
DATA_WIDTH */
8,
DLL_TRACKING_ENABLE */
1,
TRC_OVERRIDE */
12,
TRAS_OVERRIDE */
8,
TRP_OVERRIDE */
4,
TRCD_OVERRIDE */
4,
TRRD_OVERRIDE */
4,
TMRD_OVERRIDE */
4,
TRFC_OVERRIDE */
15,
TXSNR_OVERRIDE */
13,
TXSRD_OVERRIDE */
250,
TWR_OVERRIDE */
3,
TWTR_OVERRIDE */
2,
AUTOPRECHARGE_ENABLE_ADDRESS_BIT */ 8,
COL_ADDRESS_WIDTH */
8,
READ_BEFORE_WRITE_CHECK_ENABLE */
1,
CON_AUTO_PRECHARGE */
0,
ENABLE_WHY_PRECHARGE_AN_IDLE_BANK */0,
BYPASS_INIT*/
1,
NON_JEDEC*/
1,
USE_PORTS_TO_CONFIGURE*/
1,
DATA_CHECK_ENABLE */
0,
ZI_DDR_SDRAM_2_0 */
1,
DM_WIDTH */
1,
CLOCK_CHANGE_TRACKING_ENABLE */
1,
TCLK_CHECK_ENABLE */
1,
TCLK_OVERRIDE */
2, // This parameter will
// not be effective as the
// port TCLK will be used
// to configure
// this timing parameter.
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/1,
/* CLOCK_PERIOD_MAX */
10, // Specified in
// nanoseconds for a
// 100 MHz clock.
/* CLOCK_PERIOD_MIN */
5) // Specified in
// nanoseconds for a
// 200 MHz clock.
DDR_SDRAM_MONITOR0 (
.clock
(clock),
.clock_n
(clock_n),
.reset
(reset),
.areset
(areset),
.CKE
(clock_enable),
.CS_n
(chip_select_n),
.RAS_n
(row_address_strobe_n),
.CAS_n
(column_address_strobe_n),
.WE_n
(write_enable_n),
.BA
(bank_address),
.A
(address_bus_12),
.DM
(data_mask_1),
.DQ
(data_bus_8),
.DQS
(data_strobe),
.mode_register (internal_mode_register),
.extended_mode_register (internal_mode_register),
.LDQS (1'b0),
.LDM (1'b0),
.UDQS (1'b0),
153
The monitor is instantiated with BYPASS_INIT = 1 and internal signals are connected to the
monitor ports mode_register and extended_mode_register.
Note that this example also shows parameter configuration for enabling clock frequency change
support model of the monitor.
Monitor Checks
Table 6-18 shows the checks performed by a DDR SDRAM 2.0 monitor.
Table 6-18. DDR SDRAM 2.0 Monitor Checks
Check ID
Violation
Description
DDR_SDRAM_ADDRESS
DDR_SDRAM_BA
DDR_SDRAM_BYPASS_INIT
BYPASS_INIT should be
either 1 or 0.
DDR_SDRAM_CAS_n
DDR_SDRAM_CKE
DDR_SDRAM_Constraint_Mode
Constraints_Mode should be
either 1 or 0.
DDR_SDRAM_CONTROLLER_
SIDE
154
Violation
Description
DDR_SDRAM_CS_n
DDR_SDRAM_DATA_CONFIG
DDR_SDRAM_DLL_TRACKING_
ENABLE
DLL_TRACKING_ENABLE
should be either 1 or 0.
DDR_SDRAM_DM
DDR_SDRAM_DM_WIDTH
DDR_SDRAM_incorrect_
command_before_mode_reg_set
DDR_SDRAM_invalid_burst_
length
DDR_SDRAM_invalid_burst_
length_value_in_mode_reg_set
155
Violation
Description
DDR_SDRAM_invalid_cas_latency
DDR_SDRAM_invalid_cas_
latency_value_in_mode_reg_set
DDR_SDRAM_invalid_operating_
mode
DDR_SDRAM_invalid_operating_
mode_bits_mrs_or_emrs
DDR_SDRAM_RAS_n
DDR_SDRAM_TMRD
156
Violation
Description
DDR_SDRAM_TRAS
DDR_SDRAM_TRC
DDR_SDRAM_TRCD
TRCD value should not be less This check is applicable only when the
than the minimum limit of 2.
NON_JEDEC parameter is set to 0.
The value of the TRCD timing
parameter should not be specified to be
less than 2.
DDR_SDRAM_TRFC
DDR_SDRAM_TRP
DDR_SDRAM_TRRD
TRRD value should not be less This check is applicable only when the
than the minimum limit of 1.
NON_JEDEC parameter is set to 0.
The value of the TRRD timing
parameter should not be specified to be
less than 1.
DDR_SDRAM_TWR
DDR_SDRAM_TXSNR
DDR_SDRAM_TXSRD
DDR_SDRAM_violates_tRRD
157
Violation
Description
DDR_SDRAM_WE_n
Table 6-19 shows the checks for each bank performed by a DDR SDRAM 2.0 monitor.
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank
Check ID
Violation
Description
A_DDR_SDRAM_clock_change_
during_non_ppd_mode
A_DDR_SDRAM_clock_change_
during_illegal_cke
A_DDR_SDRAM_violates_tCLK
158
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
A_DDR_SDRAM_clock_
frequency_out_of_range
A_DDR_SDRAM_CKE_changed_
during_unstable_clock
A_DDR_SDRAM_ppd_exit_
during_unstable_clock
A_DDR_SDRAM_dll_not_reset_
after_ppd_exit_after_clock_change
DDR_SDRAM_bad_data
159
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_con_auto_
precharge_min_delay_violation
DDR_SDRAM_illegal_command_
active
DDR_SDRAM_illegal_command_
aref
DDR_SDRAM_illegal_command_
emrs
160
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_illegal_command_
idle
DDR_SDRAM_illegal_command_
mrs
DDR_SDRAM_illegal_command_
pall
DDR_SDRAM_illegal_command_
pre
161
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_illegal_command_
read
DDR_SDRAM_illegal_command_
reada
DDR_SDRAM_illegal_command_
write
DDR_SDRAM_illegal_command_
writea
162
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_no_auto_ refresh
DDR_SDRAM_no_dll_ reset
DDR_SDRAM_read_before_write
DDR_SDRAM_violates_tDLL
DDR_SDRAM_violates_CKE_
signal_P
DDR_SDRAM_violates_CKE_
signal_N * (see the note at the end of
this table)
DDR_SDRAM_violates_tMRD
DDR_SDRAM_violates_CKE_
signal_N
163
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
DDR_SDRAM_violates_tRAS
A command that violates RAS The command just issued violates tRAS
timing is issued.
(RAS to precharge timing). This is a
PRECHARGE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
why the commands are too close
together.
DDR_SDRAM_violates_tRC
A command that violates RAS The command just issued violates tRC
cycle timing is issued.
(RAS cycle timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
ACTIVATE command for this bank.
The user should determine why the
commands are too close together.
DDR_SDRAM_violates_tRCD
A command that violates RAS The command just issued violates tRCD
to CAS delay timing is issued. (RAS to CAS delay timing). This is a
READ/WRITE command issued too
quickly after the ACTIVATE command
for this bank. The user should determine
why the commands are too close
together.
DDR_SDRAM_violates_tRFC
DDR_SDRAM_violates_tRP
A command that violates RAS The command just issued violates tRP
precharge timing is issued.
(RAS precharge timing). This is an
ACTIVATE/REFRESH command
issued too quickly after the last
precharge command for this bank. The
user should determine why the
commands are too close together.
DDR_SDRAM_violates_tXSNR
DDR_SDRAM_violates_tXSRD
164
Description
Table 6-19. DDR SDRAM 2.0 Monitor Checks for Each Bank (cont.)
Check ID
Violation
Description
DDR_SDRAM_why_precharge_
an_idle_bank
A PRECHARGE command is
issued while the bank is
already in a precharged state.
The minimum delay from a read/write with auto precharge command to any command to a
different bank is calculated as shown in Table 6-20.
Table 6-20. Calculate Minimum Delay From a read/Write
From Command
To Command
Write with AP
Read or Read AP
(BL/2) + tWR +1
Write or Write AP
BL/2
Precharge or Active
Read or Read AP
BL/2
Write or Write AP
CL + (BL/2)
Precharge or Active
Read with AP
BL = burst length
CL = CAS latency rounded up to next integer
Description
Read Commands
Write Commands
Precharge Commands
165
Description
NOP Commands
Deselect Commands
Number of times the chip select signal (CS_n) of the DDR SDRAM is
de-asserted.
Table 6-22 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank
166
Corner Case
Description
Read Commands
Write Commands
Precharge Commands
Table 6-22. DDR SDRAM 2.0 Monitor Corner Cases Maintained for Each Bank
Corner Case
Description
Monitor Statistics
Table 6-23 shows the corner cases captured by the DDR SDRAM 2.0 monitor for the protocol.
Table 6-23. DDR SDRAM 2.0 Monitor Statistics
Statistic
Description
Active Commands
Table 6-24 shows the corner cases captured by the DDR SDRAM 2.0 monitor for each DDR
SDRAM bank.
Table 6-24. DDR SDRAM 2.0 Monitor Statistics Maintained for Each Bank
Statistic
Description
Active Commands
167
168
Chapter 7
Double Data Rate-II SDRAM (DDR-II SDRAM)
Introduction
The QVL Double Data Rate-II SDRAM (DDR-II SDRAM) monitor provides a method of
debugging DDR-II SDRAM system designs by checking that the operation of the design is
compliant with the JEDEC standard.
The DDR-II SDRAM monitor tracks all operations to the DDR-II SDRAM subsystem for a
single row of DDR-II SDRAMs. To check multiple memory rows, the user can instantiate
multiple instances of the DDR-II SDRAM monitor. Each DDR-II SDRAM monitor instance
checks operations on a virtual four-bank DDR-II SDRAM by monitoring the states of each bank
and by setting and relaxing cycle-based timing checks on all operations on the banks.
The DDR-II SDRAM monitor instance determines illegal command sequences by comparing
the bank-state against command issue. Checks for illegal commands and cycle-based timing
problems can be used as formal targets. The user can use formal analysis to find legal stimulus
sequences (that is, corner case behavior) that direct your controller design to violate legal DDRII SDRAM memory subsystem operations.
V1.0 Monitor
Reference Documentation
This DDR-II SDRAM 1.0 monitor is modeled on the requirements provided in the following
document:
JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.
Burst length 4.
169
The DDR SDRAM 1.0 monitor does not support the following:
DLL enable/disable.
The DDR SDRAM 1.0 monitor does not support the following:
170
Address
address
pipe
Control
control
DDR-II SDRAM
Memory
Application
Interface
Controller
DDR-II SDRAM
1.0 Monitor
data
in/out
Data
Monitor Connectivity
Connect the DDR-II SDRAM 1.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-1 and illustrated in Figure 7-2. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.
Figure 7-2. DDR-II SDRAM 1.0 Monitor Pin-Out Diagram
ck
ck_n
reset
areset
cke
cs_n
ras_n
cas_n
we_n
ba[1:0]
a[ROW_ADDR_WIDTH - 1:0]
dm[DM_WIDTH - 1:0]
dq[DATA_BUS_WIDTH - 1:0]
dqs
DDR-II SDRAM
Monitor
171
Description
a[ROW_ADDR_WIDTH 1:0]
Address.
areset
ba[1:0]
Bank address.
cas_n
ck
ck_n
cke
cs_n
dm[DM_WIDTH -1:0]
dq[DATA_BUS_WIDTH - 1:0]
Data lines.
dqs
Data strobe.
ras_n
reset
we_n
Note that the timing value between a WRITE command and the first dqs latching transition is
called the tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 1.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.
172
If the memory controller supports n DDR-II SDRAMs stacked by data width (for a
total data width of n x width and memory size mem), then connect only one instance
of the monitor to track the controller.
If the memory controller supports n DDR-II SDRAMs stacked by address width (for a
total data width of width and memory size n x mem), then connect n instances of the
monitor to track the controller.
Use the above scheme also when stacking by both data width and address width.
Figure 7-3. Stacking DDR-II SDRAMs by Data Width
Data
DDR-II SDRAM
Memory Controller
DDR-II SDRAM
Monitor
Address
...
DDR-II SDRAM
Memory #1
DDR-II SDRAM . . .
Memory #2
DDR-II SDRAM
Memory #n
DDR-II SDRAM
Memory Controller
DDR-II SDRAM
Monitor
DDR-II SDRAM
Memory #1
Address
DDR-II SDRAM
Memory #2
Address
...
...
DDR-II SDRAM
Monitor
Address
...
DDR-II SDRAM
Monitor
DDR-II SDRAM
Memory #n
173
Monitor Parameters
The parameters shown in Table 7-2 configures the DDR-II SDRAM 1.0 monitor. Refer to
Table 7-3 on page 176 for the JEDEC standard compliant values of the timing parameters,
which are used as default values.
Table 7-2. DDR-II SDRAM 1.0 Monitor Parameters
174
Order Parameter
Default Description
1.
Constraints_Mode
2.
CONTROLLER_SIDE
3.
ROW_ADDR_WIDTH
13
4.
DATA_BUS_WIDTH
5.
DM_WIDTH
6.
DLL_TRACKING_ENABLE
7.
TRAS
8.
TRCD
9.
TRP
10.
TRRD
11.
TCCD
12.
TRTW
13.
TWTR
14.
TWR
15.
TRFC
10
Default Description
16.
TXSNR
10
17.
TXSRD
200
18.
TMRD
19.
AUTOPRECHARGE_
ENABLE_ADDRESS_BIT
10
20.
READ_BEFORE_WRITE_
CHECK_ENABLE
21.
DATA_CHECK_ENABLE
When constraints mode is not enabled, all checks are used as targets during formal verification.
To use the checks as constraints for formal analysis, do both of the following:
175
Default: 2
Description:
This is used to delay the DQS signal during read cycles in order to align the DQS signal edges at
the center of the DQ signal to guarantee the proper latching of DQ.
By default, the DQS signal is delayed by 2 time units (i.e., #2) internally.
The user should override this with a larger value if the DQS signal that is driven by the DDR
Memory should be delayed more than #2 to guarantee proper DQ latching.
TRAS
TRCD
TRP
TRRD
TCCD
TRTW
TWTR
TWR
TRFC
10
TXSNR
10
TXSRD
200
TMRD
Instantiation Examples
Example 1
Example 7-1 instantiates a DDR-II SDRAM 1.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 13, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1.
176
Example 2
Example 7-2 instantiates two instances of the DDR-II SDRAM 1.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:
The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 32-bits of DATA_BUS_WIDTH.
The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.
Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.
Constraints_Mode
177
Monitor Checks
Table 7-4 shows the checks performed by a DDR-II SDRAM 1.0 monitor.
Table 7-4. Checks Performed by a DDR-II SDRAM 1.0 Monitor
Check ID
Violation
Description
DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID
178
Violation
Description
DDR2_SDRAM_ADDRESS_
LEVEL
DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE
DDR2_SDRAM_BANK_LEVEL
DDR2_SDRAM_CAS_LATENCY_
INVALID
DDR2_SDRAM_CAS_LEVEL
DDR2_SDRAM_CKE_LEVEL
DDR2_SDRAM_CONSTRAINTS_
MODE
Constraints_Mode parameter
should be either 1 or 0.
DDR2_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE
parameter should be either 1 or
0.
DDR2_SDRAM_CS_LEVEL
DDR2_SDRAM_DATA_WIDTH
DATA_BUS_WIDTH
parameter should not be less
than the minimum limit of 4.
DDR2_SDRAM_DLL_NOT_RESET
DDR2_SDRAM_DLL_TRACKING
DLL_TRACKING_ENABLE
parameter should be either 1 or
0.
179
Violation
Description
DDR2_SDRAM_DM_LEVEL
DDR2_SDRAM_DM_WIDTH
DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS
DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE
DDR2_SDRAM_MODE_
REGISTER_NOT_SET
DDR2_SDRAM_MRS_
PRECHARGE
DDR2_SDRAM_RAS_LEVEL
DDR2_SDRAM_ROW_ADDRESS
ROW_ADDRESS_WIDTH
parameter should not be less
than the minimum limit of 12.
DDR2_SDRAM_SELF_REFRESH_
PRECHARGE
DDR2_SDRAM_TCCD
DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET
DDR2_SDRAM_TMRD
DDR2_SDRAM_TRAS
180
Violation
Description
DDR2_SDRAM_TRCD
DDR2_SDRAM_TRFC
DDR2_SDRAM_TRP
DDR2_SDRAM_TRRD
DDR2_SDRAM_TRRD_
VIOLATION
DDR2_SDRAM_TRTW
DDR2_SDRAM_TWR
DDR2_SDRAM_TWTR
DDR2_SDRAM_TXSNR
DDR2_SDRAM_TXSRD
DDR2_SDRAM_WE_LEVEL
Table 7-5 shows the checks for each bank performed by a DDR-II SDRAM 1.0 monitor.
Table 7-5. DDR-II SDRAM 1.0 Monitor Bank Checks
Check ID
Violation
Description
DDR2_SDRAM_ACTIVATE
An ACTIVATE command is
issued to an already open
bank without an intervening
PRECHARGE.
181
Violation
Description
DDR2_SDRAM_BAD_DATA
DDR2_SDRAM_BURST_
ABORTED_P
DDR2_SDRAM_CKE_LOW
DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN
DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE
DDR2_SDRAM_ILLEGAL_
COMMAND_CBR
DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS
DDR2_SDRAM_BURST_
ABORTED_N
182
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN
DDR2_SDRAM_ILLEGAL_
COMMAND_MRS
DDR2_SDRAM_ILLEGAL_
COMMAND_NOP
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL
DDR2_SDRAM_ILLEGAL_
COMMAND_READ
183
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP
DDR2_SDRAM_ILLEGAL_
COMMAND_SFR
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP
DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK
A Precharge command is
issued to an idle bank.
DDR2_SDRAM_READ_AP_
VIOLATION
DDR2_SDRAM_READ_BEFORE_
WRITE
184
Violation
Description
DDR2_SDRAM_READ_TO_IDLE_
BANK
DDR2_SDRAM_TMRD_
VIOLATION
DDR2_SDRAM_TRC_VIOLATION
DDR2_SDRAM_TRFC_VIOLATION
185
Violation
Description
DDR2_SDRAM_TRP_VIOLATION
DDR2_SDRAM_TRTP_VIOLATION
DDR2_SDRAM_TRTW_
VIOLATION
DDR2_SDRAM_TWTR_
VIOLATION
186
Violation
Description
DDR2_SDRAM_TWTW_
VIOLATION
DDR2_SDRAM_TXSNR_
VIOLATION
DDR2_SDRAM_TXSRD_
VIOLATION
DDR2_SDRAM_UNKNOWN_
STATE
DDR2_SDRAM_WRITE_TO_IDLE_
BANK
Description
187
Description
Interleaved Bursts
Sequential Bursts
NOP Commands
Deselect Commands
Table 7-7 shows the corner cases captured by the DDR-II SDRAM 1.0 monitor for the DDR-II
SDRAM banks.
Table 7-7. DDR-II SDRAM 1.0 Bank Corner Cases
Corner Case
Description
Seamless Reads
Seamless Writes
Posted Reads
Posted Writes
188
Monitor Statistics
Table 7-8 lists the statistics collected for the protocol.
Table 7-8. DDR-II SDRAM 1.0 Monitor Statistics
Statistic
Description
Total number of data accesses to the DDR-II SDRAM for all banks.
Description
Total number of times a bank is activated and data accesses performed on the
bank.
189
V2.0 Monitor
Reference Documentation
This DDR-II SDRAM 2.0 monitor is modeled on the requirements provided in the following
document:
JEDEC Double Data Rate - II (DDR-II) SDRAM Specification, JC 42.3, JEDEC Solid
State Technology Association, December 2000.
JEDEC Standard, Double Data Rate-II (DDR) Specification, JESD79-2C, JEDEC Solid
State Technology Association, May 2006.
The DDR-II SDRAM 2.0 monitor does not support the following:
190
DLL enable/disable.
The DDR-II SDRAM 2.0 monitor does not support the following:
Normal mode.
By default (BYPASS_INIT=0), the monitor tracks the initialization sequence. In this
mode, the monitor validates the requirements described in the JEDEC specification
during the initialization sequence. For example, in the normal mode of operation, the
monitor fires if it does not detect an EMRS(2) command followed by an EMRS(3)
command.
In the normal mode of operation, the monitor tracks the MRS and EMRS commands and
configures itself accordingly. The monitor ports mode_register_in and
ex_mode_register_in can be left unconnected.
191
SDRAM memory controller design with the port signals connected to the DDR-II SDRAM
memory interface (see Figure 7-5). The user can include instantiations of the DDR-II SDRAM
2.0 monitors in a checker control file.
Figure 7-5. DDR-II SDRAM 2.0 Block Diagram
Address
address
pipe
Control
control
DDR-II SDRAM
Memory
Application
Interface
Controller
DDR-II SDRAM
2.0 Monitor
Data
data
in/out
DDR-II SDRAM Memory Controller
Monitor Connectivity
Connect the DDR-II SDRAM 2.0 monitor pins to internal signals of the target design as
specified in the pin-out Table 7-10 and illustrated in Figure 7-6. The clock, reset, and
asynchronous reset signals should be available inside the target design. The remaining signals
can be attached to the outbound control and address signals of the target design.
192
DDR-II SDRAM
Monitor
193
194
Pin
Description
a[ROW_ADDR_WIDTH 1:0]
Address.
areset
ba[BANK_ADDR_WIDTH-1:0]
Bank address.
cas_n
ck
ck_n
cke
cs_n
dm_rdqs
dq
Data bus.
dqs
ex_mode_register_in
ldm
ldqs
mode_register_in
odt
On-die-termination.
ras_n
reset
tccd_inp[31:0]
Port for tCCD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
tmrd_inp[31:0]
Port for tMRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
tras_inp[31:0]
Port for tRAS timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
trcd_inp[31:0]
Port for tRCD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
trfc_inp[31:0]
Port for tRFC timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
trp_inp[31:0]
Port for tRP timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
Description
trrd_inp[31:0]
Port for tRRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
trtw_inp[31:0]
Port for tRTW timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
twr_inp[31:0]
Port for tWR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
twtr_inp[31:0]
Port for tWTR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
txard_inp[31:0]
Port for tXARD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
txp_inp[31:0]
Port for tXP timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
txsnr_inp[31:0]
Port for tXSNR timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
txsrd_inp[31:0]
Port for tXSRD timing input. This input is valid only when
USE_PORTS_TO_CONFIGURE parameter is set to 1.
udm
udqs
we_n
The timing value between a WRITE command and the first dqs latching transition is called the
tdqss value.
In simulation, the monitor uses the dqs signal to latch the dq bus, and it supports tdqss
values from 75% to 125% of the total clock period.
For formal analysis, the DDR-II SDRAM 2.0 monitor does not use the dqs signal to latch data
from the dq bus; instead, the monitor uses the ck/ck_n signals to latch the dq bus. Note that
the monitor assumes the tdqss value to be 100%, which is equal to one clock cycle width.
This indirectly means that during write operation, the designs should drive the dq and dqs
signals such that the dqs transitions are in-line with the ck/ck_n transitions.
Also note that in simulation the monitor uses only the dqs signal to latch both odd and even
data from the dq bus, and it does not need the dqs_n in the monitor. That is, the monitor uses
the posedge of dqs to latch odd data from the dq bus, and it uses the negedge of the dqs
signal to latch even data, instead of using the posedge of dqs_n. Similarly, the monitor does not
use ldqs_n, udqs_n, and rdqs_n signals; instead, it uses both edges of ldqs, udqs, and
rdqs, respectively.
In x8 mode, if RDQS is enabled, then the DM pin can be used as the read data strobe, RDQS. In
this case, the DM function is disabled for x8 writes. Therefore, if operating in x8 configuration
and RDQS is enabled, connect DQS to DM. For writes, DQS is the data strobe and for reads RDQS
(using the DM pin) is the data strobe. DQ is the data bus for both operations.
Questa Verification Library Monitors Data Book, v2010.2
195
The x4 and x16 configurations are not affected by the RDQS function of the DM pin. In x16
mode, LDQS corresponds to the data on DQ0-DQ7 and UDQS corresponds to the data on
DQ8-DQ15. The corresponding data masks are LDM and UDM.
Monitor Parameters
The parameters shown in Table 7-11 configure the DDR-II SDRAM 2.0 monitor. Refer to
Table 7-12 for the JEDEC standard compliant values of the timing parameters, which are used
as default values.
Table 7-11. DDR-II SDRAM 2.0 Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
CONTROLLER_SIDE
3.
ROW_ADDR_WIDTH
16
4.
DATA_BUS_WIDTH
Width of data bus. Use this parameter to set the data bus
configuration to x4, x8, or x16. These are the only valid
values of this parameter.
5.
DLL_TRACKING_ENABLE
6.
TRAS
7.
TRCD
8.
TRP
9.
TRRD
196
Default Description
10.
TCCD
11.
TRTW
12.
TWTR
13.
TWR
14.
TRFC
15.
TXSNR
10
16.
TXSRD
200
17.
TMRD
18.
AUTOPRECHARGE_
ENABLE_ADDRESS_BIT
10
197
Default Description
19.
READ_BEFORE_WRITE_
CHECK_ENABLE
20.
TXP
21.
TXARD
22.
BANK_ADDR_WIDTH
23.
ENABLE_PRECHARGE_
TO_IDLE_BANK
24.
BYPASS_INIT
25.
DATA_CHECK_ENABLE
26.
OPTIONAL_ADDITIVE_
LATENCY_ENABLE
27.
IMPEDANCE_
CALIBRATION_CHECKS_
ENABLE
28.
PARTIAL_SELF_
REFRESH_ENABLE
29.
DUTY_CYCLE_
CONTROL_ENABLE
30.
DDR2_SPEED_GRADE
400
198
Default Description
31.
HIGH_TEMP_SELF_
REFRESH_RATE_ENABLE
32.
CLOCK_CHANGE_
TRACKING_ENABLE
33.
TCLK_CHECK_ENABLE
34.
TCLK
35.
CLOCK_FREQUENCY_
RANGE_CHECK_ENABLE
36.
CLOCK_PERIOD_MAX
2500
37.
CLOCK_PERIOD_MIN
1250
38.
USE_PORTS_TO_
CONFIGURE
When constraints mode is disabled, all checks are used as targets during formal analysis. To use
the checks as constraints for formal analysis, do both of the following:
199
200
TRAS
TRCD
TRP
TRRD
TCCD
TRTW
TWTR
TWR
TRFC
TXSNR
10
TXSRD
200
TMRD
TXP
TXARD
TCLK
Time is measured by an integer number of clock cycles obtained by dividing the absolute
AC timing parameter by tCK (clock period) and rounding off to the nearest integer.
Instantiation Examples
Example 1
Example 7-3 instantiates a DDR-II SDRAM 2.0 monitor on the DDR-II SDRAM controller
side with ROW_ADDR_WIDTH of 16, DATA_BUS_WIDTH of 8, and DLL_TRACKING_ENABLE set to
1. The timing parameters are the default values specified by JEDEC. The monitor is instantiated
with BYPASS_INIT = 1. Internal signals are connected to the monitor ports
mode_register_in and ex_mode_register_in.
Example 7-3. DDR-II SDRAM 2.0 Monitor Instantiation
qvl_ddr2_sdram_2_0_monitor
#( 1,
/* Constraints_Mode */
1,
/* CONTROLLER_SIDE */
16,
/* ROW_ADDR_WIDTH */
8,
/* DATA_BUS_WITH */
1,
/* DLL_TRACKING_ENABLE */
6,
/* TRAS */
201
/* TRCD */
/* TRP */
/* TRRD */
/* TCCD */
/* TRTW */
/* TWTR */
/* TWR */
/* TRFC */
/* TXSNR */
/* TXSRD */
/* TMRD */
/* AUTOPRECHARGE_ENABLE_ADDRESS_BIT*/
/* READ_BEFORE_WRITE_CHECK_ENABLE */
/* TXP */
/* TXARD */
/* BANK_ADDR_WIDTH */
/* ENABLE_PRECHARGE_TO_IDLE_BANK */
/* BYPASS_INIT */
/* ZI_DDR2_SDRAM_2_0 */
/* ZI_DM_WIDTH */
/*OPTIONAL_ADDITIVE_LATENCY_ENABLE*/
/*IMPEDANCE_CALIBRATION_CHECKS_ENABLE*/ // OCD Calibration
// enabled
0,
/* PARTIAL_SELF_REFRESH_ENABLE*/
0,
/*DUTY_CYCLE_CONTROL_ENABLE*/
800,
/*DDR2_SPEED_GRADE*/
0,
/*HIGH_TEMP_SELF_REFRESH_RATE_ENABLE*/
0,
/* CLOCK_CHANGE_TRACKING_ENABLE */
0,
/* TCLK_CHECK_ENABLE */
2,
/* TCLK*/
0,
/* CLOCK_FREQUENCY_RANGE_CHECK_ENABLE*/
2500,
/* CLOCK_PERIOD_MAX */
1250)
/* CLOCK_PERIOD_MIN */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_1),
.cs_n
(chip_select_n_1),
.ras_n
(row_address_strobe_n),
.cas_n
(column_address_strobe_n),
.we_n
(write_enable_n),
.ba
(bank_address),
.a
(address_bus_16),
.dm
(data_mask_1),
.dq
(data_bus_8),
.dqs
(data_strobe)
.ldqs
(1'b0),
.ldm
(1'b0)
.udqs
(1'b0),
.udm
(1'b0),
.mode_register_in
(internal_mode_register),
.ex_mode_register_in (internal_ex_mode_register), // If any
.odt(odt) ); // On-die-termination
202
Example 2
Example 7-4 instantiates two instances of the DDR-II SDRAM 2.0 monitor for a DDR-II
SDRAM memory. The example has the following characteristics:
The controller design interfaces two stacked DDR-II SDRAMs, each having 12-bits of
ROW_ADDR_WIDTH (4K address space) and 16-bits of DATA_BUS_WIDTH.
The cs_n, cke, ras_n, cas_n, and we_n signals of width 2-bits each, one for each
DDR-II SDRAM.
Two bank addresses of width 2-bits each, one for each DDR-II SDRAM memory.
Mode register and extended mode register ports are left unconnected.
Example 7-4. DDR-II SDRAM 2.0 Monitor Instantiation
qvl_ddr2_sdram_2_0_monitor
#( 1,
/* Constraints_Mode */
0,
/* CONTROLLER_SIDE */
12,
/* ROW_ADDR_WIDTH */
16)
/* DATA_BUS_WITH */
DDR2_SDRAM_MONITOR0 (
.ck
(clock),
.ck_n
(clock_n),
.reset
(reset),
.areset
(areset),
.cke
(clock_enable_0),
.cs_n
(chip_select_n_0),
.ras_n
(row_address_strobe_n_0),
.cas_n
(column_address_strobe_n_0),
.we_n
(write_enable_n_0),
.ba
(bank_address_0),
.a
(address_bus_12_0),
.dm_rdqs
(1'b0),
.dq
(upper_data_byte_0,lower_data_byte_0),
.dqs
(1'b0)
.ldqs
(lower_data_strobe_0),
.ldm
(lower_data_mask_0),
.udqs
(upper_data_strobe_0),
.udm
(upper_data_mask_0),
.mode_register_in
(),
.ex_mode_register_in
(),
.odt(odt) ); // On-die-termination
qvl_ddr2_sdram_2_0_monitor
#( 1,
/* Constraints_Mode */
203
Monitor Checks
Table 7-13 shows the checks performed by a DDR-II SDRAM 2.0 monitor.
Table 7-13. DDR-II SDRAM 2.0 Monitor Checks
Check ID
Violation
Description
A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR1
A_DDR2_SDRAM_ILLEGAL_
OCD_VALUE_FOR_DDR2_800_
EMR1
204
Violation
Description
A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR2
Bits BA2, A4-A6, and A8A15 are reserved for future use,
and they must be set to 0 when
programming EMR2.
A_DDR2_SDRAM_ILLEGAL_
HTSRR_BIT_STATE_IN_EMR2
A_DDR2_SDRAM_ILLEGAL_
PASR_BIT_STATES_IN_EMR2
A_DDR2_SDRAM_ILLEGAL_
DCC_BIT_STATE_IN_EMR2
A_DDR2_SDRAM_ILLEGAL_
RESERVED_STATES_IN_EMR3
A_DDR2_SDRAM_ODT_
VIOLATION_DURING_DLL_
STABILIZATION
205
Violation
Description
A_DDR2_SDRAM_FIRST_
EMRS_NOT_ISSUED_WITH_
OCD_EXIT
A_DDR2_SDRAM_EMRS2_IS_
NOT_ISSUED_AFTER_FIRST_
PRECHARGE_ALL
A_DDR2_SDRAM_OCD_
DEFAULT_CALIBRATION_NOT_
SET_AFTER_SECOND_MRS
A_DDR2_SDRAM_INVALID_BL_
BEFORE_ENTERING_OCD_
ADJUST_MODE
A_DDR2_SDRAM_OCD_
DRIVE0_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE
A_DDR2_SDRAM_OCD_
DRIVE1_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE
A_DDR2_SDRAM_OCD_
ADJUST_MODE_NOT_
FOLLOWED_BY_OCD_CALI_
EXIT_MODE
206
Violation
Description
A_DDR2_SDRAM_ILLEGAL_
DQ_DQS_IN_OCD_DRIVE0_
MODE
A_DDR2_SDRAM_ILLEGAL_
DQ_DQS_IN_OCD_DRIVE1_
MODE
DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID
DDR2_SDRAM_ADDITIVE_
LATENCY_INVALID_BYPASS
DDR2_SDRAM_ADDRESS_
LEVEL
DDR2_SDRAM_AUTO_
REFRESH_PRECHARGE
DDR2_SDRAM_BANK_LEVEL
207
Violation
Description
DDR2_SDRAM_CAS_LATENCY_
INVALID
DDR2_SDRAM_CAS_LATENCY_
INVALID_BYPASS
DDR2_SDRAM_CAS_LEVEL
DDR2_SDRAM_CKE_LEVEL
DDR2_SDRAM_CONSTRAINTS_
MODE
Constraints_Mode parameter
should be either 1 or 0.
DDR2_SDRAM_CONTROLLER_
SIDE
CONTROLLER_SIDE
parameter should be either 1 or
0.
DDR2_SDRAM_CS_LEVEL
DDR2_SDRAM_DATA_CONFIG
DATA_BUS_WIDTH
parameter should be either 4, 8,
or 16.
DDR2_SDRAM_DLL_NOT_RESET
208
Violation
Description
DDR2_SDRAM_DLL_TRACKING
DLL_TRACKING_ENABLE
parameter should be either 1 or
0
DDR2_SDRAM_DM_RDQS_
LEVEL
DDR2_SDRAM_EMRS_3_
BEFORE_EMRS_2
An EMRS(3) command is
issued prior to an EMRS(2)
command during initialization
sequence.
DDR2_SDRAM_EMRS_BEFORE_
EMRS_3
DDR2_SDRAM_EMRS_
PRECHARGE
DDR2_SDRAM_INCORRECT_
COMMAND_BEFORE_MRS
DDR2_SDRAM_INSUFFICIENT_
AUTO_REFRESH_ACTIVATE
DDR2_SDRAM_LDM_LEVEL
DDR2_SDRAM_MODE_
REGISTER_NOT_SET
209
Violation
Description
DDR2_SDRAM_MRS_
PRECHARGE
DDR2_SDRAM_RAS_LEVEL
DDR2_SDRAM_ROW_ADDRESS
ROW_ADDRESS_WIDTH
parameter should not be less
than the minimum limit of 12.
DDR2_SDRAM_SELF_REFRESH_
PRECHARGE
DDR2_SDRAM_SEQUENTIAL_
ACTIVATION_VIOLATION
DDR2_SDRAM_TCCD
DDR2_SDRAM_TDLL_
VIOLATION_AFTER_DLL_RESET
DDR2_SDRAM_TMRD
DDR2_SDRAM_TRAS
DDR2_SDRAM_TRCD
DDR2_SDRAM_TRFC
DDR2_SDRAM_TRP
210
Violation
DDR2_SDRAM_TRRD
DDR2_SDRAM_TRRD_
VIOLATION
DDR2_SDRAM_TRTW
DDR2_SDRAM_TWR
DDR2_SDRAM_TWTR
DDR2_SDRAM_TXARD
DDR2_SDRAM_TXP
DDR2_SDRAM_TXSNR
DDR2_SDRAM_TXSRD
DDR2_SDRAM_UDM_LEVEL
DDR2_SDRAM_WE_LEVEL
Description
211
Table 7-14 shows the checks for each bank performed by a DDR-II SDRAM 2.0 monitor.
Table 7-14. DDR-II SDRAM 2.0 Monitor Bank Checks
Check ID
Violation
Description
A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_NON_PPD_
MODE
A_DDR2_SDRAM_CLOCK_
CHANGE_DURING_ILLEGAL_CKE
A_DDR2_SDRAM_CLOCK_
FREQUENCY_OUT_OF_RANGE
A_DDR2_SDRAM_CKE_
CHANGED_DURING_UNSTABLE_
CLOCK
212
Violation
A_DDR2_SDRAM_PPD_EXIT_
DURING_UNSTABLE_CLOCK
A_DDR2_SDRAM_DLL_NOT_
RESET_AFTER_PPD_EXIT_
AFTER_CLOCK_CHANGE
DDR2_SDRAM_ACTIVATE
An ACTIVATE command is
issued to an already open bank
without an intervening
PRECHARGE.
DDR2_SDRAM_BAD_DATA
DDR2_SDRAM_BURST_
ABORTED_P
DDR2_SDRAM_BURST_
ABORTED_N
DDR2_SDRAM_CKE_DRIVEN_
LOW
Description
213
Violation
Description
DDR2_SDRAM_CKE_LOW
DDR2_SDRAM_ILLEGAL_
COMMAND_ACT_PWR_DN
DDR2_SDRAM_ILLEGAL_
COMMAND_ACTIVE
DDR2_SDRAM_ILLEGAL_
COMMAND_CBR
DDR2_SDRAM_ILLEGAL_
COMMAND_EMRS
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE
DDR2_SDRAM_ILLEGAL_
COMMAND_IDLE_PWR_DN
214
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_MRS
DDR2_SDRAM_ILLEGAL_
COMMAND_NOP
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE
DDR2_SDRAM_ILLEGAL_
COMMAND_PRE_ALL
DDR2_SDRAM_ILLEGAL_
COMMAND_READ
DDR2_SDRAM_ILLEGAL_
COMMAND_READ_AP
215
Violation
Description
DDR2_SDRAM_ILLEGAL_
COMMAND_SFR
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE
DDR2_SDRAM_ILLEGAL_
COMMAND_WRITE_AP
DDR2_SDRAM_ILLEGAL_RD_
BURST_8B_INTERRUPTION
DDR2_SDRAM_ILLEGAL_WR_
BURST_8B_INTERRUPTION
DDR2_SDRAM_PRECHARGE_
TO_IDLE_BANK
DDR2_SDRAM_RD_BURST_8B_
INTERRUPTED_AT_6B
216
Violation
Description
DDR2_SDRAM_READ_AP_
VIOLATION
DDR2_SDRAM_READ_BEFORE_
WRITE
DDR2_SDRAM_READ_TO_IDLE_
BANK
DDR2_SDRAM_READA_BURST_
8B_INTERRUPTED
DDR2_SDRAM_TCCD_VIOLATION
DDR2_SDRAM_TCKE_VIOLATION
217
Violation
Description
DDR2_SDRAM_TRAS_VIOLATION
DDR2_SDRAM_TRC_VIOLATION
DDR2_SDRAM_TRCD_VIOLATION
DDR2_SDRAM_TRFC_VIOLATION
DDR2_SDRAM_TRP_VIOLATION
DDR2_SDRAM_TRTP_VIOLATION
218
Violation
Description
DDR2_SDRAM_TRTR_VIOLATION
DDR2_SDRAM_TWTP_VIOLATION
DDR2_SDRAM_TWTR_
VIOLATION
DDR2_SDRAM_TWTW_
VIOLATION
DDR2_SDRAM_TXARD_
VIOLATION
219
Violation
Description
DDR2_SDRAM_TXARDS_
VIOLATION
DDR2_SDRAM_TXP_VIOLATION
DDR2_SDRAM_TXSNR_
VIOLATION
DDR2_SDRAM_TXSRD_
VIOLATION
DDR2_SDRAM_UNKNOWN_
STATE
DDR2_SDRAM_WR_BURST_8B_
INTERRUPTED_AT_6B
DDR2_SDRAM_WRITE_TO_IDLE_
BANK
220
Violation
Description
DDR2_SDRAM_WRITEA_BURST_
8B_INTERRUPTED
Description
Interleaved Bursts
Sequential Bursts
NOP Commands
Deselect Commands
Table 7-16 shows the corner cases captured by the DDR-II SDRAM 2.0 monitor for the DDR-II
SDRAM banks.
Table 7-16. DDR-II SDRAM 2.0 Bank Corner Cases
Corner Case
Description
Seamless Reads
Number of times a Read is immediately followed by another Read from the same
bank.
Seamless Writes
221
Description
Posted Reads
Posted Writes
Number of times a read operation is issued to a page that is already opened for
read in the bank.
Number of times a read operation is issued to a page that is already opened for
write in the bank.
Number of times a write operation is issued to a page that is already opened for
read in the bank.
Number of times a write operation is issued to a page that is already opened for
write in the bank.
Monitor Statistics
Table 7-17 lists the statistics collected for the protocol.
Table 7-17. DDR-II SDRAM 2.0 Monitor Statistics
Statistic
Description
Total number of data accesses to the DDR-II SDRAM for all banks.
222
Statistic
Description
Chapter 8
Gigabit Ethernet
Introduction
The Ethernet Standard ISO/IEC 8802-3 (CSMA/CD MAC) is a comprehensive International
Standard for Local Area Networks (LANs) employing CSMA/CD as the access method. This
International Standard encompasses several media types and techniques for signal rates from
1 Mb/s to 100 Mb/s.
Gigabit Ethernet couples an extended version of the ISO/IEC 8802-3 (CSMA/CD MAC) to a
family of 1000 Mb/s Physical Layers by extending the ISO/IEC 8802-3 MAC beyond 100 Mb/s
to 1000 Mb/s. The 10 Gigabit Ethernet further extends the IEEE 802.3 MAC beyond 1000 Mb/s
to 10 Gb/s. Similarly, 40G and 100G further extends the IEEE 802.3 MAC beyond 10Gb/s to
40Gb/s and 100Gb/s, respectively. The bit rate is faster and the bit times are shorter both in
proportion to the change in bandwidth. The minimum packet transmission time has been
reduced by a factor of ten. Achievable topologies for 10 Gb/s operation are comparable to those
found in 1000BASE-X Full Duplex mode and equivalent to those found in WAN applications.
The IEEE 802.3 and IEEE 802.3ae Standards define these interfaces as follows:
10/100M Ethernet Media Independent Interface (MII) between a MAC and PHY.
Gigabit Media Independent Interface (GMII) between a 1Gb/s MAC and PHY.
Ten Gigabit Media Independent Interface (XGMII) between a 10 Gb/s MAC and PHY.
Gigabit Interface (TBI) between PCS and PMA (in the case of 1000BASE-X PHYs).
Ten Gigabit Attachment Unit Interface (XAUI) between two 10 Gigabit Extenders.
Ten Gigabit Sixteen Bit Interface (XSBI) between PCS and PMA (in the case of
10GBASE-R PHYs).
Hundred Gigabit Interface (XLAUI) and Forty Gigabit interface (CAUI) (in the case of
100GBASE-R and 40GBASE-R PHYs).
The QVL Gigabit Ethernet monitor is designed for checking these Gigabit Ethernet interfaces.
Questa Verification Library Monitors Data Book, v2010.2
223
Gigabit Ethernet
Reference Documentation
In addition to the above interfaces, QVL Gigabit Ethernet Monitor also checks Low pin count
Reduced Media Independent Interface (RMII) between a MAC and PHY and Reduced Gigabit
Media Independent Interface (RGMII) for 1G speed. Also, it supports Gigabit Serial Interface
(SGMII for 1G speed only) and Reduced Ten Bit Interface (RTBI) between PCS and PMA.
Reference Documentation
This version of the Gigabit Ethernet monitor is modeled from the requirements provided in the
following documents:
802.3 IEEE Standard for Information Technology, CSMA/CD access method and
physical layer specifications, 2002.
802.3ae Amendment: Media Access Control (MAC) Parameters and Physical Layers for
10 Gb/s Operation, 2002.
P802.3ba D2.1 draft Amendment: Media Access Control Parameters, Physical Layers
and Management Parameters for 40 Gb/s and 100 Gb/s Operation.
Supported Features
Gigabit Media Independent Interface (GMII)
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
224
Single clock reference sourced from MAC to PHY (or from an external source)
Gigabit Ethernet
Supported Features
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Single clock reference sourced from MAC to PHY (or from an external source)
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
64-bit single data rate and 32-bit dual data rate modes
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
225
Gigabit Ethernet
Supported Features
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Link synchronization
8b/10b decoding
226
Gigabit Ethernet
Supported Features
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Link synchronization
8b/10b decoding
4-bit serial (1-bit per lane) and 10-bit symbol (10-bits per lane) modes
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Lane synchronization
8b/10b decoding
XAUI Limitation
The XAUI monitor is designed to support dual data rate (DDR) mode only. There is a
workaround if the user is using the single data rate (SDR) mode on the parallel interface. If your
serial interface uses a DDR mode, then use the monitors serial interface. To implement an SDR
workaround for the parallel interface, the user can hook-up a divide-by-2 clock to simulate the
DDR mode.
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
227
Gigabit Ethernet
Supported Features
Descrambling
64b/66b decoding
Block synchronization
1, 2, and 4 lanes for 40G and 1, 2, 4, 5, 10, and 20 lanes for 100G
Jumbo frames Untagged, VLAN tagged, and Priority tagged Jumbo frame
Descrambling
64b/66b decoding
228
DME timing
Gigabit Ethernet
Monitor Placement and Instantiation
Start 8'hFB
Terminate 8'hFD
Error 8'hFE
Idle 8'h07
Sequence 8'h9C
Unsupported Features
10GBASE-W PHYs
MDIO Interface
229
Gigabit Ethernet
Monitor Connectivity
MAC/ RS
XAUI
QVL
Monitor
XAUI
XGXS
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor
XGMII
XGMII
QVL
Monitor
XGMII
QVL
Monitor
XAUI
QVL
Monitor
XGXS
XGMII
QVL
Monitor
TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor
GMII
XGMII
MII
RMII
XLGMII
CGMII
QVL
Monitor
MAC
XAUI /
XSBI
TBI
SGMII
XAUI
XSBI
XLAUI
CAUI
QVL
Monitor
PMA
PHY
The QVL 10/100M Ethernet monitor can be placed on either side of a MII link to provide
interface checks. This can be on the Reconciliation Sublayer (MAC side) or the PHY side of the
link.
In the above interface, the MAC_SIDE parameter in the monitor can be used to configure the
monitor instance to be on the interface closer to the MAC or closer to the medium. The checks
in the 10/100M Ethernet monitor can also be used as search targets and check constraints while
running formal analysis on the 10/100M Ethernet components.
Monitor Connectivity
Connect the Gigabit Ethernet monitor pins as shown in Figure 8-2. Refer to pin-out Table 8-1
on page 232 through Table 8-10 on page 236 for the pin descriptions.
230
Gigabit Ethernet
Monitor Connectivity
tx_clk
txd[63:0]
txc[7:0]
40/100G GIGABIT
ETHERNET
(XLGMII/CGMII)
Monitor
rx_clk
rxd[63:0]
rxc[7:0]
areset
reset
an_clk
tx_clk
rx_clk
tx_data[19:0]
rx_data[19:0]
Auto-Negotiation
Monitor
SOURCE
sl_clk
sl0_p
sl1_p
sl2_p
sl3_p
10 GIGABIT
ETHERNET
(XAUI) Monitor
dl_clk
dl0_p
dl1_p
dl2_p
dl3_p
areset
reset
TBI
Monitor
tx_clk
txd
rx_clk
rxd
areset
reset
txc
td[3:0]
tx_ctl
RTBI
Monitor
rxc
rd[3:0]
rx_ctl
areset
reset
tx_clk
txd
DESTINATION
TRANSMIT
RECEIVE
areset
reset
areset
reset
10/100M
ETHERNET
(RMII) Monitor
10 GIGABIT
ETHERNET
(XSBI) Monitor
rx_clk
rxd
bypass_descramble
TRANSMIT
rx_clk
rxd
rxc
TRANSMIT
10 GIGABIT
ETHERNET
(XGMII) Monitor
10/100M
ETHERNET
(MII) Monitor
areset
reset
ref_clk
txd[1:0]
tx_en
txd[1:0]
crs_dv
rx_er
RECEIVE
tx_clk
txd
txc
areset
reset
tx_clk
txd[3:0]
tx_en
tx_er
rx_clk
rxd[3:0]
rx_dv
rx_er
col
crs
RECEIVE TRANSMIT
areset
reset
TRANSMIT
1 GIGABIT
ETHERNET
(GMII) Monitor
RECEIVE
areset
reset
tx_clk
txd[7:0]
tx_en
tx_er
rx_clk
rxd[7:0]
rx_dv
rx_er
col
crs
RECEIVE
RECEIVE
TRANSMIT RECEIVE
TRANSMIT
RECEIVE
TRANSMIT
RECEIVE TRANSMIT
RECEIVE
TRANSMIT
areset
reset
tx_clk
tx_lane[PHYSICAL_
LANE_COUNT-1:0]
rx_clk
rx_lane[PHYSICAL_
LANE_COUNT-1:0]
caui_interface
fec_enable
40/100M GIGABIT
ETHERNET
(XLAUI/CAUI)
Monitor
231
Gigabit Ethernet
Monitor Connectivity
Description
areset
col
Collision detect.
crs
Carrier sense.
half_duplex
reset
rx_clk
rx_dv
rx_er
Receive error.
rxd[7:0]
tx_clk
tx_en
Transmit enable.
tx_er
Transmit error.
txd[7:0]
232
Port
Description
areset
half_duplex
reset
rxc
rxd[3:0]
rx_ctl
Receive Control.
txc
tx_ctl
Transmit Control.
txd[3:0]
Gigabit Ethernet
Monitor Connectivity
Description
areset
col
Collision detect.
crs
Carrier sense.
half_duplex
reset
rx_clk
rx_dv
rx_er
Receive error.
rxd[3:0]
tx_clk
tx_en
Transmit enable.
tx_er
Transmit error.
txd[3:0]
Description
areset
crs_dv
half_duplex
reset
ref_clk
rxd[1:0]
rx_er
Receive Error.
txd[1:0]
tx_en
Transmit enable.
233
Gigabit Ethernet
Monitor Connectivity
Description
areset
reset
rx_clk
rxc[3:0] / [7:0]
Receive control lines (1 line for each lane (byte) of RXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).
rxd[31:0] / [63:0]
Receive data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).
tx_clk
txc[3:0] / [7:0]
Transmit control lines (1 line for each lane (byte) of TXD, 4 bits in case of
DDR mode and 8 bits in case of SDR mode).
txd[31:0] / [63:0]
Transmit data (4 lanes of 1 byte each in case of DDR 32-bit mode and 8 lanes
of 1 byte each in case of SDR 64-bit mode).
Description
areset
reset
tx_clk
txd[63:0]
txc[7:0]
rx_clk
rxd[63:0]
rxc[7:0]
234
Port
Description
areset
half_duplex
Gigabit Ethernet
Monitor Connectivity
Table 8-7. 1000BASE-X Ten bit Interface Monitor Pin Descriptions (cont.)
Port
Description
reset
tx_clk
txd
rx_clk
rxd
Description
areset
half_duplex
reset
txc
td[3:0]
tx_ctl
Transmit control.
rxc
rd[3:0]
rx_ctl
Receive control,
Description
areset
dl0_p
Destination lane 0.
dl1_p
Destination lane 1.
dl2_p
Destination lane 2.
dl3_p
Destination lane 3.
dl_clk
reset
sl0_p
Source lane 0.
sl1_p
Source lane 1.
235
Gigabit Ethernet
Monitor Connectivity
Description
sl2_p
Source lane 2.
sl3_p
Source lane 3.
sl_clk
Note that if SYMBOL_MODE = 1, then sl0_p, sl1_p, sl2_p, sl3_p, dl0_p, dl1_p, dl2_p, and dl3_p are 10-bits
wide; otherwise 1-bit wide.
Description
areset
bypass_descramble
reset
rx_clk
rxd
tx_clk
txd
Note that if SYMBOL_MODE = 1, then both rxd and txd are 16-bits wide; otherwise 1-bit wide.
Description
areset
reset
rx_clk
rx_lanes[PHYSICAL_LANE_COUNT-1:0]
tx_clk
tx_lanes[PHYSICAL_LANE_COUNT-1:0]
caui_interface
fec_enable
236
Gigabit Ethernet
Monitor Connectivity
Description
areset
reset
an_clk
Sampling clock (not part of standard I/F signals). It is used to sample DME
encoded data.
rx_clk
rx_data[19:0]
tx_clk
tx_data[19:0]
Notes:
1. In 64-bit SDR mode of operation of the XGMII monitor, one clock of data in the DDR
mode comprising of two columns are mapped to one column of twice the length. If say
the two columns of data in the 32-bit (DDR) mode are denoted as {d00, d01, d02,
d03} and {d10, d11, d12, d13} where d00 and d10 are the lane0 data
respectively, then the corresponding 64-bit (SDR) data is {d00, d01, d02, d03,
d10, d11, d12, d13}, where d00 is lane0 data.
2. In Full Duplex mode of operation, the CRS (carrier sense) and COL (collision detect)
signals have no meaning and can be left unconnected.
3. In TBI/RTBI/XAUI mode, the monitor only takes in the lane_p component of the
balanced differential pair {lane_p, lane_n}.
4. If {a,b,c,d,e,i,f,g,h,j} is the 10-bit encoded data, then the TBI/RTBI/XAUI
assumes the first bit received to be a and the last bit to be j in the serial mode of
operation, and the most significant bit as j and the least significant bit as a in the 10bit symbol mode of operation.
5. In XLAUI/CAUI mode, caui_interface and fec_enable are used when auto
negotiation mode is enabled to dynamically change the values. Otherwise, they are
ignored and can be tied to any value.
237
Gigabit Ethernet
Monitor Connectivity
Monitor Parameters
The parameters shown in the following tables configure the Gigabit Ethernet monitor.
Table 8-13. GMII Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
7.
SLOT_TIME
512
8.
JAM_SIZE
32
9.
BURST_LIMIT
65536
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-1 on page 232 for a detailed description.
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
238
Gigabit Ethernet
Monitor Connectivity
Parameter
Default
Description
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
7.
SLOT_TIME
512
8.
JAM_SIZE
32
9.
BURST_LIMIT
65536
10.
DUPLEX_MODE_
INDICATION
11.
CLK_SPEED_
INDICATION
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-2 on page 232 for a detailed description.
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
239
Gigabit Ethernet
Monitor Connectivity
Parameter
Default
Description
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
7.
SLOT_TIME
64
8.
JAM_SIZE
32
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-3 on page 233 for a detailed description.
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
240
Gigabit Ethernet
Monitor Connectivity
Default
Description
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-1 on page 232 for a detailed description.
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
DDR
6.
DIC_SUPPORTED
7.
MAC_MIN_TAGGED_
FRAME_SIZE_68
8.
RESERVED_CONTROL_
FRAME_SUPPORTED
241
Gigabit Ethernet
Monitor Connectivity
Parameter
Default Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
DIC_SUPPORTED
6.
MAC_MIN_TAGGED_
FRAME_SIZE_68
7.
RESERVED_CONTROL_
FRAME_SUPPORTED
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
SYMBOL_MODE
4.
JUMBO_FRAME_DATA_
LENGTH
9216
242
Gigabit Ethernet
Monitor Connectivity
Parameter
Default
Description
5.
RESERVED_VALUE_
CHECK_ENABLE
6.
MAC_MIN_TAGGED_
FRAME_SIZE_68
7.
RESERVED_CONTROL_
FRAME_SUPPORTED
8.
SLOT_TIME
512
9.
JAM_SIZE
32
10.
BURST_LIMIT
65536
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-7 on page 234 for a detailed description.
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
MAC_MIN_TAGGED_
FRAME_SIZE_68
6.
RESERVED_CONTROL_
FRAME_SUPPORTED
243
Gigabit Ethernet
Monitor Connectivity
Parameter
Default
Description
7.
SLOT_TIME
512
8.
JAM_SIZE
32
9.
BURST_LIMIT
65536
Notes:
1. The parameters must be specified in the above order.
2. The HALF_DUPLEX parameter is deprecated; instead a pin is added for dynamic switch between
half duplex and full duplex modes. See Table 8-8 on page 235 for a detailed description.
244
Order
Parameter
Default
Default
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_
LENGTH
9216
4.
RESERVED_VALUE_
CHECK_ENABLE
5.
SYMBOL_MODE
6.
BYPASS_DESKEW
7.
DIC_SUPPORTED
8.
MAC_MIN_TAGGED_
FRAME_SIZE_68
Gigabit Ethernet
Monitor Connectivity
Parameter
Default
Default
9.
RESERVED_CONTROL_
FRAME_SUPPORTED
Parameter
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_LENGTH 9216
4.
RESERVED_VALUE_CHECK_
ENABLE
5.
BYPASS_BLOCK_SYNC
6.
DIC_SUPPORTED
7.
MAC_MIN_TAGGED_FRAME_
SIZE_68
8.
RESERVED_CONTROL_FRAME_
SUPPORTED
9.
SYMBOL_MODE
245
Gigabit Ethernet
Monitor Connectivity
Default Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
JUMBO_FRAME_DATA_LENGTH
9216
4.
RESERVED_VALUE_CHECK_ENABLE
5.
CAUI_INTERFACE
6.
FEC_ENABLE
7.
AM_COUNTER_16383
800
8.
AM_LOCK_ON_FIRST_AM
9.
AUTONEG_MODE
10.
PHYSICAL_LANE_COUNT
11.
DIC_SUPPORTED
12.
MAC_MIN_TAGGED_FRAME_SIZE_68
246
Gigabit Ethernet
Monitor Connectivity
Default Description
13.
RESERVED_CONTROL_FRAME_
SUPPORTED
Default
Description
1.
Constraints_Mode
2.
MAC_SIDE
3.
CLK_TO_CLK_MIN_CYCLES
62
4.
CLK_TO_CLK_MAX_CYCLES
66
5.
CLK_TO_DATA_MIN_CYCLES
30
6.
CLK_TO_DATA_MAX_CYCLES
34
7.
MANCHESTER_DELIMITER_MIN_
CYCLES
126
247
Gigabit Ethernet
Monitor Connectivity
Default
Description
8.
MANCHESTER_DELIMITER_MAX_
CYCLES
130
Parameter MANCHESTER_
DELIMITER_MAX_CYCLES holds the
maximum number of an_clk (sampling
clock) posedge that must be sampled for
considering valid Manchester violation
delimiter. The default value 130
corresponds to maximum T6 value 13.0 ns
assuming an_clk to be of period 0.1 ns.
9.
REMAINING_ACK_COUNT_MIN
10.
REMAINING_ACK_COUNT_MAX
11.
BREAK_LINK_TIMER_CYCLES
100000
12.
PHYSICAL_LANE_COUNT
13.
JUMBO_FRAME_DATA_LENGTH
9216
14.
RESERVED_VALUE_CHECK_ENABLE
15.
BYPASS_BLOCK_SYNC
16.
DIC_SUPPORTED
17.
MAC_MIN_TAGGED_FRAME_
SIZE_68
248
Gigabit Ethernet
Monitor Connectivity
Default
Description
18.
BYPASS_DESKEW
19.
AM_COUNTER_16383
800
20.
AM_LOCK_ON_FIRST_AM
NOTE:
One can use user type frame (Len/Type) by defining the following:
Example:
The user can configure QVL to support two types, say 16'h0800 and 16'h0900, by defining the
above defines as follows:
+define+QVL_GBIT_USER_TYPES_COUNT=2
+define+QVL_GBIT_USER_TYPES="32'h08000900"
Instantiation Examples
Example 1
Example 8-1 instantiates a 1 Gigabit Ethernet GMII monitor on the MAC side (on the
Reconciliation Sublayer) with the Jumbo frame size configured as 9216. The reserved value
checking is disabled and the monitor is instantiated in Half Duplex mode.
Example 8-1. 1 Gigabit Ethernet GMII Monitor Instantiation
qvl_gigabit_ethernet_gmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
249
Gigabit Ethernet
Monitor Connectivity
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536)
)
GMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
.half_duplex(half_duplex));
Example 2
Example 8-2 instantiates a 1G RGMII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-2. Reduced Gigabit Ethernet RGMII Monitor Instantiation
qvl_gigabit_ethernet_rgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.DUPLEX_MODE_INDICATION(0),
.CLK_SPEED_INDICATION(0)
)
RGMII_MONITOR
(.areset (areset),
.reset (reset),
.txc (txc),
.td (td),
.tx_ctl (tx_ctl),
.rxc (rxc),
.rd (rd),
.rx_ctl (rx_ctl),
.half_duplex(half_duplex));
250
Gigabit Ethernet
Monitor Connectivity
Example 3
Example 8-3 instantiates a 10/100M MII monitor on the MAC side (on the Reconciliation
Sublayer) with the Jumbo frame size configured as 9216. The reserved value checking is
disabled and the monitor is instantiated in Half Duplex mode.
Example 8-3. 10/100M Gigabit Ethernet MII Monitor Instantiation
qvl_gigabit_ethernet_mii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(64),
.JAM_SIZE(32)
)
MII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.tx_en (tx_en),
.tx_er (tx_er),
.rx_clk (rx_clk),
.rxd (rxd),
.rx_dv (rx_dv),
.rx_er (rx_er),
.col (col),
.crs (crs),
.half_duplex(half_duplex));
Example 4
Example 8-4 instantiates a RMII monitor on the MAC side (on the Reconciliation Sublayer)
with the Jumbo frame size configured as 9216. The reserved value checking is disabled and the
monitor is instantiated in Half Duplex mode.
Example 8-4. 10/100M Gigabit Ethernet RMII Monitor Instantiation
qvl_gigabit_ethernet_rmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
RMII_MONITOR
(.areset (areset),
.reset (reset),
.ref_clk (ref_clk),
251
Gigabit Ethernet
Monitor Connectivity
.txd (txd),
.tx_en (tx_en),
.rxd (rxd),
.crs_dv (crs_dv),
.rx_er (rx_er),
.half_duplex(half_duplex));
Example 5
Example 8-5 instantiates a 10 Gigabit Ethernet XGMII monitor on the PHY side (on the XGMII
interface of the first XGXS from MAC or XGMII interface of PCS) with the Jumbo frame size
configured as 4096. The reserved value checking is enabled and the monitor is instantiated in
the single edge 64-bit mode.
Example 8-5. 10 Gigabit Ethernet XGMII Monitor Instantiation
qvl_gigabit_ethernet_xgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));
Example 6
Example 8-6 instantiates a 40/100 Gigabit Ethernet XLMGMII/CGMII monitor on the PHY
side (on the MAC side) with the Jumbo frame size configured as 9216. The reserved value
checking is enabled.
Example 8-6. 40/100 Gigabit Ethernet XLGMII/CGMII Monitor Instantiation
qvl_gigabit_ethernet_xlgmii_cgmii_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
252
Gigabit Ethernet
Monitor Connectivity
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XGMII_MONITOR
(.areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.txd (txd),
.txc (txc),
.rx_clk (rx_clk),
.rxd (rxd),
.rxc (rxc));
Example 7
Example 8-7 instantiates a 1000BASE-X TBI monitor on the MAC side with symbol model set
to 1 with the Jumbo frame size configured as 9216. The reserved value checking is disabled and
the monitor is instantiated in Half Duplex mode.
Example 8-7. 1000BASE-X TBI Monitor
qvl_gigabit_ethernet_tbi_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.SYMBOL_MODE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
TBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.tx_clk(tx_clk),
.txd(txd_10b),
.rx_clk(rx_clk),
.rxd(rxd_10b),
.half_duplex(half_duplex));
Example 8
Example 8-8 instantiates a Reduced Ten bit interface monitor on the MAC side with the Jumbo
frame size configured as 9216. The reserved value checking is disabled and the monitor is
instantiated in Half Duplex mode.
Example 8-8. Reduced Ten bit Interface Monitor
qvl_gigabit_ethernet_rtbi_monitor #(
.Constraints_Mode(0),
253
Gigabit Ethernet
Monitor Connectivity
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(1),
.SLOT_TIME(512),
.JAM_SIZE(32),
.BURST_LIMIT(65536))
RTBI_MONITOR (
(.areset(1'b0),
.reset(reset),
.txc(txc),
.td(td),
.tx_ctl(tx_ctl),
.rxc(rxc),
.rd(rd),
.rx_ctl(rx_ctl),
.half_duplex(half_duplex));
Example 9
Example 8-9 instantiates a 10 Gigabit Ethernet XAUI monitor on the MAC side (on the XAUI
interface of the first XGXS from MAC or XAUI interface of PCS) with the Jumbo frame size
configured as 9216. The reserved value checking is enabled and the monitor is instantiated in
symbol mode (ten-bit interface) with deskew enabled.
Example 8-9. 10 Gigabit Ethernet XAUI Monitor Instantiation
qvl_gigabit_ethernet_xaui_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.BYPASS_DESKEW(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XAUI_MONITOR
(.areset (areset),
.reset (reset),
.dl_clk (dl_clk),
.sl_clk (sl_clk),
.sl0_p (sl0_p),
.sl1_p (sl1_p),
.sl2_p (sl2_p),
.sl3_p (sl3_p),
.dl0_p (dl0_p),
.dl1_p (dl1_p),
.dl2_p (dl2_p),
.dl3_p (dl3_p));
254
Gigabit Ethernet
Monitor Connectivity
Example 10
Example 8-10 instantiates a 10 Gigabit Ethernet XSBI monitor on the PHY side (on the XSBI
interface of PMA) with the Jumbo frame size configured as 1024. The reserved value checking
is disabled and the monitor is instantiated with block synchronization disabled and
descrambling enabled.
Example 8-10. 10 Gigabit Ethernet XSBI Monitor Instantiation
qvl_gigabit_ethernet_xsbi_monitor #(
.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.BYPASS_BLOCK_SYNC(0),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(1),
.RESERVED_CONTROL_FRAME_SUPPORTED(1)
)
XSBI_MONITOR
(areset (areset),
.reset (reset),
.tx_clk (tx_clk),
.rx_clk (rx_clk),
.txd (txd),
.rxd (rxd),
.bypass_descramble (bypass_descramble));
Example 11
Example 8-11 instantiates a 100 Gigabit Ethernet XLAUI monitor on the PHY side (on the
CAUI interface of PMA) with the am counter value 1200 and physical lane count 5. The
reserved value checking is disabled.
Example 8-11. 100 Gigabit Ethernet CAUI Monitor Instantiation
qvl_gigabit_ethernet_xlaui_caui_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.CAUI_INTERFACE(1),
.FEC_ENABLE(0),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.AUTONEG_MODE(0),
.PHYSICAL_LANE_COUNT(5),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
CAUI_MONITOR
.areset(areset),
.reset (reset ),
255
Gigabit Ethernet
Monitor Checks
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.caui_interface(1'b0),
.fec_enable(1'b0),
.tx_lanes(tx_lanes),
.rx_lanes(rx_lanes));
Example 12
Example 8-12 instantiates a 40/100G Auto-Negotiation monitor on the PHY side. The reserved
value checking is disabled.
Example 8-12. 100 Gigabit Ethernet Auto-Negotiation Monitor Instantiation
qvl_gigabit_ethernet_an_monitor #
(.Constraints_Mode(0),
.MAC_SIDE(1),
.JUMBO_FRAME_DATA_LENGTH(9216),
.RESERVED_VALUE_CHECK_ENABLE(0),
.AM_COUNTER_16383(1200),
.AM_LOCK_ON_FIRST_AM(1),
.DIC_SUPPORTED(1),
.MAC_MIN_TAGGED_FRAME_SIZE_68(0),
.RESERVED_CONTROL_FRAME_SUPPORTED(0))
AN_MONITOR
.areset(areset),
.reset (reset ),
.an_clk(an_clk),
.tx_clk(tx_clk),
.rx_clk(rx_clk),
.tx_data(tx_data),
.rx_data(rx_data));
Monitor Checks
The checks performed by the Gigabit Ethernet monitor are classified as follows:
MAC checks
These validate frame formation with regards to the size, type, address, FCS, and
interframe gap requirements. These are listed in Table 8-25 on page 258.
GMII checks
These validate 1Gb/s specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-26 on page 261
256
RGMII checks
Gigabit Ethernet
Monitor Checks
These validate RGMII specific requirements (for 1 Gbps speed), mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-27 on page 263.
MII checks
These validate 10/100M specific requirements, mainly with regards to the Half Duplex
mode of operation. These are listed in Table 8-28 on page 265.
RMII checks
These validate 10/100M specific requirements of RMII Interface, mainly with regards to
the Half Duplex mode of operation. These are listed in Table 8-29 on page 268.
XGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XGMII interface. These are listed in Table 8-30 on page 269.
XLGMII/CGMII checks
These validate lane alignment, frame encapsulation, and control character related
requirements in an XLGMII/CGMII interface These are listed in Table 8-31 on
page 272.
TBI/RTBI checks
These validate 8B/10B encoding, link synchronization, ordered set location, and code
group requirements. These are listed in Table 8-32 on page 273.
XAUI checks
These validate 8B/10B encoding, link synchronization and alignment, ordered set
location, and spacing requirements. These are listed in Table 8-33 on page 275.
XLAUI/CAUI checks
These validate lane synchronization, alignment marker and deskew error. These are
listed in Table 8-35 on page 282.
257
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_P
GIGABIT_ETHERNET_
CONTROL_FRAME_
LENGTH_VIOLATION_N
GIGABIT_ETHERNET_
CRC_VIOLATION_P
GIGABIT_ETHERNET_
CRC_VIOLATION_N
GIGABIT_ETHERNET_
FRAME_LENGTH_
MISMATCH_VIOLATION_P
GIGABIT_ETHERNET_
FRAMELENGTH_
MISMATCH_VIOLATION_N
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_P
GIGABIT_ETHERNET_
LENGTH_TYPE_VIOLATION_N
GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_P
GIGABIT_ETHERNET_
MAX_FRAME_SIZE_
VIOLATION_N
258
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_P
GIGABIT_ETHERNET_
MIN_FRAME_SIZE_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_DEST_ADDR_
VIOLATION_N
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_P
GIGABIT_ETHERNET_
PAUSE_RESERVED_
VIOLATION_N
GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_P
GIGABIT_ETHERNET_
PREAMBLE_VIOLATION_N
GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_P
GIGABIT_ETHERNET_
RESERVED_CONTROL_
OPCODE_N
259
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_P
GIGABIT_ETHERNET_
RX_MIN_IFG_VIOLATION_N
GIGABIT_ETHERNET_
SFD_VIOLATION_P
GIGABIT_ETHERNET_
SFD_VIOLATION_N
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_P
GIGABIT_ETHERNET_
SOURCE_ADDR_VIOLATION_N
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_P
GIGABIT_ETHERNET_
TX_MIN_IFG_VIOLATION_N
GIGABIT_ETHERNET_
TYPE_VIOLATION_P
GIGABIT_ETHERNET_
TYPE_VIOLATION_N
260
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_GMII_
CAR_EXTN_ON_RX_
WITHOUT_FRAME
GIGABIT_ETHERNET_GMII_
CAR_EXTN_ON_TX_
WITHOUT_FRAME
GIGABIT_ETHERNET_GMII_
CAR_EXTN_FULL_DUPLEX_
VIOLATION
GIGABIT_ETHERNET_GMII_
COLLISION_DETECTED_
WITHOUT_CAR
GIGABIT_ETHERNET_GMII_
CRS_DEASSERTED_DURING_
COLLISION
GIGABIT_ETHERNET_GMII_
RESERVED_VALUES_ON_RX_
INTERFACE
GIGABIT_ETHERNET_GMII_
RESERVED_VALUES_ON_TX_
INTERFACE
GIGABIT_ETHERNET_GMII_
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE
261
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_GMII_
RX_START_WITH_
NON_PREAMBLE_OR_SFD
GIGABIT_ETHERNET_GMII_
TX_ASSERTED_WHEN_
CAR_SENSED
GIGABIT_ETHERNET_GMII_
TX_ASSERTED_WHEN_
COLLISION_DETECTED
GIGABIT_ETHERNET_GMII_
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE
GIGABIT_ETHERNET_GMII_
TX_START_WITH_
NON_PREAMBLE
GIGABIT_ETHERNET_GMII_
TX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
GIGABIT_ETHERNET_GMII_
RX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
GIGABIT_ETHERNET_GMII_
TX_EXTN_ERR
GIGABIT_ETHERNET_GMII_
RX_EXTN_ERR
262
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_FALSE_
CAR_INDICATION
GIGABIT_ETHERNET_GMII_
BURST_LIMIT_EXCEEDED
GIGABIT_ETHERNET_GMII_
INCORRECT_EXTN_LENGTH
GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED
GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED
GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT
Violation
Description
GIGABIT_ETHERNET_RGMII_
RESERVED_VALUES_ON_RX_
INTERFACE
GIGABIT_ETHERNET_RGMII_
RESERVED_VALUES_ON_TX_
INTERFACE
263
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_RGMII_
RX_INTERFACE_ACTIVE_
WHEN_TX_ACTIVE
GIGABIT_ETHERNET_RGMII_
RX_START_WITH_
NON_PREAMBLE_OR_SFD
GIGABIT_ETHERNET_RGMII_
TX_INTERFACE_ACTIVE_
WHEN_RX_ACTIVE
GIGABIT_ETHERNET_RGMII_
TX_START_WITH_
NON_PREAMBLE
GIGABIT_ETHERNET_RGMII_
TX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
GIGABIT_ETHERNET_RGMII_
RX_ER_ASSERTED_DURING_
FRAME_TRANSMISSION
GIGABIT_ETHERNET_RGMII_
TX_EXTN_ERR
GIGABIT_ETHERNET_RGMII_
RX_EXTN_ERR
GIGABIT_ETHERNET_RGMII_
INVALID_DUPLEX_STATUS
GIGABIT_ETHERNET_RGMII_
INVALID_CLK_SPEED_STATUS
GIGABIT_ETHERNET_RGMII_
RESERVED_CLK_SPEED_
STATUS
264
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_RGMII_
INVALID_NIBBLES_ON_
NEGEDGE_INTERFRAME
GIGABIT_ETHERNET_FALSE_
CAR_INDICATION
GIGABIT_ETHERNET_GMII_
BURST_LIMIT_EXCEEDED
GIGABIT_ETHERNET_GMII_
INCORRECT_EXTN_LENGTH
GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED
GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED
GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT
Violation
Description
ETHERNET_MII_COLLISION_
DETECTED_WITHOUT_CAR
265
Gigabit Ethernet
Monitor Checks
Violation
Description
ETHERNET_MII_CRS_
DEASSERTED_
DURING_COLLISION
ETHERNET_MII_RESERVED_
VALUES_ON_RX_
INTERFACE
ETHERNET_MII_RESERVED_
VALUES_ON_TX_
INTERFACE
ETHERNET_MII_RX_
EXTRA_NIBBLE_
DETECTED
ETHERNET_MII_RX_
INTERFACE_ACTIVE_
WHEN_TX_ACTIVE
ETHERNET_MII_RX_
START_WITH_NON_
PREAMBLE_OR_SFD
ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
CAR_SENSED
266
Gigabit Ethernet
Monitor Checks
Violation
Description
ETHERNET_MII_TX_EN_
ASSERTED_WHEN_
COLLISION_DETECTED
ETHERNET_MII_TX_
EXTRA_NIBBLE_
DETECTED
ETHERNET_MII_TX_
INTERFACE_ACTIVE_
WHEN_RX_ACTIVE
ETHERNET_MII_TX_
START_WITH_NON_
PREAMBLE
ETHERNET_MII_
TX_ER_ASSERTED_DURING_
FRAME
ETHERNET_MII_
RX_ER_ASSERTED_DURING_
FRAME
GIGABIT_ETHERNET_FALSE_
CAR_INDICATION
GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED
GIGABIT_ETHERNET_LATE_
COLLISION_DETECTED
267
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_JAM_
SIZE_NOT_CORRECT
Violation
Description
ETHERNET_RMII_RESERVED_
VALUES_ON_RX_INTERFACE:
ETHERNET_RMII_RESERVED_
VALUES_ON_TX_INTERFACE
ETHERNET_RMII_RX_INTERFACE_
ACTIVE_WHEN_TX_ACTIVE
ETHERNET_RMII_RX_START_
WITH_NON_PREAMBLE_OR_SFD
ETHERNET_RMII_TX_INTERFACE_
ACTIVE_WHEN_RX_ACTIVE
ETHERNET_RMII_TX_START_
WITH_NON_PREAMBLE
268
Gigabit Ethernet
Monitor Checks
Violation
Description
ETHERNET_RMII_RX_ER_
ASSERTED_DURING_FRAME
ETHERNET_RMII_FALSE_
CAR_INDICATION
GIGABIT_ETHERNET_PAUSE_
FRAME_DETECTED
Violation
Description
GIGABIT_ETHERNET_XGMII_
IDLE_BEFORE_TERM_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
IDLE_BEFORE_TERM_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
IDLE_COLUMN_VIOLATION_P
GIGABIT_ETHERNET_XGMII_
IDLE_COLUMN_VIOLATION_N
GIGABIT_ETHERNET_XGMII_
NON_IDLE_OR_SEQ_PRIOR_TO_
START_P
GIGABIT_ETHERNET_XGMII_
NON_IDLE_OR_SEQ_PRIOR_TO_
START_N
269
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XGMII_
RSVD_CONTROL_CHAR_
VIOLATION_P
Reserved control
characters should not be
used.
GIGABIT_ETHERNET_XGMII_
RSVD_CONTROL_CHAR_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
RX_ERROR_CONTROL_
CHARACTER_DETECTED_P
GIGABIT_ETHERNET_XGMII_
RX_ERROR_CONTROL_
CHARACTER_DETECTED_N
GIGABIT_ETHERNET_XGMII_
SEQUENCE_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SEQUENCE_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
SEQUENCE_OS_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SEQUENCE_OS_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
SFD_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
SFD_ALIGNMENT_
VIOLATION_N
270
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XGMII_
START_ALIGNMENT_
VIOLATION_P
When Terminate is
detected, all lanes
following the terminate
character should carry idle
control character.
GIGABIT_ETHERNET_XGMII_
START_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
START_BEFORE_TERM_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
START_BEFORE_TERM_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TERM_BEFORE_START_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
TERM_BEFORE_START_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TERMINATE_COLUMN_
VIOLATION_P
GIGABIT_ETHERNET_XGMII_
TERMINATE_COLUMN_
VIOLATION_N
GIGABIT_ETHERNET_XGMII_
TX_ERROR_CONTROL_
CHARACTER_DETECTED_P
GIGABIT_ETHERNET_XGMII_
TX_ERROR_CONTROL_
CHARACTER_DETECTED_N
271
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_
XLGMII_CGMII_START_
ALIGNMENT_VIOLATION
GIGABIT_ETHERNET_
XLGMII_CGMII_SFD_
ALIGNMENT_VIOLATION
GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
ALIGNMENT_VIOLATION
GIGABIT_ETHERNET_
XLGMII_CGMII_SEQUENCE_
OS_VIOLATION
The sequence ordered set The PHY indicates Local Fault with a
should not contain
Sequence control character in lane 0, data
reserved values.
characters of 0x00 in lanes 1 and 2, a data
character of 0x01 in lane 3, and a 0x00 on
lanes 4 to 7.
The RS indicates a Remote Fault with a
Sequence control character in lane 0, data
characters of 0x00 in lanes 1 and 2, a data
character of 0x02 in lane 3, and a 0x00 on
lanes 4 to 7.
All other values are reserved for future use and
are not to be used. This check fires when a
Sequence ordered set contains a reserved
value.
GIGABIT_ETHERNET_
XLGMII_CGMII_TERM_
BEFORE_START_VIOLATION
GIGABIT_ETHERNET_
XLGMII_CGMII_START_
BEFORE_TERM_VIOLATION
272
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
BEFORE_TERM_VIOLATION
GIGABIT_ETHERNET_
XLGMII_CGMII_RSVD_
CONTROL_CHAR_
VIOLATION
Reserved control
characters should not be
used.
GIGABIT_ETHERNET_
XLGMII_CGMII_IDLE_
COLUMN_VIOLATION
When the bus is idle, Idle Idle columns are transmitted in full columns,
control characters should except when a Terminate is detected, wherein
be detected on all lanes. only the remaining lanes are Idles.
This check fires when an Idle column is
detected with a non-Idle character.
GIGABIT_ETHERNET_
XLGMII_CGMII_TERMINATE_
COLUMN_VIOLATION
When Terminate is
detected, all lanes
following the terminate
character should carry
idle control character.
GIGABIT_ETHERNET_
XLGMII_CGMII_TX_ERROR_
CONTROL_CHARACTER_
DETECTED
GIGABIT_ETHERNET_
XLGMII_CGMII_RX_ERROR_
CONTROL_CHARACTER_
DETECTED
Violations
GIGABIT_ETHERNET_TBI_
INVALID_10B_CG
GIGABIT_ETHERNET_TBI_
DISPARITY_ERROR_IN_K_CG
GIGABIT_ETHERNET_TBI_
DISPARITY_ERROR_IN_D_CG
Descriptions
273
Gigabit Ethernet
Monitor Checks
Violations
Descriptions
GIGABIT_ETHERNET_TBI_
LOSS_OF_SYNC
GIGABIT_ETHERNET_TBI_
T_NOT_FOLLOWED_BY_R_
VIOLATION
GIGABIT_ETHERNET_TBI_
MULTI_OS_FIRST_CG_
VIOLATION
First code-group of
multigroup ordered set should
be transmitted on even
position.
GIGABIT_ETHERNET_TBI_
EPD_OS_VIOLATION
GIGABIT_ETHERNET_TBI_
R_CG_VIOLATION
GIGABIT_ETHERNET_TBI_
INVALID_CG_AFTER_K28_5
GIGABIT_ETHERNET_TBI_
INVALID_IDLE_OS_AFTER_
CONFIGURATION_OS
GIGABIT_ETHERNET_TBI_
T_BEFORE_S_VIOLATION
GIGABIT_ETHERNET_TBI_
MISALIGNED_D_CG
GIGABIT_ETHERNET_TBI_
ERROR_OS_DETECTED_
DURING_FRAME
GIGABIT_ETHERNET_TBI_
ERROR_OS_DETECTED_
DURING_IDLE
GIGABIT_ETHERNET_TBI_
INVALID_I_OS
GIGABIT_ETHERNET_TBI_
SPD_NOT_BEFORE_I_OR_R_OS
274
Gigabit Ethernet
Monitor Checks
Violations
Descriptions
GIGABIT_ETHERNET_TBI_
RESERVED_K_CG_DURING_
FRAME
GIGABIT_ETHERNET_TBI_
RESERVED_K_CG_DURING_
IDLE
GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_000111_
ERROR
Sub-blocks encoded as
000111 should be generated
only when the running
disparity at the beginning of
the sub-block is positive.
GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_111000_
ERROR
Sub-blocks encoded as
111000 should be generated
only when the running
disparity at the beginning of
the sub-block is negative.
GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_0011_
ERROR
GIGABIT_ETHERNET_TBI_
DISPARITY_NEUTRAL_1100_
ERROR
Violation
Description
GIGABIT_ETHERNET_XAUI_
10B_CODE_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
10B_CODE_VIOLATION_N
275
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XAUI_
ALIGN_COL_VIOLATION_P
Data character(s)
detected during idle
period between frames.
Subblocks encoded as
000111 should be
generated only when the
running disparity at the
beginning of the subblock
is positive.
Subblocks encoded as
0011 should be generated
only when the running
disparity at the beginning
of the subblock is
positive.
GIGABIT_ETHERNET_XAUI_
ALIGN_COL_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
ALIGNS_AFTER_SUCCESSIVE_
TERM_P
GIGABIT_ETHERNET_XAUI_
ALIGNS_AFTER_SUCCESSIVE_
TERM_N
GIGABIT_ETHERNET_XAUI_
DATA_CHAR_DURING_IDLE_P
GIGABIT_ETHERNET_XAUI_
DATA_CHAR_DURING_IDLE_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_000111_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_000111_
ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_0011_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_0011_
ERROR_N
276
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_1100_
ERROR_P
Subblocks encoded as
1100 should be generated
only when the running
disparity at the beginning
of the subblock is
negative.
Subblocks encoded as
111000 should be
generated only when the
running disparity at the
beginning of the subblock
is negative.
Reserved control
characters should not be
detected during idle.
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_1100_
ERROR_N
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_111000_
ERROR_P
GIGABIT_ETHERNET_XAUI_
DISPARITY_NEUTRAL_111000_
ERROR_N
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
FRAME_P
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
FRAME_N
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
ERROR_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
FRAME_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
FRAME_N
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
IDLE_P
GIGABIT_ETHERNET_XAUI_
INVALID_CTRL_CHAR_DURING_
IDLE_N
277
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XAUI_
LOSS_OF_ALIGNMENT_P
When Synchronization is
lost on bus.
No more than a
maximum of 31 non-||A||
columns should be
detected between two
||A|| columns.
GIGABIT_ETHERNET_XAUI_
LOSS_OF_ALIGNMENT_N
GIGABIT_ETHERNET_XAUI_
LOSS_OF_SYNC_P
GIGABIT_ETHERNET_XAUI_
LOSS_OF_SYNC_N
GIGABIT_ETHERNET_XAUI_
MAX_ALIGN_SPACING_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
MAX_ALIGN_SPACING_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
MIN_ALIGN_SPACING_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
MIN_ALIGN_SPACING_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
NON_ALIGN_OR_SYNC_AFTER_
TERM_P
GIGABIT_ETHERNET_XAUI_
NON_ALIGN_OR_SYNC_AFTER_
TERM_N
GIGABIT_ETHERNET_XAUI_
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_P
GIGABIT_ETHERNET_XAUI_
SECOND_COL_FROM_TERM_
NOT_SKP_OR_SEQ_N
278
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XAUI_
SEQUENCE_ALIGNMENT_
VIOLATION_P
A sequence control
character should not be
placed on any lane other
than lane zero.
GIGABIT_ETHERNET_XAUI_
SEQUENCE_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SEQUENCE_NOT_FOLLOWING_
ALIGN_P
GIGABIT_ETHERNET_XAUI_
SEQUENCE_NOT_FOLLOWING_
ALIGN_N
GIGABIT_ETHERNET_XAUI_
SKEW_LIMIT_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SKEW_LIMIT_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SKIP_COL_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SKIP_COL_VIOLATION_N
GIGABIT_ETHERNET_XAUI_
START_ALIGNMENT_
VIOLATION_P
GIGABIT_ETHERNET_XAUI_
START_ALIGNMENT_
VIOLATION_N
GIGABIT_ETHERNET_XAUI_
SYNC_COL_VIOLATION_P
GIGABIT_ETHERNET_XAUI_
SYNC_COL_VIOLATION_N
279
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_XAUI_
SYNCS_AFTER_SUCCESSIVE_
TERM_P
GIGABIT_ETHERNET_XAUI_
SYNCS_AFTER_SUCCESSIVE_
TERM_N
GIGABIT_ETHERNET_XAUI_
TERMINATE_OS_ERROR_P
GIGABIT_ETHERNET_XAUI_
TERMINATE_OS_ERROR_N
Violation
Description
GIGABIT_ETHERNET_BASER_
INVALID_O_CODE_
VIOLATION
280
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_BASER_
START_OR_IDLE_BLOCK_
EXPECTED
GIGABIT_ETHERNET_BASER_
TERMINATE_OR_CONTROL_
BLOCK_EXPECTED
GIGABIT_ETHERNET_BASER_
INVALID_CONTROL_
CHARACTER
281
Gigabit Ethernet
Monitor Checks
Violation
Description
Violation
Description
GIGABIT_ETHERNET_BASER_
AM_INVLD_CNT_4
GIGABIT_ETHERNET_BASER_
AM_COUNTER_EXPIRED
Alignment marker not received This check fires when alignment marker
after am_counter reached
not received after am_counter expires.
maximum value.
This check not valid for first alignment
marker after AM_RESET_CNT state.
GIGABIT_ETHERNET_BASER_
AM_BIP_ERROR
GIGABIT_ETHERNET_BASER_
AM_NOT_MATCHING
GIGABIT_ETHERNET_BASER_
AM_BIP_ON_M3_NOT_
MATCHING_BIP_ON_M7
GIGABIT_ETHERNET_BASER_
SH_INVLD_CNT_MAX
GIGABIT_ETHERNET_BASER_
LANE_LOCK_FAIL_AFTER_
MAX_SLIP
GIGABIT_ETHERNET_BASER_
SKEW_MORE_THAN_MAX
282
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_BASER_
AM_ON_FEWER_LANES_
AFTER_DSKEW_DONE
Alignment marker not received This check fires when there are
on all lanes after deskew done. alignment marker on at least one lane but
not on all lane. This check is not valid
for first alignment marker after
AM_RESET_CNT state.
GIGABIT_ETHERNET_BASER_
PARAM_PHYSICAL_LANE_
COUNT_ERR
Violation
Description
GIGABIT_ETHERNET_AN_
MANCHESTER_DELIMITER_
VIOLATION
GIGABIT_ETHERNET_AN_
CLOCK_TRANSITION_
VIOLATION
GIGABIT_ETHERNET_AN_
DATA_TRANSITION_
VIOLATION
GIGABIT_ETHERNET_AN_
RSVD_OR_UNSUPPORTED_
ELECTOR_FIELD
GIGABIT_ETHERENT_AN_
NON_ZERO_ECHOED_
NONCE_FIELD_WITH_ZERO_
ACK
GIGABIT_ETHERNET_AN_
ECHOED_NONCE_DOES_
NOT_MATCH_TX_NONCE_
FROM_LP
GIGABIT_ETHERNET_AN_
NON_ZERO_RSVD_TECH_
ABILITY_FIELD
283
Gigabit Ethernet
Monitor Checks
Violation
Description
GIGABIT_ETHERNET_AN_
FEC_REQUESTED_WITH_
NO_ABILITY
GIGABIT_ETHERNET_AN_
NULL_MESSAGE_CODE_
NOT_TRANSMITTED
GIGABIT_ETHERNET_AN_
MP_BIT_UNSET_DURING_
NULL_MESSAGE_CODE
GIGABIT_ETHERNET_AN_
NULL_HCD_RESOLVED
GIGABIT_ETHERNET_AN_
NON_NULL_MESSAGE_
CODE_TRANSMITTED_
AFTER_NULL_MESSAGE_
CODE
GIGABIT_ETHERNET_AN_
NP_BIT_SET_AFTER_NP_
BIT_UNSET
GIGABIT_ETHERNET_AN_
NUMBER_OF_ACK_PAGES_
OUT_OF_RANGE
Number of codewords
transmitted in COMPLETE
ACKNOWLEDGE state is out of
range.
While in COMPLETE
ACKNOWLEDGE state, number of
frames transmitted should be from 6 to
8. This check is fired if the number of
frames fall out of this range
GIGABIT_ETHERNET_AN_
DISSIMILAR_PAGE_
TRANSMITTED
284
Gigabit Ethernet
Monitor Corner Cases
Violation
Description
GIGABIT_ETHERNET_AN_
INVALID_ACK_BIT_
TRANSMISSION
GIGABIT_ETHERNET_AN_
PAGE_DETECTED_AFTER_
AUTONEG_COMPLETION
Description
285
Gigabit Ethernet
Monitor Corner Cases
Description
Carrier extensions
Collisions
Control frames
Data frames
Error blocks
False carriers
Frame bursts
Idle blocks
286
Gigabit Ethernet
Monitor Statistics
Description
Local faults
Packets of max_frame_size
Packets of min_frame_size
Remote faults
Monitor Statistics
Table 8-38 shows the statistics maintained by the Gigabit Ethernet monitor.
Table 8-38. Gigabit Ethernet Protocol Statistics
Statistic
Description
Total frames
287
Gigabit Ethernet
Monitor Statistics
288
Statistic
Description
Chapter 9
High-Definition Multimedia Interface (HDMI)
Introduction
This monitor checks the HDMI TMDS interface for compliance with HDMI 1.3a specification
and protocol.
HDMI 1.3a is designed to provide transmitting digital television audiovisual signals for DVD
players, set-top boxes and other audiovisual sources to television sets, projectors, and other
video displays.
Reference Documentation
This QVL HDMI monitor is modeled from the requirements provided in the following
documents:
Supported Features
HDMI supports the following features:
HDMI is compatible with Digital Visual Interface (DVI), Revision 1.0, April 2, 1999.
HDMI link includes three Transition Minimized Differential Signaling (TMDS) Data
channels and a single TMDS Clock channel.
289
HDMI link operates in three modes: Video Data Period, Data Island Period, and Control
Period.
Preamble, near the end of every Control Period, indicates whether the next Data Period
is a Video Data Period or a Data Island Period.
Data Island improves reliability by adding Error Correction Code (ECC) parity to each
packet: BCH(64,56) and BCH(32,24).
Video pixels carried across the link are in one of three different pixel encoding: RGB
4:4:4, YCBCR 4:4:4, or YCBCR 4:2:2.
Video Format Timing (number of pixels per line and number of lines per video field)
codes are supported.
Color Depth Modes 24-bit, 30-bit, 36-bit, and 48-bit are supported.
HDMI
Sink
Option 2
TMDS Channel [0-2]
HDMI
Source
290
QVL
Monitor
HDMI
Sink
Monitor Connectivity
Connect the HDMI monitor pins to internal signals as specified in the pin-out Table 9-1 and
illustrated in Figure 9-2.
Figure 9-2. HDMI Monitor Pins Diagram
clock
reset
areset
parallel_data_ch0
parallel_data_ch1
parallel_data_ch2
serial_data_ch0
serial_data_ch1
serial_data_ch2
HDMI Monitor
Description
clock
Clock (TMDS clock) or serial data sample clock (10x TMDS clock).
reset
areset
parallel_data_ch0
parallel_data_ch1
parallel_data_ch2
serial_data_ch0
serial_data_ch1
serial_data_ch2
291
Monitor Parameters
The parameters shown in Table 9-2 should be passed with appropriate values to configure the
HDMI monitor.
Table 9-2. HDMII Monitor Parameters
Order Parameters
Default
Description
1.
Constraints_Mode
2.
NUMBER_DATA_CHANNELS
3.
DATA_CHANNEL_ENCODED_
WIDTH
10
4.
DATA_CHANNEL_UNENCODED_
WIDTH
5.
BYPASS_SERIAL_TO_PARALLEL
6.
USE_CLOCK_INPUT_TO_SAMPLE_
SERIAL_DATA
7.
CLOCK_10X_PERIOD
8.
INVERT_CLOCK10X_OUT
292
Default
Description
9.
BYPASS_ENCODING
HDMI_DATA_CHANNEL_DATA_ISLAND_
PERIOD_ILLEGAL_TERC4_ENCODING
HDMI_DATA_CHANNEL_VIDEO_DATA_
PERIOD_GT5_TRANSITIONS_PER_PIXEL_
CLK_ERR
HDMI_DATA_ISLAND_PERIOD_PACKET_
NOT_32_PIXEL_CLKS_MULTIPLE_ERR
ENABLE_SAFE_HIZ_RESET_
HANDLING
11.
SET_VIDEO_FORMAT_16x8
12.
PROGRAMMING_CHECK_OFF_
GENERAL_CONTROL_CD
293
Default
Description
13.
PROGRAMMING_CHECK_OFF_
AVI_INFOFRAME_Y
0 = RGB 444
1 = YCbCr 444
2 = YCbCr 422
14.
PROGRAMMING_CHECK_OFF_
AVI_INFOFRAME_VI
for details.
15.
DATA_X_Z_CHECK_ENABLE
16.
PROGRAMMING_CHECK_
ENABLE
17.
PACKET_COVER_ENABLE
18.
PROGRAMMING_COVER_ENABLE
294
Default
Description
19.
`QVL_COVER_
ALL (15)
COVERAGE_LEVEL_FILTER
`QVL_COVER_NONE == 0;
`QVL_COVER_SANITY == 1;
`QVL_COVER_BASIC == 2;
`QVL_COVER_CORNER == 4;
`QVL_COVER_STATISTIC == 8;
`QVL_COVER_ALL == 15.
Notice that `QVL_COVER_ALL is a bit-wise OR
of the other non-zero coverage levels.
20.
COVERAGE_LEVEL_MESSAGE_
FILTER
`QVL_COVER_
MESSAGE_ALL
(15)
295
Compiler Directives
Table 9-3 describes the available Verilog and SystemVerilog compiler directives.
Table 9-3. Verilog and SystemVerilog Compiler Directives
Compiler Directive
Description
QVL_VERSION_PRINT_OFF
none
QVL_ASSERT_ON
none
Enables assertions.
QVL_XCHECK_OFF
QVL_ASSERT_ON
QVL_COVER_ON
none
QVL_SV_COVER_DIRECTIVES_OFF QVL_COVER_ON
296
Description
QVL_MW_FINAL_COVER_OFF
QVL_COVER_ON
Monitor Checks
Table 9-4 shows the data channel serial and parallel X or Z (unknown) monitor checks
performed by the HDMI monitor.
The checks in Table 9-4 can be disabled if the parameter DATA_X_Z_CHECK_ENABLE is
set to 0.
Table 9-4. HDMI Data Channel Unknown Checks
Check ID
Violation
Description
HDMI_SERIAL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN
HDMI_PARALLEL_DATA_
CHANNEL_UNKNOWN_
OR_Z_DRIVEN
Table 9-5 shows the data integrity monitor checks performed by the HDMI monitor.
Table 9-5. HDMI Data Integrity Checks
Check ID
Violation
HDMI_DATA_CHANNEL_CTL_
PERIOD_ILLEGAL_ENCODING
Illegal encoding value on data Checks that the TMDS Channel data
channel during a CTL Period. input is properly encoded from the
two-bit control signal to a 10-bit
encoding 00 -> 0x354, 01 -> 0x0AB,
10 -> 0x154, 11 -> 0x2AB.
HDMI_DATA_CHANNEL_CTL_
PREAMBLE_ILLEGAL_
ENCODING
HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
ILLEGAL_TERC4_ENCODING
Description
297
Violation
Description
HDMI_DATA_CHANNEL_
DATA_ISLAND_PERIOD_
UNEXPECTED_BCH_ECC_
VALUE
HDMI_DATA_CHANNEL_
VIDEO_DATA_PERIOD_
GT5_TRANSITIONS_PER_
PIXEL_CLK_ERR
Table 9-6 shows the protocol monitor checks performed by the HDMI monitor.
Table 9-6. HDMI Protocol Checks
Check ID
Violation
Description
HDMI_CTL_PERIOD_LT12_PIXEL_
CLKS_MINIMUM_ERR
HDMI_CTL_PERIOD_PREAMBLE_
GT8_PIXEL_CLKS_ERR
HDMI_CTL_PERIOD_PREAMBLE_
ILLEGAL_CHARACTERS
HDMI_CTL_PERIOD_
PREAMBLE_NOT_8_PIXEL_
CLKS_ERR
HDMI_DATA_ISLAND_PERIOD_
CH0_D3_ONE_AFTER_FIRST_
CLK_TERC4_ENCODING_ERR
HDMI_DATA_ISLAND_PERIOD_
CH0_D3_ZERO_AFTER_LEADING_
GUARD_BAND_ERR
HDMI_DATA_ISLAND_PERIOD_
GUARD_BAND_INVALID_VALUE
HDMI_DATA_ISLAND_PERIOD_
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR
Leading or trailing guard band The leading and trailing guard bands
during Data Island Period not 2 are 2 pixel clocks in length during a
pixel clocks error.
Data Island Period.
298
Violation
Description
HDMI_DATA_ISLAND_PERIOD_
INVALID_PACKET_TYPE_
HEADER_ERR
HDMI_DATA_ISLAND_PERIOD_
MAXIMUM_NUMBER_OF_
PACKETS_18_ERR
HDMI_DATA_ISLAND_PERIOD_
MINIMUM_NUMBER_OF_
PACKETS_1_ERR
HDMI_DATA_ISLAND_PERIOD_
PACKET_NOT_32_PIXEL_CLKS_
MULTIPLE_ERR
HDMI_DATA_ISLAND_PERIOD_
UNEXPECTED_DATA_AFTER_
TRAILING_GUARD_BAND_ERR
HDMI_DATA_ISLAND_TO_
VIDEO_DATA_PERIOD_ERR
HDMI_INVALID_NUMBER_OF_
ACTIVE_PIXELS_PER_
PROGRAMMED_VALUE
HDMI_MONITOR_STATE_
MACHINE_TO_RESET_
STATE_ERR
HDMI_MONITOR_STATE_
MACHINE_UNKNOWN_STATE_
ERR
HDMI_ONE_DATA_ISLAND_
PERIOD_PER_TWO_VIDEO_
FIELDS_ERR
HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_INVALID_VALUE
299
Violation
Description
HDMI_VIDEO_DATA_PERIOD_
GUARD_BAND_NOT_2_PIXEL_
CLKS_ERR
HDMI_VIDEO_DATA_TO_DATA_
ISLAND_PERIOD_ERR
HDMI_VIDEO_DATA_TO_VIDEO_
DATA_PERIOD_ERR
Table 9-7 shows the programming monitor checks performed by the HDMI monitor.
The checks in Table 9-7 can be disabled if the PROGRAMMING_CHECK_ENABLE
parameter is set to 0.
Table 9-7. HDMI Programming Checks
Check ID
Violation
Description
HDMI_AUDIO_CLOCK_
REGENERATION_PACKET_ERR
HDMI_AUDIO_CLOCK_
REGENERATION_SUBPACKET_
DIFF_ERR
HDMI_AUDIO_SAMPLE_
PACKET_ERR
HDMI_GENERAL_CONTROL_
PACKET_ERR
HDMI_GENERAL_CONTROL_
SUBPACKET_DIFF_ERR
HDMI_GENERAL_CONTROL_
PACKET_AVMUTE_
PROGRAMMING_ERR
300
Violation
Description
HDMI_GENERAL_CONTROL_
PACKET_CD_ZERO_PP_NOT_
ZERO_PROGRAMMING_ERR
HDMI_GENERAL_CONTROL_
PACKET_PP_RESERVED_
PROGRAMMING_ERR
HDMI_GENERAL_CONTROL_
PACKET_CD_RESERVED_
PROGRAMMING_ERR
HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ERR
HDMI_AUDIO_CONTENT_
PROTECTION_PACKET_ACP_
TYPE_RESERVED_
PROGRAMMING_ERR
HDMI_ISRC1_PACKET_ERR
HDMI_ISRC2_PACKET_ERR
HDMI_ONE_BIT_AUDIO_
SAMPLE_PACKET_ERR
HDMI_GAMUT_METADATA_
PACKET_ERR
HDMI_GAMUT_METADATA_
PACKET_GBD_PROFILE_
PROGRAMMING_ERR
301
Violation
Description
HDMI_GAMUT_METADATA_
PACKET_SEQ_NUM_
PROGRAMMING_ERR
Affected_Gamut_Seq_Num ===
Current_Gamut_Seq_Num or
Current_Gamut_Seq_Num + 1 is
required if No_Current_GBD === 0.
HDMI_INFOFRAME_PACKET_
ERR
HDMI_INFOFRAME_PACKET_
INFOFRAME_LENGTH_
PROGRAMMING_ERR
InfoFrame packet
InfoFrame_length
programming exceeds the
maximum value of 27.
HDMI_INFOFRAME_PACKET_
SUBPACKET_CHECKSUM_ERR
HDMI_AVI_INFOFRAME_
PACKET_ERR
HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_
VERSION_PROGRAMMING_ERR
HDMI_AVI_INFOFRAME_
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR
HDMI_AVI_INFOFRAME_
PACKET_SUBPACKET_
CHECKSUM_ERR
HDMI_AVI_INFOFRAME_
PACKET_Y_RESERVED_
PROGRAMMING_ERR
HDMI_AVI_INFOFRAME_
PACKET_VI_RESERVED_
PROGRAMMING_ERR
HDMI_AUDIO_INFOFRAME_
PACKET_ERR
302
Violation
Description
HDMI_AUDIO_INFOFRAME_
PACKET_INFOFRAME_LENGTH_
PROGRAMMING_ERR
HDMI_AUDIO_INFOFRAME_
PACKET_SUBPACKET_
CHECKSUM_ERR
Monitor Coverage
Table 9-8 shows the cover basic cases collected by the HDMI monitor.
Refer to the COVERAGE_LEVEL_FILTER and COVERAGE_LEVEL_MESSAGE_FILTER
parameters in Table 9-2 on page 292 for additional information.
Table 9-8. HDMI Cover Basic
Cover Basic
Description
HDMI_CONTROL_PERIOD
HDMI_CONTROL_PERIOD_DATA_ISLAND_PREAMBLE
HDMI_DATA_ISLAND_PERIOD
HDMI_DATA_ISLAND_PERIOD_PACKET
HDMI_CONTROL_PERIOD_VIDEO_DATA_PREAMBLE
HDMI_VIDEO_DATA_PERIOD
Table 9-9 shows the cover corner cases collected by the HDMI monitor.
Table 9-9. HDMI Cover Corner
Cover Corner
Description
HDMI_VIDEO_FRAME
303
Table 9-10 shows the packet cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-10 can be disabled if the PACKET_COVER_ENABLE
parameter is set to 0.
Table 9-10. HDMI Packet Cover Statistics
Packet Cover
Description
HDMI_DATA_ISLAND_PERIOD_NULL_PACKET
HDMI_DATA_ISLAND_PERIOD_AUDIO_CLOCK_
REGENERATION_PACKET
HDMI_DATA_ISLAND_PERIOD_AUDIO_
CONTENT_PROTECTION_PACKET
HDMI_DATA_ISLAND_PERIOD_ISRC1_PACKET
HDMI_DATA_ISLAND_PERIOD_ISRC2_PACKET
HDMI_DATA_ISLAND_PERIOD_ONE_BIT_
AUDIO_SAMPLE_PACKET
HDMI_DATA_ISLAND_PERIOD_DST_AUDIO_
PACKET
HDMI_DATA_ISLAND_PERIOD_HIGH_BITRATE_
AUDIO_STREAM_PACKET
HDMI_DATA_ISLAND_PERIOD_GAMUT_
METADATA_PACKET
HDMI_DATA_ISLAND_PERIOD_INFOFRAME_
PACKET
HDMI_DATA_ISLAND_PERIOD_VENDOR_
SPECIFIC_INFOFRAME_PACKET
HDMI_DATA_ISLAND_PERIOD_AVI_
INFOFRAME_PACKET
HDMI_DATA_ISLAND_PERIOD_SOURCE_
PRODUCT_DESCRIPTOR_INFOFRAME_PACKET
HDMI_DATA_ISLAND_PERIOD_AUDIO_
INFOFRAME_PACKET
HDMI_DATA_ISLAND_PERIOD_MPEG_SOURCE_
INFOFRAME_PACKET
304
Table 9-11 shows the programming cover statistics cases collected by the HDMI monitor.
The cover directives in Table 9-11 can be disabled if the parameter
PROGRAMMING_COVER_ENABLE is set to 0.
Table 9-11. HDMI Programming Cover Statistics
Programing Cover
Description
HDMI_VIDEO_DATA_PERIOD_24_BIT_COLOR_
DEPTH_MODE
HDMI_VIDEO_DATA_PERIOD_30_BIT_DEEP_
COLOR_DEPTH_MODE
HDMI_VIDEO_DATA_PERIOD_36_BIT_DEEP_
COLOR_DEPTH_MODE
HDMI_VIDEO_DATA_PERIOD_48_BIT_DEEP_
COLOR_DEPTH_MODE
HDMI_VIDEO_DATA_PERIOD_RGB_444_VIDEO_
FORMAT_MODE
HDMI_VIDEO_DATA_PERIOD_YCbCr_444_VIDEO_
FORMAT_MODE
HDMI_VIDEO_DATA_PERIOD_CbCr_422_VIDEO_
FORMAT_MODE
HDMI_VIDEO_DATA_PERIOD_40x480p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720x480p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1280x720p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080i_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x480i_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x240p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x480i_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x240p_60HZ_
VIDEO_FORMAT_ID_CODE
305
Description
HDMI_VIDEO_DATA_PERIOD_1440x480p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720x576p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1280x720p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080i_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x288p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x576i_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x576i_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x288_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1440x576p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080p_24HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080p_25HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080p_30HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x480p_60HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_2880x576p_50HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080i_1250_
TOTAL_50HZ_VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080i_100HZ_
VIDEO_FORMAT_ID_CODE
306
Description
HDMI_VIDEO_DATA_PERIOD_1280x720p_100HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720x576p_100HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x576i_100HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1920x1080i_120HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_1280x720p_120HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720x480p_120HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x480i_120HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720x576p_200HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x576i_200HZ_
VIDEO_FORMATID_CODE
HDMI_VIDEO_DATA_PERIOD_720x480p_240HZ_
VIDEO_FORMAT_ID_CODE
HDMI_VIDEO_DATA_PERIOD_720_1440x480i_240HZ_
VIDEO_FORMAT_ID_CODE
Description
Data preamble
Video preamble
307
Table 9-12. Coverage Count Totals for HDMI 1.3a Monitor (cont.)
Coverage
Description
Table 9-13 shows the statistics count totals collected by the HDMI monitor.
Table 9-13. Statistics Count Totals for HDMI 1.3a Monitor
Statistic
Description
Total [640x480p to 720(1440)x480i] Video Total number of video period transmissions using individual video
Codes
codes [640x480p to 720(1440)x480i] (should total 37 unique
totals).
Refer to the HDMI Valid Pixel Repeat Values for Each Video
Format Timing table in the HDMI Specification 1.3a for details.
Total RGB 4:4:4 Transactions
308
Chapter 10
I2C (Inter-IC) Monitor
Introduction
The I2C (Inter-IC) bus was originally developed by Philips Semiconductors to provide a simple
and uniform connectivity for a variety of peripheral and general-purpose devices such as
intelligent control, EEPROM, RAM, and LCD drivers.
The Mentor Graphics Corporation I2C QVL monitor is used to verify any I2C designs for
protocol correctness, and to measure the verification coverage through structural coverage
metrics. The I2C monitor contains assertion directives that track all I2C interface protocol rules.
The statistics block collects the occurrences of various protocol scenarios on the I2C bus.
This I2C Monitor can be simulated with Mentor Graphics Questa simulator and used with the
0-In Formal Verification tools (Search, Confirm, and Prove). With the 0-In Formal Verification
tools, the assertion directives in the I2C monitor can be used as Constraints and
Goals/Properties-to-prove-or-falsify, when used with the 0-In Formal Verification tools.
Figure 10-1 illustrates the I2C System Topology.
Figure 10-1. I2C System Topology
I2C Slave
I2C Master
I2C Bus
I2C Slave
I2C Master
309
Reference Documentation
This QVL I2C monitor is modeled from the requirements provided in the following documents:
I2C Monitor
I2C is a multiple master, multiple slave interface. Any I2C device can be of the following types:
I2C Slave
I2C Bus
I2C Slave
As shown in Figure 10-2, if you want to track multiple I2C Master/Slave and Master-Slave
devices simultaneously, then multiple instances of the appropriate I2C Master, or Slave, or
Master/Slave top modules are needed.
310
Monitor Connectivity
Connect the I2C Master, or Slave, or Master/Slave monitor pins to internal signals as specified
in the pin-out Table 10-1 and illustrated in Figure 10-3, Figure 10-4, and Figure 10-5.
Figure 10-3. I2C Master Monitor Pins Diagram
clock
reset
areset
sda_out
sda_out_en_n
sda_in
scl_out
scl_out_en_n
scl_in
clock_prescale_count
I2C Master/Slave
Monitor
311
Description
areset
clock
Clock signal. Positive edge active. This clock signal should be at least twice as
fast as scl_out/scl_in to be able to sample the scl_out/scl_in.
clock_prescale_count
reset
scl_in
I2C clock signal. The serial clock (SCL) input signal to the DUT.
scl_out
I2C clock signal. Input to the tristate buffer. SCL output signal to the DUT.
scl_out_en_n
SCL clock enable signal. Active LOW. Enable to the tristate buffer.
sda_in
I2C data signal. The serial data (SDA) input signal to the DUT.
sda_out
I2C data signal. SDA output signal from the DUT. Input to the tristate buffer.
Control and data signal.
sda_out_en_n
SDA output enable signal. Active LOW. Enable to the tristate buffer.
slave_addr
Slave address input. 10-bits wide. Both 7-bit address or 10-bit address can be
connected. When a 7-bit address is passed, 3'b0 should be appended with the
actual 7-bit address.
Note that as per the protocol, an I2C device can be configured with an address
through the hardware general call address. Hence, this monitor takes this input as
a configured address until a hardware general call address is issued on the bus, or
there is no hardware general call address at all on the bus.
Note that this signal is not available with the Master only monitor (see
Example 10-1 on page 314).
312
Monitor Parameters
The parameters shown in Table 10-2 should be passed with appropriate values to configure the
I2C monitor to track the I2C Master, I2C Slave, or I2C Master/Slave devices.
Table 10-2. I2C Monitor Parameters
Order Parameters
Default Description
0.
Constraints_Mode
1.
MAX_TXN_LENGTH
2.
CLOCK_PRESCALE_EN
3.
OUTPUT_ENABLES_ON
313
Example 10-1. I2C Master Monitor Instantiation for a Master Only Design
qvl_i2c_master_monitor #(.Constraints_Mode (1),
.CLOCK_PRESCALE_EN (1) ) MAS_ONLY0
(.clock (CLOCK),
.reset (!RESETN),
.areset (!RESETN),
.sda_out (OSDA),
.sda_out_en_n (1'b0),
.sda_in (ISDA),
.scl_out (OSCL),
.scl_out_en_n (1'b0),
.scl_in (ISCL),
.clock_prescale_count (16'd20) ) ;
314
Master Checks
Table 10-3 shows the Master checks performed by the I2C monitor.
Table 10-3. I2C Master Checks
Check ID
Violation
Description
I2C_m_cbus_not_needed_
in_fast_or_hs_mode
I2C_m_cbus_transaction_
ends_with_stop
I2C_m_during_address_
phase_master_should_drive_
sda_and_scl
I2C_m_during_arbitration_
if_own_address_master_to_
switch_role_as_slave
315
Violation
Description
I2C_m_during_write_data_
master_should_drive_scl_
during_data_txn
I2C_m_during_write_data_
master_should_drive_sda_
during_data_txn
I2C_m_except_start_byte_
start_to_follow_at_least_
one_data_phase
I2C_m_for_read_txn_mas_
should_assert_ack_or_nack
I2C_m_for_write_txn_mas_
should_deassert_sda_out_
during_ack_or_nack
I2C_m_gcall_address_2nd_
byte_8b00_not_allowed
I2C_m_mas_to_stop_or_
restart_if_slv_issues_slave_nack
I2C_m_master_to_issue_
gcall_address_first_before_
any_valid_txn
316
Violation
Description
I2C_m_max_txn_len_to_
equal_length_parameter_value
I2C_m_reserved_addresses_
not_allowed
I2C_m_sda_to_be_stable_
as_long_as_slave_asserts_
scl_low_towards_slave_wait
I2C_m_serial_data_length_
always_8_bits_wide
I2C_m_start_byte_to_
follow_repeated_start
I2C_m_why_same_address_
of_slave_which_is_part_
of_same_device
317
Violation
Description
I2C_ms_after_clock_sync_
high_width_to_be_equal_
that_of_device_had_
shortest_high
I2C_ms_no_arb_and_clk_
sync_allowed_in_hs_mode
I2C_ms_no_scl_low_when_
sda_high_bus_idle
Slave Checks
Table 10-4 shows the Slave checks performed by the I2C monitor.
Table 10-4. I2C Slave Checks
Check ID
Violation
Description
I2C_ms_no_scl_low_when_
sda_high_bus_idle
I2C_s_address_should_match_
when_the_slave_device_
responds_for_a_txn
I2C_s_bit_level_hand_shake_
is_not_allowed_by_stretching_
scl_low
I2C_s_during_read_data_
slave_should_drive_sda_
during_data_txn
For read transactions, the Slave The check ensures that the SDA is driven by
should drive SDA during data the Slave during the read data phases.
transfer.
I2C_s_for_read_txn_slv_
should_deassert_sda_out_en_
n_during_ack_or_nack
For read transactions, the Slave This check ensures that for a read
should de-assert sda_out_en
transaction the ACK/NACK bit is driven by
during ACK/NACK.
the Master, and the Slave stops driving the
SDA bit to avoid contention.
318
Violation
Description
I2C_s_for_write_txn_slv_
should_assert_ack_or_nack
I2C_s_hs_mode_signaling_
should_be_followed_w_nack
I2C_s_no_ack_for_cbus_cycle
I2C_s_start_byte_to_follow_
nack
Assertion Checks
Table 10-5 shows the Assertion checks performed by the I2C monitor.
Table 10-5. I2C Assertion Checks
Check ID
Violation
Description
I2C_KNOWN_sda_out
I2C_KNOWN_sda_in
I2C_KNOWN_sda_out_en_n
I2C_KNOWN_scl_out
I2C_KNOWN_scl_out_en_n
319
Violation
Description
I2C_KNOWN_scl_in
I2C_KNOWN_clock_prescale_count
Description
Master Statistics
Table 10-7 shows the statistics maintained by the I2C Master monitor.
Table 10-7. I2C Master Statistics
320
Name
Description
Total Starts
Total Reads
Total Writes
Total Stops
Description
Total ACKs
Total NACKs
Description
Slave Statistics
Table 10-9 shows the statistics maintained by the I2C Slave monitor.
Table 10-9. I2C Slave Statistics
Name
Description
Total Starts
Total Reads
Total Writes
Total Stops
321
322
Name
Description
Total ACKs
Total NACKs
Chapter 11
Low Pin Count (LPC)
Introduction
The Low Pin Count (LPC) bus interface is designed to enable a system without ISA or X-bus
interfaces. The LPC interface reduces the cost of traditional X-bus devices while meeting or
exceeding the data transfer rate of X-bus. LPC performs the same cycle types as the X-bus:
Memory, I/O, DMA, and Bus Master.
Reference Documentation
This LPC monitor is modeled from the requirements provided in the following document:
Low Pin Count (LPC) Interface Specification, Rev. 1.0, September 29, 1997.
PCI
Host Bus
ISA
SuperIO
Host
LPC
Monitor
LPC
Monitor
LPC Local Bus
Monitor Connectivity
Connect the LPC monitor pins to internal signals as specified in the pin-out Table 11-1 and
illustrated in Figure 11-2.
323
LPC Monitor
Description
clkrun_n
Clock Run. Stopping the clock is not supported by the monitor. The signal
is active low.
lad
The multiplexed command, address and data bus which is 4-bits wide.
lclk
ldrq_n
lframe_n
lmsi_n
SMI on I/O instruction for retry is not supported by the monitor. The signal
is active low.
lpcpd_n
Power Down. This is not supported by the monitor. The signal is active
low.
lreset_n
The reset signal for the LPC interface. The signal is active low.
pme_n
serirq
Monitor Parameters
The parameters shown in Table 11-2 configure the LPC monitor.
Table 11-2. LPC Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
LDRQ_WIDTH
324
Default Description
3.
RETAIN_DMA_ON_
ABORT
4.
CHECK_RESERVED_VALUE
5.
ALLOW_LARGE_DMA_
TRANSFERS
6.
ALLOW_DMA_AFTER_
DEACTIVATION
When the Constraints_Mode parameter is set to 0, the Constraints Mode feature is disabled, and
all the checks are used as targets when running formal analysis.
Instantiation Example
Example 11-1 instantiates the LPC monitor.
Example 11-1. LPC Monitor Instantiation
qvl_lpc_monitor #(
0,
/* Constraints_Mode */
2,
/* LDRQ_WIDTH */
1,
/* RETAIN_DMA_ON_ABORT */
0,
/* CHECK_RESERVED_VALUE */
1,
/* ALLOW_LARGE_DMA_TRANSFERS */
1
/* ALLOW_DMA_AFTER_DEACTIVATION */ )
lpc_mon (
.lclk
(lclk),
.lreset_n
(lreset_n),
.lframe_n
(lframe_n),
.lad
(lad),
.ldrq_n
(ldrq),
.serirq
(serirq),
.clkrun_n
(clkrun_n),
.pme_n
(pme_n),
.lpcpd_n
(lpcpd_n),
.lsmi_n
(lsmi_n) );
325
Monitor Checks
Table 11-3 shows the checks performed by an LPC monitor.
Table 11-3. LPC Checks
Check ID
Violation
Description
LPC_lframe_n
LPC_ldrq_n
LPC_serirq
LPC_clkrun_n
LPC_pme_n
LPC_lpcpd_n
LPC_lsmi_n
LPC_1
LPC_2
LPC_3
LPC_4
LPC_5
Value on lad port was not constant The lad port during a SYNC cycle indicates
across contiguous synchronization the type of synchronization. This value
cycles (4.2.1.8).
must remain constant across contiguous
SYNC cycles.
LPC_6
LPC_7
LPC_8
LPC_9
LPC_10
LPC_11
LPC_12
326
Violation
Description
LPC_14
LPC_15
LPC_16
LPC_17
LPC_18
LPC_19
LPC_20
LPC_21
LPC_22
LPC_23
LPC_24
LPC_25
LPC_26
Invalid size.
327
Violation
Description
LPC_27
LPC_28
LPC_29
LPC_30
LPC_31
LPC_32
LPC_unsupported_serirq
LPC_unsupported_clkrun_n
LPC_unsupported_pme_n
LPC_unsupported_lpcpd_n
LPC_unsupported_lsmi_n
328
Description
Aborted Transfers
Monitor Statistics
The statistics captured by the LPC monitor are shown in Table 11-5. These statistics are
collected separately on the master and target controllers.
Table 11-5. LPC Monitor Statistics
Statistic
Description
Total Transfers
329
330
Chapter 12
Open Core Protocol (OCP)
Introduction
The Open Core Protocol (OCP) is a core-centric protocol that comprehensively describes the
system level integration requirements of intellectual property (IP) cores. The OCP supports very
high performance data transfer models ranging from simple request-grants through pipelined
and multi-threaded objects. Higher complexity SOC communication models are supported
using thread identifiers to manage out-of-order completion of multiple concurrent transfer
sequences. The QVL OCP monitor is designed for checking the OCP interfaces.
Reference Documentation
This OCP monitor is modeled from the requirements provided in the following documents:
Open Core Protocol Specification 2.1, Document Revision 1.0, Part number: 161000125-0003.
Please refer to Instantiation Modification is Required for OCP 2.1 Users on page 333 for
additional information.
Supported Features
Commands
Data Transfers
Bursts
331
Supports WRAP, INCR, STRM, XOR, and BLCK (two-dimensional) type bursts.
Response Signaling
Tags
Data buses
Inband Signaling.
Synchronization
Locked Synchronization.
Lazy Synchronization.
Sideband Signals
332
Reset Signals.
Parameter CONNECTION and tie-off signal as per the OCP disconnect proposal.
Refer to Instantiation Modification is Required for OCP 2.1 and 2.2 Users on page 334 for
additional information.
Unsupported Features
The monitor will assume the data as-is and will not perform endianness conversion.
Interleaving of transfers on any of the phases is not supported if the dataflow transfer
checks are enabled. Dataflow transfer checks are enabled by enabling the parameter
ENABLE_INTER_PHASE_TRANFER_CHECKS.
enableclk
mareset_n
sareset_n
mblockheight
mblockstride
mdatarowlast
mreqrowlast
sresprowlast
333
The two asynchronous reset ports should each be connected to 1'b1; the remainder of the ports
should be unconnected for a OCP 2.1 specification use model.
basic_group OCP 2.2 has 8-bits instead of 7-bits in width in OCP 2.1.
burst_ext_group OCP 2.2 has 23-bits instead of 17-bits in width in OCP 2.1.
thread_ext_group OCP 2.2 has 10-bits instead of 7-bits in width in OCP 2.1.
The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 specification use model.
BLOCKHEIGHT_WDTH
BLOCKSTRIDE_WDTH
These parameters can be ignored for a OCP 2.1 specification use model instance of the monitor.
Following is the configuration port change for OCP Disconnect Proposal compliance:
sideband_sig_group Port has support for 7-bit width instead of 6-bit width in OCP
2.1 and OCP 2.2 (see Table 12-1 on page 341).
The new higher order bits are all set to 0 when connecting these configuration ports for a OCP
2.1 or 2.2 specification use model.
334
335
Refer to Instantiation Examples on page 352 for OPC 2.2 typical examples.
336
/*
/*
/*
/*
/*
/*
/*
/*
/*
SDATAINFOBYTE_WDTH */
CONTROL_WDTH */
STATUS_WDTH */
TAGS */
TAGID_WDTH */
TAG_INTERLEAVE_SIZE */
ENABLE_INTER_PHASE_TRANFER_CHECKS */
MAX_OUTSTANDING_REQ */
BLOCKHEIGHT_WDTH; To ensure backward compatibility, this parameter must be 0
for 2.1 use model as this is disabled in the configuration for 2.1 */
4
/* BLOCKSTRIDE_WDTH */
// Neglected disconnect specification relevant parameters
)
OCP_MONITOR ( .clk(Clk),
.enableclk(), // Unconnected OCP 2.2 specific port
.areset_n(1'b1),
.mdata(MData),
.mdatavalid (MDatavalid),
.mrespaccept(MRespaccept),
.scmdaccept(SCmdaccept),
.sdata(SData),
.sdataaccept(SDataaccept),
.sresp(SResp),
.maddrspace(MAddrSpace),
.mbyteen(MByteen),
.mdatabyteen(MDatabyteen),
.mdatainfo(MDataInfo),
.mreqinfo(MReqInfo),
.sdatainfo(SDataInfo),
.srespinfo(SRespInfo),
.matomiclength(MAtomicLength),
.mburstlength(MBurstLength),
.mburstprecise(MBurstPrecise),
.mburstseq(MBurstSeq),
.mburstsinglereq(MBurstSingleReq),
.mdatalast(MDatalast),
.mreqlast(MReqLast),
.sresplast(SResplast),
.mdatatagid(MDataTagID),
.mtagid(MTagID),
.mtaginorder(MTagInOrder),
.stagid(STagID),
.staginorder(STagInOrder),
.mconnid(MConnID),
.mdatathreadid(MDataThreadID),
.mthreadbusy(MThreadBusy),
.mthreadid(MThreadID),
.sdatathreadbusy(SDataThreadBusy),
.sthreadbusy(SThreadBusy),
.sthreadid(SThreadID),
.mreset_n(MReset_n),
.sreset_n(SReset_n),
.mareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.sareset_n(1'b1), // OCP 2.2 specific async reset tied to 1'b1
.control(4'd0),
.controlbusy(1'b0),
.controlwr(1'b0),
.status(4'd0),
337
OCP
MW
System / Core
OCP
MW
OCP
Compliant
Device
(Slave)
Core / System
In Figure 12-1, the Core / System side means the IP block side. The System / Core side means
the interconnect side (if any), or simply the bus wrapper interface module.
The four parameter values for the INTERFACE_TYPE parameter (see Table 12-2 on page 350)
comes from the four possible locations of the OCP monitor instance in reference to the system
configuration diagram shown in Figure 12-2. The required INTERFACE_TYPE parameter values
at specific locations in the whole system as per monitor instances are as follows:
338
If the user connects the monitor to the OCP Master DUT, then set as follows:
INTERFACE_TYPE = 0
If the user connects the monitor to the OCP Slave DUT, then set as follows:
INTERFACE_TYPE = 1
If the user connects the monitor to the Master side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 2
If the user connects the monitor to the Slave side of the interconnect/bus wrapper
module, then set as follows:
INTERFACE_TYPE = 3
Note that these parameter values come into play only when the Constraints_Mode parameter
is set to 1 (see Table 12-2 on page 350).
The system configuration block diagram (Figure 12-2) depicts the configuration around three
possible DUTs: Master DUT, Slave DUT, and both the Master DUT and Slave DUT.
339
Core
System Target
Core
Core
INTERFACE_TYPE=0
INTERFACE_TYPE=0
INTERFACE_TYPE=1
INTERFACE_TYPE=1
DUT Master
DUT Master
DUT Slave
DUT Slave
Response
OCP
Bus
wrapper
interface
module
Request
Slave
Slave
Master
Master
INTERFACE_TYPE=3
INTERFACE_TYPE=3
INTERFACE_TYPE=2
INTERFACE_TYPE=2
Bus Initiator
Bus Target
On-Chip Bus
Note:
This figure illustrates the OPC system configuration showing the OPC monitor INTERFACE_TYPE
parameter value with regards to the monitor instance location.
Monitor Connectivity
Connect the OCP monitor pins as specified in the pin-out Table 12-1 and illustrated in
Figure 12-3.
340
mconnid
mdatathreadid
mthreadbusy
mthreadid
sdatathreadbusy
sthreadbusy
sthreadid
maddrspace
mbyteen
mdatabyteen
mdatainfo
mreqinfo
sdatainfo
srespinfo
OCP
Monitor
matomiclength
mblockheight
mblockstride
mburstlength
mburstprecise
mburstseq
mburstsinglereq
mdatalast
mdatarowlast
mreqlast
mreqrowlast
sresplast
sresprowlast
mreset_n
mareset_n
sreset_n
sareset_n
control
controlbusy
controlwr
status
statusbusy
statusrd
mconnect
sconnect
swait
phase_options_group
basic_group
simple_ext_group
burst_ext_group
tag_ext_group
thread_ext_group
sideband_sig_group
cmd_enable_group
areset_n
base
Tag
Extensions
Thread
Extensions
mdatatagid
mtagid
mtaginorder
stagid
staginorder
Sideband Signals
clk
enableclk
maddr
mcmd
mdata
mdatavalid
mrespaccept
scmdaccept
sdata
sdataaccept
sresp
Monitor Signals
Burst Extensions
Simple Extensions
Basic Signals
Width (bits)
Description
areset_n
Asynchronous reset signal (active low). This signal is not part of OCP
interface.
341
Width (bits)
Description
base
configurable
BASE address for the XOR (exclusive OR) bursts. Width of this signal
is same as the maddr signal. This signal is required only if XOR bursts
are enabled.
The parameter BASE_PORT_SPECIFIED determines if the value at
this port matters. This parameter specifies if the base address for XOR
bursts is calculated by the user and passed to the monitor, or the monitor
should self-calculate the base address value for a XOR burst type
transaction. See the description of the BASE_PORT_SPECIFIED
parameter for more information.
basic_group
Bit position
0
1
2
3
4
5
6
7
See Note 2.
burst_ext_group
23
Bit position
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
clk
cmd_enable_group
Bit position
0
1
2
3
4
5
control
configurable
342
Parameter
ADDR
CMDACCEPT
DATAACCEPT
MDATA
SDATA
RESPACCEPT
RESP
ENABLECLK
Parameter
BURSTSEQ_INCR_ENABLE
BURSTSEQ_STRM_ENABLE
BURSTSEQ_WRAP_ENABLE
BURSTSEQ_XOR_ENABLE
BURSTSEQ_DFLT1_ENABLE
BURSTSEQ_DFLT2_ENABLE
BURSTSEQ_UNKN_ENABLE
ATOMICLENGTH
BURSTLENGTH
BURSTPRECISE
BURSTSEQ
BURSTSINGLEREQ
REQLAST
DATALAST
RESPLAST
BURST_ALIGNED
FORCE_ALIGNED
BURSTSEQ_BLCK_ENABLE
BLOCKHEIGHT
BLOCKSTRIDE
DATAROWLAST
REQROWLAST
RESPROWLAST
Parameter
READ_ENABLE
WRITE_ENABLE
WRITENONPOST_ENABLE
BROADCAST_ENABLE
RDLWRC_ENABLE
READEX_ENABLE
Width (bits)
Description
controlbusy
controlwr
enableclk
Gating signal for the input clock to derive the OCP clock. This signal is
effective when the OCP parameter enableclk is set to 1 (configured
under basic signal group, refer to Note 6 below).
maddr
configurable
Transfer address
maddrspace
configurable
Address space
mareset_n
matomiclength
configurable
mblockheight
configurable
mblockstride
configurable
Address difference between the first data word in each consecutive row
in a block burst.
mburstlength
configurable
Burst length
mburstprecise
mburstseq
mburstsinglereq
mbyteen
configurable
mcmd
Transfer command
mconnect
mconnid
configurable
Connection identifier
mdata
configurable
Write data
mdatabyteen
configurable
mdatainfo
configurable
mdatalast
mdatarowlast
mdatatagid
configurable
mdatathreadid
configurable
mdatavalid
mreqinfo
configurable
mreqlast
343
Width (bits)
Description
mreqrowlast
mreset_n
mrespaccept
mtagid
configurable
mtaginorder
mthreadbusy
configurable
mthreadid
configurable
phase_options_group
Bit position
0
1
2
See Note 2.
sareset_n
scmdaccept
sconnect
sdata
configurable
Read data
sdataaccept
sdatainfo
configurable
sdatathreadbusy
configurable
sideband_sig_group
Bit position
0
1
2
3
4
5
6
344
Parameter
DATAHANDSHAKE
REQDATA_TOGETHER
WRITERESP_ENABLE
Parameter
CONTROL
CONTROLBUSY
CONTROLWR
STATUS
STATUSBUSY
STATUSRD
CONNECTCAP
Width (bits)
Description
simple_ext_group
Bit position
0
1
2
3
4
5
6
See Note 2.
sreset_n
sresp
Transfer response
srespinfo
configurable
sresplast
sresprowlast
stagid
configurable
staginorder
status
configurable
statusbusy
statusrd
sthreadbusy
configurable
sthreadid
configurable
swait
tag_ext_group
Bit position
Parameter
0
TAGINORDER
thread_ext_group
10
Bit position
Parameter
0
MTHREADBUSY_EXACT
1
SDATATHREADBUSY_EXACT
2
STHREADBUSY_EXACT
3
CONNID
4
MTHREADBUSY
5
SDATATHREADBUSY
6
STHREADBUSY
7
MTHREADBUSY_PIPELINED
8
SDATATHREADBUSY_PIPELINED
9
STHREADBUSY_PIPELINED
tieoff_connectcap
tieoff_control
configurable
Parameter
ADDRSPACE
BYTEEN
MDATABYTEEN
MDATAINFO
REQINFO
RESPINFO
SDATAINFO
345
Width (bits)
Description
tieoff_controlbusy
tieoff_controlwr
tieoff_enableclk
tieoff_maddr
configurable
tieoff_maddrspace
configurable
tieoff_matomiclength
configurable
tieoff_mblockheight
configurable
tieoff_mblockstride
configurable
tieoff_mburstlength
configurable
tieoff_mburstprecise
tieoff_mburstseq
tieoff_mburstsinglereq 1
tieoff_mbyteen
configurable
tieoff_mconnid
configurable
tieoff_mdata
configurable
346
Width (bits)
Description
tieoff_mdatabyteen
configurable
tieoff_mdatainfo
configurable
tieoff_mdatalast
tieoff_mdatarowlast
tieoff_mdatatagid
configurable
tieoff_mdatathreadid
configurable
tieoff_mdatavalid
tieoff_mreqinfo
configurable
tieoff_mreqlast
tieoff_mreqrowlast
tieoff_mrespaccept
tieoff_mtagid
configurable
tieoff_mtaginorder
tieoff_mthreadbusy
configurable
tieoff_mthreadid
configurable
347
Width (bits)
Description
tieoff_scmdaccept
tieoff_sdata
configurable
tieoff_sdataaccept
tieoff_sdatainfo
configurable
tieoff_sdatathreadbusy configurable
tieoff_sresp
tieoff_srespinfo
configurable
tieoff_sresplast
tieoff_sresprowlast
tieoff_stagid
configurable
tieoff_staginorder
tieoff_status
configurable
tieoff_statusbusy
configurable
tieoff_statusrd
tieoff_sthreadbusy
configurable
348
Width (bits)
Description
tieoff_sthreadid
configurable
Notes:
1. Refer to the parameters section for description of parameters that configure the width of
the ports.
2. Bit 0 is the Least Significant Bit. Device parameters are configured as shown in the
following examples.
Example (a): If the design under test (DUT) supports the DATAHANDSHAKE
feature, then bit 0 of the port phase_options_group is set to 1'b1.
Example (b): If the design under test (DUT) supports Status signal, then bit 3 of the
port sideband_sig_group is set to 1'b1.
Example (c): If the design under test (DUT) supports disconnect protocol of OCP,
then the highest order bit 6 of the port sideband_sig_group is set to 1'b1.
3. If a signal is not configured for an interface, then the corresponding monitor port can be
left unconnected. A default tie-off value (as specified by the specification) for that signal
is assumed by the monitor. In the case where the design uses a tie-off value other than
default tie-off, the signal should be configured and tied to the tie-off value used in the
design.
The monitor also supports configuring tie-off values through additional ports in the
monitor interface. For such mode of tie-off configuration, the user has to do the
following:
i. Add +define+QVL_OCP_TIEOFF_CONFIG_ON to the command line while
compiling the monitor.
ii. The respective signal to be tied off to a custom value should not be configured in
the configuration ports.
iii. Connect the custom tie-off values to the tie-off configuration specific ports listed
in Table 12-1 on page 341.
4. Reset signals (mreset_n, sreset_n) should be tied to the proper system reset or to the
inactive condition (1'b1).
5. OCP specifies that the reset signals (mreset_n and sreset_n) should be asserted for at
least 16 clock cycles. Monitor does not check for this and enters in to reset state in the
first clock cycle on which reset is sampled asserted.
349
6. If the signal enableclk is added to the OCP interface, then the 8th bit in the monitor
configuration port, basic_signal_group should be set to 1. Then the derived OCP
clock used by the monitor is controlled by the enableclk signal. However, if the
signal enableclk is not added to the OCP interface, then the 8th bit in the same
configuration port should be set to the OCP recommended default 0. Then the derived
OCP clock used by the monitor is the same as the input clock.
Monitor Parameters
The parameters shown in Table 12-2 configure the OCP monitor.
Table 12-2. OCP Monitor Parameters
Order Parameter
Default
Description
1.
Constraints_Mode
2.
INTERFACE_TYPE
3.
ADDR_WDTH
32
4.
DATA_WDTH
32
5.
BURSTLENGTH_WDTH
6.
ATOMICLENGTH_WDTH
7.
THREADS
Number of threads.
8.
THREADID_WDTH
9.
CONNID_WDTH
10.
ADDRSPACE_WDTH
11.
MDATAINFO_WDTH
12.
MDATAINFOBYTE_WDTH
13.
REQINFO_WDTH
14.
RESPINFO_WDTH
15.
SDATAINFO_WDTH
16.
SDATAINFOBYTE_WDTH
17.
CONTROL_WDTH
350
Default
Description
18.
STATUS_WDTH
19.
TAGS
Number of tags.
20.
TAGID_WDTH
21.
TAG_INTERLEAVE_SIZE
22.
ENABLE_INTER_PHASE_
TRANFER_CHECKS
23.
MAX_OUTSTANDING_REQ
16
24.
BLOCKHEIGHT_WDTH
25.
BLOCKSTRIDE_WDTH
26.
BASE_PORT_SPECIFIED
27.
CONNECTION
28.
DATA_X_Z_CHECK_ENABLE
Notes:
1. The parameters must be specified in the above order.
351
Instantiation Examples
Example 1
Example 12-1 instantiates an OCP monitor on a master interface of the core side. The OCP
interface has an address width of 16 bits and data width of 64-bits. Datahandshake and response
phases are enabled. The interface supports all types of burst address sequences and all type of
commands. All tag extensions, thread extensions, control, and status related features are
disabled. The signals mrespaccept, scmdaccept, sdataaccept are all disabled. Therefore,
all phases are accepted on the same clock cycle.
Example 12-1. OCP Monitor Instantiation for Example 1
qvl_ocp_monitor #(
1,
/* Constraints_Mode */
0,
/* INTERFACE_TYPE */
16,
/* ADDR_WDTH */
64,
/* DATA_WDTH */
5,
/* BURSTLENGTH_WDTH */
1,
/* ATOMICLENGTH_WDTH */
1,
/* THREADS */
1,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
4,
/* ADDRSPACE_WDTH */
8,
/* MDATAINFO_WDTH */
1,
/* MDATAINFOBYTE_WDTH */
1,
/* REQINFO_WDTH */
1,
/* RESPINFO_WDTH */
8,
/* SDATAINFO_WDTH */
1,
/* SDATAINFOBYTE_WDTH */
1,
/* CONTROL_WDTH */
1,
/* STATUS_WDTH */
1,
/* TAGS */
1,
/* TAGID_WDTH */
1,
/* TAG_INTERLEAVE_SIZE */
1,
/* ENABLE_INTER_PHASE_TRANFER_CHECKS */
16,
/* MAX_OUTSTANDING_REQ */
4,
/* BLOCKHEIGHT_WDTH */
4,
/* BLOCKSTRIDE_WDTH */
0,
/* BASE_PORT_SPECIFIED */
0
/*.CONNECTION */ Disconnect parameter default at zero that
// means the device is always connected and is not
// disconnected capable.
)
OCP_MONITOR
(.clk(clk),
.areset_n(1'b1),
.maddr(maddr),
.mcmd(mcmd),
.mdata(mdata),
.mdatavalid(mdatavalid),
.mrespaccept(),
.scmdaccept(),
.sdata(sdata),
352
353
Note that the tie-off specific ports are not shown in the example instances. These ports are
available only under the specific macro QVL_OCP_TIEOFF_CONFIG_ON (see Table 12-1 on
page 341).
Example 2
Example 12-2 instantiates an OCP monitor on a slave interface of the system side. The OCP
interface has an address width of 16-bits and data width of 16-bits. Datahandshake and response
phases are enabled. The interface supports only INCR and WRAP type of burst address
sequences. All type of commands are supported. All tag extensions and thread extensions
related features are disabled. Control and status related features are enabled. The signals
mrespaccept, scmdaccept, sdataaccept are all disabled. Therefore, all phases are accepted
on the same clock cycle.
Example 12-2. OCP Monitor Instantiation for Example 2
qvl_ocp_monitor #(
1,
/* Constraints_Mode */
0,
/* INTERFACE_TYPE */
16,
/* ADDR_WDTH */
16,
/* DATA_WDTH */
5,
/* BURSTLENGTH_WDTH */
1,
/* ATOMICLENGTH_WDTH */
1,
/* THREADS */
1,
/* THREADID_WDTH */
1,
/* CONNID_WDTH */
2,
/* ADDRSPACE_WDTH */
2,
/* MDATAINFO_WDTH */
1,
/* MDATAINFOBYTE_WDTH */
1,
/* REQINFO_WDTH */
1,
/* RESPINFO_WDTH */
2,
/* SDATAINFO_WDTH */
1,
/* SDATAINFOBYTE_WDTH */
2,
/* CONTROL_WDTH */
2,
/* STATUS_WDTH */
1,
/* TAGS */
1,
/* TAGID_WDTH */
1
/* TAG_INTERLEAVE_SIZE */
1,
/* ENABLE_INTER_PHASE_TRANFER_CHECKS */
16,
/* MAX_OUTSTANDING_REQ */
4,
/* BLOCKHEIGHT_WDTH */
4,
/* BLOCKSTRIDE_WDTH */
0,
/* BASE_PORT_SPECIFIED */
0
/*.CONNECTION */ Disconnect parameter default at zero that
// means the device is always connected and is not
// disconnected capable.
)
OCP_MONITOR
(.clk(clk),
.areset_n(1'b1),
.maddr(maddr),
.mcmd(mcmd),
.mdata(mdata),
354
355
Note that the tie-off specific ports are not shown in the example instances. These ports are
available only under the specific macro QVL_OCP_TIEOFF_CONFIG_ON (see Table 12-1 on
page 341).
Monitor Checks
Table 12-3 lists the checks performed by the OCP monitor.
Table 12-3. OCP Monitor Check
Check ID
Violation
Description
FIRE_OCP_SRESPINFO_NOT_
CONSTANT_DURING_BURST
OCP_ATOMICLENGTH_
WITHOUT_BURSTLENGTH
ATOMICLENGTH should be
enabled only if
BURSTLENGTH is enabled.
OCP_BCST_CMD_WHILE_
BROADCAST_ENABLE_0
A master with
BROADCAST_ENABLE set
to 0 should not generate
Broadcast command.
OCP_BLCK_ADDRSPACE_
BOUNDARY_CROSS
OCP_BLCK_BURST_
INCORRECT_ADDRESS_
SEQUENCE
(OCP 2.2 check)
356
Violation
Description
OCP_BLCK_BURST_WHILE_
BURSTSEQ_BLCK_ENABLE_0
OCP_BURST_ALIGNED_INCR_
BURST_NOT_PRECISE
When BURST_ALIGNED is
enabled, INCR bursts should
be issued as precise bursts.
OCP_BURST_ALIGNED_
INCR_BURST_SIZE_NOT_
POWER_OF_TWO
When BURST_ALIGNED is
enabled, the total burst size of
INCR bursts should be power
of two.
OCP_BURST_ALIGNED_INCR_
BURST_UNALIGNED_START_
ADDR
When BURST_ALIGNED is
enabled, INCR bursts should
have their starting address
aligned to total burst size.
OCP_BURSTLENGTH_WDTH_
VALUE_OF_1
The
BURSTLENGTH_WDTH
value should not be set to 1.
OCP_BURSTPRECISE_
WITHOUT_BURSTLENGTH
BURSTPRECISE should be
enabled only if
BURSTLENGTH is enabled.
357
Violation
Description
OCP_BURSTSEQ_WITHOUT_
BURSTLENGTH
BURSTSEQ should be
enabled only if
BURSTLENGTH is enabled.
OCP_BURSTSINGLEREQ_
ENABLED_WHILE_ONLY_
UNKN_ADDR_SEQ_ENABLED
BURSTSINGLEREQ should
not be enabled if the only
enabled burst address sequence
is UNKN.
OCP_BURSTSINGLEREQ_
ENABLED_WITHOUT_
BURSTPRECISE
BURSTSINGLEREQ should
not be enabled if
BURSTPRECISE is not
enabled.
OCP_BURSTSINGLEREQ_
ENABLED_WITHOUT_
DATAHANDSHAKE
OCP_BURSTSINGLEREQ_
WITHOUT_BURSTLENGTH
BURSTSINGLEREQ should
be enabled only if
BURSTLENGTH is enabled.
OCP_BYTE_ENABLES_NOT_
FORCE_ALIGNED
A master with
FORCE_ALIGNED option
enabled should not generate
any byte enable patterns that
are not force aligned.
358
Violation
Description
OCP_CMDACCEPT_WHILE_
STHREADBUSY_AND_
STHREADBUSY_ XACT
STHREADBUSY_EXACT parameter
requires strict semantics for SThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter CMDACCEPT is enabled when
both the parameters STHREADBUSY and
STHREADBUSY_EXACT are enabled.
OCP_CONNECTCAP_NOT_
TIED_OFF_TO_ZERO_WHILE_
CONNECTION_PARAMETER_
CONFIGURED_ZERO
Connectcap must be
configured as zero while
parameter CONNECTION is
set to zero.
OCP_CONTROL_CHANGED_
MORE_THAN_ONCE
OCP_CONTROL_CHANGED_
If ControlBusy is sampled
WHILE_CONTROLBUSY_
asserted in the previous cycle,
ACTIVE_IN_PREVIOUS_CYCLE then the Control should not
transition in the current cycle.
OCP_CONTROL_NOT_
STEADY_AFTER_RESET
OCP_CONTROL_UNKN
OCP_CONTROLBUSY_ UNKN
OCP_CONTROLBUSY_
ASSERTED_INCORRECTLY
359
Violation
Description
OCP_CONTROLBUSY_
ENABLED_WITHOUT_
CONTROLWR
CONTROLBUSY should be
enabled only if
CONTROLWR is enabled.
OCP_CONTROLWR_
ASSERTED_FOR_MORE_
THAN_ ONE_CYCLE
OCP_CONTROLWR_
ASSERTED_IN_FIRST_CYCLE_
AFTER_RESET
OCP_CONTROLWR_
ASSERTED_WHILE_
CONTROLBUSY_ACTIVE
OCP_CONTROLWR_
DEASSERTED_WHILE_
CONTROL_ CHANGED
OCP_CONTROLWR_UNKN
OCP_DATAACCEPT_
ENABLED_WITHOUT_
DATAHANDSHAKE
360
Violation
Description
OCP_DATAACCEPT_WHILE_
SDATATHREADBUSY_AND_
SDATATHREADBUSY_EXACT
SDATATHREADBUSY_EXACT parameter
requires strict semantics for SThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter DATAACCEPT is enabled and both
the parameters SDATATHREADBUSY and
SDATATHREADBUSY_EXACT are
enabled.
OCP_DATAHANDSHAKE_
BEGINNING_BEFORE_
REQUEST
OCP_DATAHANDSHAKE_
BLOCKING_WHILE_REQ_
ON_BLOCKING_FLOW_
CONTROL
When request phase is configured for nonblocking flow control (CMDACCEPT = 0 &&
STHREADBUSY = 1 &&
STHREADBUSY_EXACT = 1),
datahandshake phase should not be configured
for blocking flow control (DATAACCEPT =
1, SDATATHREADBUSY = 0,
SDATATHREADBUSY_EXACT = 0). This
check fires if this requirement is violated.
OCP_DATAHANDSHAKE_
ENDING_BEFORE_REQUEST
OCP_DATAHANDSHAKE_
WITHOUT_WRITE_TYPE_CMD
DATAHANDSHAKE should
be enabled only if at least one
of the write-type command is
enabled.
OCP_DATALAST_ENABLED_
WITHOUT_DATAHANDSHAKE
361
Violation
Description
OCP_DATAROWLAST_
WITHOUT_BURSTLENGTH
OCP_DFLT1_BURST_WHILE_
BURSTSEQ_DFLT1_ENABLE_0
A master with
BURSTSEQ_DFLT1_
ENABLE set to 0 should not
issue DFLT1 burst.
OCP_DFLT2_BURST_WHILE_
BURSTSEQ_DFLT2_ENABLE_0
A master with
BURSTSEQ_DFLT2_
ENABLE set to 0 should not
issue DFLT2 burst.
OCP_DFLT2_SEQUENCE_
WITHOUT_ANY_BYTE_
ENABLE_ASSERTED
OCP_DFLT2_SEQUENCE_
WITHOUT_ANY_
MDATABYTE_ENABLE_
ASSERTED
OCP_DATAROWLAST_
WITHOUT_DATAHANDSHAKE
(OCP 2.2 check)
OCP_DATAROWLAST_
WITHOUT_DATLAST_AND_
BURSTSEQ_BLCK_ENABLE
(OCP 2.2 check)
362
Violation
Description
OCP_FAIL_RESPONSE_
VIOLATION
OCP_FORCE_ALIGNED_
ENABLED_WHEN_DATA_
WDTH_IS_NON_POWER_OF_
TWO
FORCE_ALIGNED should be
enabled only when
DATA_WDTH is set to a
power-of-two value.
OCP_ILLEGAL_
BLOCKHEIGHT_WIDTH
BLOCKHEIGHT_WIDTH
must be set to 0 if the
parameter blockheight is
disabled.
BLOCKHEIGHT_WIDTH
must be set to greater than 1 if
blockheight is enabled.
If the parameter
BLOCKHEIGHT_WIDTH representing
port width of the signal blockheight is not
set to 0 when the other parameter
blockheight is set to 0.
If the parameter
BLOCKHEIGHT_WIDTH is not set to
greater than 1 when the other parameter
blockheight is set to 1.
OCP_ILLEGAL_
MATOMICLENGTH_
ENCODING
OCP_ILLEGAL_
MBLOCKHEIGHT_ENCODING
363
Violation
Description
OCP_ILLEGAL_
MBLOCKSTRIDE_ENCODING
OCP_ILLEGAL_
MBURSTLENGTH_ENCODING
OCP_ILLEGAL_SETTING_OF_
MTHREADBUSY_PIPELINED
mthreadbusy_pipelined can
This check fires if the parameter
only be enabled if
mthreadbusy_pipelined is enabled without
mthreadbusy_exact is enabled. having the other parameter mthreadbusy_exact
enabled.
sdatathreadbusy_pipelined can
only be enabled if
sdatathreadbusy_exact is
enabled.
sthreadbusy_pipelined can
only be enabled if
sthreadbusy_exact is enabled.
364
Violation
Description
OCP_IMPROPER_
MDATABYTEEN_ENABLING
MDATABYTEEN should be
enabled only if MDATA is
enabled,
DATAHANDSHAKE is
enabled, and DATA_WDTH is
an integer multiple of 8.
OCP_IMPROPER_SDATAINFO_
ENABLING
OCP_INCORRECT_
MDATAINFO_WDTH
MDATAINFO_WDTH should
be greater than or equal to
MDATAINFOBYTE_
WDTH*DATA_WDTH/8.
OCP_INCORRECT_
SDATAINFO_WDTH
SDATAINFO_WDTH should
be greater than or equal to
SDATAINFOBYTE_
WDTH*DATA_WDTH/8.
365
Violation
Description
OCP_INCR_BURST_
INCORRECT_ADDRESS_
SEQUENCE
OCP_INCR_BURST_WHILE_
BURSTSEQ_INCR_ENABLE_0
A master with
BURSTSEQ_INCR_
ENABLE set to 0 should not
issue INCR burst.
OCP_LEAVING_CONNECTED_
STATE_DURING_ONGOING_
TRANSACTION
OCP_MADDR_NOT_ STEADY
OCP_MADDR_UNALIGNED_
TO_OCP_WORD_SIZE
OCP_MADDR_UNKN
OCP_MADDRSPACE_NOT_
CONSTANT_DURING_ BURST
MAddrSpace should be
constant throughout the burst.
366
Violation
Description
OCP_MADDRSPACE_NOT_
STEADY
OCP_MADDRSPACE_UNKN
MAddrSpace signal should not Checks that MAddrSpace is both known (not
be X or Z.
X) and driven (not Z).
OCP_MATOMICLENGTH_
UNKN
OCP_MBLOCKHEIGHT_NOT_
CONSTANT_DURING_BURST
MBlockHeight should be
steady from the beginning of
the request phase until the end
of the request phase.
OCP_MBLOCKHEIGHT_NOT_
STEADY
(OCP 2.2 check)
367
Violation
Description
OCP_MBLOCKHEIGHT_
UNKN
MBlockStride should be
steady from the beginning of
the request phase until the end
of the request phase.
MBlockStride should be
aligned to OCP word size.
OCP_MBLOCKSTRIDE_NOT_
STEADY
(OCP 2.2 check)
OCP_MBLOCKSTRIDE_
UNALIGNED_TO_OCP_WORD_
SIZE
(OCP 2.2 check)
OCP_MBLOCKSTRIDE_UNKN
(OCP 2.2 check)
OCP_MBURSTLENGTH_NOT_
CONSTANT_DURING_
PRECISE_BURST
368
Violation
Description
OCP_MBURSTLENGTH_NOT_
STEADY
MBurstLength should be
steady from the beginning of
the request phase until the end
of the request phase.
OCP_MBURSTLENGTH_UNKN
OCP_MBURSTPRECISE_NOT_
CONSTANT_DURING_BURST
MBurstPrecise should be
constant throughout the burst.
OCP_MBURSTPRECISE_NOT_
STEADY
MBurstPrecise should be
steady from the beginning of
the request phase until the end
of the request phase.
OCP_MBURSTPRECISE_UNKN
OCP_MBURSTSEQ_NOT_
CONSTANT_DURING_BURST
OCP_MBURSTSEQ_NOT_
STEADY
OCP_MBURSTSEQ_UNKN
369
Violation
Description
OCP_MBURSTSINGLEREQ_
ASSERTED_WHEN_
MBURSTPRECISE_
DEASSERTED
OCP_MBURSTSINGLEREQ_
NOT_CONSTANT_DURING_
BURST
MBurstSingleReq should be
constant throughout the burst.
OCP_MBURSTSINGLEREQ_
NOT_STEADY
MBurstSingleReq should be
steady from the beginning of
the request phase until the end
of the request phase.
OCP_MBURSTSINGLEREQ_
UNKN
MBurstSingleReq signal
should not be X or Z.
OCP_MBYTEEN_UNKN
OCP_MCMD_NOT_
CONSTANT_DURING_ BURST
OCP_MCMD_NOT_IDLE_
WHILE_OCP_NOT_
CONNECTED
370
Violation
Description
OCP_MCMD_NOT_STEADY
OCP_MCMD_UNKN
OCP_MCONNID_NOT_
CONSTANT_DURING_ BURST
OCP_MCONNID_NOT_STEADY
OCP_MCONNID_UNKN
OCP_MDATA_NOT_STEADY_
FOR_DATAHANDSHAKE_
PHASE
OCP_MDATA_NOT_STEADY_
FOR_REQ_PHASE
371
Violation
Description
OCP_MDATA_UNKN
OCP_MDATABYTE_ENABLES_
NOT_FORCE_ALIGNED
A master with
FORCE_ALIGNED option
enabled should not generate
any mdatabyte enable patterns
that are not force aligned.
OCP_MDATABYTEEN_NOT_
STEADY
MDataByteEn should be
steady from the beginning of
the datahandshake phase until
the end of the datahandshake
phase.
OCP_MDATABYTEEN_UNKN
OCP_MDATAINFO_NOT_
STEADY_FOR_
DATAHANDSHAKE_PHASE
OCP_MDATAINFO_NOT_
STEADY_FOR_REQ_PHASE
372
Violation
Description
OCP_MDATAINFO_UNKN
OCP_MDATALAST_NOT_
STEADY
OCP_MDATALAST_UNKN
OCP_MDATALAST_
VIOLATION
OCP_MDATAROWLAST_NOT_
STEADY
MDataRowLast should be
steady from the beginning of
the datahandshake phase until
the end of the datahandshake
phase.
373
Violation
Description
OCP_MDATATAGID_NOT_
STEADY
OCP_MDATATAGID_UNKN
MDataTagID signal should not Checks that MDataTagID is both known (not
be X or Z.
X) and driven (not Z).
OCP_MDATATAGID_VALUE_
NOT_LESS_THAN_TAGS
OCP_MDATATHREADID_
UNKN
OCP_MDATATHREADID_
VALUE_NOT_LESS_THAN_
THREADS
OCP_MDATAVALID_NOT_
STEADY
374
Violation
Description
OCP_MDATAVALID_UNKN
OCP_MREQINFO_NOT_
CONSTANT_DURING_BURST
OCP_MREQINFO_NOT_
STEADY
OCP_MREQINFO_UNKN
OCP_MREQLAST_NOT_
STEADY
OCP_MREQLAST_UNKN
MReqLast signal should not be Checks that MReqLast is both known (not X)
X or Z.
and driven (not Z).
OCP_MREQLAST_VIOLATION
OCP_MREQLAST_WITHOUT_
BURSTLENGTH
MREQLAST should be
enabled only if
BURSTLENGTH is enabled.
375
Violation
Description
OCP_MREQROWLAST_NOT_
STEADY
MReqRowLast should be
steady from the beginning of
the request phase until the end
of the request phase.
OCP_MRESPACCEPT_ UNKN
OCP_MRESPLAST_WITHOUT_
BURSTLENGTH
MRESPLAST should be
enabled only if
BURSTLENGTH is enabled.
OCP_MREQROWLAST_UNKN
(OCP 2.2 check)
OCP_MTAGID_NOT_STEADY
OCP_MTAGID_UNKN
376
Violation
Description
OCP_MTAGID_VALUE_NOT_
LESS_THAN_TAGS
OCP_MTAGINORDER_NOT_
CONSTANT_DURING_BURST
MTagInOrder should be
constant throughout the burst.
OCP_MTAGINORDER_NOT_
STEADY
OCP_MTAGINORDER_UNKN
OCP_MTHREADBUSY_
ENABLED_WITHOUT_RESP
OCP_MTHREADBUSY_EXACT_ MTHREADBUSY_
ENABLED_WITHOUT_
EXACT should be enabled
MTHREADBUSY
only if MTHREADBUSY is
enabled.
377
Violation
Description
OCP_MTHREADBUSY_
PIPELINED_RESPONSE_
PRESENTATION_VIOLATION
If MTHREADBUSY_
PIPELINED is enabled, slave
should not present a response
on a thread for which the
corresponding MThreadBusy
bit is asserted in the previous
cycle.
OCP_MTHREADBUSY_
WITHOUT_EXACTLY_ONE_
OF_MTHREADBUSY_EXACT_
AND_RESPACCEPT
(OCP 2.2 check)
OCP_MTHREADBUSY_
MTHREADBUSY should not
WITHOUT_RESPACCEPT_
be enabled when
AND_MTHREADBUSY_ EXACT RESPACCEPT and
MTHREADBUSY_
EXACT are not enabled.
MTHREADBUSY_EXACT parameter
requires strict semantics for MThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter MTHREADBUSY is enabled
without enabling RESPACCEPT and
MTHREADBUSY_EXACT.
OCP_MTHREADID_NOT_
CONSTANT_DURING_ BURST
OCP_MTHREADID_NOT_
STEADY
378
Violation
Description
OCP_MTHREADID_UNKN
OCP_MTHREADID_VALUE_
NOT_LESS_THAN_THREADS
OCP_NONE_OF_THE_BURST_
SEQUENCE_ENABLED
If BURSTSEQ is enabled, at
least one of the burst sequence
parameters should be enabled.
OCP_NONE_OF_THE_
COMMANDS_ENABLED
OCP_RD_CMD_WHILE_READ_
ENABLE_0
A master with
READ_ENABLE set to 0
should not generate Read
command.
OCP_RDEX_CMD_AS_ BURST
OCP_RDEX_CMD_WHILE_
READEX_ENABLE_0
A master with
READEX_ENABLE set to 0
should not generate ReadEx
command.
OCP_RDL_CMD_AS_ BURST
OCP_RDL_CMD_WHILE_
RDLWRC_ENABLE_0
A master with
RDLWRC_ENABLE set to 0
should not generate
ReadLinked command.
OCP_RDL_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WRITERESP_ENABLE is set
to 0 should not generate
ReadLinked command.
379
Violation
Description
OCP_RDLWRC_ENABLE_
SET_WITHOUT_WRITERESP_
ENABLE
RDLWRC_ENABLE should
be set to 1 only if
WRITERESP_ENABLE is set
to 1.
OCP_READEX_CMD_NOT_
FOLLOWED_BY_WR_WRNP_
CMD
OCP_READEX_ENABLE_SET_
WITHOUT_WRITE_ENABLE_
OR_WRITENONPOST_ENABLE
READEX_ENABLE should
not be enabled if
WRITE_ENABLE or
WRITENONPOST_
ENABLE is not set to 1.
OCP_REQDATA_TOGETHER_
MULTI_REQ_ACCEPTANCE_
VIOLATION
380
Violation
Description
OCP_REQDATA_TOGETHER_
MULTI_REQ_PRESENTATION_
VIOLATION
OCP_REQDATA_TOGETHER_
SINGLE_REQ_ACCEPTANCE_
VIOLATION
OCP_REQDATA_TOGETHER_
SINGLE_REQ_
PRESENTATION_VIOLATION
OCP_REQROWLAST_
WITHOUT_BURSTLENGTH
OCP_REQROWLAST_
WITHOUT_REQLAST_AND_
BURSTSEQ_BLCK_ENABLE
(OCP 2.2 check)
OCP_RESP_NOT_ENABLED
381
Violation
Description
OCP_RESPACCEPT_WHILE_
MTHREADBUSY_AND_
MTHREADBUSY_EXACT
OCP_RESPACCEPT_WITH_
MTHREADBUSY_EXACT_
ENABLED
OCP_RESPINFO_ENABLED_
WITHOUT_RESP
OCP_RESPLAST_ENABLED_
WITHOUT_RESP
OCP_RESPONSE_BEGINNING_
BEFORE_DATAHANDSHAKE
OCP_RESPONSE_BEGINNING_
BEFORE_REQUEST
382
Violation
Description
OCP_RESPONSE_ENDING_
BEFORE_DATAHANDSHAKE
OCP_RESPONSE_ENDING_
BEFORE_REQUEST
OCP_RESPROWLAST_
WITHOUT_BURSTLENGTH
OCP_RESPROWLAST_
WITHOUT_DATLAST_AND_
BURSTSEQ_BLCK_ENABLE
(OCP 2.2 check)
OCP_RESPROWLAST_
WITHOUT_RESP
(OCP 2.2 check)
OCP_SCMDACCEPT_UNKN
SCmdAccept signal should not Checks that SCmdAccept is both known (not
be X or Z.
X) and driven (not Z).
OCP_SDATA_ENABLED_
WITHOUT_RESP
383
Violation
Description
OCP_SDATA_NOT_STEADY
OCP_SDATA_UNKN
OCP_SDATAACCEPT_UNKN
OCP_SDATAINFO_ENABLED_
WITHOUT_RESP
OCP_SDATAINFO_NOT_
STEADY
OCP_SDATAINFO_UNKN
OCP_SDATATHREADBUSY_
EXACT_DATAHANDSHAKE_
ACCEPTANCE_VIOLATION
Datahandshake phase
presented on a thread for
which SDataThreadBusy is deasserted in the current cycle
should be accepted by the
slave in that cycle.
384
Violation
Description
OCP_SDATATHREADBUSY_
EXACT_DATAHANDSHAKE_
PRESENTATION_VIOLATION
OCP_SDATATHREADBUSY_
EXACT_ENABLED_WITHOUT_
SDATATHREADBUSY
SDATATHREADBUSY_
EXACT should be enabled
only if
SDATATHREADBUSY is
enabled.
SDATATHREADBUSY_EXACT has no
meaning if the SDATATHREADBUSY signal
is not configured for an interface in the first
place. This check fires when the parameter
SDATATHREADBUSY_EXACT is enabled
when the parameter SDATATHREADBUSY
is not enabled.
OCP_SDATATHREADBUSY_
PIPELINED_
DATAHANDSHAKE_
PRESENTATION_VIOLATION
If SDATATHREADBUSY_
PIPELINED is enabled, then a
datahandshake phase should
not be presented on a thread
for which the corresponding
SDataThreadBusy bit is
asserted in the previous cycle.
SDATATHREADBUSY
should not be enabled when
DATAACCEPT and
SDATATHREADBUSY_
EXACT are not enabled.
SDATATHREADBUSY_EXACT parameter
requires strict semantics for SDataThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter SDATATHREADBUSY is enabled
without enabling DATAACCEPT and
SDATATHREADBUSY_EXACT, as there is
no real flow control.
OCP_SDATATHREADBUSY_
WITHOUT_DATAACCEPT_
AND_
SDATATHREADBUSY_EXACT
385
Violation
Description
OCP_SRESP_NOT_STEADY
OCP_SRESP_UNKN
OCP_SRESPINFO_NOT_
STEADY
OCP_SRESPINFO_UNKN
SRespInfo signal should not be Checks that SRespInfo is both known (not X)
X or Z.
and driven (not Z).
OCP_SRESPLAST_NOT_
STEADY
OCP_SRESPLAST_UNKN
SRespLast signal should not be Checks that SRespLast is both known (not X)
X or Z.
and driven (not Z).
OCP_SRESPLAST_VIOLATION
386
Violation
Description
OCP_SRESPROWLAST_NOT_
STEADY
SRespRowLast should be
steady from the beginning of
the response phase until the
end of the response phase.
OCP_SRMD_WR_RESP_
BEGINNING_BEFORE_LAST_
WR_DATA
OCP_SRMD_WR_RESP_
ENDING_BEFORE_LAST_WR_
DATA
OCP_STAGID_NOT_STEADY
OCP_SRESPROWLAST_UNKN
(OCP 2.2 check)
387
Violation
Description
OCP_STAGID_UNKN
OCP_STAGID_VALUE_NOT_
LESS_THAN_TAGS
OCP_STAGINORDER_NOT_
STEADY
OCP_STAGINORDER_UNKN
OCP_STATUS_UNKN
OCP_STATUSBUSY_
ENABLED_WITHOUT_STATUS
OCP_STATUSBUSY_UNKN
OCP_STATUSRD_ASSERTED_
FOR_MORE_THAN_ONE_
CYCLE
OCP_STATUSRD_ASSERTED_
StatusRd signal should not be
WHILE_STATUSBUSY_ACTIVE asserted if StatusBusy is
asserted.
OCP_STATUSRD_ENABLED_
WITHOUT_STATUS
388
Violation
Description
OCP_STATUSRD_UNKN
OCP_STHREADBUSY_EXACT_
COMMAND_ACCEPTANCE_
VIOLATION
Command presented on a
thread for which SThreadBusy
is de-asserted in the current
cycle should be accepted by
the slave in that cycle.
OCP_STHREADBUSY_EXACT_
COMMAND_PESENTATION_
VIOLATION
If STHREADBUSY_EXACT
is enabled for a master, it
should not present a command
on a thread for which the
corresponding SThreadBusy
bit asserted in this cycle.
OCP_STHREADBUSY_EXACT_
ENABLED_WITHOUT_
STHREADBUSY
STHREADBUSY_EXACT
should be enabled only if
STHREADBUSY is enabled.
OCP_STHREADBUSY_
PIPELINED_COMMAND_
PRESENTATION_VIOLATION
If STHREADBUSY_EXACT
is enabled, then a command
should not be presented on a
thread for which the
corresponding SThreadBusy
bit asserted in this cycle.
STHREADBUSY_EXACT parameter
requires strict semantics for SThreadbusy
signal to ensure that multithreaded OCP
interface never blocks. This check fires when
parameter STHREADBUSY is enabled
without enabling CMDACCEPT and
STHREADBUSY_EXACT, as there is no real
flow control.
OCP_STHREADBUSY_
WITHOUT_CMDACCEPT_
ANDSTHREADBUSY_EXACT
389
Violation
Description
OCP_STHREADID_NOT_
STEADY
OCP_STHREADID_UNKN
OCP_STHREADID_VALUE_
NOT_LESS_THAN_THREADS
OCP_STRM_BURST_MADDR_
NOT_CONSTANT
OCP_STRM_BURST_WHILE_
BURSTSEQ_STRM_ENABLE_0
A master with
BURSTSEQ_STRM_
ENABLE set to 0 should not
issue STRM burst.
OCP_STRM_SEQUENCE_NOT_
HAVING_SAME_BYTE_
ENABLES
390
Violation
Description
OCP_STRM_SEQUENCE_NOT_
HAVING_SAME_
MDATABYTE_ENABLES
OCP_STRM_SEQUENCE_
WITHOUT_ANY_BYTE_
ENABLE_ASSERTED
OCP_STRM_SEQUENCE_
WITHOUT_ANY_
MDATABYTE_ENABLE_
ASSERTED
OCP_TAGGED_WRITE_DATA_
OUT_OF_ORDER
OCP_TAGID_WDTH_NOT_
LOG2_OF_TAGS
391
Violation
Description
OCP_TAGINORDER_WHEN_
TAGS_NOT_GREATER_THAN_
1
OCP_THREADID_WDTH_NOT_
LOG2_OF_THREADS
OCP_TRANSITS2MCON_
WITHOUT_SLAVE_GRANT
A master with
BURSTSEQ_UNKN_
ENABLE set to 0 should not
issue UNKN burst.
OCP_WR_CMD_WHILE_
WRITE_ENABLE_0
392
A master with
WRITE_ENABLE set to 0
should not generate Write
command.
Violation
Description
OCP_WRAP_BURST_
INCORRECT_ADDRESS_
SEQUENCE
OCP_WRAP_BURST_WHILE_
BURSTSEQ_WRAP_ENABLE_0
A master with
BURSTSEQ_WRAP_
ENABLE set to 0 should not
issue WRAP burst.
OCP_WRAP_SEQUENCE_FOR_
IMPRECISE_BURST
Burst address sequence WRAP To calculate the proper address sequence for
should be used only for precise WRAP burst, length of the burst must be
bursts.
known at the start of the burst. For this reason,
burst address sequence WRAP should be
issued as a precise burst. This check fires if
this requirement is violated. This check is
active only if the parameter BURSTSEQ is set
to 1.
OCP_WRAP_SEQUENCE_NON_
POWER_OF_TWO_BURST_
LENGTH
OCP_WRAP_SEQUENCE_NON_
POWER_OF_TWO_DATA_
WDTH
OCP_WRC_CMD_AS_ BURST
The WriteConditional
command should not be used
as part of burst.
OCP_WRC_CMD_WHILE_
RDLWRC_ENABLE_0
A master with
RDLWRC_ENABLE set to 0
should not generate
WriteConditional command.
393
Violation
Description
OCP_WRC_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WRITERESP_ENABLE is set
to 0 should not generate
WriteConditional command.
OCP_WRITENONPOST_
ENABLE_SET_WITHOUT_
WRITERESP_ENABLE
WRITENONPOST_
ENABLE should be set to 1
only if
WRITERESP_ENABLE is set
to 1.
OCP_WRNP_CMD_WHILE_
WRITENONPOST_ENABLE_0
A master with
WRITENONPOST_ENABLE
set to 0 should not generate
WriteNonPost command.
OCP_WRNP_CMD_WHILE_
WRITERESP_ENABLE_0
A master with
WRITERESP_ENABLE is set
to 0 should not generate
WriteNonPost command.
OCP_XOR_BURST_
INCORRECT_ADDRESS_
SEQUENCE
394
Violation
Description
OCP_XOR_BURST_WHILE_
BURSTSEQ_XOR_ENABLE_0
A master with
BURSTSEQ_XOR_
ENABLE set to 0 should not
issue XOR burst.
OCP_XOR_SEQUENCE_FOR_
IMPRECISE_BURST
OCP_XOR_SEQUENCE_NON_
POWER_OF_TWO_BURST_
LENGTH
OCP_XOR_SEQUENCE_NON_
POWER_OF_TWO_DATA_
WDTH
Description
Read requests
Write requests
Broadcast requests
WriteNonPost requests
WriteConditional requests
ReadLinked requests
ReadEx requests
395
Description
Imprecise bursts
DVA responses
ERR responses
FAIL responses
396
Description
Note that the corner cases are applicable only if the corresponding features (parameters) are
enabled.
Monitor Statistics
Table 12-5 lists the corner cases maintained by the OCP monitor.
Table 12-5. OCP Protocol Statistics
Statistic
Description
Total requests
Note that the statistics are applicable only if the corresponding features (parameters) are
enabled.
397
398
Chapter 13
Peripheral Component Interconnect (PCI)
Introduction
The Peripheral Component Interconnect (PCI) local bus is an industry standard, highperformance local bus architecture. The Mentor Graphic QVL PCI Monitor verifies the
operation of a PCI compliant device under simulation. When running the Assertion in
Simulation tool, the checkers defined by the monitor validate various restrictions and
requirements of the PCI specification. With formal analysis, the monitors checks can be targets
for search or they can be used to constrain the interface to provide legal stimulus.
The Mentor Graphic QVL PCI Monitor supports PCI compliant devices that use the 32-bit
standard data bus configuration and those that use the 64-bit extension.
Reference Documentation
This PCI monitor is modeled from the requirements provided in the following document:
PCI Monitor
399
Monitor Connectivity
Connect the PCI monitor pins to internal signals as specified in the pin-out Table 13-1 and
illustrated in Figure 13-2.
The PCI monitor enable signals (*_en_n) are active low signals. When asserted (low), the PCI
monitor samples the corresponding out signal (for example, pci_frame_out_n). When deasserted (high), the PCI monitor samples the corresponding in signal (for example,
pci_frame_in_n).
Figure 13-2. PCI Monitor Pin Diagram
From PCI Bus
pci_rst_in_n
pci_clk_in
pci_gnt_in_n
pci_idsel_in
pci_ad_in
pci_cbe_in_n
pci_frame_in_n
pci_irdy_in_n
pci_trdy_in_n
pci_devsel_in_n
pci_stop_in_n
pci_lock_in_n
pci_perr_in_n
PCI Monitor
pci_par_in
pci_par64_in
pci_req64_in_n
pci_ack64_in_n
pci_ad_en_n
pci_cbe_en_n
pci_frame_en_n
pci_irdy_en_n
pci_trdy_en_n
pci_devsel_en_n
pci_stop_en_n
pci_perr_en_n
pci_par_en_n
pci_par64_en_n
pci_req64_en_n
pci_ack64_en_n
pci_req_out_n
pci_ad_out
pci_cbe_out_n
pci_frame_out_n
pci_irdy_out_n
pci_trdy_out_n
pci_devsel_out_n
pci_stop_out_n
pci_perr_out_n
pci_serr_out_n
pci_par_out
pci_par64_out
pci_req64_out_n
pci_ack64_out_n
Description
pci_ack64_en_n
Enable signal from the PCI compliant device to the ACK64# buffer.
pci_ack64_in_n
PCI Acknowledge 64-bit Transfer (ACK64#) input to the PCI compliant device.
pci_ack64_out_n
PCI Acknowledge 64-bit Transfer (ACK64#) output from the PCI Compliant Device.
pci_ad_en_n
400
Description
pci_ad_in
PCI multiplexed Address and Data (AD) bus input to the PCI compliant device,
minimum 32-bits wide (default), maximum 64-bits wide.
pci_ad_out
PCI multiplexed Address and Data (AD) bus output from the PCI compliant device,
minimum 32-bits wide (default), maximum 64-bits wide.
pci_cbe_en_n
Enable signal from the PCI compliant device to the C/BE# buffers.
pci_cbe_in_n
PCI multiplexed Bus Command and Byte Enables (C/BE#) bus input to the PCI
compliant device, minimum 4-bits wide (default), maximum 8-bits wide.
pci_cbe_out_n
PCI multiplexed Bus Command and Byte Enables (C/BE#) bus output from the PCI
compliant device, minimum 4-bits wide (default), maximum 8-bits wide.
pci_clk_in
pci_devsel_en_n
Enable signal from the PCI compliant device to the DEVSEL# buffer.
pci_devsel_in_n
pci_devsel_out_n
PCI Device Select (DEVSEL#) output from the PCI compliant device.
pci_frame_en_n
Enable signal from the PCI compliant device to the FRAME# buffer.
pci_frame_in_n
pci_frame_out_n
pci_gnt_in_n
pci_idsel_in
PCI Initialization Device Select (IDSEL) input to the PCI compliant device.
pci_irdy_en_n
Enable signal from the PCI compliant device to the IRDY# buffer.
pci_irdy_in_n
pci_irdy_out_n
PCI Initiator Ready (IRDY#) output from the PCI compliant device.
pci_lock_in_n
pci_par64_en_n
Enable signal from the PCI compliant device to the PAR64 buffer.
pci_par64_in
PCI Parity Upper DWORD (PAR64) input for pci_ad_in[63:32] and pci_cbe_in_n[7:4]
to the PCI compliant device.
pci_par64_out
pci_par_en_n
Enable signal from the PCI compliant device to the PAR buffer.
pci_par_in
PCI parity (PAR) input for pci_ad_in[31:0] and pci_cbe_in_n[3:0] to the PCI
compliant device.
pci_par_out
PCI parity (PAR) output for pci_ad_out[31:0] and pci_cbe_out_n[3:0] from the PCI
compliant device.
pci_perr_en_n
Enable signal from the PCI compliant device to the PERR# buffer.
pci_perr_in_n
pci_perr_out_n
PCI Parity Error (PERR#) output from the PCI compliant device.
pci_req64_en_n
Enable signal from the PCI compliant device to the REQ64# buffer.
pci_req64_in_n
PCI Request 64-bit Transfer (REQ64#) input to the PCI compliant device.
401
Description
pci_req64_out_n
PCI Request 64-bit Transfer (REQ64#) output from the PCI compliant device.
pci_req_out_n
pci_rst_in_n
pci_serr_out_n
PCI System Error (SERR#) output from the PCI compliant device
pci_stop_en_n
Enable signal from the PCI compliant device to the STOP# buffer.
pci_stop_in_n
pci_stop_out_n
pci_trdy_en_n
Enable signal from the PCI compliant device to the TRDY# buffer.
pci_trdy_in_n
pci_trdy_out_n
PCI Target Ready (TRDY#) output from the PCI compliant device.
Monitor Parameters
The parameters shown in Table 13-2 configure the PCI monitor.
Table 13-2. PCI Monitor Parameters
Order
Parameter
Default
Description
1.
Bit64Mode
2.
Constraints_Mode
3.
Parity_Error_Response
4.
Self_Config
Instantiation Example
Example 13-1 instantiates the PCI monitor inside a 64-bit capable PCI compliant device.
Constraints mode is not enabled.
402
1,
0) pci_mon
(pci_aden_n),
(pci_cbe_en_n),
(pci_frame_en_n),
(pci_irdy_en_n),
(pci_trdy_en_n),
(pci_devsel_en_n),
(pci_stop_en_n),
(pci_perr_en_n),
(pci_par_en_n),
(pci_par64_en_n),
(pci_req64_en_n),
(pci_ack64_en_n),
(pci_rst_in_n),
(pci_clk_in),
(pci_gnt_in_n),
(pci_idsel_in),
(pci_adin),
(pci_cbein_n),
(pci_frame_in_n),
(pci_irdy_in_n),
(pci_trdy_in_n),
(pci_devsel_in_n),
(pci_stop_in_n),
(pci_lock_in_n),
(pci_perr_in_n),
(pci_par_in),
(pci_par64_in),
(pci_req64_in_n),
(pci_ack64_in_n),
(pci_req_out_n),
(pci_adout),
(pci_cbeout_n),
(pci_frame_out_n),
(pci_irdy_out_n),
(pci_trdy_out_n),
(pci_devsel_out_n),
(pci_stop_out_n),
(pci_perr_out_n),
(pci_serr_out_n),
(pci_par_out),
(pci_par64_out),
(pci_req64_out_n),
(pci_ack64_out_n)
);
Monitor Checks
The checks defined for the PCI monitor are separated into the following classes:
403
Target checks
These classes correspond to the two submodules and the top-level module defined for the PCI
monitor.
404
Check ID and
Section Number
Violation
Description
MZ01
(*)
MZ02
(*)
MZ03
(*)
MZ04
(*)
MZ05
(*)
MZ06
(*)
MZ07_1, MZ07_2
(*)
MZ08
(3.2.2)
MZ09
(2.2.8 and 3.8)
Violation
Description
MZ10
(*)
MZ11
(3.8)
IUT always drives REQ64# only A master has to assert REQ64# only during
during memory transactions.
memory transactions. Interrupt Acknowledge and
Special Cycle commands are basically 32-bit
transactions and must not be used with REQ64#.
The bandwidth requirements for I/O and
Configuration Cycles cannot justify the added
complexity, and therefore, only memory
transactions support 64-bit data transfers.
MP02_1, MP02_2
(3.1.1)
MP03
(3.1.1)
MP06
(3.2.1)
MP07
(3.2.1)
MP08
(3.2.2)
MP09
(3.2.2)
MP11_1, MP11_2
(3.2.4)
405
406
Check ID and
Section Number
Violation
Description
MP12_1, MP12_2
(3.3.1)
MP14
(3.3.3.1)
MP15
(3.3.3.1)
MP16
(3.3.3.1)
MP17
(3.3.3.1)
MP18
(3.3.3.1)
MP20
(3.4.1)
MP23
(3.5.2)
MP27
(3.2.2.3.4)
Violation
Description
MP28_1, MP28_2
(3.7.1)
MP29_1
(3.7.1)
MP29_2
(3.7.1)
MP30
(3.7.4.1)
MP32
(3.9)
MP33
(3.9)
(*) Indicates check is not part of the Rev. 2.2 compliance list.
Target Checks
Table 13-4 lists the checks performed by the monitor submodule that verifies the operation of
the target.
Table 13-4. PCI Target Checks
Check ID and
Section Number
Violation
Description
TZ01
(*)
407
408
Check ID and
Section Number
Violation
Description
TZ02_1
TZ02_2
TZ03
(*)
TZ04
(*)
TZ05
(*)
TZ06
(*)
TZ07
(2.2.8 and 3.8)
TZ08
(3.8)
TZ09
(*)
TP02
Violation
Description
TP03
(3.1.1)
TP05
(3.2.1)
TP06
(3.2.1)
TP07
(3.2.1)
TP08
(3.2.1)
TP09
(3.2.1)
TP10
(3.2.1)
TP14
(3.2.2)
TP15
(3.2.2.3.4)
TP16
(3.2.2)
TP17_1, TP17_2
(3.2.4)
409
410
Check ID and
Section Number
Violation
Description
TP19
(3.3.1)
TP20
(3.3.3.2.1)
TP22
(3.3.3.2.1)
TP23
(3.3.3.2.1)
TP24
(3.3.3.2.1)
TP25
(3.3.3.2.1)
TP26
Violation
Description
TP29
(3.6.1 and 3.3.3.2)
Once DEVSEL# is asserted, it cannot be deasserted until the last data phase has completed,
except to signal Target-Abort. Target abort can
be signaled on any clock subsequent to the
assertion of DEVSEL#. Target-Abort is signaled
by de-asserting DEVSEL# and asserting STOP#
at the same time.
TP30
(3.6.2)
TP31_1, TP31_2
(3.7.1)
TP32_1
(3.7.1)
TP32_2
411
Violation
Description
IO10
(*)
IO11
(*)
IO12
(*)
IO21
(*)
IO22
(*)
IO23
(3.4.1)
MP22
(3.4.3)
412
Violation
Description
TP01_devsel,
TP01_trdy,
TP01_stop,
TP01_ack64MP01_frame,
MP01_irdy,
MP01_perr,
MP01_req64
(2.1)
IO_pci_ack64_en_n
pci_ack64_en_n is undriven.
IO_pci_ad_en_n
pci_ad_en_n is undriven.
IO_pci_cbe_en_n
pci_cbe_en_n is undriven.
IO_pci_devsel_en_n
pci_devsel_en_n is undriven.
IO_pci_frame_en_n
pci_frame_en_n is undriven.
IO_pci_irdy_en_n
pci_irdy_en_n is undriven.
IO_pci_par64_en_n
pci_par64_en_n is undriven.
IO_pci_par_en_n
pci_par_en_n is undriven.
IO_pci_perr_en_n
pci_perr_en_n is undriven.
IO_pci_req64_en_n
pci_req64_en_n is undriven.
IO_pci_stop_en_n
pci_stop_en_n is undriven.
IO_pci_trdy_en_n
pci_trdy_en_n is undriven.
413
Description
Read Transfers
Write Transfers
Special Cycles
Reserved Cycles
Address States
Retry States
Disconnect C States
Target Aborts
Master Aborts
Monitor Statistics
The statistics maintained by the PCI monitor are shown in Table 13-7. These statistics are
collected separately on the master and target controllers.
Table 13-7. PCI Monitor Statistics
414
Statistic
Description
Total Transfers
Unknown Commands
Chapter 14
PCI Express
Introduction
PCI Express is a high-performance, general purpose I/O interconnect defined for a wide variety
of future computing and communication platforms. It is a high-speed point-to-point, highly
scalable, serial interconnect. The PCI Express link consists of two signal groups, a transmit and
a receive.
The PHY Interface for the PCI Express architecture (PIPE) is an extension to the PCI Express
protocol, which defines the interface between the MAC Layer and PHY Layer of a PCI Express
compatible device.
The QVL PCI Express monitor can be instantiated in a standard configuration for checking PCI
Express implementations. It also can be instantiated in a PIPE configuration for checking PHY
Interface for PCI Express implementations. The monitor works in both Gen1 and Gen2 mode
and can be instantiated separately in both mode.
Reference Documentation
This PCI Express monitor is modeled from the requirements provided in the following
document:
PHY Interface for the PCI Express Architecture, Version 1.0, June 19, 2003.
PHY Interface for the PCI Express Architecture, Draft Version 1.87, September 28,
2006.
Supported Features
Lane Widths
Monitor supports lane widths of x1, x2, x4, x8, x12, x16, x32.
Packet Types
Monitor tracks transaction layer packet (TLP), data link layer packet (DLLP) and
physical layer packet (PLP) for proper encoding of various fields of the packets.
415
PCI Express
Supported Features
Monitor tracks the sequence number generated by the data link layer.
Monitor tracks address translation (AT) field of TLP packet in Gen2 mode.
Transaction Types
Monitor tracks all types of transactions, namely Memory, I/O, Configuration, and
Message.
The monitor treats trusted configuration request as deprecated request in Gen2 mode.
Data Integrity
Monitor supports data integrity checking for DLL packets (16-bit CRC).
Monitor supports end to end data integrity checking for TL packets (32-bit ECRC).
Flow Control
416
Monitor supports Link training and Initialization sequence in both Gen1 and Gen2
mode.
Monitor tracks the Training sequence ordered sets (TS1 and TS2).
PCI Express
Supported Features
Monitor tracks data rate and upconfigurabilty record in configuration complete state in
Gen2 mode.
Power Management
Monitor tracks power management protocol.
Lane-to-Lane Deskew
Monitor supports multilane deskew on the receive interface. The deskew must be in the order of
multiple of symbol times.
Implementations
Monitor can be instantiated in any of the following implementations:
Root complex.
Device or the component that is the root of an I/O hierarchy.
Switch.
Device or component that is a logical assembly of multiple virtual PCI-to-PCI bridge
device.
End points.
Device that can be a requestor or completer of PCI Express transaction. End points are
classified as either legacy or PCI Express end points.
PIPE
The monitor supports 8-bit and 16-bit PIPE.
417
PCI Express
Monitor Placement and Instantiation
Unsupported Features
This monitor does not track transaction ordering rules.
The monitor does not support FLR in Gen2 mode.
The monitor does not support all ACS violation scenarios.
418
PCI Express
Monitor Placement and Instantiation
reset
areset
Rx_interface
Tx_interface
rx_symbols_plus
rx_symbols_minus
rx_clk
tx_symbols_plus
tx_symbols_minus
tx_clk
skip_link_training
extended_sync_enable
device_control_register
device_capabilities_register
phy_layer_checks_disable
link_layer_checks_disable
transaction_layer_checks_disable
L0s_entry_supported
enable_vc_id
tc_mapped_to_vc_id_0
tc_mapped_to_vc_id_1
tc_mapped_to_vc_id_2
tc_mapped_to_vc_id_3
tc_mapped_to_vc_id_4
tc_mapped_to_vc_id_5
tc_mapped_to_vc_id_6
tc_mapped_to_vc_id_7
419
PCI Express
Monitor Placement and Instantiation
reset
areset
Rx_interface
Tx_interface
420
rx_symbols_plus
rx_symbols_minus
rx_clk
tx_symbols_plus
tx_symbols_minus
tx_clk
skip_link_training
extended_sync_enable
device_control_register
device_capabilities_register
phy_layer_checks_disable
link_layer_checks_disable
transaction_layer_checks_disable
L0s_entry_supported
acs_translation_blocking_enable
disable_cpl_timeout
enable_vc_id
tc_mapped_to_vc_id_0
tc_mapped_to_vc_id_1
tc_mapped_to_vc_id_2
tc_mapped_to_vc_id_3
tc_mapped_to_vc_id_4
tc_mapped_to_vc_id_5
tc_mapped_to_vc_id_6
tc_mapped_to_vc_id_7
PCI Express
Monitor Placement and Instantiation
Monitor Connectivity
Connect the PCI Express monitor pins as specified in the pin-out Table 14-1 and illustrated in
Figure 14-3.
Figure 14-3. PCI Express Monitor Pin Diagram
reset
areset
rx_symbols_plus
rx_symbols_minus
rx_clk
Receiver
tx_symbols_plus
tx_symbols_minus
tx_clk
Transmitter
skip_link_training
extended_sync_enable
device_control_register
device_capabilities_register
phy_layer_checks_disable
link_layer_checks_disable
transaction_layer_checks_disable
L0s_entry_supported
acs_translation_blocking_enable
disable_cpl_timeout
enable_vc_id
tc_mapped_to_vc_id_0
tc_mapped_to_vc_id_1
tc_mapped_to_vc_id_2
tc_mapped_to_vc_id_3
tc_mapped_to_vc_id_4
tc_mapped_to_vc_id_5
tc_mapped_to_vc_id_6
tc_mapped_to_vc_id_7
Description
areset
Asynchronous reset, active high. This is not a part of the PCI Express interface.
device_capabilities_register
(32 bits)
device_control_register
(16 bits)
Device control register offset 08h. If this configuration data is not available,
then wire 16'b0 to this port in which case the monitor is configured for a 5-bit
tag field and maximum payload size of 128-bytes (Connectivity Note 1).
enable_vc_id [7:0]
Bit positions of this input correspond to virtual channel numbers. Set the bit
corresponding to the virtual channel number supported in the design, along
with the VC_SUPPORT parameter and the tc_mapped_to_vc_id_n inputs.
This input can be left unconnected if the parameter VC_SUPPORT is 0 or 1.
extended_sync_enable
Extended sync bit of Link Control Register offset 10h. When set, configures
the monitor to track maximum of 4096 FTS sequences. By default, the monitor
tracks 255 FTS sequences.
L0s_entry_supported
When set, indicates that the entry in to L0s ASPM state is supported.
421
PCI Express
Monitor Placement and Instantiation
Description
link_layer_checks_disable
When set, disables all the data link layer checks performed by the monitor.
phy_layer_checks_disable
When set, disables all the physical layer checks performed by the monitor.
reset
Synchronous reset, active high. This is not a part of the PCI Express interface.
rx_clk
Receive clock. This clock is used by the receiver to sample the symbols on the
lane. The clock is active on the posedge or on both edges based on the mode of
operation.
rx_symbols_minus
Inputs to the PCI Express device. In serial mode of operation, this should be
connected to the D- inputs of the device.
rx_symbols_plus
Inputs to the PCI Express device. In serial mode of operation, this should be
connected to D+ inputs of the device. In symbol mode of operation, this should
be connected to 10B encoded symbols.
skip_link_training
When set, link width negotiation is not tracked and the operating link width is
set to maximum link width for which the monitor is configured. Wire this port
to 1'b0 if link width negotiation needs to be tracked. The default link training
state of the monitor is POLLING. Monitor does not perform any receiver
detection. When link training and width negotiation is not tracked, the monitor
expects few TS1/TS2 ordered sets to be in sync and to register the n_fts values.
tc_mapped_to_vc_id_0 [7:0]
Configures the TCs mapped to VC0. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_1 [7:0]
Configures the TCs mapped to VC1. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_2 [7:0]
Configures the TCs mapped to VC2. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_3 [7:0]
Configures the TCs mapped to VC3. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_4 [7:0]
Configures the TCs mapped to VC4. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_5 [7:0]
Configures the TCs mapped to VC5. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_6 [7:0]
Configures the TCs mapped to VC6. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_7 [7:0]
Configures the TCs mapped to VC7. Bit locations within this field corresponds
to TC values.
transaction_layer_checks_
disable
When set, disables all the transaction layer checks performed by the monitor.
tx_clk
Transmit clock. This clock is used by the transmitter to drive the symbols on
the lane. The clock is active on the posedge or on both edges based on the
mode of operation.
tx_symbols_minus
Outputs from the PCI Express device. In serial mode of operation, this should
be connected to the D- outputs of the device.
422
PCI Express
Monitor Placement and Instantiation
Description
tx_symbols_plus
Outputs from the PCI Express device. In serial mode of operation, this should
be connected to D+ outputs of the device. In symbol mode of operation, this
should be connected to the 10B encoded symbols.
acs_translation_blocking_enable
When set, enables the acs translation blocking enable bit in configuration
space. This bit is applicable for Gen2 mode.
disable_cpl_timeout
When set, disables the completion timeout mechanism of monitor. this bit is
applicable for Gen2 mode.
Connectivity Notes
1. Implementation under tests device control configuration register must be connected to
the monitor. The monitor is reconfigured depending on the value in
device_control_register. If this configuration data is not available, then pass 16'b0
to this port. The monitor requires Max_Payload_Size
(device_control_register[7:5]), Max_Read_Request_Size
(device_control_register[14:12]), and Extended_Tag_Field_Enable
(device_control_register[8]) fields of this register.
The encoding for the Max_Payload_Size and Max_Read_Request_Size fields is as
follows:
000b
001b
010b
011b
100b
101b
110b
111b
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Reserved
Reserved
When the Extended_Tag_Field_Enable bit is set, an 8-bit tag field is used. If the bit
is cleared, then a 5-bit tag field is used.
2. In symbol mode of operation, the encoded 10B symbols should be connected to the
monitor as shown below.
tx_symbols_plus [9:0] = {j,h,g,f,i,e,d,c,b,a}
where bit a is the LSB of the symbol and bit j is the MSB of the symbol.
3. The reset and areset inputs are not part of the PCI Express interface. Connect
reset/areset of the implementation under test (IUT) to the monitor. The
reset/areset must be asserted for at least one clock during initial time before the link
training starts.
4. When the skip_link_training option is set, the monitor expects a few TS-ordered
sets to be transmitted and received to be in sync and to register the n_FTS values.
423
PCI Express
Monitor Placement and Instantiation
Monitor Parameters
The parameters shown in Table 14-2 configure the PCI Express monitor.
Table 14-2. PCI Express Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
PCI_EXPRESS_DEVICE_
TYPE
3.
INTERFACE_TYPE
4.
MAX_LINK_WIDTH
5.
DOUBLE_DATA_RATE
6.
MAX_REQUESTS_ADDR_
WIDTH
424
PCI Express
Monitor Placement and Instantiation
Default Description
7.
ELECTRICAL_IDLE_VAL
8.
RESERVED_FIELD_
CHECK_ENABLE
9.
VENDOR_SPECIFIC_
ENCODING_ENABLE
10.
OVERRIDE_TIMER_VALUE
11.
REPLAY_TIMER_VALUE
711
12.
ACKNAK_TIMER_VALUE
237
13.
MIN_TS1_COUNT
1024
14.
DESKEW_SUPPORT
425
PCI Express
Monitor Placement and Instantiation
Default Description
15.
VC_SUPPORT
16.
HOT_PLUG_MESSAGE_
ENABLE
17.
TX_SKEW_SUPPORT
18.
ENABLE_DATA_PLUS_
MINUS_CHECK
19
CPL_TIMEOUT_CLK
30000
20
UPDATE_FC_30US_TIMER_
CLK
75000
/7500
426
PCI Express
Monitor Placement and Instantiation
Instantiation Examples
Example 1
Example 14-1 instantiates a PCI Express monitor within a PCI Express end point device. The
input to the device is serial 10B symbols. The maximum link width is set to 1. Reserved-bit
field checking is disabled. The maximum number of requests that can be outstanding is 32. The
device uses a 5-bit tag field. The maximum pay load size and maximum read request size are set
to 128 bytes. The example supports only VC0.
Example 14-1. PCI Express Monitor Instantiation Example 1
qvl_pci_express_monitor
#( /* Constraints_Mode */
0,
/* PCI_EXPRESS_DEVICE_TYPE */
0,
/* INTERFACE_TYPE */
0,
/* MAX_LINK_WIDTH */
1,
/* DOUBLE_DATA_RATE */
0,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* ELECTRICAL_IDLE_VAL */
0,
/* RESERVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */0)
MONITOR_END_POINT(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data_plus),
.tx_symbols_minus
(tx_data_minus),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data_plus),
.rx_symbols_minus
(rx_data_minus),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b0),
.device_control_register
(16'b0),
427
PCI Express
Monitor Placement and Instantiation
.device_capabilities_register
.phy_layer_checks_disable
.link_layer_checks_disable
.transaction_layer_checks_disable
(32'h5),
(1'b0),
(1'b0),
(1'b0) );
Example 2
Example 14-2 instantiates a PCI Express monitor within a Legacy end point device. The input
to the device is parallel 10B symbols. The maximum link width is set to 8. The clocks are active
on both the edges. Reserved-bit field checking is disabled. The maximum number of requests
that can be outstanding is 32. The device uses a 5-bit tag field. The maximum pay load size and
maximum read request size are set to 128 bytes. The maximum number of FTS sequences is set
to 4096. This example supports only VC0.
Example 14-2. PCI Express Monitor Instantiation Example 2
qvl_pci_express_monitor
#( /* Constraints_Mode */
0,
/* PCI_EXPRESS_DEVICE_TYPE */
1,
/* INTERFACE_TYPE */
1,
/* MAX_LINK_WIDTH */
8,
/* DOUBLE_DATA_RATE */
1,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* ELECTRICAL_IDLE_VAL */
0,
/* RESRVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */0)
MONITOR_END_POINT(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data),
.tx_symbols_minus
(tx_data),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data),
.rx_symbols_minus
(rx_data),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b1),
.device_control_register
(16'b0),
.device_capabilities_register
(32'h5),
.phy_layer_checks_disable
(1'b0),
.link_layer_checks_disable
(1'b0),
.transaction_layer_checks_disable(1'b0));
Example 3
Example 14-3 instantiates a PCI Express Gen2 monitor within a Root Complex device. The
input to the device is parallel 10B symbols. The maximum link width is set to 16. The clocks are
active on both the edges. Reserved-bit field checking is enabled. The maximum number of
requests that can be outstanding is 32. The device uses a 5-bit tag field. The maximum pay load
size and maximum read request size are set to 128 bytes. The maximum number of FTS
428
PCI Express
Monitor Placement and Instantiation
sequences is set to 4096. This example supports only VC0. Completion timeout value is 40000
clk.
Example 14-3. PCI Express Gen2 Monitor Instantiation Example 3
qvl_pci_express_gen2_monitor
#( /* Constraints_Mode */
0,
/* PCI_EXPRESS_DEVICE_TYPE */
4,
/* INTERFACE_TYPE */
1,
/* MAX_LINK_WIDTH */
16,
/* DOUBLE_DATA_RATE */
1,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* ELECTRICAL_IDLE_VAL */
0,
/* RESRVED_FIELD_CHECK_ENABLE */
1,
/* VENDOR_SPECIFIC_ENCOING_ENABLE */0,
/* OVERRIDE_TIMER_VALUE */
0,
/* REPLAY_TIMER_VALUE */
711,
/* ACK_NAK_TIMER_VALUE */
237,
/* MIN_TS1_COUNT */
16,
/* DESKEW_SUPPORT */
0,
/* VC_SUPPORT */
0,
/* HOT_PLUG_MESSAGE_ENABLE */
0,
/* TX_SKEW_SUPPORT */
0,
/* ENABLE_DATA_PLUS_MINUS_CHECK */ 0,
/* CPL_TIMEOUT_CLK */
40000)
MONITOR_ROOT_COMPLEX(
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_symbols_plus
(tx_data),
.tx_symbols_minus
(tx_data),
.rx_clk
(rx_clk),
.rx_symbols_plus
(rx_data),
.rx_symbols_minus
(rx_data),
.acs_translation_blocking_enable (1b0),
.disable_cpl_timeout
(1b0),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b1),
.device_control_register
(16'b0),
.device_capabilities_register
(32'h5),
.phy_layer_checks_disable
(1'b0),
.link_layer_checks_disable
(1'b0),
.transaction_layer_checks_disable(1'b0));
PIPE Configuration
To use the QVL PIPE monitor, place an instance of the monitor inside the PHY Layer or MAC
Layer of a root complex (RC) device, a PCI Express end point, a legacy end point, an upstream
port of the PCI Express switch or a downstream port of the PCI Express switch as shown in
Figure 14-4 on page 430.
The PIPE monitor can be instantiated in either 8-bit mode or 16-bit mode. You can include
instances of a PIPE monitor in a checker control file. The term upstream refers to an interface
Questa Verification Library Monitors Data Book, v2010.2
429
PCI Express
Monitor Placement and Instantiation
nearer to the root complex (RC). The term downstream refers to an interface farther from the
root complex (RC).
The PIPE monitor can be instantiated in either Gen1 mode or Gen2 mode. In Gen1 mode
monitor is compatible with PCI Express Base Specification 1.1. In this mode all Gen2 features
are disabled. In Gen2 mode monitor is compatible with PCI Express Base Specification 2.0. In
this mode, all Gen1 features which are not part of 2.0 specification are disabled. The monitor is
having two separate top file for Gen1 and Gen2. This allows two PIPE monitors to be
instantiated in an environment where both Gen1 and Gen2 buses are present.
Figure 14-4. Gen1 PIPE Monitor Implementation
PHY/MAC Interface
TxData 16 or 8 bits
PHY Layer Device
16 or 8 bits RxData
PIPE
Monitor
2 or 1 bit RxDataK
6 Bits Status
PCLK
16 or 8 bits RxData
PIPE
Monitor
2 or 1 bit RxDataK
12 Bits Status
PCLK
430
PCI Express
Monitor Placement and Instantiation
PIPE
Monitor
disable_descrambler
skip_link_training
extended_sync_enable
device_control_register
device_capabilities_register
phy_layer_checks_disable
link_layer_checks_disable
transaction_layer_checks_disable
L0s_entry_supported
acs_translation_blocking_enable
disable_cpl_timeout
enable_vc_id
tc_mapped_to_vc_id_0
tc_mapped_to_vc_id_1
tc_mapped_to_vc_id_2
tc_mapped_to_vc_id_3
tc_mapped_to_vc_id_4
tc_mapped_to_vc_id_5
tc_mapped_to_vc_id_6
tc_mapped_to_vc_id_7
Description
areset_n
device_capabilities_register
(32 bits)
device_control_register
(16 bits)
Device control register - offset 08h. If this configuration data is not available,
then wire 16'b0 to this port in which case the monitor is configured for a 5-bit
tag field and maximum pay load and maximum read request size of 128 bytes
(Connectivity Note 1).
disable_descrambler
enable_vc_id [7:0]
Bit positions of this input corresponds to virtual channel numbers. Set the bit
corresponding to the virtual channel number supported in the design along
with the VC_SUPPORT parameter and tc_mapped_to_vc_id_x inputs. This
input can be left unconnected if parameter VC_SUPPORT = 0 or 1.
431
PCI Express
Monitor Placement and Instantiation
Description
extended_sync_enable
Extended sync bit of Link Control Register - offset 10h. When set, configures
the monitor to track maximum of 4096 FTS sequences. By default, the monitor
tracks 255 FTS sequences.
L0s_entry_supported
When set, indicates that the entry in to L0s ASPM state is supported.
link_layer_checks_disable
When set, disables all the data link layer checks performed by the monitor.
pclk
Clock output from the PHY layer device. The data on the PIPE interface is
synchronous to this clock. The clock operates at 125 Mhz for the 16-bit
interface and 250 Mhz for the 8-bit interface.
phy_layer_checks_disable
When set, disables all the physical layer checks performed by the monitor.
phystatus
Output from the PHY Layer device. Indicates the completion of several PHY
functions such as power management state transition, receiver detection, etc.
power_down
Input to the PHY Layer device. Indicates when to power down or power up the
transceiver.
reset_n
rx_data
Parallel PCI Express data output from the PHY layer device. The data bus
width can be 8-bits or 16-bits based on the mode of operation.
rx_data_k
Data/Control output for the symbols on rx_data bus. The width of this output is
1-bit if rx_data is 8-bits wide and 2-bits if rx_data output is 16-bits wide.
rx_elecidle
Output from the PHY Layer device. Indicates that the receiver has detected
electrical idle.
rx_polarity
rx_status
Output from the PHY Layer device. Encodes the receiver status and error.
rx_valid
Output from the PHY Layer device. Indicates symbol_lock and valid data on
rx_data and rx_data_k.
skip_link_training
When set, link width negotiation is not tracked and the operating link width is
set to the maximum link width for which the monitor is configured. Wire this
port to 1'b0 if the link width negotiation needs to be tracked. The default link
training state of the monitor is POLLING. Monitor does not perform any
receiver detection. When link training and width negotiation is not tracked, the
monitor expects few TS1/TS2 ordered sets to be in sync and to register n_FTS.
tc_mapped_to_vc_id_0 [7:0]
Configures the TCs mapped to VC0. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_1 [7:0]
Configures the TCs mapped to VC1. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_2 [7:0]
Configures the TCs mapped to VC2. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_3 [7:0]
Configures the TCs mapped to VC3. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_4 [7:0]
Configures the TCs mapped to VC4. Bit locations within this field corresponds
to TC values.
432
PCI Express
Monitor Placement and Instantiation
Description
tc_mapped_to_vc_id_5 [7:0]
Configures the TCs mapped to VC5. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_6 [7:0]
Configures the TCs mapped to VC6. Bit locations within this field corresponds
to TC values.
tc_mapped_to_vc_id_7 [7:0]
Configures the TCs mapped to VC7. Bit locations within this field corresponds
to TC values.
acs_translation_blocking_enable
When set, enables the acs translation blocking enable bit in the configuration
space. This bit is applicable for Gen2 mode.
disable_cpl_timeout
When set, disables the completion timeout mechanism of monitor. This bit is
applicable for Gen2 mode.
transaction_layer_checks_
disable
When set, disables all the transaction layer checks performed by the monitor.
tx_compliance
Input to the PHY Layer device. Indicates when to drive compliance pattern.
tx_data
Parallel PCI Express data input to the PHY layer device. The data bus width
can be 8-bits or 16-bits based on the mode of operation.
tx_data_k
Data/Control input for the symbols on tx_data bus. The width of this input is
1-bit if tx_data input is 8-bits wide and 2-bits if tx_data input is 16-bits wide.
tx_detect_rx_loopback
Input to the PHY Layer device that indicates when to start receiver detection or
loopback.
tx_elecidle
Input to the PHY Layer device. Indicates when to drive electrical idle.
rate
Input to PHY Layer device indicates current speed of operation. This bit is
applicable for Gen2 mode.
tx_margin
Input to PHY Layer device. Indicates transmitter voltage level. This bit is
applicable for Gen2 mode.
tx_deemph
tx_swing
Input to PHY Layer device. Indicates transmitter voltage swing level. This bit
is applicable for Gen2 mode.
433
PCI Express
Monitor Placement and Instantiation
128 Bytes
256 Bytes
512 Bytes
1024 Bytes
2048 Bytes
4096 Bytes
Reserved
Reserved
When the Extended_Tag_Field_Enable bit is set, an 8-bit tag field is used. If the bit
is cleared, then a 5-bit tag field is used.
2. The reset_n and areset_n inputs are not part of the PCI Express interface. Connect
reset_n/areset_n or RESET# of the implementation under test (IUT) to the monitor.
The reset_n/areset_n must be asserted for at least one clock during initial time
before the link training starts.
3. When the skip_link_training option is set, the monitor expects a few TS-ordered
sets to be transmitted and received to be in sync and to register the n_FTS values.
4. The tc_mapped_to_vc_id_n ports can be left unconnected if the configuration
parameter VC_SUPPORT is 0 or 1.
5. 9-Bit Interface Mode:
Connect tx_elecidle and rx_elecidle so that port bits are asserted when
electrical idle is detected on Tx/Rx.
You can assert rx_valid port bits whenever valid 8b data are received.
434
PCI Express
Monitor Placement and Instantiation
Default Description
1.
Constraints_Mode
2.
PCI_EXPRESS_DEVICE_
TYPE
3.
MAC_LAYER_SIDE
4.
INTERFACE_TYPE
5.
MAX_LINK_WIDTH
6.
MAX_REQUESTS_ADDR_
WIDTH
7.
RESERVED_FIELD_
CHECK_ENABLE
8.
VENDOR_SPECIFIC_
ENCODING_ENABLE
435
PCI Express
Monitor Placement and Instantiation
436
Order Parameter
Default Description
9.
OVERRIDE_TIMER_VALUE
10.
REPLAY_TIMER_VALUE
711
11.
ACKNAK_TIMER_VALUE
237
12.
MIN_TS1_COUNT
1024
13.
DESKEW_SUPPORT
14.
VC_SUPPORT
15.
HOT_PLUG_MESSAGE_
ENABLE
16.
TX_SKEW_SUPPORT
17
CPL_TIMEOUT_CLK
30000
PCI Express
Monitor Placement and Instantiation
Default Description
18
7500
/3750
UPDATE_FC_30US_TIMER_
CLK
Notes:
1. The parameters must be specified in the above order.
2. The width of ports tx_data and rx_data is n*8-bits (n is the number of lanes on the
link, MAX_LINK_WIDTH) if the monitor is configured to track the 8-bit PIPE interface of
a multiple lane link. The width is n*16-bits if the monitor is configured to track the 16bit PIPE interface of a multilane PIPE. The allowed values of n are 1, 2, 4, 8, 12, 16, and
32.
Example: The width is 64-bits if the monitor is configured to track the 8-bit PIPE
interface and 128-bits if the monitor is configured to track the 16-bit PIPE interface for
n=8 (i.e., x8 link).
3. The width of ports tx_data_k and rx_data_k is n bits (n is the maximum number of
lanes supported by the device, MAX_LINK_WIDTH) if the monitor is configured to track
the 8-bit PIPE interface. The width is 2*n bits if the monitor is configured to track the
16-bit PIPE interface of a multilane PIPE.
4. The width of ports tx_elecidle, tx_compliance, rx_polarity, rx_valid, and
rx_elecidle is n bits (n is the maximum number of lanes supported by the device,
MAX_LINK_WIDTH) if the monitor is configured to track a multilane PIPE.
5. The width of ports rate, tx_deemph, and tx_swing is 1-bit in Gen2 mode.
6. The width of port tx_margin is 3 bits in Gen2 mode.
7. The width of port rx_status is 3*n bits (n is the maximum number of lanes supported
by the device, MAX_LINK_WIDTH) if the monitor is configured to track a multilane PIPE.
8. If the monitor is configured to track a multilane PIPE, then the per-lane signals should
be concatenated and connected to the respective monitor ports (see the following
classification of signals).
Shared signals
pclk
tx_detect_rx_ loopback
power_down [1:0]
phystatus
rate(Gen2 only)
tx_margin(Gen2 only)
tx_deemph(Gen2 only)
tx_swing(Gen2 only)
Per-lane Signals
(tx_data, tx_data_k)
(rx_data, rx_data_k)
(tx_elecidle)
(tx_compliance, rx_polarity, rx_valid,
rx_elecidle, rx_status[2:0])
437
PCI Express
Monitor Placement and Instantiation
438
PCI Express
Monitor Placement and Instantiation
.phystatus
(PhyStatus),
.disable_descrambler
(1'b0),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b0),
.device_control_register
(16'b0),
.device_capabilities_register
(32'h5),
.phy_layer_checks_disable
(1'b0),
.link_layer_checks_disable
(1'b0),
.transaction_layer_checks_disable (1'b0) );
Example 2
Example 14-5 instantiates the PIPE monitor within an end point component. The monitor is
instantiated on the PHY Layer side of the multilane PIPE interface. The input to the device is
parallel 8-bit symbols. The maximum link width is set to 2. Reserved-bit field checking is
disabled. The maximum number of requests that can be outstanding is 32. The device uses 5-bit
tag field. The maximum pay load size and maximum read request size are set to 128 bytes.
Supports only VC0.
Example 14-5. PIPE Monitor Instantiation
qvl_pci_express_pipe_monitor
#( /* Constraints_Mode */
0,
/* PCI_EXPRESS_DEVICE_TYPE */
0,
/* MAC_LAYER_SIDE */
0,
/* INTERFACE_TYPE */
0,
/* MAX_LINK_WIDTH */
2,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* RESERVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE * 0)
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK),
.tx_data
({TxData_ln1, TxData_ln0}),
.tx_data_k
({TxDataK_ln1, TxDataK_ln0}),
.tx_detect_rx_loopback
(TxDetectRx/Loopback),
.tx_elecidle
({TxElecidle_ln1,
TxElecidle_ln0}),
.tx_compliance
({TxCompliance_ln1,
TxCompliance_ln0}),
.rx_polarity
({RxPolarity_ln1,
RxPolarity_ln0}),
.power_down
(Power_Down[1:0]),
.rx_data
({RxData_ln1, RxData_ln0}),
.rx_data_k
({RxDataK_ln1, RxDataK_ln0}),
.rx_valid
({RxValid_ln1, RxValid_ln0}),
.rx_elecidle
({RxElecidle_ln1,
RxElecidle_ln0}),
.rx_status
({RxStatus_ln1,
RxStatus_ln0}),
.phystatus
(PhyStatus),
.disable_descrambler
(1'b0),
.skip_link_training
(1'b0),
439
PCI Express
Monitor Placement and Instantiation
.extended_sync_enable
(1'b0),
.device_control_register
(16'b0),
.device_capabilities_register
(32'h5),
.phy_layer_checks_disable
(1'b0),
.link_layer_checks_disable
(1'b0),
.transaction_layer_checks_disable (1'b0) );
Note that when instantiating the monitor in a multilane PIPE interface, the per-lane signals
should be concatenated and connected to the monitor as shown in the example.
440
PCI Express
Monitor Placement and Instantiation
Example 3
Example 14-7 instantiates the Gen2 PIPE monitor within an end point component. The monitor
is instantiated on the PHY Layer side of the multilane PIPE interface. The input to the device is
parallel 8-bit symbols. The maximum link width is set to 2. Reserved-bit field checking is
disabled. The maximum number of requests that can be outstanding is 32. The device uses 5-bit
tag field. The maximum pay load size and maximum read request size are set to 128 bytes.
Supports only VC0.
Example 14-7. PIPE Monitor Instantiation
qvl_pci_express_gen2_pipe_monitor
#( /* Constraints_Mode */
0,
/* PCI_EXPRESS_DEVICE_TYPE */
0,
/* MAC_LAYER_SIDE */
0,
/* INTERFACE_TYPE */
0,
/* MAX_LINK_WIDTH */
2,
/* MAX_REQUESTS_ADDR_WIDTH */
5,
/* RESERVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_ENCOING_ENABLE * 0)
MONITOR_PIPE(
.areset_n
(RESET#),
.reset_n
(1'b1),
.pclk
(PCLK),
.tx_data
({TxData_ln1, TxData_ln0}),
.tx_data_k
({TxDataK_ln1, TxDataK_ln0}),
.tx_detect_rx_loopback
(TxDetectRx/Loopback),
.tx_elecidle
({TxElecidle_ln1,
TxElecidle_ln0}),
.tx_compliance
({TxCompliance_ln1,
TxCompliance_ln0}),
.rx_polarity
({RxPolarity_ln1,
RxPolarity_ln0}),
.power_down
(Power_Down[1:0]),
.rate
(rate),
.tx_margin
(tx_margin),
.tx_deemph
(tx_deemph),
.tx_swing
(tx_swing),
.rx_data
({RxData_ln1, RxData_ln0}),
.rx_data_k
({RxDataK_ln1, RxDataK_ln0}),
.rx_valid
({RxValid_ln1, RxValid_ln0}),
.rx_elecidle
({RxElecidle_ln1,
RxElecidle_ln0}),
.rx_status
({RxStatus_ln1,
RxStatus_ln0}),
.phystatus
(PhyStatus),
.disable_descrambler
(1'b0),
.skip_link_training
(1'b0),
.extended_sync_enable
(1'b0),
.device_control_register
(16'b0),
.device_capabilities_register
(32'h5),
.phy_layer_checks_disable
(1'b0),
.link_layer_checks_disable
(1'b0),
441
PCI Express
Monitor Checks
.transaction_layer_checks_disable (1'b0) );
Note that when instantiating the monitor in a multilane PIPE interface, the per-lane signals
should be concatenated and connected to the monitor as shown in the example.
Monitor Checks
The checks performed by the PCI Express monitor are classified as follows:
Note that all checks are performed in both transmit and receive directions.
Violation
Description
PCI_EXPRESS_10B_CODING_
VIOLATION_P
PCI_EXPRESS_10B_CODING_
VIOLATION_N
PCI_EXPRESS_COM_IN_
DLLP_TLP_P
PCI_EXPRESS_COM_IN_
DLLP_TLP_N
442
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_DATA_PLUS_
MINUS_ERROR_P
PCI_EXPRESS_DATA_PLUS_
MINUS_ERROR_N
Sub-blocks encoded as
6'b000111 should be
generated only when the
running disparity at the
beginning of the sub-block is
positive.
Sub-blocks encoded as
4'b0011 should be generated
only when the running
disparity at the beginning of
the sub-block is positive.
Sub-blocks encoded as
4'b1100 should be generated
only when the running
disparity at the beginning of
the sub-block is negative.
Sub-blocks encoded as
6'b111000 should be
generated only when the
running disparity at the
beginning of the sub-block is
negative.
443
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_EDB_
WITHOUT_STP_P
PCI_EXPRESS_FTS_COUNT_
ERROR_N
PCI_EXPRESS_FTS_IN_
DLLP_TLP_P
PCI_EXPRESS_EDB_
WITHOUT_STP_N
PCI_EXPRESS_EIDLE_NOT_
DETECTED_P
PCI_EXPRESS_EIDLE_NOT_
DETECTED_N
PCI_EXPRESS_END_OF_PKT_
ERROR_P
PCI_EXPRESS_END_OF_PKT_
ERROR_N
PCI_EXPRESS_END_
WITHOUT_STP_SDP_P
PCI_EXPRESS_END_
WITHOUT_STP_SDP_N
PCI_EXPRESS_FTS_COUNT_
ERROR_P
PCI_EXPRESS_FTS_IN_
DLLP_TLP_N
PCI_EXPRESS_FTS_NOT_
PART_OF_FTS_OS_P
PCI_EXPRESS_FTS_NOT_
PART_OF_FTS_OS_N
PCI_EXPRESS_FTS_
ORDERED_SET_ERROR_P
PCI_EXPRESS_FTS_
ORDERED_SET_ERROR_N
444
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_IDL_IN_
DLLP_TLP_P
ELECTRICAL IDLE
ordered set error on this lane
of the TX/RX interface.
PCI_EXPRESS_IDL_IN_
DLLP_TLP_N
PCI_EXPRESS_IDL_NOT_
PART_OF_EIDL_OS_P
PCI_EXPRESS_IDL_NOT_
PART_OF_EIDL_OS_N
PCI_EXPRESS_IDLE_
ORDERED_SET_ERROR_P
PCI_EXPRESS_IDLE_
ORDERED_SET_ERROR_N
PCI_EXPRESS_ILLEGAL_
ASSIGNED_LANE_NUMBER_
P
PCI_EXPRESS_ILLEGAL_
ASSIGNED_LANE_NUMBER_
N
445
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_ILLEGAL_
SYMBOL_FOLLOWING_
COM_SYMBOL_P
PCI_EXPRESS_ILLEGAL_
SYMBOL_FOLLOWING_
COM_SYMBOL_N
PCI_EXPRESS_ILLEGAL_TS_
IDENTIFIER_P
PCI_EXPRESS_ILLEGAL_TS_
IDENTIFIER_N
PCI_EXPRESS_INVALID_
CODE_IN_DLLP_TLP_P
PCI_EXPRESS_INVALID_
CODE_IN_DLLP_TLP_N
PCI_EXPRESS_MORE_
THAN_ONE_SDP_P
Invalid 10B codes should not Invalid 10B codes should not be detected in
be part of the DLL or TL
a TL or DLL packet. This check fires if an
packet.
invalid 10B code is detected in a TL or DLL
packet.
There should not be more
than one SDP symbol in a
symbol time.
PCI_EXPRESS_MORE_
THAN_ONE_SDP_N
PCI_EXPRESS_MORE_
THAN_ONE_STP_P
PCI_EXPRESS_MORE_
THAN_ONE_STP_N
PCI_EXPRESS_NO_IDLE_
DATA_P
PCI_EXPRESS_NO_IDLE_
DATA_N
PCI_EXPRESS_NO_STP_
SDP_LANE0_P
PCI_EXPRESS_NO_STP_
SDP_LANE0_N
PCI_EXPRESS_PAD_IN_
DLLP_TLP_P
PCI_EXPRESS_PAD_IN_
DLLP_TLP_N
446
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_PAD_WHEN_
LINK_WIDTH_1_2_4_P
PCI_EXPRESS_PAD_WHEN_
LINK_WIDTH_1_2_4_N
PCI_EXPRESS_PADDING_
ERROR_P
PCI_EXPRESS_PADDING_
ERROR_N
PCI_EXPRESS_RESERVED_
K_CODE_P
PCI_EXPRESS_RESERVED_
K_CODE_N
PCI_EXPRESS_SDP_NOT_
FOLLOWED_BY_END_P
PCI_EXPRESS_SDP_NOT_
FOLLOWED_BY_END_N
PCI_EXPRESS_SDP_STP_ON_
INCORRECT_LANES_P
PCI_EXPRESS_SDP_STP_ON_
INCORRECT_LANES_N
PCI_EXPRESS_SKP_NOT_
PART_OF_SKP_OS_P
PCI_EXPRESS_SKP_NOT_
PART_OF_SKP_OS_N
PCI_EXPRESS_SKP_OS_NOT_
RECEIVED_P
PCI_EXPRESS_SKP_OS_NOT_
RECEIVED_N
PCI_EXPRESS_SKP_OS_NOT_
XMTD_P
SKP ordered sets should be The maximum interval between two skip
received within 5664 symbol ordered sets can be 5664 symbols. This
times.
check fires if the interval between two skip
ordered sets exceeds the above specified
number of symbol times.
SKP ordered sets should be
scheduled once every 1180
to 1538 symbol times.
PCI_EXPRESS_SKP_OS_NOT_
XMTD_N
447
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR_P
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR_N
PCI_EXPRESS_SKP_
WITHIN_N_FTS_P
PCI_EXPRESS_SKP_
WITHIN_N_FTS_N
PCI_EXPRESS_SPL_
RESERVED_SYMBOLS_IN_
DLLP_TLP_P
PCI_EXPRESS_SPL_
RESERVED_SYMBOLS_IN_
DLLP_TLP_N
PCI_EXPRESS_STP_NOT_
FOLLOWED_BY_END_EDB_P
PCI_EXPRESS_STP_NOT_
FOLLOWED_BY_END_EDB_N
PCI_EXPRESS_TLP_WHEN_
LINK_DOWN_P
PCI_EXPRESS_TLP_WHEN_
LINK_DOWN_
PCI_EXPRESS_TS1_
ORDERED_SET_ERROR_P
PCI_EXPRESS_TS1_
ORDERED_SET_ERROR_N
PCI_EXPRESS_TS2_
ORDERED_SET_ERROR_P
PCI_EXPRESS_TS2_
ORDERED_SET_ERROR_N
PCI_EXPRESS_TTX_IDLE_
MIN_VIOLATION_P
PCI_EXPRESS_TTX_IDLE_
MIN_VIOLATION_N
448
PCI Express
Monitor Checks
Notes:
1. Checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
2. Checkers with a _TX_P or _TX_N suffix are performed in the transmit direction and
checkers with a _RX_P or _RX_N suffix are performed in the receive direction. All
other checks are performed in both directions.
Violation
Description
PCI_EXPRESS_CHANGE_IN_
LINK_WIDTH_TX_P
PCI_EXPRESS_CHANGE_IN_
LINK_WIDTH_TX_N
PCI_EXPRESS_CHANGE_IN_
LINK_WIDTH_RX_P
PCI_EXPRESS_CHANGE_IN_
LINK_WIDTH_RX_N
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK_P
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK_N
PCI_EXPRESS_CONFIG_
ILLEGAL_TS2_P
PCI_EXPRESS_CONFIG_
ILLEGAL_TS2_N
PCI_EXPRESS_COUNTER_
PROPOSED_GREATER_TX_P
PCI_EXPRESS_COUNTER_
PROPOSED_GREATER_TX_N
PCI_EXPRESS_COUNTER_
PROPOSED_GREATER_RX_P
PCI_EXPRESS_COUNTER_
PROPOSED_GREATER_RX_N
449
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_COUNTER_
PROPOSED_WIDTH_ERROR_
TX_P
PCI_EXPRESS_COUNTER_
PROPOSED_WIDTH_ERROR_
TX_N
PCI_EXPRESS_COUNTER_
PROPOSED_WIDTH_ERROR_
RX_P
PCI_EXPRESS_COUNTER_
PROPOSED_WIDTH_ERROR_
RX_N
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED_P
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED_N
PCI_EXPRESS_DISABLE_NOT_
ENTERED_P
PCI_EXPRESS_DISABLE_NOT_
ENTERED_N
PCI_EXPRESS_DISABLE_OS_
ERROR_P
PCI_EXPRESS_DISABLE_OS_
ERROR_N
PCI_EXPRESS_FTS_IN_NON_
L0s_P
PCI_EXPRESS_FTS_IN_NON_
L0s_N
PCI_EXPRESS_FTS_NOT_
ALL_LANES_TX_P
PCI_EXPRESS_FTS_NOT_
ALL_LANES_TX_N
PCI_EXPRESS_FTS_NOT_
ALL_LANES_RX_P
PCI_EXPRESS_FTS_NOT_
ALL_LANES_RX_N
450
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_IDL_NOT_
ALL_LANES_TX_P
PCI_EXPRESS_IDL_NOT_
ALL_LANES_TX_N
PCI_EXPRESS_IDL_NOT_
ALL_LANES_RX_P
PCI_EXPRESS_IDL_NOT_
ALL_LANES_RX_N
PCI_EXPRESS_IDLE_COUNT_
ERROR_P
PCI_EXPRESS_IDLE_COUNT_
ERROR_N
PCI_EXPRESS_IDLE_DATA_
BEFORE_NEG_TX_P
PCI_EXPRESS_IDLE_DATA_
BEFORE_NEG_TX_N
PCI_EXPRESS_IDLE_DATA_
BEFORE_NEG_RX_P
Idle data should be detected During link training, only training sequences
after link width negotiation. are transmitted and received. Idle data is
transmitted/received only after link training
and width negotiation. This check fires if
idle data is detected on the transmit/receive
interface before the completion of link width
negotiation.
PCI_EXPRESS_IDLE_DATA_
BEFORE_NEG_RX_N
PCI_EXPRESS_IDLE_DATA_
NOT_ALL_LANES_TX_P
PCI_EXPRESS_IDLE_DATA_
NOT_ALL_LANES_TX_N
Idle data should be detected Idle data should be detected on all lanes of
on all lanes of the link.
the configured link. This check fires if idle
data is not detected on all lanes of the
configured link.
PCI_EXPRESS_IDLE_DATA_
NOT_ALL_LANES_RX_P
PCI_EXPRESS_IDLE_DATA_
NOT_ALL_LANES_RX_N
451
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_ILLEGAL_IDLE_
DATA_P
PCI_EXPRESS_ILLEGAL_IDLE_
DATA_N
PCI_EXPRESS_ILLEGAL_LINK_
WIDTH_P
PCI_EXPRESS_ILLEGAL_LINK_
WIDTH_N
PCI_EXPRESS_ILLEGAL_TS1_
OS_P
PCI_EXPRESS_ILLEGAL_TS1_
OS_N
PCI_EXPRESS_ILLEGAL_TS2_
OS_P
PCI_EXPRESS_ILLEGAL_TS2_
OS_N
PCI_EXPRESS_LANE_ASSIGN_
ERROR_TX_P
PCI_EXPRESS_LANE_ASSIGN_
ERROR_TX_N
PCI_EXPRESS_LANE_ASSIGN_
ERROR_RX_P
PCI_EXPRESS_LANE_ASSIGN_
ERROR_RX_N
452
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_LANE_INIT_
BEFORE_LINK_INIT_TX_P
PCI_EXPRESS_LANE_INIT_
BEFORE_LINK_INIT_TX_N
PCI_EXPRESS_LANE_INIT_
BEFORE_LINK_INIT_RX_P
PCI_EXPRESS_LANE_INIT_
BEFORE_LINK_INIT_RX_N
PCI_EXPRESS_LANE_LINK_
MISMATCH_TX_P
PCI_EXPRESS_LANE_LINK_
MISMATCH_TX_N
PCI_EXPRESS_LANE_LINK_
MISMATCH_RX_P
PCI_EXPRESS_LANE_LINK_
MISMATCH_RX_N
PCI_EXPRESS_LANE_NT_
PAD_IN_CONFIG_START_P
PCI_EXPRESS_LANE_NT_
PAD_IN_CONFIG_START_N
PCI_EXPRESS_LANE_NT_
PAD_IN_POLLING_ACT_P
PCI_EXPRESS_LANE_NT_
PAD_IN_POLLING_ACT_N
PCI_EXPRESS_LANE_NT_
PAD_IN_POLLING_CFG_P
PCI_EXPRESS_LANE_NT_
PAD_IN_POLLING_CFG_N
PCI_EXPRESS_LANE_PAD_
IN_CONFIG_COMPLETE_P
PCI_EXPRESS_LANE_PAD_
IN_CONFIG_COMPLETE_N
In Polling Configuration,
This check fires if non-PAD lane number is
the lane number must be set detected in TS1 in Polling Active state. This
to PAD.
check is enabled only when the skip link
training option is not set.
In Configuration Complete This check fires if the lane number set to
State, the lane number must PAD is detected in TS2 OS in configuration
be non-PAD in TS2.
complete state. This check is enabled only
when the skip link training option is not set.
453
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_LINK_CTRL_
NOT_SAME_TX_P
PCI_EXPRESS_LINK_NUM_
MISMATCH_P
In Configuration Complete
State, the link number must
be non-PAD in TS2.
PCI_EXPRESS_LINK_CTRL_
NOT_SAME_TX_N
PCI_EXPRESS_LINK_CTRL_
NOT_SAME_RX_P
PCI_EXPRESS_LINK_CTRL_
NOT_SAME_RX_N
PCI_EXPRESS_LINK_NUM_
MISMATCH_N
PCI_EXPRESS_LINK_PAD_
IN_CONFIG_COMPLETE_P
PCI_EXPRESS_LINK_PAD_
IN_CONFIG_COMPLETE_N
PCI_EXPRESS_LINK_PAD_
IN_CONFIG_P
PCI_EXPRESS_LINK_PAD_
IN_CONFIG_N
PCI_EXPRESS_LINK_RESET_
UPSTREAM_P
In Configuration State, the This check fires if TS1 is detected with the
link number must be nonlink number set to PAD in Configuration
PAD for downstream lanes. state for downstream lanes. This check is
enabled only when the skip link training
option is not set.
Training control reset
should not be issued in the
upstream direction.
PCI_EXPRESS_LINK_RESET_
UPSTREAM_N
PCI_EXPRESS_LOOPBK_
NOT_ENTERED_P
PCI_EXPRESS_LOOPBK_
NOT_ENTERED_N
454
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_MIN_TS1_
COUNT_VIOLATION_P
At least
MIN_TS1_COUNT
number of TS1 ordered sets
should be transmitted.
PCI_EXPRESS_MIN_TS1_
COUNT_VIOLATION_N
PCI_EXPRESS_N_FTS_NOT_
SAME_TX_P
PCI_EXPRESS_N_FTS_NOT_
SAME_TX_N
PCI_EXPRESS_N_FTS_NOT_
SAME_RX_P
PCI_EXPRESS_N_FTS_NOT_
SAME_RX_N
PCI_EXPRESS_NO_SKP_
AFTER_FTS_P
PCI_EXPRESS_NO_SKP_
AFTER_FTS_N
PCI_EXPRESS_PROPOSED_
WIDTH_ERROR_TX_P
PCI_EXPRESS_PROPOSED_
WIDTH_ERROR_TX_N
PCI_EXPRESS_PROPOSED_
WIDTH_ERROR_RX_P
PCI_EXPRESS_PROPOSED_
WIDTH_ERROR_RX_N
PCI_EXPRESS_RECOCFG_
NOT_ENTERED_P
PCI_EXPRESS_RECOCFG_
NOT_ENTERED_N
455
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_RECOLK_
NOT_ENTERED_P
PCI_EXPRESS_RECOLK_
NOT_ENTERED_N
PCI_EXPRESS_RESET_NOT_
ENTERED_P
PCI_EXPRESS_RESET_NOT_
ENTERED_N
PCI_EXPRESS_SCRAMBLING_
DISABLE_ERROR_P
PCI_EXPRESS_SCRAMBLING_
DISABLE_ERROR_N
PCI_EXPRESS_SKP_NOT_
ALL_LANES_TX_P
PCI_EXPRESS_SKP_NOT_
ALL_LANES_TX_N
PCI_EXPRESS_SKP_NOT_
ALL_LANES_RX_P
PCI_EXPRESS_SKP_NOT_
ALL_LANES_RX_N
PCI_EXPRESS_SKP_XMTD_
DURING_COMPLIANCE_P
PCI_EXPRESS_SKP_XMTD_
DURING_COMPLIANCE_N
PCI_EXPRESS_TS1_NOT_
ALL_LANES_TX_P
PCI_EXPRESS_TS1_NOT_
ALL_LANES_TX_N
PCI_EXPRESS_TS1_NOT_
ALL_LANES_RX_P
PCI_EXPRESS_TS1_NOT_
ALL_LANES_RX_N
456
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_TS2_COUNT_
ERROR_P
PCI_EXPRESS_TS2_COUNT_
ERROR_N
PCI_EXPRESS_TS2_NOT_
ALL_LANES_TX_P
PCI_EXPRESS_TS2_NOT_
ALL_LANES_TX_N
PCI_EXPRESS_TS2_NOT_
ALL_LANES_RX_P
PCI_EXPRESS_TS2_NOT_
ALL_LANES_RX_N
PCI_EXPRESS_UPSTREAM_
PORT_INIT_LANE_NUM_TX_P
PCI_EXPRESS_UPSTREAM_
PORT_INIT_LANE_NUM_TX_N
PCI_EXPRESS_UPSTREAM_
PORT_INIT_LANE_NUM_RX_P
PCI_EXPRESS_UPSTREAM_
PORT_INIT_LANE_NUM_RX_N
PCI_EXPRESS_UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG_TX_P
PCI_EXPRESS_UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG_TX_N
PCI_EXPRESS_UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG_RX_P
PCI_EXPRESS_UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG_RX_N
457
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_VALID_
LINK_NUM_TX_P
PCI_EXPRESS_VALID_
LINK_NUM_TX_N
PCI_EXPRESS_VALID_
LINK_NUM_RX_P
PCI_EXPRESS_VALID_
LINK_NUM_RX_N
Notes:
1. Checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
2. Checkers with a _TX_P or _TX_N suffix are performed in the transmit direction and
checkers with a _RX_P or _RX_N suffix are performed in the receive direction. All
other checks are performed in both directions.
Violation
Description
PCI_EXPRESS_ACKNAK_
SEQ_NUM_P
PCI_EXPRESS_ACKNAK_
SEQ_NUM_N
PCI_EXPRESS_ACKNAK_
TIMER_EXPIRED_P
PCI_EXPRESS_ACKNAK_
TIMER_EXPIRED_N
PCI_EXPRESS_ALL_OLD_
TLPs_RETRANSMITTED_P
PCI_EXPRESS_ALL_OLD_
TLPs_RETRANSMITTED_N
458
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_CPD_FC1_
FC2_MISMATCH_P
Completion data credit should This check fires if value of completion data
match in InitFC1 and InitFC2. credit is different in InitFC1 and InitFC2.
PCI_EXPRESS_CPD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_CPH_FC1_
FC2_MISMATCH_P
PCI_EXPRESS_CPH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_CPLD_
MINIMUM_CREDIT_
VIOLATION_P
PCI_EXPRESS_CPLD_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_CPLH_
MINIMUM_CREDIT_
VIOLATION_P
PCI_EXPRESS_CPLH_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_DLL_PKT_
16BIT_CRC_P
PCI_EXPRESS_DLL_PKT_
16BIT_CRC_N
PCI_EXPRESS_DLL_PKT_
LENGTH_P
PCI_EXPRESS_DLL_PKT_
LENGTH_N
PCI_EXPRESS_DLP_TLP_IN_
DL_DOWN_P
PCI_EXPRESS_DLP_TLP_IN_
DL_DOWN_N
459
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_FC_DLLP_
AFTER_INIT_P
InitFC1/InitFC2 DLLPs
should not be detected once
the VC initialization is done.
InitFC1/InitFC2 DLLPs
should not be detected in the
DL_Active state.
PCI_EXPRESS_INFC_CPH_
INVL_P
PCI_EXPRESS_INFC_CPH_
INVL_N
PCI_EXPRESS_INFC_NPD_
INVL_P
This check fires if more than 2047 nonposted header credit detected in InitFC.
This check fires if more than 127 nonposted header credit detected in InitFC.
PCI_EXPRESS_FC_DLLP_
AFTER_INIT_N
PCI_EXPRESS_FC_DLLP_
IN_DL_ACTIVE_P
PCI_EXPRESS_FC_DLLP_
IN_DL_ACTIVE_N
PCI_EXPRESS_FIRST_TLP_
AFTER_LINK_UP_P
PCI_EXPRESS_FIRST_TLP_
AFTER_LINK_UP_N
PCI_EXPRESS_INCR_SEQ_
NUM_TLP_P
PCI_EXPRESS_INCR_SEQ_
NUM_TLP_N
PCI_EXPRESS_INFC_CPD_
INVL_P
PCI_EXPRESS_INFC_CPD_
INVL_N
PCI_EXPRESS_INFC_NPD_
INVL_N
PCI_EXPRESS_INFC_NPH_
INVL_P
PCI_EXPRESS_INFC_NPH_
INVL_N
460
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_INFC_PD_
INVL_P
PCI_EXPRESS_INFC_PD_
INVL_N
PCI_EXPRESS_INFC_PH_
INVL_P
PCI_EXPRESS_INFC_PH_
INVL_N
PCI_EXPRESS_MAX_
UNACKD_TLP_P
PCI_EXPRESS_MAX_
UNACKD_TLP_N
PCI_EXPRESS_NO_ACK_
DLLP_FOR_TLP_P
Maximum number of
The maximum number of TLP packets that
unacknowledged TLPs should can be outstanding without an
not exceed 2048.
acknowledgment is 2047. This check fires if
a TLP is detected when there are 2047
outstanding TLPs without an
acknowledgment.
Transmitter should send a
NAK DLLP for TLPs
received with an error.
PCI_EXPRESS_NO_ACK_
DLLP_FOR_TLP_N
PCI_EXPRESS_NO_NAK_
DLLP_FOR_TLP_P
PCI_EXPRESS_NO_NAK_
DLLP_FOR_TLP_N
PCI_EXPRESS_NO_VC0_
INITIALIZTION_P
PCI_EXPRESS_NO_VC0_
INITIALIZTION_N
PCI_EXPRESS_NPD_FC1_
FC2_MISMATCH_P
Non-posted data credit should This check fires if value of non-posted data
match in InitFC1 and InitFC2. credit is different in InitFC1 and InitFC2.
PCI_EXPRESS_NPD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_NPH_FC1_
FC2_MISMATCH_P
PCI_EXPRESS_NPH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_NULL_TLP_
LINK_CRC_P
PCI_EXPRESS_NULL_TLP_
LINK_CRC_N
461
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_NULL_TLP_
WITH_END_P
PCI_EXPRESS_NULL_TLP_
WITH_END_N
PCI_EXPRESS_PD_FC1_
FC2_MISMATCH_P
PCI_EXPRESS_PD_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_PD_
MINIMUM_CREDIT_
VIOLATION_P
PCI_EXPRESS_PD_
MINIMUM_CREDIT_
VIOLATION_N
PCI_EXPRESS_PH_FC1_
FC2_MISMATCH_P
PCI_EXPRESS_PH_FC1_
FC2_MISMATCH_N
PCI_EXPRESS_REPLAY_
NUM_EXPIRED_P
PCI_EXPRESS_REPLAY_
NUM_EXPIRED_N
PCI_EXPRESS_RESERVED_
FIELD_ERROR_P
PCI_EXPRESS_RESERVED_
FIELD_ERROR_N
PCI_EXPRESS_RETRY_
AFTER_NAK_P
PCI_EXPRESS_RETRY_
AFTER_NAK_N
462
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_RETRY_
TLPS_P
Uninterrupted sequence of
InitFC1-P, InitFC1-NP, and
InitFC1-Cpl DLLPs not
transmitted in the FC-Init1
state.
PCI_EXPRESS_RETRY_
TLPS_N
PCI_EXPRESS_RETRY_
WITHOUT_REPLAY_OR_
NAK_P
PCI_EXPRESS_RETRY_
WITHOUT_REPLAY_OR_
NAK_N
PCI_EXPRESS_SEQ_NUM_
AFTER_NULL_TLP_P
PCI_EXPRESS_SEQ_NUM_
AFTER_NULL_TLP_N
PCI_EXPRESS_TLP_IN_FC_
INIT1_P
PCI_EXPRESS_TLP_IN_FC_
INIT1_N
PCI_EXPRESS_TLP_LINK_
CRC_P
PCI_EXPRESS_TLP_LINK_
CRC_N
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT1_P
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT1_N
463
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT2_P
Uninterrupted sequence of
InitFC2-P, InitFC2-NP, and
InitFC2-Cpl DLLPs not
transmitted in the FC-Init2
state.
PCI_EXPRESS_TX_FC_
DLLP_IN_FC_INIT2_N
PCI_EXPRESS_TX_SAME_
HDRFC_DLLP_FC_INIT1_P
PCI_EXPRESS_TX_SAME_
HDRFC_DLLP_FC_INIT1_N
PCI_EXPRESS_UFC_BEFORE_
INITFC_P
The flow control packets, InitFC-P, InitFCNP, and InitFC-Cpl contain the credit limit
available. The credit limit values for data
should remain constant across the InitFC-P,
NP, CPL sequences. This check fires if the
credit limit is not constant across the
sequences.
The flow control packets, InitFC-P, InitFCNP, and InitFC-Cpl contain the Credit Limit
available. The Credit Limit values for
headers should remain constant across the
InitFC-P, NP, CPL sequences. This check
fires if the Credit Limit is not constant
across the sequences.
PCI_EXPRESS_UFC_BEFORE_
INITFC_N
PCI_EXPRESS_UFC_CPL_
FOR_INFINIT_CREDIT_P
PCI_EXPRESS_UFC_CPL_
FOR_INFINIT_CREDIT_N
PCI_EXPRESS_UFC_CPL_
MISSING_P
PCI_EXPRESS_UFC_CPL_
MISSING_N
PCI_EXPRESS_UFC_CPLD_
INVL_P
PCI_EXPRESS_UFC_CPLD_
INVL_N
PCI_EXPRESS_UFC_CPLH_
INVL_P
PCI_EXPRESS_UFC_CPLH_
INVL_N
464
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_UFC_NP_
FOR_INFINIT_CREDIT_P
UFC need not be transmitted This check fires if UFC detected for infinite
for infinite advertised nonadvertised non-posted header and data
posted header and data credit. credit.
PCI_EXPRESS_UFC_NP_
FOR_INFINIT_CREDIT_N
PCI_EXPRESS_UFC_NP_
MISSING_P
PCI_EXPRESS_UFC_NP_
MISSING_N
PCI_EXPRESS_UFC_NPD_
INVL_P
PCI_EXPRESS_UFC_NPD_
INVL_N
PCI_EXPRESS_UFC_NPH_
INVL_P
PCI_EXPRESS_UFC_NPH_
INVL_N
PCI_EXPRESS_UFC_P_FOR_
INFINIT_CREDIT_P
PCI_EXPRESS_UFC_P_FOR_
INFINIT_CREDIT_N
PCI_EXPRESS_UFC_P_
MISSING_P
PCI_EXPRESS_UFC_P_
MISSING_N
PCI_EXPRESS_UFC_PD_
INVL_P
PCI_EXPRESS_UFC_PD_
INVL_N
PCI_EXPRESS_UFC_PH_
INVL_P
PCI_EXPRESS_UFC_PH_
INVL_N
PCI_EXPRESS_UNDEFINED_
DLLP_ENCODING_P
PCI_EXPRESS_UNDEFINED_
DLLP_ENCODING_N
465
PCI Express
Monitor Checks
Table 14-7. PCI Express Monitor Data Link Layer Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_VENDOR_
SPEC_DLLP_TYPE_P
PCI_EXPRESS_VENDOR_
SPEC_DLLP_TYPE_N
Note that checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
Violation
Description
PCI_EXPRESS_ADDRESS_
FORMAT_ERROR_P
PCI_EXPRESS_ADDRESS_
FORMAT_ERROR_N
PCI_EXPRESS_AI_BL_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AI_BL_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AI_OFF_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AI_OFF_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AI_ON_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AI_ON_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_AT_BT_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_AT_BT_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_BUS_DEV_NOT_
0_FOR_CPL_BEFORE_INIT_
WR_P
PCI_EXPRESS_BUS_DEV_NOT_
0_FOR_CPL_BEFORE_INIT_
WR_N
466
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_CFG1_CPL_NE_
UR_P
Attribute field of
configuration request should
be 2'b00.
PCI_EXPRESS_CFG1_CPL_NE_
UR_N
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR_P
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR_N
PCI_EXPRESS_CFG_REQ_
HDR_LENGTH_ERROR_P
PCI_EXPRESS_CFG_REQ_
HDR_LENGTH_ERROR_N
PCI_EXPRESS_CFG_REQ_
LEGACY_END_POINT_P
PCI_EXPRESS_CFG_REQ_
LEGACY_END_POINT_N
PCI_EXPRESS_CFG_REQ_
LENGTH_FIELD_ERROR_P
PCI_EXPRESS_CFG_REQ_
LENGTH_FIELD_ERROR_N
PCI_EXPRESS_CFG_REQ_PCI_
EXPRESS_END_POINT_P
PCI_EXPRESS_CFG_REQ_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_CFG_REQ_TC_
FIELD_ERROR_P
PCI_EXPRESS_CFG_REQ_TC_
FIELD_ERROR_N
PCI_EXPRESS_COMPLETION_
BCM_BIT_SET_P
PCI_EXPRESS_COMPLETION_
BCM_BIT_SET_N
PCI_EXPRESS_COMPLETION_
FOR_UR_NE_UR_P
PCI_EXPRESS_COMPLETION_
FOR_UR_NE_UR_N
467
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_COR_ERR_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_COR_ERR_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_COR_ERR_P
PCI_EXPRESS_COR_ERR_N
PCI_EXPRESS_CPL_HEADER_
LENGTH_ERROR_P
PCI_EXPRESS_CPL_HEADER_
LENGTH_ERROR_N
PCI_EXPRESS_CPL_LENGTH_
FIELD_ERROR_P
PCI_EXPRESS_CPL_LENGTH_
FIELD_ERROR_N
PCI_EXPRESS_CPL_LK_ERR_P
PCI_EXPRESS_CPL_LK_ERR_N
PCI_EXPRESS_CPL_LK_REQ_
PCI_EXPRESS_END_POINT_P
PCI_EXPRESS_CPL_LK_REQ_P
CI_EXPRESS_END_POINT_N
PCI_EXPRESS_CPL_LK_REQ_
ROOT_COMPLEX_P
PCI_EXPRESS_CPL_LK_REQ_
ROOT_COMPLEX_N
PCI_EXPRESS_CPL_LK_TC_
NE_0_P
PCI_EXPRESS_CPL_LK_TC_
NE_0_N
PCI_EXPRESS_CPL_STATUS_
CA_P
PCI_EXPRESS_CPL_STATUS_
CA_N
468
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_CPL_STATUS_
CRS_P
PCI_EXPRESS_CPL_STATUS_
CRS_N
PCI_EXPRESS_CPL_STATUS_
FIELD_ERROR_P
PCI_EXPRESS_CPL_STATUS_
FIELD_ERROR_N
PCI_EXPRESS_CPL_STATUS_
UR_P
PCI_EXPRESS_CPL_STATUS_
UR_N
PCI_EXPRESS_ECRC_
ERROR_P
PCI_EXPRESS_ECRC_
ERROR_ N
PCI_EXPRESS_ERR_MSG_
CODE_ERROR_P
PCI_EXPRESS_ERR_MSG_
CODE_ERROR_N
PCI_EXPRESS_ERR_MSG_
ROUTING_NT_000_P
PCI_EXPRESS_ERR_MSG_
ROUTING_NT_000_N
PCI_EXPRESS_FATAL_ERR_
MSG_DIRECTION_INVL_P
PCI_EXPRESS_FATAL_ERR_
MSG_DIRECTION_INVL_N
PCI_EXPRESS_FIRST_DW_BE_
NON_ZERO_ERROR_P
PCI_EXPRESS_FIRST_DW_BE_
NON_ZERO_ERROR_N
PCI_EXPRESS_FT_ERR_P
PCI_EXPRESS_FT_ERR_N
469
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_HOT_PLUG_
MSG_CODE_ERROR_P
PCI_EXPRESS_HOT_PLUG_
MSG_CODE_ERROR_N
PCI_EXPRESS_HOT_PLUG_
MSG_ROUTING_NT_100_P
PCI_EXPRESS_HOT_PLUG_
MSG_ROUTING_NT_100_N
PCI_EXPRESS_IGNORED_
MESSAGE_DETECTED_P
PCI_EXPRESS_IGNORED_
MESSAGE_DETECTED_N
PCI_EXPRESS_ILLEGAL_
ADDRESS_LENGTH_
COMBINATION_P
PCI_EXPRESS_ILLEGAL_
ADDRESS_LENGTH_
COMBINATION_N
PCI_EXPRESS_INTR_MSG_
CODE_ERROR_P
PCI_EXPRESS_INTR_MSG_
CODE_ERROR_N
PCI_EXPRESS_INTX_FROM_
DOWNSTREAM_PORT_P
PCI_EXPRESS_INTX_FROM_
DOWNSTREAM_PORT_N
PCI_EXPRESS_INTX_MSG_
NON_RSVD_FN_NUMBER_P
PCI_EXPRESS_INTX_MSG_
NON_RSVD_FN_NUMBER_N
PCI_EXPRESS_INTX_MSG_
ROUTING_NT_100_P
PCI_EXPRESS_INTX_MSG_
ROUTING_NT_100_N
470
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_INVALID_
COMPLETER_ID_P
PCI_EXPRESS_INVALID_
COMPLETER_ID_N
PCI_EXPRESS_INVALID_REQ_
ID_P
PCI_EXPRESS_INVALID_REQ_
ID_N
PCI_EXPRESS_IO_REQ_ATTR_
FIELD_ERROR_P
PCI_EXPRESS_IO_REQ_ATTR_
FIELD_ERROR_N
PCI_EXPRESS_IO_REQ_HDR_
LENGTH_ERROR_P
PCI_EXPRESS_IO_REQ_HDR_
LENGTH_ERROR_N
PCI_EXPRESS_IO_REQ_LENGTH
_FIELD_ERROR_P
PCI_EXPRESS_IO_REQ_LENGTH
_FIELD_ERROR_N
PCI_EXPRESS_IO_REQ_PCI_
EXPRESS_END_POINT_P
PCI_EXPRESS_IO_REQ_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_IO_REQ_TC_
FIELD_ERROR_P
PCI_EXPRESS_IO_REQ_TC_
FIELD_ERROR_N
471
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_LAST_DW_BE_
ERROR_P
PCI_EXPRESS_LAST_DW_BE_
ERROR_N
PCI_EXPRESS_LAST_DW_BE_
NON_ZERO_ERROR_P
PCI_EXPRESS_LAST_DW_BE_
NON_ZERO_ERROR_N
PCI_EXPRESS_LINK_DOWN_
PENDING_REQUESTS_P
PCI_EXPRESS_LINK_DOWN_
PENDING_REQUESTS_N
PCI_EXPRESS_LK_ERR_P
PCI_EXPRESS_LK_ERR_N
PCI_EXPRESS_LOCK_REQ_
LEGACY_END_POINT_P
PCI_EXPRESS_LOCK_REQ_
LEGACY_END_POINT_N
PCI_EXPRESS_LOCK_REQ_
PCI_EXPRESS_END_POINT_P
PCI_EXPRESS_LOCK_REQ_
PCI_EXPRESS_END_POINT_N
PCI_EXPRESS_LOCKED_TRAN_
MSG_CODE_ERROR_P
PCI_EXPRESS_LOCKED_TRAN_
MSG_CODE_ERROR_N
PCI_EXPRESS_MAX_PAYLOAD_
SIZE_ERROR_P
PCI_EXPRESS_MAX_PAYLOAD_
SIZE_ERROR_N
472
Payload should not exceed the The maximum DWs that can be present
specified maximum number
on a TLP packet is specified in Device
of bytes.
Control Register. This check fires if a
TLP packet with a data payload more
than the specified maximum pay load
size is detected. The TLP packet can be
request or a completion packet.
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_MAX_READ_
REQ_SIZE_ERROR_P
PCI_EXPRESS_MAX_READ_
REQ_SIZE_ERROR_N
PCI_EXPRESS_MRD_LK_TC_
NE_0_P
PCI_EXPRESS_MRD_LK_TC_
NE_0_N
PCI_EXPRESS_MSG_NOT_
ROUTED_BY_ID_BYT8_9_
RSVD_ERROR_P
PCI_EXPRESS_MSG_NOT_
ROUTED_BY_ID_BYT8_9_
RSVD_ERROR_N
PCI_EXPRESS_MSG_REQ_ATTR_
FIELD_ERROR_P
PCI_EXPRESS_MSG_REQ_ATTR_
FIELD_ERROR_N
PCI_EXPRESS_MSG_REQ_HDR_
LENGTH_ERROR_P
PCI_EXPRESS_MSG_REQ_HDR_
LENGTH_ERROR_N
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR_P
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR_N
PCI_EXPRESS_MSG_REQ_TC_
FIELD_ERROR_P
PCI_EXPRESS_MSG_REQ_TC_
FIELD_ERROR_N
PCI_EXPRESS_MSG_ROUTING_
000_FROM_RC_P
PCI_EXPRESS_MSG_ROUTING_
000_FROM_RC_N
473
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_MSG_ROUTING_
011_FROM_EP_P
PCI_EXPRESS_NO_SSPL_N
PCI_EXPRESS_NO_TLP_
DIGEST_P
PCI_EXPRESS_MSG_ROUTING_
011_FROM_EP_N
PCI_EXPRESS_MSG_TYPE_
ERROR_P
PCI_EXPRESS_MSG_TYPE_
ERROR_N
PCI_EXPRESS_NFT_ERR_P
PCI_EXPRESS_NFT_ERR_N
PCI_EXPRESS_NO_LK_ERR_P
PCI_EXPRESS_NO_LK_ERR_N
PCI_EXPRESS_NO_SSPL_P
PCI_EXPRESS_NO_TLP_
DIGEST_N
PCI_EXPRESS_NON_
CONTIGUOUS_FIRST_DW_BE_
ERROR_FOR_LEN_EQ_2DW_
NON_QW_ALIGNED_P
PCI_EXPRESS_NON_
CONTIGUOUS_FIRST_DW_BE_
ERROR_FOR_LEN_EQ_2DW_
NON_QW_ALIGNED_N
PCI_EXPRESS_NON_
CONTIGUOUS_FIRST_DW_BE_
ERROR_FOR_LEN_MT_2DW_P
PCI_EXPRESS_NON_
CONTIGUOUS_FIRST_DW_BE_
ERROR_FOR_LEN_MT_2DW_N
474
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_NON_
CONTIGUOUS_LAST_DW_BE_
ERROR_FOR_LEN_EQ_2DW_
NON_QW_ALIGNED_P
PCI_EXPRESS_PARAM_DEVICE_
TYPE_ERR
PCI_EXPRESS_PARAM_MAX_
LINK_WIDTH_ERR
PCI_EXPRESS_PI_BL_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_NON_
CONTIGUOUS_LAST_DW_BE_
ERROR_FOR_LEN_EQ_2DW_
NON_QW_ALIGNED_N
PCI_EXPRESS_NON_
CONTIGUOUS_LAST_DW_BE_
ERROR_FOR_LEN_MT_2DW_P
PCI_EXPRESS_NON_
CONTIGUOUS_LAST_DW_BE_
ERROR_FOR_LEN_MT_2DW_N
PCI_EXPRESS_NON_FATAL_
ERR_MSG_DIRECTION_INVL_P
PCI_EXPRESS_NON_FATAL_
ERR_MSG_DIRECTION_INVL_N
PCI_EXPRESS_NON_ZERO_
RESERVED_FIELD_ERROR_P
PCI_EXPRESS_NON_ZERO_
RESERVED_FIELD_ERROR_N
PCI_EXPRESS_PI_BL_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_PI_OFF_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_PI_OFF_MSG_
DIRECTION_INVL_N
475
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_PI_ON_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_PI_ON_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_PM_ASN_MSG_
ROUTING_NT_100_P
PCI_EXPRESS_PM_ASN_MSG_
ROUTING_NT_100_N
PCI_EXPRESS_PM_MSG_NON_
RSVD_FN_NUMBER_P
PCI_EXPRESS_PM_MSG_NON_
RSVD_FN_NUMBER_N
PCI_EXPRESS_PM_PME_MSG_
ROUTING_NT_000_P
TLP is poisoned.
PCI_EXPRESS_PM_PME_MSG_
ROUTING_NT_000_N
PCI_EXPRESS_PME_2_ACK_
MSG_ROUTING_NT_101_P
PCI_EXPRESS_PME_2_ACK_
MSG_ROUTING_NT_101_N
PCI_EXPRESS_PME_MSG_
CODE_ERROR_P
PCI_EXPRESS_PME_MSG_
CODE_ERROR_N
PCI_EXPRESS_PME_TO_MSG_
ROUTING_NT_011_P
PCI_EXPRESS_PME_TO_MSG_
ROUTING_NT_011_N
PCI_EXPRESS_POISONED_TLP_P
PCI_EXPRESS_POISONED_TLP_N
PCI_EXPRESS_RESERVED_
VALUE_FOR_MAX_READ_
REQUEST_SIZE
476
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_RESERVED_
VALUE_FOR_MAX_PAYLOAD_
SIZE
PCI_EXPRESS_ROOT_
COMPLEX_RCVD_CFG_REQ_P
PCI_EXPRESS_ROOT_
COMPLEX_RCVD_CFG_REQ_N
PCI_EXPRESS_RX_COMPLETION_
TC_ATTR_MISMATCH_P
PCI_EXPRESS_RX_COMPLETION_
TC_ATTR_MISMATCH_N
PCI_EXPRESS_RX_COMPLETION_
TIMEOUT_P
PCI_EXPRESS_RX_COMPLETION_
TIMEOUT_N
PCI_EXPRESS_RX_COMPLETION_
WITHOUT_REQUEST_P
PCI_EXPRESS_RX_COMPLETION_
WITHOUT_REQUEST_N
PCI_EXPRESS_RX_CPL_BYTE_
COUNT_VALUE_ERROR_P
PCI_EXPRESS_RX_CPL_BYTE_
COUNT_VALUE_ERROR_N
PCI_EXPRESS_RX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_P
PCI_EXPRESS_RX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_N
PCI_EXPRESS_RX_CPL_LK_
FOR_NON_LOCKED_REQ_P
PCI_EXPRESS_RX_CPL_LK_
FOR_NON_LOCKED_REQ_N
477
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_RX_CPL_LWR_
ADDRESS_VALUE_ERROR_P
PCI_EXPRESS_RX_CPL_LWR_
ADDRESS_VALUE_ERROR_N
PCI_EXPRESS_RX_CPL_NOT_
UR_FOR_POISONED_CFG_WR_P
PCI_EXPRESS_RX_CPL_NOT_
UR_FOR_POISONED_CFG_WR_N
PCI_EXPRESS_RX_CPL_NOT_
UR_FOR_POISONED_IO_WR_P
Unsuccessful completions
should not contain data
payload.
PCI_EXPRESS_RX_CPL_NOT_
UR_FOR_POISONED_IO_WR_N
PCI_EXPRESS_RX_CPL_STATUS_
CSR_FOR_NONCFG_
REQ_P
PCI_EXPRESS_RX_CPL_STATUS_
CSR_FOR_NONCFG_
REQ_N
PCI_EXPRESS_RX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_P
PCI_EXPRESS_RX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_N
PCI_EXPRESS_RX_CPLD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_CPLD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_CPLD_FOR_
UNSUCCESFUL_CPL_P
PCI_EXPRESS_RX_CPLD_FOR_
UNSUCCESFUL_CPL_N
478
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_RX_CPLH_
CREDIT_LIMIT_VIOLATION_P
PCI_EXPRESS_RX_MRD_CPL_
LOW_ADDR_N
PCI_EXPRESS_RX_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ_P
PCI_EXPRESS_RX_CPLH_
CREDIT_LIMIT_VIOLATION_N
PCI_EXPRESS_RX_MRD_CPL_
LOW_ADDR_P
PCI_EXPRESS_RX_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ_N
PCI_EXPRESS_RX_NPD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_NPD_CREDIT_
LIMIT_VIOLATION_N
479
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_RX_NPH_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_NPH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_PD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_PD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_PH_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_RX_PH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_RX_RD_CPL_
WITHOUT_DATA_P
PCI_EXPRESS_RX_RD_CPL_
WITHOUT_DATA_N
480
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_SLOT_PWR_MSG_
BIT_31_10_DATA_PAYLOAD_
ERROR_P
PCI_EXPRESS_SLOT_PWR_MSG_
BIT_31_10_DATA_PAYLOAD_
ERROR_N
PCI_EXPRESS_SLOT_PWR_MSG_
CODE_ERROR_P
PCI_EXPRESS_SLOT_PWR_MSG_
CODE_ERROR_N
PCI_EXPRESS_SLOT_PWR_MSG_
TYPE_ERROR_P
PCI_EXPRESS_SLOT_PWR_MSG_
TYPE_ERROR_N
PCI_EXPRESS_SSPL_LENTH_
NT_1_P
PCI_EXPRESS_SSPL_LENTH_
NT_1_N
PCI_EXPRESS_SSPL_MSG_
DIRECTION_INVL_P
PCI_EXPRESS_SSPL_MSG_
DIRECTION_INVL_N
PCI_EXPRESS_SSPL_MSG_
ROUTING_NT_100_P
PCI_EXPRESS_SSPL_MSG_
ROUTING_NT_100_N
PCI_EXPRESS_TAG_FIELD_
ERROR_P
PCI_EXPRESS_TAG_FIELD_
ERROR_N
PCI_EXPRESS_TLP_BEFORE_
INITIAL_CONFIG_WRITE_P
PCI_EXPRESS_TLP_BEFORE_
INITIAL_CONFIG_WRITE_N
481
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TLP_DOESNOT_
MAP_TO_ANY_VC_P
Transmitted completions
should have the same value
for TC and ATTR fields of
the associated received
requests.
Completion transmitted
without a request.
PCI_EXPRESS_TLP_DOESNOT_
MAP_TO_ANY_VC_N
PCI_EXPRESS_TLP_NON_
UNIQUE_TAG_P
PCI_EXPRESS_TLP_NON_
UNIQUE_TAG_N
PCI_EXPRESS_TLP_PKT_SIZE_
ERROR_P
PCI_EXPRESS_TLP_PKT_SIZE_
ERROR_N
PCI_EXPRESS_TLP_USING_
UNINIT_VC_P
PCI_EXPRESS_TLP_USING_
UNINIT_VC_N
PCI_EXPRESS_TX_COMPLETION_
TC_ATTR_MISMATCH_P
PCI_EXPRESS_TX_COMPLETION_
TC_ATTR_MISMATCH_N
PCI_EXPRESS_TX_COMPLETION_
TIMEOUT_P
PCI_EXPRESS_TX_COMPLETION_
TIMEOUT_N
PCI_EXPRESS_TX_COMPLETION_
WITHOUT_REQUEST_P
PCI_EXPRESS_TX_COMPLETION_
WITHOUT_REQUEST_N
PCI_EXPRESS_TX_CPL_BYTE_
COUNT_VALUE_ERROR_P
PCI_EXPRESS_TX_CPL_BYTE_
COUNT_VALUE_ERROR_N
482
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_P
PCI_EXPRESS_TX_CPL_LEN_
NT_1DW_FOR_FLUSH_REQ_N
PCI_EXPRESS_TX_CPL_LK_
FOR_NON_LOCKED_REQ_P
PCI_EXPRESS_TX_CPL_LK_
FOR_NON_LOCKED_REQ_N
PCI_EXPRESS_TX_CPL_LWR_
ADDRESS_VALUE_ERROR_P
PCI_EXPRESS_TX_CPL_LWR_
ADDRESS_VALUE_ERROR_N
PCI_EXPRESS_TX_CPL_NOT_
UR_FOR_POISONED_IO_WR_P
PCI_EXPRESS_TX_CPL_NOT_
UR_FOR_POISONED_IO_WR_N
PCI_EXPRESS_TX_CPL_NOT_
UR_FOR_POISONED_CFG_WR_P
PCI_EXPRESS_TX_CPL_NOT_
UR_FOR_POISONED_CFG_WR_N
PCI_EXPRESS_TX_CPL_STATUS_
CSR_FOR_NONCFG_REQ_P
PCI_EXPRESS_TX_CPL_STATUS_
CSR_FOR_NONCFG_REQ_N
PCI_EXPRESS_TX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_P
PCI_EXPRESS_TX_CPLD_CPL_
FOR_IO_CFG_WRITE_REQ_N
483
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TX_CPLD_CREDIT_
LIMIT_VIOLATION_P
Unsuccessful completions
should not contain data
payload.
PCI_EXPRESS_TX_MRD_CPL_
LOW_ADDR_N
PCI_EXPRESS_TX_NO_
LOCKED_COMPLETION_FOR_
LOCKED_REQ_P
PCI_EXPRESS_TX_CPLD_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_TX_CPLD_FOR_
UNSUCCESFUL_CPL_P
PCI_EXPRESS_TX_CPLD_FOR_
UNSUCCESFUL_CPL_N
PCI_EXPRESS_TX_CPLH_
CREDIT_LIMIT_VIOLATION_P
PCI_EXPRESS_TX_CPLH_
CREDIT_LIMIT_VIOLATION_N
PCI_EXPRESS_TX_MRD_CPL_
LOW_ADDR_P
PCI_EXPRESS_TX_NO_
LOCKED_COMPLETION_FOR_
LOCKED_REQ_N
484
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TX_NPD_
CREDIT_LIMIT_VIOLATION_P
PCI_EXPRESS_TX_NPD_
CREDIT_LIMIT_VIOLATION_N
PCI_EXPRESS_TX_NPH_
CREDIT_LIMIT_VIOLATION_P
PCI_EXPRESS_TX_NPH_
CREDIT_LIMIT_VIOLATION_N
PCI_EXPRESS_TX_PD_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_TX_PD_CREDIT_
LIMIT_VIOLATION_N
485
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_TX_PH_CREDIT_
LIMIT_VIOLATION_P
PCI_EXPRESS_TX_PH_CREDIT_
LIMIT_VIOLATION_N
PCI_EXPRESS_TX_RD_CPL_
WITHOUT_DATA_P
PCI_EXPRESS_TX_RD_CPL_
WITHOUT_DATA_N
PCI_EXPRESS_UNDEFINED_
HEADER_FIELD_P
PCI_EXPRESS_UNDEFINED_
HEADER_FIELD_N
PCI_EXPRESS_UNDEFINED_
MSG_CODE_GROUP_P
PCI_EXPRESS_UNDEFINED_
MSG_CODE_GROUP_N
PCI_EXPRESS_UNLOCK_MSG_
NON_RSVD_FN_NUMBER_P
PCI_EXPRESS_UNLOCK_MSG_
NON_RSVD_FN_NUMBER_N
PCI_EXPRESS_UNLOCK_MSG_
ROUTING_NT_011_P
PCI_EXPRESS_UNLOCK_MSG_
ROUTING_NT_011_N
PCI_EXPRESS_VENDOR_MSG_
ROUTING_NT_VALID_P
PCI_EXPRESS_VENDOR_MSG_
ROUTING_NT_VALID_N
486
PCI Express
Monitor Checks
Table 14-8. PCI Express Monitor Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_VENDOR_
SPECIFIC_MSG_CODE_
ERROR_P
PCI_EXPRESS_VENDOR_
SPECIFIC_MSG_CODE_
ERROR_N
Note that checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
Violation
Description
PCI_EXPRESS_ACK_
WITHOUT_PM_
COMMAND_P
PCI_EXPRESS_ACK_
WITHOUT_PM_
COMMAND_N
PM_Request_Ack DLL
packet should not be
transmitted without receiving
PM_Enter_L1,
PM_Enter_L23, or
PM_Active_State_Request_
L1 DLL packet.
PCI_EXPRESS_DLLP_IN_
L0S_P
No DLLP communication
allowed in L0s.
No DLLP communication
allowed in L1.
No DLLP communication
allowed in L2.
PCI_EXPRESS_DLLP_IN_
L0S_N
PCI_EXPRESS_DLLP_IN_
L1_P
PCI_EXPRESS_DLLP_IN_
L1_N
PCI_EXPRESS_DLLP_IN_
L2_P
PCI_EXPRESS_DLLP_IN_
L2_N
487
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK_P
PM_Active_State_Nak
should not be transmitted
without receiving
PM_Active_State_Request_
L1 DLL packet.
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK_N
PCI_EXPRESS_L0S_ENTRY_
WHEN_DISABLED_P
PCI_EXPRESS_L0s_ENTRY_
WHEN_DISABLED_N
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ_P
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ_N
PCI_EXPRESS_PM_ACTIVE_
STATE_NAK_UPSTREAM_P
PCI_EXPRESS_PM_ACTIVE_
STATE_NAK_UPSTREAM_N
PCI_EXPRESS_PM_ENTER_
DOWNSTREAM_P
PCI_EXPRESS_PM_ENTER_
DOWNSTREAM_N
PCI_EXPRESS_PM_ENTER_
L23_BEFORE_ACK_P
PCI_EXPRESS_PM_ENTER_
L23_BEFORE_ACK_N
488
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_PM_PME_
DOWNSTREAM_P
PCI_EXPRESS_PM_PME_
DOWNSTREAM_N
PCI_EXPRESS_PM_TURN_
OFF_UPSTREAM_P
PME_TO_Ack message
should not be transmitted
without receiving
PME_Turn_Off message.
No TLP communication
allowed in L0s.
No TLP communication
allowed in L1.
No TLP communication
allowed in L2.
PCI_EXPRESS_PM_TURN_
OFF_UPSTREAM_N
PCI_EXPRESS_PME_ACK_
WITHOUT_TURN_OFF_P
PCI_EXPRESS_PME_ACK_
WITHOUT_TURN_OFF_N
PCI_EXPRESS_PME_TO_
ACK_DOWNSTREAM_P
PCI_EXPRESS_PME_TO_
ACK_DOWNSTREAM_N
PCI_EXPRESS_TLP_IN_L0S_P
PCI_EXPRESS_TLP_IN_L0S_N
PCI_EXPRESS_TLP_IN_L1_P
PCI_EXPRESS_TLP_IN_L1_N
PCI_EXPRESS_TLP_IN_L2_P
PCI_EXPRESS_TLP_IN_L2_N
489
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_TLPS_AFTER_
ACK_P
PM_Enter_L1,
PM_Enter_L23,
PM_Active_State_Request_
L1 DLL packets should not
be transmitted when TL
packets are outstanding.
PM_Request_Ack DLL
packet should not be
transmitted when TL packets
are outstanding.
PCI_EXPRESS_TLPS_AFTER_
ACK_N
PCI_EXPRESS_TLPS_AFTER_
PM_P
PCI_EXPRESS_TLPS_AFTER_
PM_N
PCI_EXPRESS_TLPS_
OUTSTANDING_P
PCI_EXPRESS_TLPS_
OUTSTANDING_N
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_
ACK_P
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_
ACK_N
Notes:
1. Checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
2. Power management checks are active when both link layer and transaction layer checks
are enabled.
490
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_ACK_RCVD_
WITHOUT_PM_ENTER_P
PM_Active_State_Nak message
should not be issued in the
upstream direction.
PM_Active_State_Nak message
should not be issued in the
downstream direction without a
PM_Active_State_Request_L1
DLL packet.
PM_Enter_L1, PM_Enter_L23,
and
PM_Active_State_Request_L1
DLL packets should not be
issued in the downstream
direction.
PCI_EXPRESS_ACK_RCVD_
WITHOUT_PM_ENTER_N
PCI_EXPRESS_ACTIVE_
STATE_NAK_
DOWNSTREAM_P
PCI_EXPRESS_ACTIVE_
STATE_NAK_
DOWNSTREAM_N
PCI_EXPRESS_NAK_
WITHOUT_REQ_
UPSTREAM_P
PCI_EXPRESS_NAK_
WITHOUT_REQ_
UPSTREAM_N
PCI_EXPRESS_PM_ENTER_
L23_BEFORE_ACK_
UPSTREAM_P
PCI_EXPRESS_PM_ENTER_
L23_BEFORE_ACK_
UPSTREAM_N
PCI_EXPRESS_PM_ENTER_
UPSTREAM_P
PCI_EXPRESS_PM_ENTER_
UPSTREAM_N
491
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_PM_PME_
UPSTREAM_P
PCI_EXPRESS_PM_PME_
UPSTREAM_N
PCI_EXPRESS_PM_TURN_
OFF_DOWNSTREAM_P
PCI_EXPRESS_PM_TURN_
OFF_DOWNSTREAM_N
PCI_EXPRESS_PME_TO_
ACK_UPSTREAM_P
PCI_EXPRESS_PME_TO_
ACK_UPSTREAM_N
PCI_EXPRESS_PME_TO_
ACK_WITHOUT_TURN_
OFF_P
PCI_EXPRESS_PME_TO_
ACK_WITHOUT_TURN_
OFF_N
PCI_EXPRESS_RX_IDLE_
OS_WITHOUT_ACK_P
PCI_EXPRESS_RX_IDLE_
OS_WITHOUT_ACK_N
492
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_RX_TLPS_
AFTER_PM_P
PM_Request_Ack message
should not be issued when the
TL packets are outstanding.
PCI_EXPRESS_RX_TLPS_
OUTSTANDING_PM_P
PM_Enter_L1, PM_Enter_L23,
or
PM_Active_State_Request_L1
DLL packet should not be issued
when TL packets are
outstanding.
PCI_EXPRESS_TL_PKT_
AFTER_ACK_UPSTREAM_P
TL packets should not be issued Upstream ports should not receive any
once the PM_Request_Ack DLL TL packets after receiving a
packet is issued.
PM_Request_Ack DLL packet. This
check fires if a TL packet is received
after receiving a PM_Request_Ack DLL
packet.
PCI_EXPRESS_RX_TLPS_
AFTER_PM_P
PCI_EXPRESS_RX_TLPS_
OUTSTANDING_P
PCI_EXPRESS_RX_TLPS_
OUTSTANDING_N
PCI_EXPRESS_TL_PKT_
AFTER_ACK_UPSTREAM_N
Notes:
1. Checkers with a _P suffix are active on the rising edge of the clock. Those with an _N
suffix are active on the falling edge of the clock.
2. Power management checks are active when both link layer and transaction layer checks
are enabled.
Violation
Description
PIPE_16_BIT_COM_ON_
HIGH
PIPE_DECODE_ERR_NO_
EDB_SYM
493
PCI Express
Monitor Checks
Violation
Description
PIPE_DECODE_ERROR
PIPE_DISPARITY_ERROR
PIPE_EB_OVERERFLOW_
ERROR
PIPE_EB_UNDERFLOW_
ERROR
PIPE_ILLEGAL_POWER_
DOWN_COMMAND
PIPE_PHYSTATUS_
ASSERTED_MORE_
THAN_ONE_CLOCK
PIPE_PHYSTATUS_
DURING_RESET
PIPE_POWERDOWN_
DURING_RESET
PIPE_POWERDOWN_NOT_
P0_IN_L0
PowerDown should be P0 in L0
state.
PIPE_POWERDOWN_NOT_
P0s_IN_L0s
PIPE_POWERDOWN_NOT_
P1_IN_L1_L2_DETECT_
DISABLE
PowerDown should be P1 in
This check fires if other than P1
L1, L2, Detect, or Disable state. Powerdown is detected in L1, L2, detect,
or disable state.
PIPE_REC_DETECT_
PHYSTATUS_DEASSERTED
PIPE_REC_DETECT_
RXSTATUS_INVALID
494
PCI Express
Monitor Checks
Violation
Description
PIPE_RX_POLARITY_
During Reset#, RxPolarity
ASSERTED_DURING_RESET should be de-asserted.
PIPE_RX_POLARITY_IN_
OTHERTHAN_POL_CONFIG
PIPE_RXSTATUS_001_
NOT_ALIGN_WITH_COM
PIPE_RXSTATUS_010_
NOT_ALIGN_WITH_COM
PIPE_SKP_ADDED_
RXSTATUS_NOT_001
PIPE_SKP_REMOVED_
RXSTATUS_NOT_010
PIPE_TX_COMPLIANCE_
During Reset#, TxCompliance
ASSERTED_DURING_RESET should be de-asserted.
PIPE_TX_COMPLIANCE_
IN_OTHERTHAN_POL_
COMP
PIPE_TX_COMPLIANCE_
MORE_THAN_ONE_CLOCK
PIPE_TX_DETECT_RX_
ASSERTED
TxDetectRx/Loopback should
be asserted only when the PHY
is P1, P0 state.
PIPE_TX_DETECT_RX_
During Reset#,
ASSERTED_DURING_RESET TxDetectRxLoopback should
be de-asserted.
495
PCI Express
Monitor Checks
Violation
Description
PIPE_TX_DETECT_RX_
DEASSERT_ERROR
TxdetectRx/Loopback should
be de-asserted at the clock edge
where the PHY component
signals the completion of
receiver detection by asserting
PhyStatus for one clock.
PIPE_TX_ELECIDLE_
DEASSERTED_DURING_
RESET
PIPE_TXCOMPLIANCE_
RXPOLARITY_ASSERTED
PIPE_TXDETECTRX_
TXELECIDLE_ASSERTED
TxdetectRx/Loopback and
TxElecidle should not be
asserted together when the
PHY is in P0 state.
PIPE_TXELECIDLE_NOT_
ASSERTED
496
PCI Express
Monitor Checks
Violation
Description
PCI_EXPRESS_GEN2_EIE_
SYMBOL_IN_2_5_GT_P
PCI_EXPRESS_GEN2_EIE_
SYMBOL_IN_2_5_GT_N
PCI_EXPRESS_GEN2_EIE_
INCONSISTENT_IN_EIEOS_P
PCI_EXPRESS_GEN2_EIE_
IN_DLLP_TLP_N
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_TS2_P
Compliance Receive bit should Compliance receive bit can only be set in
not be set in TS2 OS.
TS1 OS. This bit is reserved in TS2. This
check fires if bit 4 of symbol 5 of TS2 is set
to 1.
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_TS2_N
PCI_EXPRESS_GEN2_
ILLEGAL_EIOS_COUNT_
ON_NON_2_5_GT_P
PCI_EXPRESS_GEN2_
ILLEGAL_EIOS_COUNT_
ON_NON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIEOS_WITHOUT_D10_2_
SYMBOL_P
PCI_EXPRESS_GEN2_
EIEOS_WITHOUT_D10_2_
SYMBOL_N
PCI_EXPRESS_GEN2_
MODIFIED_COMPLIANCE_
PATTERN_ERROR_P
PCI_EXPRESS_GEN2_
MODIFIED_COMPLIANCE_
PATTERN_ERROR_N
497
PCI Express
Monitor Checks
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_NON_POLLING_
STATE_P
PCI_EXPRESS_GEN2_
Minimum four EIE symbol
EIE_LT_4_BEFORE_FTS_ON_ should be transmitted before
NON_2_5_GT_P
FTS on a speed other than 2.5
GT/s while exiting L0s.
PCI_EXPRESS_GEN2_
EIE_LT_4_BEFORE_FTS_ON_
NON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIE_MT_8_BEFORE_FTS_
ON_NON_2_5_GT_P
PCI_EXPRESS_GEN2_
COMPLIANCE_RECEIVE_
SET_IN_NON_POLLING_
STATE_N
PCI_EXPRESS_GEN2_
DATA_RATE_CHANGE_IN_
CONFIG_COMPLETE_P
PCI_EXPRESS_GEN2_
DATA_RATE_CHANGE_IN_
CONFIG_COMPLETE_N
PCI_EXPRESS_GEN2_
EIE_MT_8_BEFORE_FTS_
ON_NON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIEOS_ILLEGAL_COUNT_P
PCI_EXPRESS_GEN2_
EIEOS_ILLEGAL_COUNT_N
PCI_EXPRESS_GEN2_
EIEOS_IN_ILLEGAL_
STATE_P
PCI_EXPRESS_GEN2_
EIEOS_IN_ILLEGAL_
498
PCI Express
Monitor Checks
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
Electrical Idle Exit sequence
EIEOS_NOT_SENT_BEFORE_ Ordered Set(EIEOS) should be
FIRST_TS1_P
transmitted before first TS1 OS
in Recovery.RcvrLk/
PCI_EXPRESS_GEN2_
Configuration.Linkwidth.Start
EIEOS_NOT_SENT_BEFORE_ on a speed greater than 2.5
FIRST_TS1_N
GT/s.
PCI_EXPRESS_GEN2_
EIEOS_ON_2_5_GT_P
PCI_EXPRESS_GEN2_
EIEOS_ON_2_5_GT_N
PCI_EXPRESS_GEN2_
EIOS_NOT_SENT_PRIOR_
TO_ENTERING_REC_
SPEED_P
PCI_EXPRESS_GEN2_
EIOS_NOT_SENT_PRIOR_
TO_ENTERING_REC_
SPEED_N
PCI_EXPRESS_GEN2_
ILLEGAL_RECO_SPEED_
TO_RECO_CFG_P
PCI_EXPRESS_GEN2_
ILLEGAL_RECO_SPEED_
TO_RECO_CFG_N
PCI_EXPRESS_GEN2_
ILLEGAL_SPEED_CHANGE_
BIT_IN_REC_CFG_P
PCI_EXPRESS_GEN2_
ILLEGAL_SPEED_CHANGE_
BIT_IN_REC_CFG_N
PCI_EXPRESS_GEN2_
ILLEGAL_SPEED_CHANGE_
BIT_IN_REC_LK_P
PCI_EXPRESS_GEN2_
ILLEGAL_SPEED_CHANGE_
BIT_IN_REC_LK_N
499
PCI Express
Monitor Checks
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
L1_IDLE_LT_40NS_ON_
SPEED_NOT_2_5_GT_P
PCI_EXPRESS_GEN2_
L1_IDLE_LT_40NS_ON_
SPEED_NOT_2_5_GT_N
PCI_EXPRESS_GEN2_
RECO_LK_NOT_ENTERED_
FROM_CONFIG_IDLE_P
PCI_EXPRESS_GEN2_
RECO_LK_NOT_ENTERED_
FROM_CONFIG_IDLE_N
PCI_EXPRESS_GEN2_
RECO_SPEED_ILLEGAL_
TRANSITION_P
PCI_EXPRESS_GEN2_
RECO_SPEED_ILLEGAL_
TRANSITION_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_
OTHER_DEVICE_NOT_
CAPABLE_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_
OTHER_DEVICE_NOT_
CAPABLE_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_NOT_
CAPABLE_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
INITIATED_WHEN_NOT_
CAPABLE_N
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
MISMATCH_P
PCI_EXPRESS_GEN2_
SPEED_CHANGE_
MISMATCH_N
500
PCI Express
Monitor Checks
Table 14-13. PCI Express Gen2 Link Training and Width Negotiation Checks
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
SPEED_CHNG_NOT_0_P
PCI_EXPRESS_GEN2_
SPEED_CHNG_NOT_0_N
PCI_EXPRESS_GEN2_
SPEED_CHNG_OTHER_
THAN_RECO_P
PCI_EXPRESS_GEN2_
SPEED_CHNG_OTHER_
THAN_RECO_N
PCI_EXPRESS_GEN2_
UPCONFIG_BIT_CHANGE_
IN_CONFIG_COMPLETE_P
PCI_EXPRESS_GEN2_
UPCONFIG_BIT_CHANGE_
IN_CONFIG_COMPLETE_N
PCI_EXPRESS_GEN2_
UPCONFIG_INITIATED_
WHEN_NOT_CAPABLE_P
PCI_EXPRESS_GEN2_
UPCONFIG_INITIATED_
WHEN_NOT_CAPABLE_N
Violation
Description
PCI_EXPRESS_GEN2_
CFG_REQ_AT_FIELD_
ERROR_P
PCI_EXPRESS_GEN2_
CFG_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
CPL_AT_FIELD_ERROR_P
PCI_EXPRESS_GEN2_
CPL_AT_FIELD_ERROR_N
501
PCI Express
Monitor Checks
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
ERROR_P
Deprecated TLP
types(TCfgRd/ TcfgWr) are
malformed and should not be
issued.
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
ERROR_N
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
LEGACY_END_POINT_P
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_
LEGACY_END_POINT_N
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_PCI_
EXPRESS_END_POINT_P
PCI_EXPRESS_GEN2_
DEPRECATED_TLP_PCI_
EXPRESS_END_POINT_N
PCI_EXPRESS_GEN2_
EP_BIT_VIOLATION_P
PCI_EXPRESS_GEN2_
EP_BIT_VIOLATION_N
PCI_EXPRESS_GEN2_
IGNORED_MSG_ROUTING_
NT_100_P
PCI_EXPRESS_GEN2_
IGNORED_MSG_ROUTING_
NT_100_N
PCI_EXPRESS_GEN2_
IO_REQ_AT_FIELD_
ERROR_P
PCI_EXPRESS_GEN2_
IO_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
MEM_REQ_ACS_
VIOLATION_P
PCI_EXPRESS_GEN2_
MEM_REQ_ACS_
VIOLATION_N
502
PCI Express
Monitor Checks
Table 14-14. PCI Express Gen2 Transaction Layer Transmit Checks (cont.)
Check ID
Violation
Description
PCI_EXPRESS_GEN2_
MSG_REQ_AT_FIELD_
ERROR_P
PCI_EXPRESS_GEN2_
MSG_REQ_AT_FIELD_
ERROR_N
PCI_EXPRESS_GEN2_
PME_2_ACK_MSG_NON_
RSVD_FN_NUMBER_P
PCI_EXPRESS_GEN2_
PME_2_ACK_MSG_NON_
RSVD_FN_NUMBER_N
PCI_EXPRESS_GEN2_
RX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_P
PCI_EXPRESS_GEN2_
RX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_N
PCI_EXPRESS_GEN2_
TX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_P
PCI_EXPRESS_GEN2_
TX_CPL_STATUS_NON_CA_
FOR_ACS_VIOLATED_
REQ_N
Violation
Description
PCI_EXPRESS_GEN2_
ILLEGAL_ROUTING_FOR_
NON_PME_TO_ACK_MSG_P
PCI_EXPRESS_GEN2_
ILLEGAL_ROUTING_FOR_
NON_PME_TO_ACK_MSG_N
503
PCI Express
Monitor Checks
Violation
Description
PIPE_GEN2_RATE_CHANGE_
IN_P1_P2
PIPE_GEN2_RATE_CHANGES_
WHEN_TXELECIDLE_
DEASSERTED
PIPE_GEN2_RATE_INVALID_
DURING_P1_P2
PIPE_GEN2_RATE_INVALID_
DURING_RESET
PIPE_GEN2_TXDEEMPH_
CHANGE_IN_P1_P2
PIPE_GEN2_TXELECIDLE_
DEASSERTED_BEFORE_
PHYSTATUS_ASSERTED_
DURING_RATE_CHANGES
PIPE_GEN2_TXMARGIN_
CHANGE_IN_P1_P2
504
PCI Express
Monitor Checks
Table 14-18 on page 506: PCI Express Compliance Checklist: Transaction Protocol
Table 14-19 on page 530: PCI Express Compliance Checklist: Link Protocol
Table 14-20 on page 538: PCI Express Compliance Checklist: Link-Physical Layer
Interface
Table 14-22 on page 567: PCI Express Compliance Checklist: Power Management
Table 14-23 on page 572: PCI Express Compliance Checklist: System Architecture
Table 14-25 on page 573: PCI Express Compliance Checklist: Isochronous Applications
The following tables show the checklist applicable for the respective PCI Express devices:
Table 14-27 on page 574: Checklist Applicable for End Point Only
Table 14-28 on page 589: Checklist Applicable for Root Complex Only
Monitor cannot check for initial minimum credit advertisement, because it is not
clear when to perform the checks and when to fire. Some checks relate to timing that
spans 8 us. Only after 8 us are firings possible. (e.g., TXN 6.1# 18, 19, 20, and 21.)
Most of the checks in the link training section cannot be performed because the
monitor changes its state on bus activity.
Monitor sits on the interface and it is not possible to track the events within the
device that do not appear on the interface.
505
PCI Express
Monitor Checks
TXN5.1#3 and TXN5.2#3 check whether or not the user has configured TC/VC
mapping properly.
TXN2.21#16 and TXN 2.21#18 are not performed as the monitor does not track the
device configuration.
Rule
Check ID
Violation
TPL.4.0#1
Monitor cannot
perform this check.
Rule
Check ID
Violation
Transaction Layer
Protocol Packet
Definition
TXN.2.0#2
PCI_EXPRESS_ NON_ZERO_
RESERVED_ FIELD
TXN.2.0#3
TXN.2.1#1
PCI_EXPRESS_IO_REQ_HDR_
LENGTH_ERROR
Common Packet
Header Fields
PCI_EXPRESS_CFG_REQ_
HDR_ LENGTH_ERROR
PCI_EXPRESS_MSG_REQ_
HDR_ LENGTH_ERROR
PCI_EXPRESS_ CPL_HDR_
LENGTH_ ERROR
TXN.2.1#2
506
PCI_EXPRESS_ UNDEFINED_
HEADER_FIELD
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.2.1#3
PCI_EXPRESS_NO_TLP_
DIGEST
TXN.2.1#4
PCI_EXPRESS_TLP_PKT_
SIZE_ ERROR
TXN.2.1#5
PCI_EXPRESS_
CPL_LENGTH_
FIELD_ ERROR
TXN.2.2#1
TXN.2.2#3
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
TXN.2.2#4
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
TXN.2.2#5
PCI_EXPRESS_
TLP_PKT_SIZE_ ERROR
TXN.2.2#6
PCI_EXPRESS_
MAX_PAYLOAD_
SIZE_ERROR
TXN.2.2#7
507
PCI Express
Monitor Checks
Address Based
Routing Rules
ID Based Routing
Rules
First/Last DW Byte
Enable Rules
508
Rule
Check ID
Violation
TXN.2.2#8
TXN.2.2#9
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR
TXN.2.2#10
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR
Note: Two address formats are specified, a 64-bit format used with a 4 DW Header and
a 32-bit format used with a 3 DW Header.
TXN.2.4#3
TXN.2.5#1
TXN.2.5#3
TXN.2.5#4
Note: Two address formats are specified, a 64-bit format used with a 4 DW Header and
a 32-bit format used with a 3 DW Header.
TXN.2.6#1
PCI_EXPRESS_
FIRST_DW_BE_
NON_ZERO_ ERROR
TXN.2.6#2
PCI_EXPRESS_
LAST_DW_BE_ ERROR
PCI Express
Monitor Checks
Transaction
Descriptor
Transaction ID
Field
Rule
Check ID
Violation
TXN.2.6#3
PCI_EXPRESS_
LAST_DW_BE_
NON_ZERO_ ERROR
TXN.2.6#4
TXN.2.6#5
TXN.2.6#7
TXN.2.6#8
TXN.2.7#1
TXN.2.7#2
PCI_EXPRESS_TAG_ FIELD_
ERROR
TXN.2.7#3
PCI_EXPRESS_TAG_ FIELD_
ERROR
TXN.2.7#5
509
PCI Express
Monitor Checks
Relaxed Ordering
Attribute
Rule
Check ID
Violation
TXN.2.7#7
TXN.2.7#13
TXN.2.8#1
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ERROR
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR
PCI_EXPRESS_MSG_REQ_
ATTR_FIELD_ERROR
No Snoop Attribute
TXN.2.9#1
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ERROR
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR
PCI_EXPRESS_MSG_REQ_
ATTR_FIELD_ERROR
Transaction
Descriptor Traffic
Class Field
TXN.2.10#1
TXN.2.11#1
PCI_EXPRESS_IO_REQ_
HDR_LENGTH_ERROR
PCI_EXPRESS_CFG_REQ_
HDR_LENGTH_ERROR
PCI_EXPRESS_MSG_REQ_
HDR_LENGTH_ERROR
510
TXN.2.11#2
TXN.2.11#3
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.2.11#4
PCI_EXPRESS_IO_REQ_
ATTR_FIELD_ ERROR
PCI_EXPRESS_IO_REQ_TC_
FIELD_ ERROR
PCI_EXPRESS_IO_REQ_
LENGTH_ FIELD_ERROR
0001b
Last DW BE[3:0] must be
0000b
TXN.2.11#5
PCI_EXPRESS_CFG_REQ_
HDR_LENGTH_ERROR
TXN.2.11#6
TXN.2.11#7
PCI_EXPRESS_CFG_REQ_
ATTR_FIELD_ERROR
PCI_EXPRESS_CFG_REQ_TC_
FIELD_ERROR
PCI_EXPRESS_CFG_REQ_
LENGTH_FIELD_ERROR
TXN.2.11#8
Message Request
Rules
Note: The following rules apply to all Baseline Message Group Requests.
511
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.2.12#1
PCI_EXPRESS_MSG_REQ_
HDR_LENGTH_ERROR
TXN.2.12#2
PCI_EXPRESS_UNDEFINED_
MSG_ CODE_ GROUP
TXN.2.12#3
TXN.2.12#4
PCI_EXPRESS_MSG_REQ_
ATTR_ FIELD_
TXN.2.12#5
TXN.2.12#6
TXN.2.12#7
TXN.2.13#7
PCI_EXPRESS_MSG_REQ_
TC_FIELD_ERROR
TXN.2.13#8
INTx Interrupt
Signaling Rules
512
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.2.13#11 PCI_EXPRESS_INTR_MSG_
CODE_ERROR
TXN.2.14#1
PCI_EXPRESS_PME_MSG_
CODE_ ERROR
TXN.2.14#2
PCI_EXPRESS_ MSG_TYPE_
ERROR
TXN.2.14#3
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR
TXN.2.14#4
PCI_EXPRESS_MSG_REQ_
TC_FIELD_ERROR
TXN.2.14#5
Error Signaling
Messages
TXN.2.15#1
PCI_EXPRESS_ERR_MSG_
CODE_ ERROR
Locked Transactions
Support
Note: The following rules apply to the formation of the Unlock Message.
Power Management
Messages
TXN.2.16#1
PCI_EXPRESS_LOCKED_
TRAN_ MESSAGE_CODE_
ERROR
TXN.2.16#2
PCI_EXPRESS_ MSG_TYPE_
ERROR
513
PCI Express
Monitor Checks
514
Rule
Check ID
Violation
TXN.2.16#3
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR
TXN.2.16#4
PCI_EXPRESS_MSG_REQ_
TC_ FIELD_ERROR
TXN.2.16#5
TXN.2.17#1
PCI_EXPRESS_SLOT_PWR_
MSG_ CODE_ERROR
Set_Slot_Power_Limit Messages
must comply with the encoding in
the PCI Express Base Specification
Table 2-17.
TXN.2.17#2
PCI_EXPRESS_SLOT_PWR_
MSG_ TYPE_ERROR
The Set_Slot_Power_Limit
Message includes a one DW data
payload (TLP Type is MsgD).
TXN.2.17#3
The Set_Slot_Power_Limit
message data payload must be
copied from the Slot Capabilities
Register of the Downstream Port
and is written into the Device
Capabilities Register of the
Upstream Port on the other side of
the Link. See exception,
TXN.2.17#4.
TXN.2.17#4
TXN.2.17#5
Set_Slot_Power_Limit Message:
Bits 9:8 of the data payload map to
the Slot Power Limit Scale field.
TXN.2.17#6
Set_Slot_Power_Limit Message:
Bits 7:0 of the data payload map to
the Slot Power Limit Value field.
PCI Express
Monitor Checks
Vendor Defined
Messages
Rule
Check ID
Violation
TXN.2.17#7
Set_Slot_Power_Limit Message:
Bits 31:10 of the data payload must
be set to all 0s by the transmitter.
TXN.2.17#8
Set_Slot_Power_Limit Message:
Bits 31:10 of the data payload must
be ignored by the receiver.
TXN.2.17#11 PCI_EXPRESS_MSG_REQ_
TC_FIELD_ ERROR
The Set_Slot_Power_Limit
Message must use the default
Traffic Class designator (TC0).
TXN.2.18#1
PCI_EXPRESS_MSG_REQ_
HDR_ LENGTH_ ERROR
TXN.2.18#2
TXN.2.18#3
TXN.2.18#4
TXN.2.18#5
TXN.2.18#6
TXN.2.18#7
TXN.2.18#8
515
PCI Express
Monitor Checks
Completion Rules
516
Rule
Check ID
Violation
TXN.2.18#9
TXN.2.19#1
PCI_EXPRESS_HOT_PLUG_
MSG_CODE_ERROR
TXN.2.19#2
TXN.2.19#3
TXN.2.19#4
PCI_EXPRESS_HOT_PLUG_
MSG_CODE_ERROR
TXN.2.21#1
TXN.2.21#2
PCI_EXPRESS_CPL_HDR_
LENGTH_ ERROR
TXN.2.21#3
TXN.2.21#4
PCI_EXPRESS_CPL_HDR_
LENGTH_ ERROR
TXN.2.21#5
TXN.2.21#6
PCI_EXPRESS_CPL_STATUS_
FIELD_ ERROR
PCI Express
Monitor Checks
Handling of Received
TLPs
Rule
Check ID
Violation
TXN.2.21#7
PCI_EXPRESS_CPL_STATUS_
FIELD_ERROR
TXN.2.21#8
TXN.2.21#21 PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
TXN.2.21#22 PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
TXN.3.0#1
PCI_EXPRESS_ NON_ZERO_
RESERVED_ FIELD_ERROR
TXN.3.0#2
TXN.3.0#3
517
PCI Express
Monitor Checks
Rule
Check ID
Violation
Request Handling
Rules
TXN.3.1#1
PCI_EXPRESS_ UNDEFINED_
HEADER_FIELD
TXN.3.1#2
TXN.3.1#3
TXN.3.1#6
TXN.3.1#8
TXN.3.1#9
TXN.3.1#10
TXN.3.1#11
PCI_EXPRESS_CPL_STATUS_
CSR_FOR_NONCFG_REQ
518
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.3.1#12
PCI_EXPRESS_CPL_STATUS_
CSR_FOR_NONCFG_REQ
TXN.3.2#3
PCI_EXPRESS_CPL_BYTE_
COUNT_ VALUE_ERROR
TXN.3.2#4
TXN.3.2#5
TXN.3.2#6
TXN.3.2#7
PCI_EXPRESS_MAX_
PAYLOAD_SIZE_ERROR
TXN.3.2#27
PCI_EXPRESS_MRD_CPL_LO
W_ADDR
TXN.3.2#33
519
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.3.2#35
Completion Handling
Rules
TXN.3.3#1
Transaction Ordering
NOTE: Conceptually, traffic that flows through VCs is multiplexed onto a common
physical Link resource on the transmit side and de-multiplexed into separate VC paths
on the receive side.
TXN.5.0#2
TXN.5.0#3
TXN.5.0#4
PCI_EXPRESS_TX_
COMPLETION_TC_ATTR_
MISMATCH
PCI_EXPRESS_RX_
COMPLETION_TC_ATTR _
MISMATCH
520
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.5.0#7
Virtual Channel
Identification (VC
ID)
TXN.5.1#1
TC to VC Mapping
TXN.5.2#1
VC and TC Rules
TXN.5.3#1
TXN.5.3#6
PCI_EXPRESS_TLP_
DOESNOT_
MAP_TO_ANY_VC
Ordering and
Receive Buffer Flow
Control
Note: The Flow Control mechanism is used by the Requester to track the queue/buffer
space available in the Agent across the Link.
TXN.6.0#3
TXN.6.1#2
521
PCI Express
Monitor Checks
522
Rule
Check ID
Violation
TXN.6.1#3
TXN.6.1#5
TXN.6.1#6
TXN.6.1#7
TXN.6.1#8
TXN.6.1#9
TXN.6.1#10
TXN.6.1#13
TXN.6.1#14
PCI_EXPRESS_FC_DLLP_IN_
DL_ACTIVE
TXN.6.1#15
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.6.1#16
PCI_EXPRESS_PD_CREDIT_
LIMIT_VIOLATION
PCI_EXPRESS_CPLH_
CREDIT_ LIMIT_VIOLATION
PCI_EXPRESS_CPLD_
CREDIT_ LIMIT_VIOLATION
TXN.6.1#17
PCI_EXPRESS_PD_CREDIT_
LIMIT_VIOLATION
PCI_EXPRESS_CPLH_
CREDIT_ LIMIT_VIOLATION
PCI_EXPRESS_CPLD_
CREDIT_ LIMIT_VIOLATION
TXN.6.1#18
TXN.6.1#19
TXN.6.1#20
PCI_EXPRESS_UFC_PH_INVL
PCI_EXPRESS_UFC_PD_INVL
PCI_EXPRESS_UFC_NPH_INV
L
PCI_EXPRESS_UFC_NPD_INV
L
PCI_EXPRESS_UFC_CPLH_IN
VL
PCI_EXPRESS_UFC_CPLD_IN
VL
523
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.6.1#21
PCI_EXPRESS_UFC_PH_INVL
PCI_EXPRESS_UFC_PD_INVL
PCI_EXPRESS_UFC_NPH_INV
L
PCI_EXPRESS_UFC_NPD_INV
L
PCI_EXPRESS_UFC_CPLH_IN
VL
PCI_EXPRESS_UFC_CPLD_IN
VL
FC Information
Tracked by
Transmitter
524
TXN.6.1#22
TXN.6.1#23
TXN.6.1#24
PCI_EXPRESS_TLP_USING_U
NIT_VC
TXN.6.1#25
Referring to TXN.6.1#22, if
UpdateFC DLLPs are sent, then the
credit value fields must be set to
zero and must be ignored by the
receiver.
TXN.6.2#1
CREDITS_CONSUMED is set to
all 0s at the Interface Initialization.
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.6.2#2
CREDITS_CONSUMED is
updated for each TLP the
Transaction Layer allows to pass
the Flow Control gate for
Transmission
CREDITS_CONSUMED :=
(CREDITS_CONSUMED +
Increment) modulo 2[Field Size] where [Field Size] is 8 for PH,
NPH, and CPLH and 12 for PD,
NPD and CPLD where Increment
is the size in FC credits of the
corresponding part of the TLP
passed through the gate.
TXN.6.2#4
CREDIT_LIMIT is undefined at
Interface Initialization.
TXN.6.2#5
TXN.6.2#6
TXN.6.2#7
TXN.6.2#8
PCI_EXPRESS_TX_PH_
CREDIT_LIMIT_ VIOLATION
PCI_EXPRESS_TX_NPH_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_TX_CPLH_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_TX_PD_
CREDIT_LIMIT_ VIOLATION
PCI_EXPRESS_TX_NPD_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_TX_CPLD_
CREDIT_ LIMIT_ VIOLATION
525
PCI Express
Monitor Checks
FC Information
Tracked by Receiver
526
Rule
Check ID
Violation
TXN.6.2#9
TXN.6.2#10
TXN.6.2#11
TXN.6.2#12
TXN.6.2#13
TXN.6.2#14
TXN.6.3#1
CREDITS_ALLOCATED is
initially set according to the buffer
size and allocation policies of the
Receiver.
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.6.3#2
CREDITS_ALLOCATED is
incremented as the Receiver
Transaction Layer makes additional
receive buffer space available as
follows:
CREDITS_ALLOCATED :=
CREDITS_ALLOCATED +
Increment) modulo 2[Field Size]
where [Field Size] is 8 for PH,
NPH, and CPLH and 12 for PD,
NPD, and CPLD
where Increment corresponds to the
credits made available.
TXN.6.3#3
TXN.6.3#4
CREDITS_RECEIVED (optional)
is the count of the total number of
FC units consumed by valid TLPs
Received since Flow Control
initialization.
TXN.6.3#6
TXN.6.3#7
TXN.6.3#8
527
PCI Express
Monitor Checks
Rule
Check ID
Violation
TXN.6.3#9
PCI_EXPRESS_RX_PH_
CREDIT_LIMIT_ VIOLATION
PCI_EXPRESS_RX_NPH_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_RX_CPLH_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_RX_PD_
CREDIT_LIMIT_ VIOLATION
PCI_EXPRESS_RX_NPD_
CREDIT_ LIMIT_ VIOLATION
PCI_EXPRESS_RX_CPLD_
CREDIT_ LIMIT_ VIOLATION
TXN.6.3#10
528
TXN.6.3#11
TXN.6.3#12
TXN.7.1#3
PCI Express
Monitor Checks
Error Forwarding
Usage Model
Rule
Check ID
TXN.7.1#4
TXN.7.1#6
TXN.7.1#7
TXN.7.1#8
TXN.7.1#9
TXN.7.1#10
TXN.7.1#11
TXN.7.2#1
TXN.7.2#2
TXN.7.2#3
TXN.7.2#4
Violation
529
PCI Express
Monitor Checks
Rule
Check ID
TXN.7.3#1
TXN.7.3#2
PCI_EXPRESS_POISONNED_T
LP
TXN.7.3#3
PCI_EXPRESS_POISONNED_T
LP
TXN.7.3#4
TXN.7.3#5
TXN.9.1#7
Transaction Layer
Behavior in
DL_Down Status
Violation
Rule
Check IDs
Violation
DLL.2.1#1
530
PCI Express
Monitor Checks
Rule
Check IDs
Violation
DLL.2.1#2
DLL.2.1#11
DLL.2.1#12
DLL.2.1#13
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN
DLL.2.1#14
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN
DLL.2.1#15
PCI_EXPRESS_DLP_
TLP_IN_DL_DOWN
DLL.2.1#16
DLL.2.1#17
DLL.2.1#18
DLL.2.1#19
DLL.2.1#20
DLL2.1#21
Flow Control
DLL.3.1#1
Initialization Protocol
531
PCI Express
Monitor Checks
532
Rule
Check IDs
Violation
DLL.3.1#2
PCI_EXPRESS_TLP_
IN_FC_INIT1
DLL.3.1#3
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT1
DLL.3.1#4
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT1
DLL.3.1#5
DLL.3.1#6
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT2
DLL.3.1#6.1
DLL.3.1#7
PCI_EXPRESS_FC_
DLLP_IN_FC_INIT2
DLL.3.1#8
DLL.3.1#9
DLL.3.1#10
PCI Express
Monitor Checks
Rule
Check IDs
Violation
DLL.4.1#1
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
DLL.4.1#2
PCI_EXPRESS_
RESERVED_
FIELD_ ERROR
DLL.4.1#3
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.4.1#4
PCI_EXPRESS_FC_
DLLP_IN_DL_ACTIVE
DLL.4.1#5
DLL.4.1#6
DLL.4.1#7
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
DLL.4.1#8
DLL.4.1#9
DLL.4.1#10
DLL.4.1#11
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
DLL.4.1#12
DLL.4.1#13
DLL.4.1#14
DLL.4.1#15
DLL.4.1#16
DLL.4.1#17
533
PCI Express
Monitor Checks
534
Rule
Check IDs
Violation
DLL.4.1#18
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
DLL.4.1#19
DLL.4.1#20
DLL.4.1#21
DLL.4.1#22
DLL.4.1#23
DLL.4.1#24
DLL.4.1#25
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
DLL.4.1#26
DLL.4.1#27
DLL.4.1#28
DLL.4.1#29
DLL.4.1#30
DLL.4.1#31
DLL.4.1#32
DLL.4.1#33
PCI Express
Monitor Checks
Rule
Check IDs
Violation
DLL.4.1#34
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.4.1#34.1
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.4.1#34.2
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.4.1#34.3
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.4.1#34.4
PCI_EXPRESS_DLL_
PKT_16BIT_CRC
DLL.5.2#1
DLL.5.2#1.1
DLL.5.2#1.2
PCI_EXPRESS_
REPLAY_NUM_
EXPIRED
DLL.5.2#1.3
DLL.5.2#2
PCI_EXPRESS_
REPLY_NUM_
EXPIRED
535
PCI Express
Monitor Checks
536
Rule
Check IDs
Violation
DLL.5.2#3
PCI_EXPRESS_FIRST_
TLP_AFTER_LINK_ UP
DLL.5.2#4
DLL.5.2#5
PCI_EXPRESS_MAX_
UNACKD_TLP
DLL.5.2#6
PCI_EXPRESS_SEQ_
NUM_AFTER_ NULL_
TLP
DLL.5.2#7
DLL.5.2#8
DLL.5.2#9
DLL.5.2#10
PCI_EXPRESS_
RETRY_TLP
DLL.5.2#12
DLL.5.2#13
DLL.5.2#14
PCI Express
Monitor Checks
Rule
Check IDs
Violation
DLL.5.2#15
DLL.5.2#16
PCI_EXPRESS_
UNDEFINED_
DLLP_ ENCODING
DLL.5.2#17
PCI_EXPRESS_
ACKNAK_SEQ_
NUM_ ERROR
DLL.5.2#18
DLL.5.2#19
DLL.5.2#20
PCI_EXPRESS_ TLP_
LINK_CRC
DLL.5.3#1
DLL.5.3#2
PCI_EXPRESS_NO_
NAK_DLLP_FOR_TLP
DLL.5.3#3
PCI_EXPRESS_INCR_
SEQ_NUM_TLP
537
PCI Express
Monitor Checks
Rule
Check IDs
Violation
DLL.5.3#4
PCI_EXPRESS_
ACKNAK_
TIMER_ EXPIRED
DLL.5.3#5
DLL.5.3#6
PCI_EXPRESS_ TLP_
LINK_CRC
DLL.5.4#1
PCI_EXPRESS_
RESERVED_
FIELD_ERROR
Rule
Check IDs
Violation
Symbol Encoding
PHY.2.1#1
PCI_EXPRESS_DISPARITY_
ERROR
PHY.2.1#2
PCI_EXPRESS_10B_
CODING_VIOLATION
538
PCI Express
Monitor Checks
Rule
Check IDs
Violation
Framing and
Application of
Symbols to Lanes
PHY.2.2#1
PCI_EXPRESS_TS1_NOT_
ALL_LANES
PCI_EXPRESS_TS2_NOT_
ALL_LANES
PCI_EXPRESS_FTS_NOT_
ALL_LANES
PCI_EXPRESS_SKP_NOT_
ALL_LANES
PCI_EXPRESS_IDL_NOT_
ALL_LANES
PHY.2.2#2
PCI_EXPRESS_END_
WITHOUT_STP_SDP
PHY.2.2#3
PCI_EXPRESS_END_
WITHOUT_STP_SDP
PHY.2.2#4
PCI_EXPRESS_STP_NOT_
FOLLOWED_BY_END_EDB
PHY.2.3#1
PHY.2.3#2
PHY.2.3#3
PCI_EXPRESS_NO_IDLE_
DATA
PHY.2.3#4
PHY.2.3#5
PCI_EXPRESS_NO_SDP_
STP_LANE0
539
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.3#6
PCI_EXPRESS_NO_SDP_
STP_LANE0
PHY.2.3#7
PCI_EXPRESS_MORE_
THAN_ONE_STP
PHY.2.3#8
PCI_EXPRESS_MORE_
THAN_ONE_SDP
PHY.2.3#9
PCI_EXPRESS_MORE_
THAN_ONE_STP
PCI_EXPRESS_MORE_
THAN_ONE_SDP
Data Scrambling
540
PHY.2.3#10
PCI_EXPRESS_PADDING_
ERROR
PHY.2.3#11
PCI_EXPRESS_NULL_TLP_
WITH_END
PHY.2.3#12
PHY.2.4#1
PHY.2.4#2
PHY.2.4#3
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.4#4
PHY.2.4#5
PHY.2.4#6
PHY.2.4#7
PHY.2.4#8
PHY.2.4#9
PCI_EXPRESS_SCRAMBLIN
G_DISABLE_ERROR
PHY.2.4#10
PHY.2.4#11
PHY.2.6#2
PHY.2.6#3
541
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.7#1
Not a check.
PHY.2.7#2
PHY.2.7#3
PCI_EXPRESS_FTS_
COUNT_ERROR
PHY.2.8#2
PCI_EXPRESS_FTS_
COUNT_ERROR
PHY.2.8#3
PCI_EXPRESS_SKP_OS_
NOT_XMTD
PCI_EXPRESS_SKP_OS_
NOT_RCVD
PHY.2.8#4
PCI_EXPRESS_NO_SKP_
AFTER_FTS
PHY.2.8#5
542
Yes
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.9#2
PHY.2.9#3
PHY.2.9#4
Fundamental Reset
PHY.2.10#1
PHY.2.10#2
PHY.2.10#3
PHY.2.10#4
PCI_EXPRESS_ILLEGAL_
DATA_RATE
543
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.11#2
PCI_EXPRESS_ILLEGAL_
LINK_WIDTH
PHY.2.12#2
PHY.2.12#3
PHY.2.12#4
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED
544
PHY.2.13#1
PCI_EXPRESS_ILLEGAL_
LINK_WIDTH
PHY.2.13#2
PHY.2.13#3
PHY.2.13#4
PHY.2.13#5
PCI Express
Monitor Checks
Rule
Check IDs
Violation
Lane-to-Lane
De-skew
PHY.2.14#1
PCI_EXPRESS_DESKEW_
LIMIT_EXCEEDED
PHY.2.14#2
PHY.2.14#3
PHY.2.15#1
PCI_EXPRESS_ILLEGAL_
DATA_RATE_IDENTIFIER
PCI_EXPRESS_ILLEGAL_
LINK_CONTROL_FIELD
PHY.2.15#2
PHY.2.16#1
PHY.2.16#1
PHY.2.17#1
In Detect.Quiet:
Transmitter is in Electrical Idle
state.
Generation 1 data rate is selected.
LinkUp=0.
PHY.2.17#2
PHY.2.17#3
Detect
545
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.17#4
PHY.2.17#5
PHY.2.17#6
PHY.2.17#7
PHY.2.17#8
PHY.2.18#1
PCI_EXPRESS_VALID_
LINK_NUM
PHY.2.18#2
PCI_EXPRESS_MIN_TS1_
COUNT_ERROR
Polling
546
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.18#3
After a 24 ms timeout in
Polling.Active, the LTSSM enters
Polling.Configuration if any Lane,
which detected a Receiver during
Detect, received 8 consecutive TS1 or
TS2 ordered-sets (or their
complement) with the Lane and Link
numbers set to PAD (K23.7), and a
minimum of 1024 TS1s are transmitted
after receiving one TS1;
and all lanes that detected a Receiver
during Detect have detected an exit
from Electrical Idle at least once since
entering Polling.
PHY.2.18#4
After a 24 ms timeout in
Polling.Active, the LTSSM enters
Polling.Compliance if at least one
Lanes Receiver, which detected a
Receiver during Detect, has never
detected an exit from Electrical Idle
since entering Polling.Active.
PHY.2.18#5
After a 24 ms timeout in
Polling.Active, the LTSSM enters
Detect if no TS1 or TS2 ordered-set is
received with Link and Lane number
set to Pad on any Lane. The highest
advertised speed in TS1 and TS2 is
lowered (unless generation 1 is the
highest advertised speed).
PHY.2.18#6
PHY.2.18#7
PHY.2.18#8
PHY.2.18#9
547
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.18#10 PCI_EXPRESS_TS2_
COUNT_ERROR
PHY.2.18#11 PCI_EXPRESS_TS2_
COUNT_ERROR
In Polling.Speed:
The transmitter enters Electrical
Idle for a minimum of TTX-IDLEMIN (see PCI Express Base
Specification Table 4-5) and no
longer than 2 ms.
Data rate is changed on all lanes to
the highest common data rate
supported on both sides of the
Link indicated by the training
sequence (see PCI Express Base
Specification Section 4.2.4.1).
The LTSSM then reverts back to
Polling.Active.
Configuration
548
PHY.2.19#1
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Disable if directed.
PHY.2.19#2
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Loopback if directed,
and the Transmitter is capable of being
a Loopback Master.
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.19#3
(Downstream Lanes) In
Configuration.Linkwidth.Start, where
a cross-link is supported, LTSSM exits
to Disable after all Lanes that detected
a Receiver during Detect and are
receiving TS1 ordered-sets with the
Disable Link bit asserted in 2
consecutive TS1 ordered-sets.
PHY.2.19#4
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Loopback if all Lanes
that detected a Receiver during Detect
receive the Loopback bit asserted in 2
consecutive TS1 ordered-sets on all
Lanes receiving a TS1 ordered-set.
PHY.2.19#5
PCI_EXPRESS_VALID_
LINK_NUM
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
Transmitter sends TS1 ordered-sets
with selected Link numbers and sets
Lane numbers to PAD (K23.7) on
Downstream Lanes that are in
Configuration.
PHY.2.19#6
(Downstream Lanes) In
Configuration.Linkwidth.Start, if any
Lanes first received at least one or
more TS1 ordered-sets with a Link and
Lane number set to PAD (K23.7), then
the next state is
Configuration.Linkwidth.Accept
immediately after any of those same
downstream Lanes receive 2
consecutive TS1 ordered-sets with a
non-PAD Link number that matches
any of the transmitted Link.
PHY.2.19#7
549
PCI Express
Monitor Checks
550
Rule
Check IDs
Violation
PHY.2.19#8
(Downstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Detect after a 24 ms
timeout.
PHY.2.19#9
(Upstream Lanes) In
Configuration.Linkwidth.Start, where
a cross-link is supported, the LTSSM
exits to Disable if directed (by a higher
Layer to assert the Disable Link bit
(TS1 and TS2) on all Lanes that
detected a receiver during Detect).
(Upstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Loopback if directed
(by a higher Layer to assert the
Loopback bit (TS1 and TS2) on all
Lanes that detected a receiver during
Detect), and the Transmitter is capable
of being a Loopback Master.
(Upstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Disable after any
Lanes (all Lanes in the optional case
where a cross-link is supported) that
detected a Receiver during Detect and
are receiving TS1 ordered-sets with the
Disable Link bit asserted in 2
consecutive TS1 ordered-sets.
(Upstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Loopback if all Lanes
that detected a Receiver during Detect,
that are also receiving TS1 ordered
sets, receive the Loopback bit asserted
in 2 consecutive TS1 ordered-sets.
PHY.2.19#13 PCI_EXPRESS_VALID_
LINK_NUM
(Upstream Lanes) In
Configuration.Linkwidth.Start, the
Transmitter sends out TS1 ordered-sets
with Link numbers and Lane numbers
set to PAD (K23.7) on Upstream Lanes
that detected a Receiver during Detect.
PCI Express
Monitor Checks
Rule
Check IDs
PHY.2.19#14 PCI_EXPRESS_
UPSTREAM_
PORT_STARTED_LINK_
WIDTH_NEG
Violation
(Upstream Lanes) In
Configuration.Linkwidth.Start, if any
Lanes receive 2 consecutive TS1
ordered sets with Link numbers that
are different than PAD (K23.7), a
single Link number is selected and
transmitted on all Lanes that both
detected a Receiver and also received
two consecutive TS1 ordered sets with
Link numbers that are different than
PAD (K23.7) and Lane number is set
to PAD (K23.7). Any leftover Lanes
that detected a Receiver during Detect
must transmit TS1 ordered-sets with
the Link and Lane number set to PAD
(K23.7). The next state is
Configuration.Linkwidth.Accept.
Optionally, if cross-links are supported
and all Upstream Lanes first receive 2
consecutive TS1 ordered set with Link
and Lane numbers set to PAD (K23.7),
then the following:
The Transmitter continues to send
out TS1 ordered-sets with Link
numbers and Lane numbers set to
PAD (K23.7).
If any Lanes receive 2 consecutive
TS1 ordered sets with Link
numbers that are different than
PAD (K23.7), then a single Link
number is selected and transmitted
on all Lanes that both detected a
Receiver and also received two
consecutive TS1 ordered sets with
Link numbers that are different
than PAD (K23.7) and Lane
number is set to PAD (K23.7).
Any left over Lanes that detected a
Receiver during Detect must
transmit TS1 ordered-sets with the
Link and Lane number set to PAD
(K23.7). The next state is
Configuration.Linkwidth.Accept.
Otherwise, after a Tcrosslink
timeout the Upstream Lanes
become Downstream Lanes and
the next state is
Configuration.Linkwidth.Start as
Downstream Lanes.
551
PCI Express
Monitor Checks
552
Rule
Check IDs
Violation
(Upstream Lanes) In
Configuration.Linkwidth.Start, the
LTSSM exits to Detect after a 24 ms
timeout.
PHY.2.19#16 PCI_EXPRESS_ILLEGAL_
LANE_NUMBER_
ASSIGNED
(Downstream Lanes) In
Configuration.Linkwidth.Accept, if a
configured Link can be formed with at
least one group of Lanes that received
2 consecutive TS1 ordered-sets with
the same received Link number (nonPAD and matching one that was
transmitted by the Downstream
Lanes), then TS1 ordered sets are
transmitted with the same Link number
and unique non-PAD Lane numbers
are assigned to all these same Lanes
NOTE: The assigned non-PAD Lane
numbers must range from 0 to n 1, be
assigned sequentially to the same
grouping of Lanes that are receiving
the same Link numbers, and
Downstream Lanes that are not
receiving TS1 ordered sets must not
disrupt the initial sequential numbering
of the widest possible Link.
Any leftover Lanes must transmit TS1
ordered sets with the Link and Lane
number set to PAD (K23.7). The
LTSSM then enters
Configuration.Lanenum.Wait.
(Downstream Lanes) In
Configuration.Linkwidth.Accept, the
LTSSM exits to Detect after a 2 ms
timeout or if no Link can be configured
or if all Lanes receive 2 consecutive
TS1 ordered-sets with Link and Lane
numbers set to PAD (K23.7).
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.19#18 PCI_EXPRESS_ILLEGAL_
LANE_NUMBER_
ASSIGNED
(Upstream Lanes) In
Configuration.Linkwidth.Accept, if a
configured Link can be formed using
Lanes that transmitted a non-PAD Link
number which are receiving 2
consecutive TS1 ordered-sets with the
same (non-PAD) Link number and any
non-PAD Lane number, then TS1 Lane
numbers are transmitted that if possible
match the received Lane numbers or
are different if necessary (i.e., lanereversed).
NOTE: the newly assigned transmitted
Lane numbers must range from 0 to
m-1, be assigned sequentially only to
some continuous grouping of Lanes
that are receiving non-PAD Lane
numbers (i.e., Lanes which are not
receiving any TS1 ordered sets always
disrupt a continuous grouping and
must not be included in the grouping),
must include either Lane 0 or n-1
(largest received Lane number), and
m-1 must be equal to or smaller than
the largest received Lane number
(n-1).
Remaining Lanes must transmit TS1
with Link and Lane numbers set to
PAD (K23.7). The LTSSM then enters
Configuration.Lanenum.Wait.
(Upstream Lanes) In
Configuration.Linkwidth.Accept, the
LTSSM exits to Detect after a 2 ms
timeout or if no Link can be configured
or if all Lanes receive 2 consecutive
TS1 ordered-sets with Link and Lane
numbers set to PAD (K23.7).
(Downstream Lanes) In
Configuration.Lanenum.Wait, the
LTSSM enters
Configuration.Lanenum.Accept if any
of the Lanes receive 2 consecutive TS1
that have a Lane number different from
when it first entered
Configuration.Lanenum.Wait, and not
all the Lanes Link numbers are set to
PAD (K23.7).
553
PCI Express
Monitor Checks
554
Rule
Check IDs
Violation
(Downstream Lanes) In
Configuration.Lanenum.Wait, the
LTSSM exits to Detect after a 2 ms
timeout or if all Lanes receive 2
consecutive TS1 ordered-sets with
Link and Lane numbers set to PAD
(K23.7).
(Upstream Lanes) In
Configuration.Lanenum.Wait, the
LTSSM transitions to
Configuration.Lanenum.Accept if the
following:
Any of the Lanes receive 2
consecutive TS1 that have a Lane
number different from when it first
entered
Configuration.Lanenum.Wait, and
not all the Lanes Link numbers
are set to PAD (K23.7), or
Any Lane receives 2 consecutive
TS2 ordered-sets.
(Upstream Lanes) In
Configuration.Lanenum.Wait, the
LTSSM exits to Detect after a 2 ms
timeout or if all Lanes receive 2
consecutive TS1 ordered-sets with
Link and Lane numbers set to PAD
(K23.7).
(Downstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM enters
Configuration.Complete if two
consecutive TS1 ordered-sets are
received with non-PAD Link and nonPAD Lane numbers (or reversed Lane
numbers if Lane reversal is optionally
supported) that are being transmitted in
Downstream Lane TS1 ordered-sets.
(Downstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM transmits TS1 ordered-sets
with new Lane numbers assigned and
enters Configuration.Lanenum.Wait if
a configured Link can be formed with
any subset of the Lanes that receive
two consecutive TS1 ordered sets with
the same transmitted non-PAD Link
numbers and any non-PAD Lane
numbers.
PCI Express
Monitor Checks
Rule
Check IDs
Violation
(Downstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM exits to Detect if no Link can
be configured or if all Lanes receive 2
consecutive TS1 ordered-sets with
Link and Lane numbers set to PAD
(K23.7).
(Upstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM enters
Configuration.Complete if two
consecutive TS2 ordered-sets are
received with non-PAD Link and nonPAD Lane numbers that match all nonPAD Link and non-PAD Lane
numbers that are being transmitted in
Upstream Lane TS1 ordered-sets.
(Upstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM transmits TS1 ordered-sets
with new Lane numbers assigned and
enters Configuration.Lanenum.Wait if
a configured Link can be formed with
any subset of the Lanes that receive
two consecutive TS1 ordered-sets with
the same transmitted non-PAD Link
numbers and any non-PAD Lane
numbers.
(Downstream Lanes) In
Configuration.Lanenum.Accept, the
LTSSM exits to Detect if no Link can
be configured or if all Lanes receive 2
consecutive TS1 ordered-sets with
Link and Lane numbers set to PAD
(K23.7).
555
PCI Express
Monitor Checks
556
Rule
Check IDs
Violation
(Downstream Lanes) In
Configuration.Complete,
TS2 ordered-sets are transmitted
using Link and Lane numbers that
match the received TS1 Link and
Lane numbers.
N_FTS must be noted for use in
L0s when leaving this state.
Lane-to-Lane de-skew must be
completed when leaving this state.
Scrambling is disabled if all
configured Lanes have the Disable
Scrambling bit asserted in 2
consecutively-received TS2
ordered-sets.
PHY.2.19#31 PCI_EXPRESS_ILLEGAL_
IDLE_DATA
(Downstream Lanes) In
Configuration.Complete, the LTSSM
transitions to Configuration.Idle
immediately after all Lanes that are
transmitting TS2 ordered-sets receive 8
consecutive TS2 ordered-sets with
matching Lane and Link numbers
(non-PAD) and 16 TS2 ordered-sets
are sent after receiving one TS2
ordered-set.
(Downstream Lanes) In
Configuration.Complete, the LTSSM
exits to Detect after a 2 ms timeout.
(Upstream Lanes) In
Configuration.Complete,
TS2 ordered-sets are transmitted
using Link and Lane numbers that
match the received TS2 Link and
Lane numbers.
N_FTS must be noted for use in
L0s when leaving this state.
Lane-to-Lane de-skew must be
completed when leaving this state.
Scrambling is disabled if all
configured Lanes have the Disable
Scrambling bit asserted in 2
consecutively received TS2
ordered-sets.
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.19#34 PCI_EXPRESS_ILLEGAL_
IDLE_DATA
(Upstream Lanes) In
Configuration.Complete, the LTSSM
transitions to Configuration.Idle
immediately after all Lanes that are
transmitting TS2 ordered-sets receive 8
consecutive TS2 ordered-sets with
matching Lane and Link numbers
(non-PAD) and 16 TS2 ordered-sets
are sent after receiving one TS2
ordered-set.
(Upstream Lanes) In
Configuration.Complete, the LTSSM
exits to Detect after a 2 ms timeout.
Recovery
PHY.2.20#1
PCI_EXPRESS_TS1_NOT_
ALL_LANES
PHY.2.20#2
PCI_EXPRESS_ILLEGAL_
TS2_OS
557
PCI Express
Monitor Checks
558
Rule
Check IDs
Violation
PHY.2.20#3
In Recovery.RcvrLock, after a 24 ms
timeout, the LTSSM reverts to
Configuration if all the configured
Lanes that are receiving a TS1 or TS2
ordered-set have received at least one
TS1 or TS2 with Link and Lane
numbers that match what is being
transmitted on those same Lanes.
Otherwise, the LTSSM reverts to
Detect.
PHY.2.20#4
PCI_EXPRESS_TS2_NOT_
ALL_LANES
PHY.2.20#5
PCI_EXPRESS_ILLEGAL_
IDLE_DATA
PHY.2.20#6
PHY.2.20#7
PHY.2.20#8
PHY.2.20#9
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.20#16 PCI_EXPRESS_IDLE_
DATA_NOT_ALL_LANES
PHY.2.20#17 PCI_EXPRESS_IDLE_
COUNT_ERROR
L0
PHY.2.21#1
In L0, LinkUp = 1.
PHY.2.21#2
559
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.21#3
PHY.2.21#4
PHY.2.21#5
PHY.2.21#6
PHY.2.21#7
PHY.2.22#1
PHY.2.22#2
PHY.2.22#3
PCI_EXPRESS_SKP_NOT_
ALL_LANES
PHY.2.22#4
PHY.2.22#5
PHY.2.22#6
PHY.2.22#7
L0s
560
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.22#8
PCI_EXPRESS_FTS_
COUNT_ERROR
PHY.2.23#1
PHY.2.23#2
PHY.2.23#3
PHY.2.23#4
PHY.2.24#1
PHY.2.24#2
PHY.2.24#3
PHY.2.24#4
PHY.2.24#5
PHY.2.24#6
L1
L2
561
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.24#7
PHY.2.24#8
PHY.2.25#1
PCI_EXPRESS_DISABLE_
OS_ERROR
PHY.2.25#2
PHY.2.25#3
PHY.2.26#1
PHY.2.26#2
PHY.2.26#3
PHY.2.26#4
PCI_EXPRESS_CODE_
VIOLATION_LOOPBACK
In Loopback.Active, the
Loopback.Master must send valid
8b/10b characters and enter
Loopback.Exit if directed.
Disabled
Loopback
562
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.26#5
PHY.2.26#6
PHY.2.26#7
563
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PHY.2.26#8
In Loopback.Exit:
The Loopback Master sends an
Electrical Idle ordered-set and
enters Electrical Idle on all Lanes
for a minimum of 2 ms.
The Loopback Master must
transition to a valid Electrical Idle
condition on all Lanes within
TTX-IDLE-SET-TO-IDLE after
sending the Electrical Idle
ordered-set.
The Loopback Slave must enter
Electrical Idle on all Lanes for a
minimum of 2 ms. NOTE: Before
entering Electrical Idle, the
Loopback Slave must Loopback
all Symbols that were received
prior to detecting Electrical Idle.
The Loopback Master and Slave
then exit to Detect.
Hot Reset
PHY.2.27#1
564
PCI Express
Monitor Checks
Clock Tolerance
Compensation
Rule
Check IDs
Violation
PHY.2.27#2
PHY.2.28#1
PHY.2.28#2
PHY.2.28#3
PCI_EXPRESS_SKP_NOT_
ALL_LANES
PHY.2.28#4
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR
PHY.2.28#5
PCI_EXPRESS_SKP_OS_
NOT_XMTD
565
PCI Express
Monitor Checks
566
Rule
Check IDs
Violation
PHY.2.28#6
PCI_EXPRESS_SKP_OS_
NOT_XMTD
PHY.2.28#7
PHY.2.28#8
PCI_EXPRESS_SKP_
ORDERED_SET_ERROR
PHY.2.28#9
PCI_EXPRESS_SKP_OS_
NOT_RECEIVED
PCI Express
Monitor Checks
Rule
Check IDs
Violation
Compliance Pattern
PHY.2.29#1
PHY.2.29#2
PCI_EXPRESS_
COMPLIANCE_
PATTERN_ERROR
PHY.2.29#4
PHY.2.29#5
Rule
Check IDs
PHY.3.1#1 to PHY.3.4#11
Violation
Rule
Check IDs
Violation
PMG.1.0#1
PMG.2.0#11
PMG.3.7#1
567
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.3.7#2
PMG.1.1#2
PMG.2.0#1
PMG.2.0#2
PMG.2.0#3
PCI_EXPRESS_TLP_IN_L0S
PCI_EXPRESS_DLLP_IN_L0S
General L1
Requirements
PMG.2.0#4
PCI_EXPRESS_TLP_IN_L1
PCI_EXPRESS_DLLP_IN_L1
General L2/L3
Ready, L2, and L3
Requirements
PMG.2.0#5
PMG.2.0#8
PMG.2.0#9
PCI_EXPRESS_TLP_IN_L2
PCI_EXPRESS_DLLP_IN_L2
PMG.2.0#10
PMG.2.0#15
PCI_EXPRESS_TLP_IN_L2
PCI_EXPRESS_DLLP_IN_L2
568
PMG.2.0#16
PMG.2.0#19
PCI Express
Monitor Checks
Rule
Check IDs
Violation
Device Power
Management States
(D-States)
PMG.3.1#1
PMG.3.2#1
PMG.3.2#2
PMG.3.2#3
PMG.3.3#1
PMG.3.3#3
PMG.3.4#2
PMG.3.4#3
PMG.3.5#1
PMG.3.5#2
PMG.3.5#3
PMG.3.6#1
PMG.3.6#2
569
PCI Express
Monitor Checks
General
Requirements for
Software Control of
the Link Power
Management State
Rule
Check IDs
Violation
PMG.3.6#3
PMG.3.8#9
PME
Synchronization
Before Power
Removal
PMG.3.13#2
PCI_EXPRESS_PME_ACK_
WITHOUT_TURN_OFF
Additional PME
Rules
PMG.3.15#1
PMG.3.15#2
PMG.4.1#1
PMG.4.1#2
570
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.4.2#1
PMG.4.2#2
PMG.4.3#1
PMG.4.3#2
PMG.4.4#1
PMG.4.4#4
If a PM_Active_State_Request_L1
DLLP is sent and refused, then the
Link must enter L0s ASAP if the
L0s entry conditions are met.
PMG.4.7#9
PCI_EXPRESS_L0S_ENTRY_
WHEN_DISABLED
PMG.4.7#10
Auxiliary Power
Support
PMG.5.1#2
Power Management
and System
Messages and
DLLPs
PMG.6.0#1
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR
PMG.6.0#2
PCI_EXPRESS_MSG_REQ_
ATTR_FIELD_ERROR
571
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.6.0#4
PMG.6.0#5
PCI_EXPRESS_MSG_REQ_
TC_FIELD_ERROR
Rule
Check IDs
Interrupt Support
Requirements
SYS.1.1#2 to
SYS.1.2#4
General Error
Reporting
Requirements
SYS.2.1#1 to
SYS.2.3#1
Error Logging
Requirements
SYS.2.4#1 to
SYS.2.6#1
SYS.2.7#1 to
SYS.2.7#24
PCI Mapping
SYS.2.8#1,2,3
Isochronous
Support Rules for
Software
Configuration
SYS.3.3#2 to
SYS.3.4#2
Isochronous
Rules for
Requesters
SYS.3.4#1,2
Isochronous
Rules for
Completers
SYS.3.5#3, 4
Device
Synchronization
SYS.4.0#1 to
SYS.4.0#5
SYS.5.1#3
PCI_EXPRESS_CPL_LK_
REQ_ ROOT_COMPLEX
SYS.5.2#2
Initiation and
Propagation of
Locked
Transactions
572
Violation
PCI Express
Monitor Checks
Rule
Check IDs
Violation
SYS.5.2#3
SYS.5.2#6
PCI_EXPRESS_NO_LOCKED_
COMPLETION_FOR_
LOCKED_REQ
SYS.5.6#1
SYS.5.6#2
SYS.5.6#3
SYS.5.7#1
PCI_EXPRESS_CPL_LK_
REQ_PCI_EXPRESS_
ENDPOINT
PCI Express
Reset - Rules
SYS.6.0.#1,2,3
PCI Express
Native Hot Plug
Support
SYS.7.3#1 to
SYS.7.9#1
Rule
Check IDs
CFG.1.0#1 to CFG.13.4#1
Violation
Rule
Check IDs
Violation
573
PCI Express
Monitor Checks
Rule
Check IDs
EM.6#4
Violation
Rule
Check IDs
Violation
DLL.4.1#1
PCI_EXPRESS_RESERVED_
FIELD_ERROR
TPL.3.2#1
PCI_EXPRESS_CFG_REQ_
PCI_ EXPRESS_ END_POINT
TPL.3.2#2
PCI_EXPRESS_LOCK_REQ_
PCI_EXPRESS_ END_POINT
TPL.3.3#1
PCI_EXPRESS_CFG_REQ_
PCI_ EXPRESS_ END_POINT
TPL.3.3#2
TPL.3.3#3
PCI_EXPRESS_IO_ REQ_
PCI_ EXPRESS_ END_POINT
TPL.3.3#4
PCI_EXPRESS_LOC_REQ_
PCI_EXPRESS_END_ POINT
PCI_EXPRESS_CPL_LK_REQ_
PCI_ EXPRESS_END_ POINT
TPL.4.0#1
TXN.2.3#1
PCI_EXPRESS_NO_TLP_
DIGEST
PCI_EXPRESS_TLP_PKT_
SIZE_ERROR
574
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.3#2
PCI_EXPRESS_NO_TLP_
DIGEST
PCI_EXPRESS_TLP_PKT_
SIZE_ ERROR
TXN.2.3#3
TXN.2.3#5
PCI_EXPRESS_ ECRC_ERROR
TXN.2.4#1
PCI_EXPRESS_ ADDRESS_
FORMAT_ERROR
TXN.2.4#2
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
TXN.2.6#6
TXN.2.6#9
PCI_EXPRESS_CPL_LEN_NT_
1DW_FOR_FLUSH_REQ
575
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.6#10
TXN.2.6#11
PCI_EXPRESS_NON_CONTIG
UOUS_FIRST_DW_BE_ERROR
_FOR_LEN_EQ_2DW_NON_Q
W_ALLIGNED
PCI_EXPRESS_NON_CONTIG
UOUS_LAST_DW_BE_ERROR
_FOR_LEN_EQ_2DW_NON_Q
W_ALLIGNED
576
TXN.2.6#12
TXN.2.7#4
TXN.2.7#6
TXN.2.7#8
TXN.2.7#9
PCI_EXPRESS_INVALID_REQ
_ID
TXN.2.7#10
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.7#11
PCI_EXPRESS_TLP_BEFORE_
INIT_CONFIG_WRITE
TXN.2.11#9
PCI_EXPRESS_ILLEGAL_
ADDRESS_ LENGTH_
COMBINATION
TXN.2.11#10
PCI_EXPRESS_MAX_READ_
REQ_SIZE_ ERROR
TXN.2.13#3
PCI_EXPRESS_ MSG_TYPE_
ERROR
Assert_INTx/Deassert_INTx Messages
do not include a data payload (TLP Type
field encoding is Msg).
TXN.2.13#4
PCI_EXPRESS_ MSG_TYPE_
ERROR
TXN.2.13#6
TXN.2.13#9
TXN.2.13#12
TXN.2.13#14
577
PCI Express
Monitor Checks
578
Rule
Check IDs
Violation
TXN.2.13#17
TXN.2.13#18
TXN.2.13#22
TXN.2.15#1
PCI_EXPRESS_ERR_MSG_
CODE_ ERROR
TXN.2.15#2
PCI_EXPRESS_ MSG_TYPE_
ERROR
TXN.2.15#3
PCI_EXPRESS_MSG_REQ_
LENGTH_FIELD_ERROR
TXN.2.15#4
PCI_EXPRESS_MSG_REQ_
TC_FIELD_ERROR
TXN.2.21#10
TXN.2.21#11
TXN.2.21#12
PCI_EXPRESS_MRD_CPL_LO
W_ADDR
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.21#13
PCI_EXPRESS_CPL_LWR_
ADDRESS_ VALUE_ERROR
TXN.2.21#14
TXN.2.21#15
PCI_EXPRESS_INVALID_CO
MPLETER_ID
TXN.2.21#16
TXN.2.21#19
PCI_EXPRESS_
COMPLETION_TC_ATTR_
MISMATCH
TXN.3.1#4
TXN.3.1#5
TXN.3.2#1
TXN.3.2#2
TXN.3.2#11
579
PCI Express
Monitor Checks
580
Rule
Check IDs
Violation
TXN.3.2#12
TXN.3.2#13
TXN.3.2#14
TXN.3.2#15
TXN.3.2#16
TXN.3.2#17
TXN.3.2#18
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.3.2#19
TXN.3.2#21
TXN.3.2#23
TXN.3.2#25
TXN.3.2#32
PCI_EXPRESS_ CPLD_FOR_
UNSUCCESFUL_ CPL
TXN.3.2#36
TXN.3.2#36
TXN.3.3#1
581
PCI Express
Monitor Checks
582
Rule
Check IDs
Violation
TXN.3.3#2
PCI_EXPRESS_
COMPLETION_
WITHOUT_ REQUEST
TXN.3.3#3
TXN.3.3#5
PCI_EXPRESS_CPL_STATUS_
CSR_FOR_ NONCFG_REQ
TXN.3.3#6
PCI_EXPRESS_CPL_STATUS_
FIELD_ ERROR
TXN.5.1#1
TXN.5.1#2
TXN.5.1#3
TXN.5.2#1
TXN.5.2#3
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.6.3#5
CREDITS_RECEIVED is updated as
follows:
CREDITS_RECEIVED
:CREDITS_RECEIVED (optional) is the
count of the total number of FC units
consumed by valid TLPs Received since
Flow Control initialization.
(CREDITS_ RECEIVED + Increment)
modulo 2[Field Size]
where [Field Size] is 8 for
PCREDITS_RECEIVED (optional)
is the count of the total number of FC
units consumed by valid TLPs
received since Flow Control
initialization H, NPH, and CPLH and
12 for PD, NPD, and CPLD, where
Increment corresponds to the credits
received.
TXN.7.1#1
PCI_EXPRESS_NO_TLP_
DIGEST
TXN.8.0#1
TXN.8.0#2
PCI_EXPRESS_COMPLETION
_TIMEOUT
TXN.8.0#3
PCI_EXPRESS_COMPLETION
_TIMEOUT
TXN.8.0#4
TXN.8.0#5
583
PCI Express
Monitor Checks
584
Rule
Check IDs
Violation
TXN.8.0#6
TXN.9.1#8
PMG.2.0#7
PMG.3.3#2
PMG.3.4#1
PMG.3.8#1
PMG.3.8#2
PMG.3.8#3
PMG.3.8#4
PMG.3.8#5
PMG.3.8#6
PMG.3.8#7
PMG.3.8#8
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.3.8#10
PMG.3.8#11
PMG.3.8#12
PMG.3.8#13
PMG.3.9#1
PMG.3.9#2
PMG.3.9#3
PCI_EXPRESS_TLPS_
AFTER_PM
585
PCI Express
Monitor Checks
586
Rule
Check IDs
Violation
PMG.3.9#6
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK
PMG.3.9#8
PMG.3.9#9
PMG.3.11#1
PMG.3.12#2
PMG.3.12#3
PMG.3.12#6
PMG.3.12#7
PMG.3.13#4
PMG.3.14#3
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.3.15#4
PMG.4.1#3
PMG.4.1#4
PMG.4.1#5
PMG.4.5#4
PMG.4.5#5
PCI_EXPRESS_TLPS_
OUTSTANDING
PMG.4.5#7
PMG.4.5#8
PCI_EXPRESS_TLPS_
AFTER_PM
PMG.4.5#9
PMG.4.5#10
Before sending a
PM_Request_Ack_DLLP downstream,
an upstream component must acquire the
minimum number of credits required to
send the largest possible packet for any
FC type.
587
PCI Express
Monitor Checks
588
Rule
Check IDs
Violation
PMG.4.5#13
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK
When a PM_Request_Ack_DLLP is
detected on its receive lanes, the
PM_Active_State_Request_L1_DLLP
must cease being sent and the link layer
must be disabled, an electrical idle
ordered set sent, and the transmit lanes
brought into the electrical idle state.
PMG.4.5#16
PMG.4.5#17
PMG.4.7#2
PMG.4.7#3
PMG.4.7#4
PMG.4.7#6
PMG.4.7#8
PMG.6.0#3
SYS.5.1#1
PCI_EXPRESS_LOCKED_
REQ_PCI_EXPRESS_END_
POINT
SYS.5.1#2
PCI Express
Monitor Checks
Rule
Check IDs
Violation
SYS.5.2#4
Rule
Check IDs
Violation
DLL.4.1#1
PCI_EXPRESS_RESERVED_
FIELD_ERROR
TXN.2.3#1
PCI_EXPRESS_NO_
TLP_DIGEST
PCI_EXPRESS_
TLP_PKT_SIZE_ERROR
TXN.2.3#2
PCI_EXPRESS_NO_
TLP_DIGEST
TXN.2.3#3
TXN.2.3#5
PCI_EXPRESS_ ECRC_ERROR
TXN.2.4#1
PCI_EXPRESS_ ADDRESS_
FORMAT_ERROR
TXN.2.4#2
PCI_EXPRESS_IO_REQ_
HDR_ LENGTH_ERROR
589
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.6#9
PCI_EXPRESS_CPL_LEN_NT_1
DW_FOR_FLUSH_REQ
TXN.2.6#10
TXN.2.6#11
PCI_EXPRESS_NON_CONTIGU
OUS_FIRST_DW_BE_ERROR_F
OR_LEN_MT_2DW
PCI_EXPRESS_NON_CONTIGU
OUS_LAST_DW_BE_ERROR_F
OR_LEN_MT_2DW
590
TXN.2.6#12
PCI_EXPRESS_CPL_LEN_NT_1
DW_FOR_FLUSH_REQ
TXN.2.7#4
TXN.2.7#9
TXN.2.7#10
TXN.2.7#11
PCI_EXPRESS_TLP_BEFORE_I
NITIAL_CONFIG_WRITE
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.11#9
PCI_EXPRESS_ILLEGAL_
ADDRESS_ LENGTH_
COMBINATION
TXN.2.11#10
PCI_EXPRESS_MAX_READ_
REQ_SIZE_ ERROR
TXN.2.13#9
TXN.2.13#22
TXN.2.15#1
PCI_EXPRESS_ERR_ MSG_
CODE_ ERROR
TXN.2.15#2
PCI_EXPRESS_ MSG_TYPE_
ERROR
TXN.2.15#3
PCI_EXPRESS_MSG_ REQ_
LENGTH_FIELD_ERROR
TXN.2.21#10
TXN.2.21#11
591
PCI Express
Monitor Checks
592
Rule
Check IDs
Violation
TXN.2.21#12
PCI_EXPRESS_MRD_CPL_LOW
_ADDR
TXN.2.21#13
PCI_EXPRESS_CPL_LWR_
ADDRESS_ VALUE_ERROR
TXN.3.1#14
TXN.3.1#16
TXN.3.2#1
TXN.3.2#2
TXN.3.2#10
TXN.3.2#12
TXN.3.2#13
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.3.2#14
TXN.3.2#15
TXN.3.2#16
TXN.3.2#17
TXN.3.2#18
TXN.3.2#19
TXN.3.2#21
593
PCI Express
Monitor Checks
594
Rule
Check IDs
Violation
TXN.3.2#23
TXN.3.2#25
TXN.3.2#30
TXN.3.2#32
PCI_EXPRESS_ CPLD_FOR_
UNSUCCESFUL_ CPL
TXN.3.2#34
TXN.3.2#35
PCI_EXPRESS_MRD_CPL_LOW
_ADDR
TXN.3.2#36
TXN.3.3#1
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.3.3#2
PCI_EXPRESS_ COMPLETION_
WITHOUT_ REQUEST
TXN.3.3#3
TXN.3.3#5
PCI_EXPRESS_CPL_STATUS_
CSR_FOR_ NONCFG_REQ
TXN.3.3#6
PCI_EXPRESS_CPL_STATUS_
FIELD_ ERROR
TXN.7.1#1
PCI_EXPRESS_NO_TLP_
DIGEST
TXN.8.0#1
TXN.8.0#2
TXN.8.0#3
595
PCI Express
Monitor Checks
596
Rule
Check IDs
Violation
TXN.8.0#4
TXN.8.0#5
TXN.8.0#6
TXN.2.15#4
PCI_EXPRESS_ MSG_REQ_TC_
FIELD_ERROR
TPL.03.01#03
PCI_EXPRESS_CPL_LK_
REQ_ROOT_ COMPLEX
TPL.04.00#02
TXN.02.13#05 PCI_EXPRESS_INTX_FROM_D
OWNSTREAM_PORT
Assert_INTx/Deassert_INTx Messages
are only issued by Upstream Ports.
TXN.02.15#05 PCI_EXPRESS_MSG_REQ_
TC_FIELD_ ERROR
TXN.5.1#4
PCI Express
Monitor Checks
Rule
Check IDs
TXN.5.3#8
TXN.5.3#10
TXN.9.1#1
TXN.9.1#2
TXN.9.1#3
TXN.9.1#4
TXN.9.1#5
TXN.9.1#6
Violation
597
PCI Express
Monitor Checks
598
Rule
Check IDs
Violation
TXN.9.2#1
SYS.5.2#2
SYS.5.2#5
SYS.6.0#8
SYS.6.0#15
PMG.2.0#7
PMG.3.3#2
PMG.3.4#1
PMG.3.8#2
PMG.3.8#3
PMG.3.8#4
PMG.3.8#5
PMG.3.8#6
PMG.3.8#7
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.3.8#8
PMG.3.8#10
PMG3.8#14
PCI_EXPRESS_ACK_
WITHOUT_PM_ COMMAND
PMG.3.9#1
PMG3.9#4
PCI_EXPRESS_TLPS_
AFTER_ACK
PMG3.9#5
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_ACK
PMG3.9#7
PMG3.10#1
599
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG3.10#2
PMG4.5#2
PCI_EXPRESS_TLPS_
OUTSTANDING
PCI_EXPRESS_NAK_
WITHOUT_PM_REQ
PCI_EXPRESS_ACK_
WITHOUT_PM_ COMMAND
600
A component receiving a
PM_Active_State_Request_L1_DLLP
must respond immediately with an
acceptance or a rejection.
PMG4.5#11
PCI_EXPRESS_TLPS_
OUTSTANDING_WHEN_ACK
Before sending a
PM_Request_Ack_DLLP downstream,
an upstream component must block TLP
scheduling and receive an
acknowledgement for the last TLP it sent.
PMG4.5#12
A component sending
PM_Request_ACK_DLLP downstream
must do so continuously until its receive
lanes enter the electrical idle state.
PMG4.5#14
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK
PMG4.5#15
PMG4.5#17
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG4.7#1
PMG4.7#3
PCI_EXPRESS_TLPS_
OUTSTANDING
PMG4.7#5
PMG4.7#7
PMG4.7#9
PMG4.7#10
SYS.5.1#2
SYS.5.2#4
Rule
Check IDs
DLL.05.02#11
Monitor cannot perform this check. After replay has successfully received
all expected Acks, re-enable receiving
TLPs from the Transaction Layer.
TXN.2.7#9
PCI_EXPRESS_INVALID_REQ_
ID
Violation
601
PCI Express
Monitor Checks
602
Rule
Check IDs
Violation
TXN.2.7#10
TXN.2.7#11
PCI_EXPRESS_TLP_BEFORE_I
NITIAL_CONFIG_WRITE
TXN.2.7#15
TXN.2.13#12
TXN.2.13#15
TXN.2.13#16
TXN.2.13#23
TXN.2.13#24
TXN.2.13#25
TXN.2.15#05
PCI_EXPRESS_ MSG_REQ_
TC_ FIELD_ERROR
PCI Express
Monitor Checks
Rule
Check IDs
Violation
TXN.2.21#15
PCI_EXPRESS_INVALID_COM
PLETER_ID
TXN.2.21#16
PCI_EXPRESS_BUS_DEV_NOT
_0_FOR_CPL_BEFORE_INIT_W
R
TXN.2.21#19
PCI_EXPRESS_COMPLETION_
TC_ ATTR_MISMATCH
TXN.3.1#4
Monitor cannot perform this check. If the Request violates the programming
model of the device, then the device can
optionally treat the Request as a
Completer Abort, instead of handling
the Request normally.
TXN.3.1#5
TXN.9.1#8
PCI_EXPRESS_ LINK_DOWN_
PENDING_ REQUESTS
TXN.02.17#09
603
PCI Express
Monitor Checks
604
Rule
Check IDs
Violation
TXN.02.17#10
TXN.03.00#04
Monitor cannot perform this check. Switches must process both TLPs that
address resources within the Switch as
well as TLPs that address resources
residing outside the Switch.
TXN.03.00#05
Monitor cannot perform this check. Switches handle all TLPs that address
internal resources of the Switch
(according to the PCI Express Base
Specification, (flow chart) Figure 2-23).
TXN.03.00#06
Monitor cannot perform this check. TLPs that pass through the Switch, or
that address the Switch as well as
passing through it, are handled
according to the PCI Express Base
Specification, (flow chart) Figure 2-24.
TXN.05.00#05
Monitor cannot perform this check. Switches that do not implement the
optional PCI Express Virtual Channel
Capability Structure must map all TCs
to VC0.
TXN.05.00#06
Monitor cannot perform this check. Switches that do not implement the
optional PCI Express Virtual Channel
Capability Structure must forward all
transactions regardless of the TC Label.
TXN.05.01#04
TXN.05.03#05
TXN.05.03#07
PCI_EXPRESS_TLP_
DOESNOT_ MAP_TO_
ANY_VC
TXN.05.03#09
TXN.07.01#02
Monitor cannot perform this check. Switches must pass TLPs with ECRC
unchanged from the Ingress Port to the
Egress port.
TXN.07.01#05
PCI_EXPRESS_ ECRC_ERROR
PCI Express
Monitor Checks
Rule
Check IDs
TXN.07.03#07
Monitor cannot perform this check. A Switch (that is not also the Completer
for the Request) must route a poisoned
I/O, or Memory Write Request, or a
message with data in the same way it
would route a non-poisoned request of
the same type.
TXN.09.01#01
Monitor cannot perform this check. For a Root Complex, or any Port on a
Switch other than the one closest to the
Root Complex, DL_Down status is
handled by initializing back to their
default state any buffers or internal state
associated with outstanding requests
transmitted downstream. (Note: Port
configuration registers must not be
affected, except as required to update
status associated with the transition to
DL_Down).
TXN.09.01#02
Monitor cannot perform this check. For a Root Complex, or any Port on a
Switch other than the one closest to the
Root Complex, DL_Down status is
handled by forming completions for any
Requests submitted by the device core
for Transmission, returning
Unsupported Request Completion
Status, and then discarding the
Requests.
TXN.09.01#03
TXN.09.01#04
TXN.09.02#01
PMG.1.01#2
Monitor cannot perform this check. Active State Link Power Management
using the L0s state must be supported by
all PCI Express components.
Violation
605
PCI Express
Monitor Checks
606
Rule
Check IDs
Violation
PMG.3.08#14
PCI_EXPRESS_ACK_
WITHOUT_ PM_COMMAND
PMG.3.09#04
PMG.3.09#05
PCI_EXPRESS_ TLPS_
OUTSTANDING_
WHEN_ACK
PMG.3.09#07
PMG.3.10#01
PMG.3.10#02
PMG.3.13#02
PCI_EXPRESS_ PME_TO_
ACK_ WITHOUT_TURN_OFF
PMG.3.13#03
PCI Express
Monitor Checks
Rule
Check IDs
PMG.3.13#05
PMG.3.15#03
PMG.4.04#02
Monitor cannot perform this check. If the upstream port of the switch
receive lanes are transitioned from L0s
to L0, then the downstream port
transmit lanes must be transition to L0
for all downstream components in the
D0 state.
PMG.4.05#02
Monitor cannot perform this check. A root complex root port or Switch
Downstream port must accept a request
to enter L1 if the following are true:
The port supports active state link
PM L1 entry, and it is enabled.
No TLP is scheduled for
transmission.
No Ack or Nak DLLP is scheduled
for transmission.
PMG.4.05#03
Monitor cannot perform this check. If any of the following conditions are
false, then a Switch must not request L1
entry on its upstream port:
The upstream port supports Active
State Link PM L1 entry and is
enabled.
All of the Switchs Downstream
Port Links are in the L1 state (or
deeper).
No pending TLPs to transmit.
No pending DLLPs to transmit.
The Upstream Ports receive lanes
are idle.
PMG.4.06#01
Violation
607
PCI Express
Monitor Checks
608
Rule
Check IDs
Violation
PMG.4.06#02
PMG.4.07#05
Monitor cannot perform this check. When the ASPM control field for a
component is set to 00b, a port receiving
a PM_Active_State_Request_L1_DLLP
command must respond with
PM_Active_State_Nak.
PMG.4.07#07
Monitor cannot perform this check. When the ASPM control field for a
downstream port is set to 01b (L0s
only), it must respond to an L1 entry
request with PM_Active_State_Nak.
PMG.5.01#02
PMG.3.8#11
PMG.3.8#12
PMG.3.9#2
PMG.3.9#3
PCI_EXPRESS_TLPS_
AFTER_PM
PCI Express
Monitor Checks
Rule
Check IDs
Violation
PMG.3.9#6
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK
PMG.3.9#8
PMG.3.9#9
Monitor cannot perform this check. Once both ends of a link are in L1, the
components must suspend operation of
Flow Control Update, DLLP
ACK/NAK Latency, and the TLP
Completion Timeout counter
mechanisms.
PMG.3.11#1
PMG.3.12#2
Monitor cannot perform this check. A device must cease requesting Link
reactivation of any form once it has
entered the D0-uninitialized state.
PMG.3.12#3
PMG.3.12#6
PMG.3.12#7
PMG.3.15#4
PMG.4.5#4
609
PCI Express
Monitor Checks
610
Rule
Check IDs
Violation
PMG.4.5#5
PCI_EXPRESS_TLPS_
OUTSTANDING
PMG.4.5#7
PMG.4.5#8
PCI_EXPRESS_TLPS_
AFTER_PM
PMG.4.5#9
PMG.4.5#10
PMG.4.5#13
PCI_EXPRESS_IDLE_OS_
WITHOUT_ACK
PMG.4.5#16
PMG.4.5#17
Monitor cannot perform this check. Flow control update times must be
frozen while in L1.
PMG.4.7#2
PMG.4.7#3
Monitor cannot perform this check. A port enabled for L0s entry only must
bring the port to L0s if all conditions
defined in the PCI Express Base
Specification are met.
When a PM_Request_Ack_DLLP is
detected on its receive lanes, the
PM_Active_State_Request_L1_DLLP
must cease being sent and the link layer
must be disabled, an electrical idle
ordered set sent, and the transmit lanes
brought into the electrical idle state.
PCI Express
Monitor Checks
Rule
Check IDs
PMG.4.7#4
Monitor cannot perform this check. When the ASPM control field for a
component is set to 00b (Disabled), the
port must not bring a link into the L0s
state or issue
PM_Active_State_Request_L1_DLLP
commands.
PMG.4.7#6
Monitor cannot perform this check. When the ASPM control field for a
component is set to 01b (L0s only), a
port must bring a link into L0s when
allowed.
PMG.4.7#8
Monitor cannot perform this check. When the ASPM control field for a
component is set to 01b (L0s only), an
upstream port must not send a
PM_Active_State_Request_L1_DLLP.
SYS.01.01#05
PCI_EXPRESS_ MSG_REQ_
TC_ FIELD_ERROR
SYS.05.03#01
SYS.05.03#02
SYS.05.03#04
Monitor cannot perform this check. When a CplDLk for the first MRdLk is
returned with a successful completion
status, the switch must block all requests
from all ports from being propagated to
either port involved in the locked
access, except for Requests that map to
non-VC0 on the egress port.
SYS.05.03#06
SYS.05.03#07
SYS.05.03#08
Monitor cannot perform this check. A locked egress port must be unblocked
following the transmission of the
Unlock Message out of the egress port.
SYS.05.03#09
Monitor cannot perform this check. Ports that are not involved in a locked
access must not be affected by an
Unlock Message.
SYS.06.00#02
Monitor cannot perform this check. A component must enter the initial
active Link Training state within 20 ms
of the end of Fundamental Reset.
Violation
611
PCI Express
Monitor Checks
612
Rule
Check IDs
Violation
SYS.06.00#03
SYS.06.00#08
Monitor cannot perform this check. The secondary side of the bridge must
undergo a hot reset if the Secondary Bus
Reset bit of the bridge control register is
set.
SYS.06.00#11
Monitor cannot perform this check. A hot reset must be sent on all
downstream ports if the Secondary Bus
Reset bit of the upstream port is set.
SYS.06.00#12
Monitor cannot perform this check. A hot reset must be sent on all
downstream ports if the data link layer
of the upstream port reports
DL_DOWN.
SYS.06.00#13
Monitor cannot perform this check. When a hot reset is received on the
upstream port of the switch, a hot reset
must be sent on all downstream ports.
SYS.07.01#01
Monitor cannot perform this check. PCI Express hot plug capable ports must
meet the PCI Standard Hot-Plug
Controller and Subsystem Specification,
Revision 1.0 usage model. (Appear
identical from a user perspective to ports
meeting that specification).
SYS.07.02#01
Monitor cannot perform this check. Indicators must have three states: On,
Off, and blinking.
SYS.07.02#02
SYS.07.02#03
Monitor cannot perform this check. The state of an indicator must only be
controlled by software unless hardware
detects a stuck-on power fault.
SYS.7.9 to
SYS.9.5
PCI Express
Monitor Corner Cases
Description
COM Symbols
Nullified TLPs
Total number of symbol times both STP and SDP symbols were
sampled on the link. This corner case is applicable for multilane links.
Total number of TS1/TS2 ordered sets with disable scrambling bit set.
Table 14-31 shows the corner cases maintained by the PCI Express monitor for the data link
layer. These corner cases are collected for both transmit and receive interface.
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express
Monitor
Corner Cases
Description
ACK DLLPs
Duplicate TLPs
InitFC1-Cpl DLLPs
InitFC1-NP DLLPs
InitFC1-P DLLPs
613
PCI Express
Monitor Corner Cases
Table 14-31. Data Link Layer Corner Cases Maintained by the PCI Express
Monitor (cont.)
Corner Cases
Description
InitFC2-Cpl DLLPs
InitFC2-NP DLLPs
InitFC2-P DLLPs
NAK DLLPs
PM_Active_State_Request_L0s DLLPs
PM_Active_State_Request_L1 DLLPs
PM_Enter_L1 DLLPs
PM_Enter_L23 DLLPs
PM_Request_Ack DLLPs
TLP retransmissions
UpdateFC-Cpl DLLPs
UpdateFC-NP DLLPs
UpdateFC-P DLLPs
Table 14-32 shows the corner cases maintained by the PCI Express monitor for the transaction
layer. These corner cases are collected for the transmit and receive interfaces.
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express
Monitor
Corner Cases
Description
Completer aborts
Completion packets
Locked completions
614
PCI Express
Monitor Statistics
Table 14-32. Transaction Layer Corner Cases Maintained by the PCI Express
Monitor (cont.)
Corner Cases
Description
Message requests
Monitor Statistics
Table 14-33 shows the statistics maintained by the PCI Express monitor for the physical layer.
These statistics are collected for the transmit and receive interface.
Table 14-33. Physical Layer Statistics
Statistics
Description
Number of packets
Table 14-34 shows the statistics maintained by the PCI Express monitor for the data link layer.
These statistics are collected for the transmit and receive interface.
Table 14-34. Data Link Layer Statistics
Statistics
Description
No statistics are maintained by the PCI Express monitor for the data link layer
Table 14-35 shows the statistics maintained by the PCI Express monitor for the transaction
layer. These statistics are collected for the transmit and receive interface.
Table 14-35. Transaction Layer Statistics
Statistics
Description
Malformed TLPs
615
PCI Express
Monitor Gen2 Corner Cases
Description
Total number of TLPs started on lanes other than lane number zero.
Total number of symbol times where more than one packet ended in a
symbol time.
Description
Total number of EIOS(Two set of Com, Idle, Idle and Idle) on speed greater
than 2.5 GT/s.
Total number of TS1 ordered sets with speed change bit set.
Total number of TS2 ordered sets with speed change bit set.
TS1 ordered sets with compliance Total number of TS1 ordered sets with compliance receive bit set.
receive bit.
More than 4 EIE symbol
occurrence before FTS.
Total number of times more than 4 EIE symbol before FTS on speed greater
than 2.5 GT/s.
Number of times state transition to L0s on speed greater than 2.5 GT/s.
616
PCI Express
Monitor Gen2 Statistics
Table 14-37 shows there are no corner cases maintained by the PCI Express Monitor Gen2 for
the data link layer.
Table 14-37. Data Link Layer Corner Cases PCI Express Monitor Gen2
Statistics
Description
There are no corner cases maintained by the PCI Express Monitor Gen2 for the data link layer.
Table 14-38 shows the corner cases maintained by the PCI Express monitor for the transaction
layer. These corner cases are collected for the transmit and receive interfaces.
Table 14-38. Transaction Layer Corner Cases PCI Express Monitor Gen2
Corner Cases
Description
Deprecated TLP.
Description
617
PCI Express
Monitor Gen2 Statistics
Table 14-40 shows the statistics maintained by the PCI Express monitor for the data link layer.
These statistics are collected for the transmit and receive interface.
Table 14-40. Data Link Layer Statistics PCI Express Monitor Gen2
Statistics
Description
Table 14-35 shows the statistics maintained by the PCI Express monitor for the transaction
layer. These statistics are collected for the transmit and receive interface.
Table 14-41. Transaction Layer Statistics PCI Express Monitor Gen2
618
Statistics
Description
PCI Express
Monitor FAQ
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL PCI Express
monitor.
What are the various interfaces supported by the monitor?
619
PCI Express
Monitor FAQ
The monitor provides tc_mapped_to_vcx ports for accepting the TC/VC mapping. By
default, all TCs are mapped to VC0, and only VC0 is supported. For example, if TC0
and TC1 are mapped to VC0, then the port tc_mapped_to_vc0 should be set to
8'b0000_0011.
Does the monitor track ordering rules?
No.
Why is the DOUBLE_DATA_RATE parameter provided?
The DOUBLE_DATA_RATE parameter configures the active edges of the PCI Express
clock. By default, the clocks are active on only the rising edge. The monitor can be
configured such that the clock is active on the rising edge as well as the falling edge.
Is there an option to configure the monitor to track short training sequences?
Yes. The MIN_TS1_COUNT parameter configures the monitor for the number of TS1
ordered sets. By default, the monitor expects 1024 TS1 ordered sets to be transmitted in
the Polling.Active state of the LTSSM.
Can I turn off the checks for individual layers?
The phy_layer_checks_disable, link_layer_checks_disable, and
transaction_layer_checks_disable monitor inputs disable checks for
the
individual layers (see Monitor Connectivity on page 421 and Monitor Connectivity
(PIPE) on page 431).
How do I disable scrambling?
Scrambling and de-scrambling are disabled by transmitting and receiving a few
TS1/TS2 ordered sets with the disable scramble bit set. Also, for the PIPE monitor, the
user can disable scrambling using the disable_descrambler port.
What happens if the skip link training is set and the DUT performs link training?
If skip link training is set, then the link width is configured through the
MAX_LANE_WIDTH parameter. It is OK to perform link training and width negotiation if
the negotiated link width matches the value of the MAX_LANE_WIDTH parameter.
Otherwise, the monitor will not be synchronized with the DUT.
Is it possible to disable scrambling for TX lanes only?
No. Scrambling and de-scrambling is disabled only for the test mode of operation and
only can be disabled for the device as a whole.
How do I hook up the monitor when 9B signals (8 data bits/lane and 1 control bit/lane) are
available?
620
PCI Express
Monitor FAQ
The user can hook up PIPE monitor when 9B signals are available, but the PIPE
interface signals that are not relevant should be set to either 1'b0 or 1'b1 as required (see
Instantiation Examples (PIPE) on page 438.
How does the monitor perform symbol lock?
The monitor uses the COM symbol to perform symbol lock. The monitor samples the
serial bits and waits until a proper COM symbol is detected. The monitor considers
detection of a COM symbol as symbol lock.
Does the monitor support a multilane PIPE interface?
Yes.
Does the PCI Express monitor support polarity inversion?
Yes. The monitor determines the polarity inversion through the TS1 and TS2 identifiers.
Is it possible to configure the Ack_Nak and Reply timer values?
Yes. The OVERRIDE_TIMER_VALUES parameter configures the Ack_Nak and Reply
Timer values. By default, the monitor determines the Ack_Nak and Reply Timer
values based on the Max_Payload_Size configured.
Is it possible to instantiate the monitor on the Link or Transaction layer only?
No. These interfaces being implementation specific, the user cannot instantiate the
monitor on Link layer, Transaction layer, etc. The monitor must be instantiated at the
interface between the transceiver and the PCI Express component or at the PIPE
interface.
Is it possible to turn off/on the layer checks dynamically?
Yes. The user can turn off/on the layer checks dynamically through the monitor input
ports provided. Even though the checks are turned off, the monitor will be in sync with
the device. When the checks are enabled, all the checks are performed.
Why does the PCI Express monitor have clock signals when the PCI Express interface
does not specify clock signals?
The monitor does not perform the clock recovery function. It expects clock signals.
Does the monitor handle lane-to-lane skew?
Yes. The user must configure the DESKEW_SUPPORT parameter accordingly. By default,
the monitor does not support lane-to-lane skew.
Does the monitor track/check only the packets detected on the transmit lanes?
621
PCI Express
Monitor FAQ
No. As the monitor sits on the bus as a whole, in general it performs all the checks on
receive lanes as well as on transmit lanes.
622
Chapter 15
Serial Attached SCSI (SAS)
Introduction
The Serial Attached SCSI (SAS) protocol defines the transmission of the SCSI protocol over a
Serial ATA compatible physical layer and defines addressing of multiple target devices for the
Serial ATA protocol. The SAS link consists of two signal groups: transmit and receive. The
QVL SAS monitor is designed for checking SAS implementations.
Reference Documentation
This SAS monitor is modeled from the requirements provided in the following document:
Supported Features
Primitives
The monitor tracks SAS primitives (e.g., AIP, ALIGN, CHANGE, etc.).
The monitor tracks SSP and SMP primitives (e.g., ACK, NAK, DONE, SOF, EOF and
RRDY).
Data Integrity
The monitor supports data integrity checking for Address frames, SSP, STP, and SMP
frames.
Flow Control
The monitor tracks the flow control for SSP, SMP, and STP frames.
The monitor tracks the PHY reset sequence including the speed negotiation sequence.
623
Implementations
The monitor can be instantiated in any of the following implementations in a SAS domain for
the following connections:
Unsupported Features
This monitor cannot be instantiated in the ATA target port (using SATA protocol) in a
SAS domain.
624
SAS Device
SAS
Monitor
Rx_interface
Tx_interface
rx_data_plus
rx_data_minus
rx_idle_signal
rx_clk
tx_data_plus
tx_data_minus
tx_idle_signal
tx_clk
bypass_reset_sequence
reset
areset
start_speed_negotiation
625
Rx_interface
Tx_interface
SAS
Monitor
rx_data_plus
rx_data_minus
rx_idle_signal
rx_clk
rx_cominit_idle_time_min
rx_cominit_idle_time_max
rx_comsas_idle_time_min
rx_comsas_idle_time_max
rx_cominit_neg_time
rx_comsas_neg_time
tx_data_plus
tx_data_minus
tx_idle_signal
tx_clk
bypass_reset_sequence
reset
areset
start_speed_negotiation
tx_cominit_idle_time
tx_comsas_idle_time
tx_cominit_neg_time
tx_comsas_neg_time
rate_change_delay
spd_neg_lock_time
spd_neg_transmit_time
hotplug_timeout
comsas_timeout
hard_reset_timeout
ident_frame_timeout
break_timeout
open_addr_res_timeout
credit_timeout
ack_nak_timeout
close_timeout
done_timeout
Monitor Connectivity
Connect the SAS monitor pins as specified in the pin out Table 15-1 and illustrated in
Figure 15-3.
626
SAS Monitor
tx_clk
tx_data_plus
tx_data_minus
tx_idle_signal
rx_clk
rx_data_plus
rx_data_minus
rx_idle_signal
reset
areset
bypass_reset_sequence
start_speed_negotiation
tx_cominit_idle_time
tx_comsas_idle_time
rx_cominit_idle_time_min
rx_cominit_idle_time_max
rx_comsas_idle_time_min
rx_comsas_idle_time_max
tx_cominit_neg_time
tx_comsas_neg_time
rx_cominit_neg_time
rx_comsas_neg_time
rate_change_delay
spd_neg_lock_time
spd_neg_transmit_time
hotplug_timeout
comsas_timeout
hard_reset_timeout
ident_frame_timeout
break_timeout
open_addr_res_timeout
credit_timeout
ack_nak_timeout
close_timeout
done_timeout
SAS Monitor
(dynamic timer values)
627
628
Pin
Description
ack_nak_timeout
Configures the ACK/NAK timeout period. If the port sends an SSP frame, it
should be acknowledged within 1 millisecond.
areset
Asynchronous reset, Active high. This is not part of the SAS interface.
break_timeout
Configures the break timeout period. If the port sends a break, it should receive
the break within one 1 millisecond.
bypass_reset_sequence
Configure this port to 1'b0 to track the PHY reset sequence. Configure this port
to 1'b1 to skip tracking the PHY reset sequence.
close_timeout
Configures the Close timeout period. If the port sends a close, it should receive
a close within one 1 millisecond.
comsas_timeout
credit_timeout
Configures the credit timeout period. Port which accepts an open address frame
should send credit within 1 millisecond.
done_timeout
Configures the done timeout period. If the port sends a done, then it should
receive a done within one 1 millisecond.
hard_reset_timeout
Configures the hard reset period. After a port detects hard reset, it should not
send any valid primitives within one millisecond.
hotplug_timeout
ident_frame_timeout
Configures the identification address frame timeout period. If the port transmits
an identification address frame, it should receive the same from the other side
within one millisecond.
open_addr_res_timeout
Configures the open address response timeout period. After a port sends an
open address frame, it should receive a response within 1 millisecond.
rate_change_delay
Specifies the time the transmitter transmits D.C. idle between rates during
speed negotiation. The idle time period must be specified in UIs.
reset
Synchronous reset, Active high. This is not part of the SAS interface.
rx_clk
Receive clock.The receiver uses this clock to sample the bit pattern. The
monitor uses this clock to sample the received bit pattern. The clock is active on
posedge or on both edges based on the mode of operation.
rx_cominit_idle_time_max
Configures the receiver idle time period between ALIGN bursts in a COMINIT
sequence. The idle time period must be specified in UIs.
rx_cominit_idle_time_min
Configures the receiver idle time period between ALIGN bursts in a COMINIT
sequence. The idle time period must be specified in UIs.
rx_cominit_neg_time
Configures the receiver negation time after a COMINIT sequence. The idle
time period must be specified in UIs.
rx_comsas_idle_time_max
Configures the receiver idle time period between ALIGN bursts in a COMSAS
sequence. The idle time period must be specified in UIs.
rx_comsas_idle_time_min
Configures the receiver idle time period between ALIGN bursts in a COMSAS
sequence. The idle time period must be specified in UIs.
Description
rx_comsas_neg_time
Configures the receiver negation time after a COMSAS sequence. The idle time
period must be specified in UIs.
rx_data_minus
Input to SAS device. In serial mode, connect this input to the D input of the
device. In parallel mode, leave this input unconnected.
rx_data_plus
Input to the SAS device. In serial mode, connect this input to the D+ input of
the device. In parallel mode, connect this input to the 10B encoded data.
rx_idle_signal
Receive electrical idle signal. In parallel mode, this signal indicates an electrical
idle period. An active high on this signal indicates electrical idle. The SAS
monitor also provides an alternate method of indicating electrical idle on the
parallel 10b bus, apart from using the rx_idle_signal. You can configure the
parameter provided (see Monitor Parameters on page 630) and when the
value on the parallel bus equals the programmed parameter value, the monitor
infers an electrical idle scenario.
You should connect rx_idle_signal to 1'b0 during monitor instantiation if you
want to use the parameter method of indicating electrical idle on the bus.
spd_neg_lock_time
Specifies the maximum time during the speed negotiation window for a
transmitter to reply with ALIGN (1).
spd_neg_transmit_time
Specifies time during which ALIGN (0) or ALIGN (1) is transmitted at each
physical link rate during the speed negotiation sequence.
start_speed_negotiation
Configures the monitor to track from the speed negotiation sequence. This
signal is active high. The rising edge of this signal indicates the starting point of
an RCD period. This signal is used only when the monitor is configured in the
parallel mode (i.e., parameter INTERFACE_TYPE is 1 or 2). In serial mode,
this signal must be connected to 1'b0.
tx_clk
Transmit clock. This clock is used by the transmitter to drive the bit pattern.
The monitor uses this clock to sample the transmitted bit pattern. The clock is
active on posedge or on both edges based on the mode of operation.
tx_cominit_idle_time
tx_cominit_neg_time
Configures the negation time after a COMINIT sequence. The idle time period
must be specified in UIs.
tx_comsas_idle_time
tx_comsas_neg_time
Configures the negation time after a COMSAS sequence. The idle time period
must be specified in UIs.
tx_data_minus
Output from SAS device. In serial mode, connect this input to the D output of
the device. In parallel mode, leave this input unconnected.
tx_data_plus
Output from the SAS device. In serial mode, connect this input to the D+ output
of the device. In parallel mode, connect this input to the 10B encoded data.
tx_idle_signal
629
Connectivity Notes
In parallel mode, connect the encoded 10B symbols as follows:
tx_data_plus[9:0] = {j,h,g,f,i,e,d,c,b,a}
where bit a is the LSB of the 10B data and bit j is the MSB of the 10B data.
Monitor Parameters
The parameters shown in Table 15-2 configure the SAS monitor.
Table 15-2. SAS Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
SAS_DEVICE_TYPE
3.
INTERFACE_TYPE
4.
DOUBLE_DATA_RATE
5.
TX_DEVICE_SPEED_RATE
6.
RX_DEVICE_SPEED_RATE
7.
TX_COMINIT_IDLE_TIME
480
8.
TX_COMSAS_IDLE_TIME
1440
630
Default Description
9.
TX_COMINIT_NEGATION_
TIME_PERIOD
800
10.
TX_COMSAS_NEGATION_
TIME_PERIOD
2400
11.
ELECTRICAL_IDLE_TIME_
BIT_PATTERN
1023
12.
RATE_CHANGE_DELAY
750000
13.
SPEED_NEGOTIATION_
LOCK_TIME
153600
14.
SPEED_NEGOTIATION_
TRANSMIT_TIME
163840
15.
TX_MAX_SUPPORTED_RATE
16.
RX_MAX_SUPPORTED_RATE
17.
REPEATED_PRIMITIVE_SEQ
18.
TRANSPORT_LAYER_
CHECKS_ENABLE
19.
HOTPLUG_TIMEOUT_
PERIOD
1499250
631
Default Description
20.
COMSAS_TIMEOUT_
PERIOD
20480
21.
HARD_RESET_PERIOD
1499250
22.
DISABLE_DESCRAMBLER
23.
IDENT_TIMEOUT
1499250
24.
BREAK_TIMEOUT
1499250
25.
OPEN_ADDR_RES_TIMEOUT
1499250
26.
CREDIT_TIMEOUT
1499250
27.
ACK_NAK_TIMEOUT
1499250
28.
CLOSE_TIMEOUT
1499250
29.
DONE_TIMEOUT
1499250
30.
PHY_RESET_SEQ_CHECK_
ENABLE
31.
RESERVED_FIELD_CHECK_
ENABLE
632
Default Description
32.
VENDOR_SPECIFIC_
ENCODING_ENABLE
33.
RX_COMINIT_IDLE_
TIME_MIN
260
34.
RX_COMINIT_IDLE_TIME_
MAX
780
35.
RX_COMSAS_IDLE_TIME_
MIN
780
36.
RX_COMSAS_IDLE_TIME_
MAX
2360
37.
RX_COMINIT_NEGATION_
TIME_PERIOD
780
38.
RX_COMSAS_NEGATION_
TIME_PERIOD
2360
The term UI (Unit Interval) is the number of active edges of the clock.
The SAS monitor supports 20-bit parallel interface implementations (with some
restrictions). To configure the monitor to track a 20-bit parallel interface, set the
INTERFACE_TYPE parameter to 2. In this mode, the monitor cannot be configured for
double data rate operation, (i.e., the parameter DOUBLE_DATA_RATE must be set to 0). In
other words, the monitor supports only single data rate implementations in 20-bit
parallel mode.
The parameters shown in Table 15-3 configure the SAS (dynamic timer values) monitor.
Table 15-3. SAS Monitor (dynamic timer values) Parameters
Order
Parameter
Default Description
1.
Constraints_Mode
633
634
Order
Parameter
Default Description
2.
SAS_DEVICE_TYPE
3.
INTERFACE_TYPE
4.
DOUBLE_DATA_RATE
5.
TX_DEVICE_SPEED_RATE
6.
RX_DEVICE_SPEED_RATE
7.
ELECTRICAL_IDLE_TIME_
BIT_PATTERN
1023
8.
TX_MAX_SUPPORTED_RATE
9.
RX_MAX_SUPPORTED_RATE
10.
REPEATED_PRIMITIVE_SEQ
11.
TRANSPORT_LAYER_
CHECKS_ENABLE
Parameter
Default Description
12.
DISABLE_DESCRAMBLER
13.
PHY_RESET_SEQ_CHECK_
ENABLE
14.
RESERVED_FIELD_CHECK_
ENABLE
15.
VENDOR_SPECIFIC_
ENCODING_ENABLE
Configures the monitor to check for vendorspecific encodings in the SSP and SMP frames. Set
this parameter to 1 to configure the monitor to
perform the check for vendor-specific encodings.
By default, the monitor allows vendor-specific
encodings.
The term UI (Unit Interval) is the number of active edges of the clock.
The SAS monitor supports 20-bit parallel interface implementations (with some
restrictions). To configure the monitor to track a 20-bit parallel interface, set the
INTERFACE_TYPE parameter to 2. In this mode, the monitor cannot be configured for
double data rate operation, (i.e., the parameter DOUBLE_DATA_RATE must be set to 0). In
other words, the monitor supports only single data rate implementations in 20-bit
parallel mode.
Instantiation Examples
Example 15-1 and Example 15-2 show instantiating an SAS monitor. Example 15-3 and
Example 15-4 shows instantiating an SAS (dynamic timer values) monitor.
Example 1
Example 15-1 instantiates an SAS monitor within an SAS device. The input to the device is
serial data. The clocks are active on the rising edge. The value of bypass_reset_sequence is
set to 1'b1. This instance does not track the PHY reset sequence.
635
636
Example 2
Example 15-2 instantiates an SAS monitor within an expander device. The inputs to the
expander device are parallel 10B data. The clocks are active on both edges. The value of
bypass_reset_sequence is set to 1'b0. This instance will track the PHY reset sequence.
Example 15-2. SAS Monitor Within an Expander Device
qvl_sas_monitor
#( 0,
/* Constraints_Mode */
1,
/* SAS_DEVICE_TYPE */
1,
/* INTERFACE_TYPE */
1,
/* DOUBLE_DATA_RATE */
0,
/* TX_DEVICE_SPEED_RATE */
0,
/* RX_DEVICE_SPEED_RATE */
48,
/* TX_COMINIT_IDLE_TIME */
144,
/* TX_COMSAS_IDLE_TIME */
80,
/* TX_COMINIT_NEGATION_TIME_PERIOD */
240,
/* TX_COMSAS_NEGATION_TIME_PERIOD */
1023,
/* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
75000,
/* RATE_CHANGE_DELAY */
15360,
/* SPEED_NEGOTIATION_LOCK_TIME */
16384,
/* SPEED_NEGOTIATION_TRANSMIT_TIME */
0,
/* TX_MAX_SUPPORTED_RATE */
0,
/* RX_MAX_SUPPORTED_RATE */
1,
/* REPEATED_PRIMITIVE_SEQ */
1,
/* TRANSPORT_LAYER_CHECKS_ENABLE */
149925, /* HOTPLUG_TIMEOUT_PERIOD */
2048,
/* COMSAS_TIMEOUT_PERIOD */
149925, /* HARD_RESET_PERIOD */
0,
/* DISABLE_DESCRAMBLER */
149925, /* IDENT_TIMEOUT */
149925, /* BREAK_TIMEOUT */
149925, /* OPEN_ADDR_RES_TIMEOUT */
149925, /* CREDIT_TIMEOUT */
149925, /* ACK_NAK_TIMEOUT */
149925, /* CLOSE_TIMEOUT */
149925, /* DONE_TIMEOUT */
0,
/* PHY_RESET_SEQ_CHECK_ENABLE*/
1,
/* RESERVED_FIELD_CHECK_ENABLE */
0,
/* VENDOR_SPECIFIC_CHECK_ENABLE */
26,
/* RX_COMINIT_IDLE_TIME_MIN */
78,
/* RX_COMINIT_IDLE_TIME_MAX */
78,
/* RX_COMSAS_IDLE_TIME_MIN */
236,
/* RX_COMSAS_IDLE_TIME_MAX */
78,
/* RX_COMINIT_NEGATION_TIME_PERIOD */
236)
/* RX_COMSAS_NEGATION_TIME_PERIOD */
PARALLEL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
637
Example 3
Example 15-3 instantiates an SAS monitor within a SAS device. The input to the device is serial
data. The clocks are active on the rising edge. The value of bypass_reset_sequence is set to
1'b1. This instance does not track the PHY reset sequence.
Example 15-3. SAS Monitor Within a SAS Device
qvl_sas_dynamic_timer_values_monitor
#( 0,
/* Constraints_Mode */
0,
/* SAS_DEVICE_TYPE */
0,
/* INTERFACE_TYPE */
0,
/* DOUBLE_DATA_RATE */
0,
/* TX_DEVICE_SPEED_RATE */
0,
/* RX_DEVICE_SPEED_RATE */
1023, /* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
0,
/* TX_MAX_SUPPORTED_RATE */
0,
/* RX_MAX_SUPPORTED_RATE */
1,
/* REPEATED_PRIMITIVE_SEQ */
1,
/* TRANSPORT_LAYER_CHECKS_ENABLE */
0,
/* DISABLE_DESCRAMBLER */
0,
/* PHY_RESET_SEQ_CHECK_ENABLE*/
1,
/* RESERVED_FIELD_CHECK_ENABLE */
0)
/* VENDOR_SPECIFIC_ENCODING_ENABLE*/
SERIAL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence
(1'b1),
.start_speed_negotiation
(1'b0),
.tx_cominit_idle_time
(cominit_idle_time),
.tx_comsas_idle_time
(comsas_idle_time),
.rx_cominit_idle_time_min (cominit_neg_time),
.rx_cominit_idle_time_max (comsas_neg_time),
.rx_comsas_idle_time_min
(rate_change_delay),
.rx_comsas_idle_time_max
(spd_neg_lock_time),
.tx_cominit_neg_time
(spd_neg_transmit_time),
.tx_comsas_neg_time
(hotplug_timeout),
.rx_cominit_neg_time
(comsas_timeout),
.rx_comsas_neg_time
(hard_reset_timeout),
.rate_change_delay
(ident_frame_timeout),
.spd_neg_lock_time
(break_timeout),
.spd_neg_transmit_time
(open_addr_res_timeout),
638
(credit_timeout),
(ack_nak_timeout),
(close_timeout) );
Example 4
Example 15-4 instantiates an SAS monitor within an expander device. The inputs to the
expander device are parallel 10B data. The clocks are active on both edges. The value of
bypass_reset_sequence is set to 1'b0. This instance will track the PHY reset sequence.
Example 15-4. SAS Monitor Within an Expander Device
qvl_sas_dynamic_timer_values_monitor
#( 0,
/* Constraints_Mode */
1,
/* SAS_DEVICE_TYPE */
1,
/* INTERFACE_TYPE */
1,
/* DOUBLE_DATA_RATE */
0,
/* TX_DEVICE_SPEED_RATE */
0,
/* RX_DEVICE_SPEED_RATE */
1023, /* ELECTRICAL_IDLE_TIME_BIT_PATTERN */
0,
/* TX_MAX_SUPPORTED_RATE */
0,
/* RX_MAX_SUPPORTED_RATE */
1,
/* REPEATED_PRIMITIVE_SEQ */
1,
/* TRANSPORT_LAYER_CHECKS_ENABLE */
0,
/* DISABLE_DESCRAMBLER */
0,
/* PHY_RESET_SEQ_CHECK_ENABLE*/
1,
/* RESERVED_FIELD_CHECK_ENABLE */
0)
/* VENDOR_SPECIFIC_ENCODING_ENABLE*/
PARALLEL_MODE (
.areset
(areset),
.reset
(reset),
.tx_clk
(tx_clk),
.tx_data_plus
(tx_data_plus),
.tx_data_minus
(tx_data_minus),
.tx_idle_signal
(tx_idle_signal),
.rx_clk
(rx_clk),
.rx_data_plus
(rx_data_plus),
.rx_data_minus
(rx_data_minus),
.rx_idle_signal
(rx_idle_signal),
.bypass_reset_sequence
(1'b0)
.start_speed_negotiation
(start_speed_negotiation)
.tx_cominit_idle_time
(tx_cominit_idle_time),
.tx_comsas_idle_time
(tx_comsas_idle_time),
.rx_cominit_idle_time_min (rx_cominit_idle_time_min),
.rx_cominit_idle_time_max (rx_cominit_idle_time_max),
.rx_comsas_idle_time_min
(rx_comsas_idle_time_min),
.rx_comsas_idle_time_max
(rx_comsas_idle_time_max),
.tx_cominit_neg_time
(tx_cominit_neg_time),
639
(tx_comsas_neg_time),
(rx_cominit_neg_time),
(rx_comsas_neg_time),
(rate_change_delay),
(spd_neg_lock_time),
(spd_neg_transmit_time),
(hotplug_timeout),
(comsas_timeout),
(hard_reset_timeout),
(ident_frame_timeout),
(break_timeout),
(open_addr_res_timeout),
(credit_timeout),
(ack_nak_timeout),
(close_timeout)
(done_timeout));
Clk_Recovery
Tx
Rx
tx_data
Device A
Device B
Rx
Tx
rx_data
Clk_Recovery
recovered_clock
recovered_clock
rx_clk
tx_clk
SAS Monitor
640
Table 15-4 configure the clock recovery modules. Example 15-5 shows an instantiation
example.
Figure 15-5. Connecting Clock Recovery Modules
rx_data_plus
tx_data_plus
Rx Clk Recovery
Tx Clk Recovery
rx_data_minus
tx_data_minus
rx_recovered_clock
tx_recovered_clock
rx_clk
tx_clk
SAS Monitor
Note that the clock recovery module is used for simulation with assertions only (not formal
verification).
Do not use the clock recovery module if a pulse width of 1 UI for a particular speed (G1 or G2)
changes dynamically during simulation.
Default Description
1.
ELECTRICAL_IDLE_LENGTH
30000
2.
TIME_UNIT
Example 15-5 instantiates a clock recovery monitor. The RATE CHANGE DELAY period is
250000 UIs and the time unit used in the testbench is in fs (i.e., 1 UI at a G2 rate equals 333000
fs and 1 UI at a G1 rate equals 666000 fs).
641
Monitor Checks
The checks performed by the SAS monitor are classified as follows:
Violation
Description
SAS_10B_CODING_
VIOLATION_P
SAS_10B_CODING_
VIOLATION_N
SAS_ADDR_FRAME_TYPE_
VIOLATION_P
SAS_ADDR_FRAME_TYPE_
VIOLATION_N
SAS_AIP_DWORD_COUNT_
VIOLATION_P
SAS_AIP_DWORD_COUNT_
VIOLATION_N
642
Address Frame Type field in Address frame type field in the address
the Address Frame should
frame should be equal to 0h or 1h. This
have the value 0h or 1h.
check fires if the address frame type is not
0h or 1h, and the
RESERVED_FIELD_CHECK_
ENABLE parameter is set.
AIP primitives should be
detected once in every 128
dwords.
Violation
Description
SAS_ALIGN0_TO_ALIGN1_
TRANS_VIOLATION_P
ALIGN(0) to ALIGN(1)
transition should happen
within speed negotiation
lock time (SNLT).
Sub-blocks encoded as
6'b000111 should be
generated only when the
running disparity at the
beginning of the sub-block
is positive.
Sub-blocks encoded as
4'b0011 should be generated
only when the running
disparity at the beginning of
the sub-block is positive.
Sub-blocks encoded as
4'b1100 should be generated
only when the running
disparity at the beginning of
the sub-block is negative.
SAS_ALIGN0_TO_ALIGN1_
TRANS_VIOLATION_N
SAS_ALIGN_COUNT_
VIOLATION_P
SAS_ALIGN_COUNT_
VIOLATION_N
SAS_ALIGN_DWORD_COUNT_
VIOLATION_P
SAS_ALIGN_DWORD_COUNT_
VIOLATION_N
SAS_CONNECTION_TAG_
VIOLATION_P
SAS_CONNECTION_TAG_
VIOLATION_N
SAS_DISPARITY_NEUTRAL_
000111_ERROR_P
SAS_DISPARITY_NEUTRAL_
000111_ERROR _N
SAS_DISPARITY_NEUTRAL_
0011_ERROR_P
SAS_DISPARITY_NEUTRAL_
0011_ERROR_N
SAS_DISPARITY_NEUTRAL_
1100_ERROR_P
SAS_DISPARITY_NEUTRAL_
1100_ERROR_N
643
Violation
Description
SAS_DISPARITY_NEUTRAL_
111000_ERROR_P
Sub-blocks encoded as
6'b111000 should be
generated only when the
running disparity at the
beginning of the sub-block
is negative.
SAS_DISPARITY_NEUTRAL_
111000_ERROR_N
SAS_ELECTRICAL_IDLE_
DETECTED_DURING_SNTT_P
SAS_ELECTRICAL_IDLE_
DETECTED_DURING_SNTT_N
SAS_G1_RATE_SUPPORTED_
WITHOUT_ALIGN_P
SAS_G1_RATE_SUPPORTED_
WITHOUT_ALIGN_N
SAS_G2_RATE_SUPPORTED_
WITHOUT_ALIGN_P
SAS_G2_RATE_SUPPORTED_
WITHOUT_ALIGN_N
644
Violation
Description
SAS_IAF_FRAME_SIZE_
VIOLATION_P
Identification Address
Frame should contain 32
bytes.
SAS_IAF_FRAME_SIZE_
VIOLATION_N
SAS_IDLE_COUNT_
VIOLATION_P
SAS_IDLE_COUNT_
VIOLATION_N
SAS_ILLEGAL_PRIMITIVE_P
SAS_ILLEGAL_PRIMITIVE_N
SAS_ILLEGAL_PRIMITIVE_
OUTSIDE_CONNECTION_P
SAS_ILLEGAL_PRIMITIVE_
OUTSIDE_CONNECTION_N
SAS_MORE_THAN_
3CONSECUTIVE_AIP_P
SAS_MORE_THAN_
3CONSECUTIVE_AIP_N
SAS_NON_ALIGN_PRIMITIVE_
IN_SPD_NEG_WINDOW_P
SAS_NON_ALIGN_PRIMTIVE_
IN_SPD_NEG_WINDOW_N
SAS_OAF_FEATURE_
VIOLATION_P
SAS_OAF_FEATURE_
VIOLATION_N
SAS_OAF_FRAME_SIZE_
VIOLATION_P
SAS_OAF_FRAME_SIZE_
VIOLATION_N
Open Address Frame should Length of the Open address frame should
contain 32 bytes.
be equal to 32 bytes. This check fires if the
open address frame length is not equal to
32 bytes.
645
Violation
SAS_OAF_LINK_RATE_
VIOLATION_P
Link Rate field in the Open Current link rate field in the Open address
Address Frame should be 0h frame should be either 0h (1.5Gbps) or 1h
or 1h.
(3.0Gbps). This check fires if the link rate
field contains a value other than 0h or 1h,
and the RESERVED_FIELD_CHECK_
ENABLE parameter is set.
SAS_OAF_LINK_RATE_
VIOLATION_N
SAS_OAF_PROTOCOL_
VIOLATION_P
Description
A nonexpander device
should not transmit OPEN
REJECT (BAD
DESTINATION).
A nonexpander device
should not transmit OPEN
REJECT (NO
DESTINATION).
A nonexpander device
should not transmit OPEN
REJECT(PATHWAY
BLOCKED).
Reserved BROADCAST
primitives should not be
detected on SAS interface.
SAS_OAF_PROTOCOL_
VIOLATION_N
SAS_OPEN_REJ_BAD_
DESTINATION_VIOLATION_P
SAS_OPEN_REJ_BAD_
DESTINATION_VIOLATION_N
SAS_OPEN_REJ_NO_
DESTINATION_VIOLATION_P
SAS_OPEN_REJ_NO_
DESTINATION_VIOLATION_N
SAS_OPEN_REJ_PATHWAY_
BLOCK_VIOLATION_P
SAS_OPEN_REJ_PATHWAY_
BLOCK_VIOLATION_N
SAS_RESERVED_AIP_
PRIMITIVE_P
SAS_RESERVED_AIP_
PRIMITIVE_N
SAS_RESERVED_BROADCAST_
PRIMITIVE_P
SAS_RESERVED_BROADCAST_
PRIMITIVE_N
SAS_RESERVED_K_CODE_P
SAS_RESERVED_K_CODE_N
646
Violation
Description
SAS_RESERVED_
NOTIFY_PRIMITIVE_P
Reserved NOTIFY
primitives should not be
detected.
Reserved OPEN_REJECT
primitives should not be
detected.
SAS_RESERVED_
NOTIFY_PRIMITIVE_N
SAS_RESERVED_OPEN_REJ_
PRIMITIVE_P
SAS_RESERVED_OPEN_REJ_
PRIMITIVE_N
SAS_SPD_NEG_WINDOW_
VIOLATION_P
SAS_SPD_NEG_WINDOW_
VIOLATION_N
Violation
Description
SAS_ACK_NAK_RECEIVED_
WITHOUT_FRAME_
TRANSMISSION_P
SAS_ACK_NAK_RECEIVED_
WITHOUT_FRAME_
TRANSMISSION_N
SAS_ACK_NAK_TIMEOUT_
VIOLATION_P
SAS_ACK_NAK_TIMEOUT_
VIOLATION_N
SAS_ALIGN0_PRIMITIVE_
EXPECTED_P
SAS_ALIGN0_PRIMITIVE_
EXPECTED_N
647
Violation
Description
SAS_ALIGN1_PRIMITIVE_
EXPECTED_P
BROADCAST primitive is a
redundant primitive, and it should
be detected six times. This check
fires if six consecutive
BROADCAST primitives are not
detected, and the
REPEATED_PRIMITIVE_SEQ
parameter is set.
CLOSE_AFFILIATION primitive
is a triple primitive and should be
detected 3 times. This check fires if
three consecutive
CLOSE_AFFILIATION primitives
are not detected and the
REPEATED_PRIMITIVE_SEQ
parameter is set.
SAS_ALIGN1_PRIMITIVE_
EXPECTED_N
SAS_ALIGN2_PRIMITIVE_
EXPECTED_P
SAS_ALIGN2_PRIMITIVE_
EXPECTED_N
SAS_ALIGN3_PRIMITIVE_
EXPECTED_P
SAS_ALIGN3_PRIMITIVE_
EXPECTED_N
SAS_BREAK_PRIMITIVE_
VIOLATION_P
SAS_BREAK_PRIMITIVE_
VIOLATION_N
SAS_BREAK_TIMEOUT_
VIOLATION_P
SAS_BREAK_TIMEOUT_
VIOLATION_N
SAS_BROADCAST_PRIMITIVE_
VIOLATION_P
SAS_BROADCAST_PRIMITIVE_
VIOLATION_N
SAS_CLOSE_AFFILIATION_
PRIM_VIOLATION_P
SAS_CLOSE_AFFILIATION_
PRIM_VIOLATION_N
648
Violation
Description
SAS_CLOSE_PRIMITIVE_
VIOLATION_P
SAS_CREDIT_TIMEOUT_
VIOLATION_N
SAS_DATA_FRAME_FROM_
INITIATOR_WITHOUT_
XFERRDY_FRAME_P
SAS_CLOSE_PRIMITIVE_
VIOLATION_N
SAS_CLOSE_TIMEOUT_
VIOLATION_P
SAS_CLOSE_TIMEOUT_
VIOLATION_N
SAS_COMSAS_TIMEOUT_
VIOLATION_P
SAS_COMSAS_TIMEOUT_
VIOLATION_N
SAS_CRC_VIOLATION_P
SAS_CRC_VIOLATION_N
SAS_CREDIT_TIMEOUT_
VIOLATION_P
SAS_DATA_FRAME_FROM_
INITIATOR_WITHOUT_
XFERRDY_FRAME_N
SAS_DATA_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_P
SAS_DATA_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_N
649
Violation
Description
SAS_DONE_PRIMITIVE_IN_
SMP_OR_STP_P
SAS_DONE_PRIMITIVE_IN_
SMP_OR_STP_N
SAS_DONE_TIMEOUT_
VIOLATION_P
SAS_DONE_TIMEOUT_
VIOLATION_N
SAS_EOF_DETECTED_
WITHOUT_SOF_P
SAS_EOF_DETECTED_
WITHOUT_SOF_N
SAS_EXPANDER_AIP_
VIOLATION_P
SAS_EXPANDER_AIP_
VIOLATION_N
SAS_EXPANDER_ERROR_
VIOLATION_P
SAS_EXPANDER_ERROR_
VIOLATION_N
SAS_FIS_TRANSMITTED_
WITHOUT_EXCHANGING_
XRDY_AND_RRDY_P
SAS_FIS_TRANSMITTED_
WITHOUT_EXCHANGING_
XRDY_AND_RRDY_N
SAS_FIS_TYPE_VIOLATION_P
SAS_FIS_TYPE_VIOLATION_N
SAS_FOUR_BYTE_ALIGN_
VIOLATION_P
SAS_FOUR_BYTE_ALIGN_
VIOLATION_N
650
Violation
Description
SAS_FRAME_RECEIVED_
WITHOUT_CREDIT_P
SAS_FRAME_RECEIVED_
WITHOUT_CREDIT_N
SAS_FRAME_WITH_CRC_ERR_
WITHOUT_NAK_P
SAS_FRAME_WITH_CRC_ERR_
WITHOUT_NAK_N
SAS_HARD_RESET_
VIOLATION_P
SAS_HARD_RESET_
VIOLATION_N
SAS_HOTPLUG_TIMEOUT_
VIOLATION_P
SAS_HOTPLUG_TIMEOUT_
VIOLATION_N
SAS_IDENT_FRAME_TIMEOUT_
VIOLATION_P
SAS_IDENT_FRAME_TIMEOUT_
VIOLATION_N
SAS_ILLEGAL_PRIMITIVE_
INSIDE_SMP_CONNECTION_P
SAS_ILLEGAL_PRIMITIVE_
INSIDE_SMP_CONNECTION_N
SAS_ILLEGAL_PRIMITIVE_
INSIDE_SSP_CONNECTION_P
SAS_ILLEGAL_PRIMITIVE_
INSIDE_SSP_CONNECTION_N
SAS_ILLEGAL_PRIMITIVE_
INSIDE_STP_CONNECTION_P
SAS_ILLEGAL_PRIMITIVE_
INSIDE_STP_CONNECTION_N
651
Violation
Description
SAS_INTERLOCKED_FRAME_
WITHOUT_ACK_NAK_P
SAS_INTERLOCKED_FRAME_
WITHOUT_ACK_NAK_N
SAS_NO_FRAME_AFTER_
DONE_PRIMITIVE_P
SAS_NO_FRAME_AFTER_
DONE_PRIMITIVE_N
SAS_OPEN_ADDR_RESPOSNE_
TIMEOUT_VIOLATION_P
SAS_OPEN_ADDR_RESPOSNE_
TIMEOUT_VIOLATION_N
SAS_PHY_IDENTIFIER_
VIOLATION_P
SAS_PHY_IDENTIFIER_
VIOLATION_N
SAS_RESERVED_CLOSE_
PRIMITIVE_P
SAS_RESERVED_CLOSE_
PRIMITIVE_N
SAS_RESERVED_DONE_
PRIMITIVE_P
SAS_RESERVED_DONE_
PRIMITIVE_N
SAS_RESERVED_NAK_
PRIMITIVE_P
SAS_RESERVED_NAK_
PRIMITIVE_N
SAS_RESERVED_RRDY_
PRIMITIVE_P
SAS_RESERVED_RRDY_
PRIMITIVE_N
SAS_RESPONSE_LENGTH_
VIOLATION_P
SAS_RESPONSE_LENGTH_
VIOLATION_N
652
Violation
Description
SAS_RESPONSE_LIST_
LENGTH_VIOLATION_P
Receive D (rx_data_minus) is
not driven to a valid level.
SAS_RESPONSE_LIST_
LENGTH_VIOLATION_N
SAS_RETRANSMIT_BIT_
VIOLATION_P
SAS_RETRANSMIT_BIT_
VIOLATION_N
SAS_ROK_OR_RERR_
DETECTED_BEFORE_WTRM_P
SAS_ROK_OR_RERR_
DETECTED_BEFORE_WTRM_N
SAS_RX_DN_UNKN_P
SAS_RX_DN_UNKN_N
SAS_RX_DP_UNKN_P
SAS_RX_DP_UNKN_N
SAS_SATA_HOLD_PRIMITIVE_
VIOLATION_P
SAS_SATA_HOLD_PRIMITIVE_
VIOLATION_N
SAS_SATA_HOLDA_PRIMITIVE_
VIOLATION_P
SAS_SATA_HOLDA_PRIMITIVE_
VIOLATION_N
SAS_SATA_RERR_PRIMITIVE_
VIOLATION_P
SAS_SATA_RERR_PRIMITIVE_
VIOLATION_N
SAS_SATA_RIP_PRIMITIVE_
VIOLATION_P
SAS_SATA_RIP_PRIMITIVE_
VIOLATION_N
653
Violation
Description
SAS_SATA_ROK_PRIMITIVE_
VIOLATION_P
SAS_SATA_ROK_PRIMITIVE_
VIOLATION_N
SAS_SATA_RRDY_PRIMITIVE_
VIOLATION_P
SAS_SATA_RRDY_PRIMITIVE_
VIOLATION_N
SAS_SATA_SYNC_PRIMITIVE_
VIOLATION_P
SAS_SATA_SYNC_PRIMITIVE_
VIOLATION_N
SAS_SATA_WTRM_PRIMITIVE_
VIOLATION_P
SAS_SATA_WTRM_PRIMITIVE_
VIOLATION_N
SAS_SATA_XRDY_PRIMITIVE_
VIOLATION_P
SAS_SATA_XRDY_PRIMITIVE_
VIOLATION_N
SAS_SENSE_DATA_LIST_
LENGTH_VIOLATION_P
SAS_SENSE_DATA_LIST_
LENGTH_VIOLATION_N
SAS_SENSE_LENGTH_
VIOLATION_P
SAS_SENSE_LENGTH_
VIOLATION_N
SAS_SMP_REQ_FRAME_TYPE_
VIOLATION_P
SAS_SMP_REQ_FRAME_TYPE_
VIOLATION_N
654
Violation
Description
SAS_SMP_REQ_FUNCTION_
VIOLATION_P
SAS_SMP_REQ_FUNCTION_
VIOLATION_N
SAS_SMP_REQ_PHY_
OPERATION_VIOLATION_P
SAS_SMP_REQ_PHY_
OPERATION_VIOLATION_N
SAS_SMP_REQ_PROG_MAX_
PHY_RATE_VIOLATION_P
SAS_SMP_REQ_PROG_MAX_
PHY_RATE_VIOLATION_N
SAS_SMP_REQ_PROG_MIN_
PHY_RATE_VIOLATION_P
SAS_SMP_REQ_PROG_MIN_
PHY_RATE_VIOLATION_N
SAS_SMP_REQ_RES_FN_
VIOLATION_P
SAS_SMP_REQ_RES_FN_
VIOLATION_N
655
Violation
Description
SAS_SMP_RES_ATTACHED_
DEV_TYPE_VIOLATION_P
SAS_SMP_RES_ATTACHED_
DEV_TYPE_VIOLATION_N
SAS_SMP_RES_CUR_PHY_
RATE_VIOLATION_P
SAS_SMP_RES_CUR_PHY_
RATE_VIOLATION_N
SAS_SMP_RES_FRAME_TYPE_
VIOLATION_P
SAS_SMP_RES_FRAME_TYPE_
VIOLATION_P
SAS_SMP_RES_FUNCTION_
RESULT_VIOLATION_P
SAS_SMP_RES_FUNCTION_
RESULT_VIOLATION_N
SAS_SMP_RES_FUNCTION_
VIOLATION_P
SAS_SMP_RES_FUNCTION_
VIOLATION_N
656
Violation
Description
SAS_SMP_RES_ROUTE_
ATTRIBUTE_VIOLATION_P
SAS_SMP_RES_ROUTE_
ATTRIBUTE_VIOLATION_N
SAS_SOAF_WITHOUT_EOAF_P
SAS_SOAF_WITHOUT_EOAF_N
SAS_SOF_DETECTED_
WITHOUT_EOF_P
SAS_SOF_DETECTED_
WITHOUT_SOF_N
SAS_SSP_COM_TASK_
ATTRIBUTE_VIOLATION_P
SAS_SSP_COM_TASK_
ATTRIBUTE_VIOLATION_N
SAS_SSP_DATA_PRES_
VIOLATION_P
SAS_SSP_DATA_PRES_
VIOLATION_N
SAS_SSP_INVALID_FRAME_
TYPE_P
SAS_SSP_INVALID_FRAME_
TYPE_N
657
Violation
Description
SAS_SSP_MAX_FRAME_SIZE_
VIOLATION_P
SAS_SSP_MAX_FRAME_SIZE_
VIOLATION_N
SAS_SSP_MIN_FRAME_SIZE_
VIOLATION_P
SAS_SSP_MIN_FRAME_SIZE_
VIOLATION_N
SAS_SSP_RESPONSE_CODE_
VIOLATION_P
SAS_SSP_RESPONSE_CODE_
VIOLATION_N
SAS_SSP_RESPONSE_STATUS_
VIOLATION_P
SAS_SSP_RESPONSE_STATUS_
VIOLATION_N
SAS_SSP_TASK_
MANAGEMENT_FN_
VIOLATION_P
SAS_SSP_TASK_
MANAGEMENT_FN_
VIOLATION_N
658
Violation
Description
SAS_STP_ALIGN_DWORD_
COUNT_VIOLATION_P
Transmit D (tx_data_minus) is
not driven to a valid level.
SAS_STP_ALIGN_DWORD_
COUNT_VIOLATION_N
SAS_STP_HOLD_HOLDA_
DWORD_VIOLATION_P
SAS_STP_HOLD_HOLDA_
DWORD_VIOLATION_N
SAS_TARGET_PORT_XFER_
TAG_VIOLATION_P
SAS_TARGET_PORT_XFER_
TAG_VIOLATION_N
SAS_TX_DN_UNKN_P
SAS_TX_DN_UNKN_N
SAS_TX_DP_UNKN_P
SAS_TX_DP_UNKN_N
SAS_XFER_RDY_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_P
SAS_XFER_RDY_RECEIVED_
WITHOUT_ACK_NAK_
WITHOUT_DONE_ACK_NAK_N
659
660
661
Description
Transactions completed
ACK received
662
Description
SSP transactions
SMP transactions
STP transactions
Time outs
Number of timeouts.
ACK/NAK timeouts
Credit timeouts
Monitor Statistics
Table 15-11 shows the statistics maintained by the SAS monitor. These statistics are collected
for the transmit and the receive interfaces.
Table 15-11. SAS Monitor Statistics
Statistics
Description
Transactions
Number of transactions.
Disparity errors
Data frames
Command frames
Xferrdy frames
Response frames
Task frames
Times outs
Number of timeouts.
663
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL SAS monitor.
What types of devices are tracked by the SAS monitor?
SAS monitor can track SAS end devices and SAS expander devices. Use the
SAS_DEVICE_TYPE parameter to configure the device tracked. The SAS monitor does
not track SATA devices.
How is the SAS monitor instantiated in a multi-PHY core?
Each SAS monitor tracks only one PHY. Multiple SAS monitor instances are required to
track multiple PHYs of a device (see Figure 15-6).
Figure 15-6. Examples of Single- and Multi-PHY Devices
1-PHY Device
SAS Device B
SAS Device A
SAS Monitor
PHY
PHY
3-PHY Device
SAS Device A
SAS Device B
SAS Monitor
PHY
PHY
SAS Monitor
PHY
PHY
SAS Monitor
PHY
664
PHY
bit
19
18
17
16
15
14
13
12
11
10
encoding
-------------------------K28.5--------------------------
An SAS interface does not have a clock signal, but the SAS monitor has a clock
input. How are an SAS monitors clock signals connected?
If recovered clocks are available from the design, then connect the recovered clocks to
the SAS monitor clock inputs. The SAS monitor uses these clocks to sample data. If
recovered clocks are not available from the design, use the clock recovery module (see
Clock Recovery Module on page 640) to recover the clocks and connect the recovered
clocks to the monitor.
For example, the following instantiations recover the Tx and Rx clocks:
qvl_clock_recovery TX_CLOCK_RECOVERY (
665
(tx_data_plus),
(tx_data_minus),
(tx_recovered_clk)
);
qvl_clock_recovery RX_CLOCK_RECOVERY (
.pos_data
(rx_data_plus),
.neg_data
(rx_data_minus),
.clock
(rx_recovered_clk)
);
666
(rx_comsas_neg_time),
(rate_change_delay),
(spd_neg_lock_time),
(spd_neg_transmit_time),
(hotplug_timeout),
(comsas_timeout),
(hard_reset_timeout),
(ident_frame_timeout),
(break_timeout),
(open_addr_res_timeout),
(credit_timeout),
(ack_nak_timeout),
(close_timeout),
(done_timeout)
);
667
an electrical idle condition is assumed. By default, a bit pattern of 10'h3FF on the 10b
encoded data reflects an electrical idle condition on the bus.
Applicable only in parallel mode. In serial mode, all of these inputs are not applicable.
What value should the ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter be in
serial mode?
In serial mode, the value of the ELECTRICAL_IDLE_TIME_BIT_PATTERN parameter is
redundant. In this mode, the SAS monitor looks for equal data_plus and
data_minus signals to infer electrical idle periods.
The designs clocks are active on both edges. How is the SAS monitor connected?
Set the DOUBLE_DATA_RATE parameter to 1. Monitor cannot be configured for
DOUBLE_DATA_RATE mode for a 20 bit interface.
How does the monitor track the speed negotiation sequence?
SAS monitor configures the speed negotiation timers (RCDT, SNLT, and SNTT)
through the following parameters:
o
RATE_CHANGE_DELAY
SPEED_NEGOTIATION_LOCK_TIME
SPEED_NEGOTIATION_TRANSMIT_TIME
The values passed to these parameters correspond to OOBIs (One UI of G1). Therefore,
the length of each speed negotiation window is RCDT + SNTT. Parameter
TX_MAX_SUPPORTED_RATE configures the length of the entire speed negotiation
sequence by configuring the total number of speed negotiation windows in the speed
negotiation sequence.
During each window of the speed negotiation sequence, the RCD timer will expire first,
and start the SNLT and SNTT timers. If ALIGN0 to ALIGN1 transition is detected by
the monitor before the expiry of the SNLT timer, then the monitor assumes the device
supports this particular rate and waits for the expiry of the SNTT timer.
If ALIGN0 to ALIGN1 transition is not detected within the expiry of the SNLT timer in
a speed negotiation window, then that window is considered as failed. The monitor
assumes that the speed corresponding to this window is not supported.
What should the clock frequency be during G1, G2 and G3 windows of the speed
negotiation sequence?
The frequency of the clock should match the data rate of the speed negotiation window.
For example, if the speed negotiation sequence is in a G2 window, then the clock
frequency should correspond to 3 Gbps.
How does the SAS monitor detect dword synchronization?
668
If not specified, then the monitor takes the default range specified in the SAS
specification.
669
670
Chapter 16
SERIAL ATA (SATA)
Introduction
Serial ATA is a high-speed serial link replacement for the parallel ATA attachment of mass
storage devices. The serial link employed is a high-speed differential layer that utilizes Gigabit
technology and 8b/10b encoding. Serial ATA II specification defines enhancements to the
Serial ATA 1.0a specification that provide additional capabilities while retaining Serial ATA
1.0a compatibility and desktop cost structure.
The QVL SATA monitor is designed for checking the Serial ATA and Serial ATA II interfaces.
Reference Documentation
This SATA monitor is modeled from the requirements provided in the following documents:
Serial ATA II: Extensions to Serial ATA 1.0a Revision 1.2, 27-August-2004
SATA PHY Interface Specification (SAPIS) Draft Rev 0.90, February 8, 2002
Supported Features
Implementations
Host ports
Device ports
Interfaces
Serial Interface
SAPIS interface
671
Phy Layer
Speed negotiation
Power management
Link Layer
Framing
FIS sequencing
Auto-activate DMA
Asynchronous notification
672
SAPIS
SAPIS
MW
SATA
SAPIS
MW
SATA
MW
SATA
MW
Host Side
SATA
SATA
SATA
MW
SATA
MW
Host B
SATA
SATA
Host
Host A
SATA
MW
SATA
MW
SAPIS
MW
Device Side
Port Multiplier
SATA
MW
SAPIS
SAPIS
MW
Link Layer
Link Layer
Phy Layer
SATA
Port Selector
SATA
SATA
MW
SATA
SATA
MW
Device A
SATA
MW
Device B
SATA
MW
Device C
SATA
MW
Device
SATA
MW
Monitor Connectivity
Connect the SATA monitor as specified in the pin-out Table 16-1 and Table 16-2 and illustrated
in Figure 16-2.
673
RECEIVE
TRANSMIT
RECEIVE
TRANSMIT
SERIAL ATA
(Serial/Parallel10b interface)
Monitor
scrambling_off
bypass_power_on_seq
SERIAL ATA
(SAPIS Interface)
Monitor
scrambling_off
bypass_power_on_seq
areset
reset
tx_data[n:0]
tx_enable
tbc
rx_data[n:0]
rx_data_valid
rbc
rx_locked
k28.5_detect
comwake_detect
comreset_detect
cominit_detect
partial
slumber
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins
674
Port
Description
areset
Asynchronous reset signal, active high (not part of standard I/F signals).
bypass_power_on_seq
When this signal is active high the monitor does not track power on
sequence. See note 1 on page 676.
reset
Synchronous reset signal, active high (not part of standard I/F signals).
rx_clk
RX_data_plus
RX_data_minus
Input to the Phy. The differential data input to the serial interface when
the INTERFACE_TYPE parameter is set to 0. Connect parallel 10b
outputs from the serializer to this port when the INTERFACE_TYPE
parameter is set to 1.
scrambling_off
When this signal is active high, the incoming data will not be
descrambled.
Table 16-1. SATA - Serial and parallel 10B Interface Monitor Pins (cont.)
Port
Description
tx_clk
TX_data_plus
TX_data_minus
Output from the Phy. The differential data output from the serial
interface when the INTERFACE_TYPE parameter is set to 0. Connect
parallel 10b data input of the de-serializer to this port when the
INTERFACE_TYPE parameter is set to 1.
Description
areset
bypass_power_on_seq
When this signal is active high the monitor does not track power on sequence.
See note 1 on page 676.
comreset_detect
cominit_detect
Output from the Phy. This output goes high while the criteria for detecting
COMINIT_DETECT and/or COMRESET_DETECT have been met.
comwake_detect
Output from the Phy. This output goes high while the criteria for detecting
COM_WAKE are met.
k28.5_detect
Output from the Phy. K28.5_DETECT goes high while the K28.5 control
character is present (with either disparity) on the RX_DATA pins. Note that the
RX block is allowed to drop any instance of the Align character (as long as it is
dropped in its four byte entirety).
partial
Input to the Phy. When driven high, PARTIAL places the PHY in its Partial
power state as defined by the SATA specification.
rbc
Output from the Phy. RBC is the clock used by the PHY to transfer recovered
data to the link layer. The rbc[1] clock signal of the implementation under test
must be connected to this input.
reset
rx_data[n:0]
Output from the Phy. This delivers the recovered 10b or 20b or 40b data. The
RX block byte aligns the data. Note that RX_DATA bit 0 is the earliest bit
received at the RX inputs, and bit n is the latest received.
rx_data_valid
Output from the Phy. RX_DATA_VALID signal is used for flow control. A
high indicates that the concurrent RX_DATA outputs are valid; a low indicates
that they should be ignored.
rx_locked
Output from the Phy. RX_LOCKED goes high when the following three
conditions are met:
1. The differential input signal exceeds the Squelch Detector threshold
as defined by the SATA specification
2. The receiver is locked to the incoming signal
3. The RX byte alignment is correctly established
scrambling_off
When this signal is active high, the incoming data will not be descrambled.
slumber
Input to the Phy. When driven high, SLUMBER places the PHY in its Slumber
power state as defined by the SATA specification.
675
Description
tbc
Input to the Phy. TBC is the transmit byte clock used to clock data into the PHY
on the TX_DATA bus. TX data transitions occur concurrently with both edges
of TBC. Thus, TBC will nominally operate at 75MHz for Gen 1, and 150 MHz
for Gen2 signaling.
tx_data[n:0]
Input to the Phy. Encoded 10b or 20b or 40b parallel data sent from the Link
layer to the Phy layer for serialization and transmission. Note that TX_DATA
bit 0 is transmitted first, and bit n is transmitted last.
tx_enable
Input to the Phy. TX_ENABLE enables the SATA cable drivers in the
transmitter portion of the PHY. When this signal is high, the drivers generate
normal drive levels. When low, the PHY outputs are idle and maintain common
mode bias as specified in the SATA specification.
where bit a is the LSB of the 10B data and bit j is the MSB of the 10B data.
Monitor Parameters
The parameters shown in Table 16-3 and Table 16-4 on page 678 configure the SATA monitor.
Table 16-3. SATA Monitor Parameters - Serial / Parallel10B Interfaces
Order Parameter
Default Description
1.
Constraints_Mode
2.
INTERFACE_TYPE
3.
DEVICE_TYPE
676
Default Description
4.
PARALLEL_DATA_WIDTH
10
5.
DOUBLE_DATA_RATE
6.
MAX_DEV_SPEED
7.
NCQ_COMMAND_ENABLE
8.
LEGACY_QUEUED_
COMMAND_ENABLE
9.
PORT_SELECTOR_ENABLE
10.
PORT_MULTIPLIER_ENABLE
11.
PACKET_COMMAND_ENABLE
12.
RESERVED_VALUE_
CHECKING_ENABLE
13.
POWER_MGMT_ENABLE
14.
MAX_QUEUE_DEPTH
15.
ASYNC_SIGNAL_RECOVERY
677
Default Description
16.
RETRY_INTERVAL
17.
RESERVED_FIS_TYPE_
ENABLE
18.
VENDOR_FIS_TYPE_ENABLE
19.
ELECTRICAL_IDLE_
PATTERN
Note that the RETRY_INTERVAL parameter is by default configured to 14999250 GEN serial
clock - 1UI (unit interval - 1bit time). When the monitor is configured in parallel 10B mode, the
default value of this parameter is set to 1499925 GEN1 parallel 10B clocks (10 UIs).
Default
Description
1.
Constraints_Mode
2.
LINK_SIDE
3.
DEVICE_TYPE
4.
PARALLEL_DATA_WIDTH
10
5.
DOUBLE_DATA_RATE
678
Default
Description
6.
MAX_DEV_SPEED
7.
NCQ_COMMAND_ENABLE
8.
LEGACY_QUEUED_COMMAND_
ENABLE
9.
PORT_SELECTOR_ENABLE
10.
PORT_MULTIPLIER_ENABLE
11.
PACKET_COMMAND_ENABLE
12.
RESERVED_VALUE_CHECKING_ 1
ENABLE
13.
POWER_MGMT_ENABLE
14.
MAX_QUEUE_DEPTH
15.
ASYNC_SIGNAL_RECOVERY
16.
RETRY_INTERVAL
14999250
17.
RESERVED_FIS_TYPE_ENABLE
18.
VENDOR_FIS_TYPE_ENABLE
679
Note that the RETRY_INTERVAL parameter is by default configured to 14999250 GEN serial
clock - 1UI (unit interval - 1bit time). When the monitor is configured in parallel 10B mode, the
default value of this parameter is set to 1499925 GEN1 parallel 10B clocks (10 UIs).
Instantiation Examples
Example 1
Example 16-1 instantiates a SATA monitor on a Host serial interface with maximum speed of
GEN1, power management mode, legacy queued commands and reserved field checking
enabled and double data rate, packet command, NCQ commands, asynchronous signal
recovery, reserved FIS and vendor specific FIS disabled.
Example 16-1. SATA Monitor Instantiation
qvl_sata_monitor #(
0, /* Constraints_Mode */
0, /* INTERFACE_TYPE */
0, /* DEVICE_TYPE */
0, /* PARALLEL_DATA_WIDTH */
0, /* DOUBLE_DATA_RATE */
0, /* MAX_DEV_SPEED */
0, /* NCQ_COMMAND_ENABLE */
1, /* LEGACY_QUEUED_COMMAND_ENABLE */
0, /* PORT_SELECTOR_ENABLE */
0, /* PORT_MULTIPLIER_ENABLE */
0, /* PACKET_COMMAND_ENABLE */
1, /* RESERVED_VALUE_CHECKING_ENABLE */
1, /* POWER_MGMT_ENABLE */
32,/* MAX_QUEUE_DEPTH */
0, /* ASYNC_SIGNAL_RECOVERY */
0, /* RETRY_INTERVAL */
0, /* RESERVED_FIS_TYPE_ENABLE */
0, /* VENDOR_FIS_TYPE_ENABLE */
0 /* ELECTRICAL_IDLE_PATTERN */
)
SATA_MONITOR
(.areset(areset),
.reset(reset),
.tx_clk(tx_clk),
.tx_data_plus(tx_data_plus),
.tx_data_minus(tx_data_minus),
.rx_clk(rx_clk),
.rx_data_plus(rx_data_plus),
.rx_data_minus(rx_data_minus),
.scrambling_off(scrambling_off),
.bypass_power_on_seq(bypass_power_on_seq));
680
Example 2
Example 16-2 instantiates a SATA monitor on a Device 10B interface with maximum
supported speed of GEN2, double data rate, power management mode, NCQ commands with
max queue depth of 16 and reserved field checking enabled and packet command, legacy
queued commands, asynchronous signal recovery, reserved FIS and vendor specific FIS
disabled.
Example 16-2. SATA Monitor Instantiation
qvl_sata_monitor #(
0, /* Constraints_Mode */
1, /* INTERFACE_TYPE */
1, /* DEVICE_TYPE */
10,/* PARALLEL_DATA_WIDTH */
1, /* DOUBLE_DATA_RATE */
1, /* MAX_DEV_SPEED */
1, /* NCQ_COMMAND_ENABLE */
0, /* LEGACY_QUEUED_COMMAND_ENABLE */
0, /* PORT_SELECTOR_ENABLE */
0, /* PORT_MULTIPLIER_ENABLE */
0, /* PACKET_COMMAND_ENABLE */
1, /* RESERVED_VALUE_CHECKING_ENABLE */
1, /* POWER_MGMT_ENABLE */
16,/* MAX_QUEUE_DEPTH */
0, /* ASYNC_SIGNAL_RECOVERY */
0, /* RETRY_INTERVAL */
0, /* RESERVED_FIS_TYPE_ENABLE */
0, /* VENDOR_FIS_TYPE_ENABLE */
0 /* ELECTRICAL_IDLE_PATTERN */
)
SATA_MONITOR
(.areset(areset),
.reset(reset),
.tx_clk(tx_clk),
.tx_data_plus(tx_data_plus),
.tx_data_minus(tx_data_minus),
.rx_clk(rx_clk),
.rx_data_plus(rx_data_plus),
.rx_data_minus(rx_data_minus),
.scrambling_off(scrambling_off),
.bypass_power_on_seq(bypass_power_on_seq)
);
Example 3
Example 16-3 instantiates a SATA monitor on a 40B interface in the host side of the port
multiplier with maximum supported speed of GEN1, double data rate, power management
mode, NCQ commands with max queue depth of 16 and reserved field checking enabled and
packet command, legacy queued commands, asynchronous signal recovery, reserved FIS and
vendor specific FIS disabled.
681
Example 4
Example 16-4 instantiates a SATA monitor on a 20B SAPIS interface on the link side of the
device with maximum supported speed of GEN2, double data rate, packet command,
asynchronous signal recovery, reserved FIS and vendor specific FIS enabled and power
management mode, NCQ commands, legacy queued commands and reserved field checking
disabled.
Example 16-4. SATA Monitor Instantiation
qvl_sata_sapis_monitor #(
0, /* Constraints_Mode */
1, /* LINK_SIDE */
1, /* DEVICE_TYPE */
20,/* PARALLEL_DATA_WIDTH */
1, /* DOUBLE_DATA_RATE */
1, /* MAX_DEV_SPEED */
0, /* NCQ_COMMAND_ENABLE */
682
Monitor Checks
The checks performed by the SATA monitor are listed in the following subsections.
Violation
Description
SATA_ALIGNP_D24_3_
VIOLATION_P
SATA_ALIGNP_D24_3_
VIOLATION_N
683
Violation
Description
SATA_COMINIT_BURST_
TIME_VIOLATION_P
SATA_COMINIT_BURST_
TIME_VIOLATION_N
SATA_COMINIT_BURST_
VIOLATION_P
SATA_COMINIT_BURST_
VIOLATION_N
SATA_COMINIT_INTER_
BURST_TIME_VIOLATION_P
SATA_COMINIT_INTER_
BURST_TIME_VIOLATION_N
SATA_COMRESET_BURST_
VIOLATION_P
SATA_COMRESET_BURST_
VIOLATION_N
SATA_COMRESET_BURST_
TIME_VIOLATION_P
SATA_COMRESET_BURST_
TIME_VIOLATION_N
SATA_COMRESET_INTER_
BURST_TIME_VIOLATION_P
SATA_COMRESET_INTER_
BURST_TIME_VIOLATION_N
684
Violation
Description
SATA_COMWAKE_BURST_
TIME_VIOLATION_P
SATA_COMWAKE_BURST_
TIME_VIOLATION_N
SATA_COMWAKE_BURST_
VIOLATION_P
SATA_COMWAKE_BURST_
VIOLATION_N
SATA_COMWAKE_INTER_
BURST_TIME_VIOLATION_P
SATA_COMWAKE_INTER_
BURST_TIME_VIOLATION_N
SATA_COMWAKE_LAST_
IDLE_VIOLATION_P
SATA_COMWAKE_LAST_
IDLE_VIOLATION_N
SATA_D10_2_BEFORE_D_
COMWAKE_VIOLATION_P
SATA_D10_2_BEFORE_D_
COMWAKE_VIOLATION_N
SATA_D_COMWAKE_WO_
H_COMWAKE_VIOLATION_P
SATA_D_COMWAKE_WO_
H_COMWAKE_VIOLATION_N
SATA_H_COMWAKE_WO_
COMINIT_VIOLATION_P
SATA_H_COMWAKE_WO_
COMINIT_VIOLATION_N
685
Violation
Description
SATA_RX_D_COMWAKE_TO_
D10_2_VIOLATION_P
After receiving
COMWAKE, the host must
receive at least 2048
ALIGNp primitives.
SATA_RX_D_COMWAKE_TO_
D10_2_VIOLATION_N
SATA_RX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_P
SATA_RX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_N
SATA_RX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_P
SATA_RX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_N
SATA_RX_NO_2048_ALIGNP_
VIOLATION_P
SATA_RX_NO_2048_ALIGNP_
VIOLATION_N
686
Violation
Description
SATA_TX_D_COMWAKE_TO_
D10_2_VIOLATION_P
After transmitting
COMWAKE, the device
must transmit at least 2048
ALIGNp primitives.
SATA_TX_D_COMWAKE_TO_
D10_2_VIOLATION_N
SATA_TX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_P
SATA_TX_H_ALIGN_BEFORE_
D_ALIGN_VIOLATION_N
SATA_TX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_P
SATA_TX_H_COMWAKE_TO_
D_ALIGNP_VIOLATION_N
SATA_TX_NO_2048_ALIGNP_
VIOLATION_P
SATA_TX_NO_2048_ALIGNP_
VIOLATION_N
SATA_TX_RETRY_INTERVAL_
VIOLATION_P
SATA_TX_RETRY_INTERVAL_
VIOLATION_N
687
Violation
Description
SATA_ALIGN_P_PAIR_
VIOLATION_P
SATA_CONT_P_VIOLATION_N
SATA_CRC_ERROR_
VIOLATION_P
SATA_ALIGN_P_PAIR_
VIOLATION_N
SATA_CODE_ERR_
VIOLATION_P
SATA_CODE_ERR_
VIOLATION_N
SATA_CONT_P_VIOLATION_P
SATA_CRC_ERRORCODE_ERR_
VIOLATION_N
SATA_DATA_OUTSIDE_SOF_
EOF_VIOLATION_P
SATA_DATA_OUTSIDE_SOF_
EOF_VIOLATION_N
SATA_DISPARITY_
VIOLATION_P
SATA_DISPARITY_
VIOLATION_N
688
Violation
Description
SATA_DMAT_BY_
TRANSMITTER_VIOLATION_P
SATA_DMAT_BY_
TRANSMITTER_VIOLATION_N
SATA_DMAT_P_RIP_P_
VIOLATION_P
SATA_DMAT_P_RIP_P_
VIOLATION_N
SATA_EOF_P_MORE_THAN_
ONCE_VIOLATION_P
SATA_EOF_P_MORE_THAN_
ONCE_VIOLATION_N
SATA_EOF_P_WTRM_P_
VIOLATION_P
SATA_EOF_P_WTRM_P_
VIOLATION_N
689
Violation
Description
SATA_INVALID_K_CODE_
VIOLATION_P
SATA_INVALID_K_CODE_
VIOLATION_N
SATA_INVALID_PRIMITIVE_P
SATA_INVALID_PRIMITIVE_N
SATA_K_CODE_NOT_BYTE0_
VIOLATION_P
SATA_K_CODE_NOT_BYTE0_
VIOLATION_N
SATA_NON_ALIGN_DWORD_
VIOLATION_P
SATA_NON_ALIGN_DWORD_
VIOLATION_N
SATA_PMACK_P_LESS_
THAN_4_VIOLATION_P
SATA_PMACK_P_LESS_
THAN_4_VIOLATION_N
690
Violation
Description
SATA_PMACK_P_MORE_
THAN_16_VIOLATION_P
SATA_PMACK_P_MORE_
THAN_16_VIOLATION_N
SATA_R_OK_P_WHEN_
CRC_ERR_VIOLATION_P
SATA_R_OK_P_WHEN_
CRC_ERR_VIOLATION_N
SATA_RD_000111_SUB_BLK_
VIOLATION_P
SATA_RD_000111_SUB_BLK_
VIOLATION_N
SATA_RD_0011_SUB_BLK_
VIOLATION_P
SATA_RD_0011_SUB_BLK_
VIOLATION_N
SATA_RD_1100_SUB_BLK_
VIOLATION_P
SATA_RD_1100_SUB_BLK_
VIOLATION_N
SATA_RD_111000_SUB_BLK_
VIOLATION_P
SATA_RD_111000_SUB_BLK_
VIOLATION_N
691
Violation
SATA_REPEAT_PRIMITIVE_
VIOLATION_P
SATA_REPEAT_PRIMITIVE_
VIOLATION_N
SATA_ROK_FOR_10B_
DISPERR_VIOLATION_P
SATA_ROK_FOR_10B_
DISPERR_VIOLATION_N
SATA_ROK_FOR_INVALID_
FIS_VIOLATION_P
SATA_ROK_FOR_INVALID_
FIS_VIOLATION_N
SATA_ROK_FOR_MALF_FIS_
VIOLATION_P
SATA_ROK_FOR_MALF_FIS_
VIOLATION_N
SATA_RX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_RX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_N
692
Description
On reception of a malformed
frame, such as a frame with
incorrect length, the host or
device must negatively
acknowledge by issuing R_ERRp
during the frame
acknowledgement handshake.
This check fires when the frame
is acknowledged by R_OKp
primitive.
Violation
Description
SATA_RX_DPMREQ_WHILE_
HPMREQ_VIOLATION_P
On receipt of PMREQ_Pp or
PMREQ_Sp from the device
while transmitting PMREQ_Pp or
PMREQ_Sp, the host must start
transmitting SYNCp without
entering power down mode.
SATA_RX_DPMREQ_WHILE_
HPMREQ_VIOLATION_N
SATA_RX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_RX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_RX_HOLDA_P_
LATENCY_VIOLATION_P
SATA_RX_HOLDA_P_
LATENCY_VIOLATION_N
SATA_RX_HOLDA_UNTIL_
HOLD_VIOLATION_P
SATA_RX_HOLDA_UNTIL_
HOLD_VIOLATION_N
SATA_RX_HOLDA_WO_
HOLD_VIOLATION_P
SATA_RX_HOLDA_WO_
HOLD_VIOLATION_N
SATA_RX_HOST_BACK_OFF_
VIOLATION_P
SATA_RX_HOST_BACK_OFF_
VIOLATION_N
693
Violation
Description
SATA_RX_HPMREQ_WHILE_
DPMREQ_VIOLATION_P
On receipt of PMREQ_Pp or
PMREQ_Sp from the host, the
device must continue transmitting
PMREQ and enter power down
mode.
SATA_RX_HPMREQ_WHILE_
DPMREQ_VIOLATION_N
SATA_RX_PMACK_WO_
PMREQ_VIOLATION_P
SATA_RX_PMACK_WO_
PMREQ_VIOLATION_N
SATA_RX_PMNACK_WO_
PMREQ_VIOLATION_P
SATA_RX_PMNACK_WO_
PMREQ_VIOLATION_N
SATA_RX_R_RDY_WO_
X_RDY_VIOLATION_P
SATA_RX_R_RDY_WO_
X_RDY_VIOLATION_N
SATA_RX_RERR_UNTIL_
SYNC_VIOLATION_P
SATA_RX_RERR_UNTIL_
SYNC_VIOLATION_N
SATA_RX_RIP_AFTER_EOF_
VIOLATION_P
SATA_RX_RIP_AFTER_EOF_
VIOLATION_N
694
Violation
Description
SATA_RX_ROK_FOR_
TX_CNT_ERR_VIOLATION_P
SATA_RX_ROK_FOR_
TX_CNT_ERR_VIOLATION_N
SATA_RX_ROK_UNTIL_SYNC_
VIOLATION_P
SATA_RX_ROK_UNTIL_SYNC_
VIOLATION_N
SATA_RX_SOF_WO_RRDY_
VIOLATION_P
SATA_RX_SOF_WO_RRDY_
VIOLATION_N
SATA_RX_SYNC_AFTER_
TX_SYNC_VIOLATION_P
SATA_RX_SYNC_AFTER_
TX_SYNC_VIOLATION_N
SATA_RX_SYNC_UNTIL_
SYNC_VIOLATION_P
SATA_RX_SYNC_UNTIL_
SYNC_VIOLATION_N
SATA_RX_WTRM_UNTIL_
S_VIOLATION_P
SATA_RX_WTRM_UNTIL_
STS_VIOLATION_N
695
Violation
Description
SATA_RX_XRDY_DURING_
PMREQ_VIOLATION_P
On receipt of PMREQ_Pp or
PMREQ_Sp from the device
while transmitting PMREQ_Pp or
PMREQ_Sp, the host must start
transmitting SYNCp without
entering power down mode.
SATA_RX_XRDY_DURING_
PMREQ_VIOLATION_N
SATA_SOF_P_MORE_THAN_
ONCE_VIOLATION_P
SATA_SOF_P_MORE_THAN_
ONCE_VIOLATION_N
SATA_SYNC_P_BEFORE_
PMREQP_P_VIOLATION_P
SATA_SYNC_P_BEFORE_
PMREQP_P_VIOLATION_N
SATA_SYNC_P_BEFORE_
PMREQS_P_VIOLATION_P
SATA_SYNC_P_BEFORE_
PMREQS_P_VIOLATION_N
SATA_TX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_TX_DMAT_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_TX_DPMREQ_WHILE_
HPMREQ_VIOLATION_P
SATA_TX_DPMREQ_WHILE_
HPMREQ_VIOLATION_N
696
Violation
Description
SATA_TX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_P
SATA_TX_HOLD_OUTSIDE_
EOF_SOF_VIOLATION_N
SATA_TX_HOLDA_P_
LATENCY_VIOLATION_P
SATA_TX_HOLDA_P_
LATENCY_VIOLATION_N
SATA_TX_HOLDA_UNTIL_
HOLD_VIOLATION_P
SATA_TX_HOLDA_UNTIL_
HOLD_VIOLATION_N
SATA_TX_HOLDA_WO_
HOLD_VIOLATION_P
On receipt of PMREQ_Pp or
PMREQ_Sp from the host while
transmitting PMREQ_Pp or
PMREQ_Sp, the device must
continue transmitting PMREQ
and enter power down mode.
SATA_TX_HOLDA_WO_
HOLD_VIOLATION_N
SATA_TX_HOST_BACK_OFF_
VIOLATION_P
SATA_TX_HOST_BACK_OFF_
VIOLATION_N
SATA_TX_HPMREQ_WHILE_
DPMREQ_VIOLATION_P
SATA_TX_HPMREQ_WHILE_
DPMREQ_VIOLATION_N
697
Violation
Description
SATA_TX_PMACK_WO_
PMREQ_VIOLATION_P
SATA_TX_PMACK_WO_
PMREQ_VIOLATION_N
SATA_TX_PMNACK_WO_
PMREQ_VIOLATION_P
SATA_TX_PMNACK_WO_
PMREQ_VIOLATION_N
SATA_TX_R_RDY_WO_
X_RDY_VIOLATION_P
SATA_TX_R_RDY_WO_
X_RDY_VIOLATION_N
SATA_TX_RERR_UNTIL_
SYNC_VIOLATION_P
SATA_TX_RERR_UNTIL_
SYNC_VIOLATION_N
SATA_TX_RIP_AFTER_EOF_
VIOLATION_P
SATA_TX_RIP_AFTER_EOF_
VIOLATION_N
SATA_TX_ROK_FOR_
TX_CNT_ERR_VIOLATION_P
SATA_TX_ROK_FOR_
TX_CNT_ERR_VIOLATION_N
698
Violation
Description
SATA_TX_ROK_UNTIL_SYNC_
VIOLATION_P
SATA_TX_ROK_UNTIL_SYNC_
VIOLATION_N
SATA_TX_SOF_WO_RRDY_
VIOLATION_P
SATA_TX_SOF_WO_RRDY_
VIOLATION_N
SATA_TX_SYNC_AFTER_
RX_SYNC_VIOLATION_P
SATA_TX_SYNC_AFTER_
RX_SYNC_VIOLATION_N
SATA_TX_SYNC_UNTIL_
SYNC_VIOLATION_P
SATA_TX_SYNC_UNTIL_
SYNC_VIOLATION_N
SATA_TX_WTRM_UNTIL_
STS_VIOLATION_P
SATA_TX_WTRM_UNTIL_
STS_VIOLATION_N
SATA_TX_XRDY_DURING_
PMREQ_VIOLATION_P
SATA_TX_XRDY_DURING_
PMREQ_VIOLATION_N
699
Violation
Description
SATA_AN_IN_SET_DEV_BIT_
VIOLATION_P
SATA_AN_IN_SET_DEV_BIT_
VIOLATION_N
SATA_AN_WHEN_NOTF_
PEND_VIOLATION_P
SATA_AN_WHEN_NOTF_
PEND_VIOLATION_N
SATA_AUTO_ACT_IN_
RD_TX_VIOLATION_P
SATA_AUTO_ACT_IN_
RD_TX_VIOLATION_N
SATA_BIST_ACT_FIS_
COUNT_VIOLATION_P
SATA_BIST_ACT_FIS_
COUNT_VIOLATION_N
SATA_DATA_COUNT_
VIOLATION_P
SATA_DATA_COUNT_
VIOLATION_N
SATA_DATA_FIS_IN_
PIO_CMD_VIOLATION_P
SATA_DATA_FIS_IN_
PIO_CMD_VIOLATION_N
SATA_DATA_NOT_DWORD_
ALIGNED_VIOLATION_P
SATA_DATA_NOT_DWORD_
ALIGNED_VIOLATION_N
700
The data is not dword aligned. The SATA protocol requires that the
data transferred to be dword aligned.
This check fires when data is not dword
aligned.
Violation
Description
SATA_DEV_RST_CMD_IN_
PM_VIOLATION_P
On receipt of DMA-IN
command from the host, the
device shall transmit either
REG device to host FIS or
data FIS.
A REG host to device FIS with DMAIN command from the host must be
followed by either REG device to host
fis or data FIS. This check fires when a
FIS other than REG device to host or
data FIS follows REG host to device
FIS with DMA IN command.
SATA_DMA_OUT_CMD_
VIOLATION_N
On receipt of DMA-OUT
command from the host, the
device must not transmit any
other FIS other than DMA
activate FIS.
SATA_DMA_SETUP_FIS_
COUNT_VIOLATION_P
SATA_DEV_RST_CMD_IN_
PM_VIOLATION_N
SATA_DEV_RST_GS_
VIOLATION_P
SATA_DEV_RST_GS_
VIOLATION_N
SATA_DMA_ACT_CMD_
VIOLATION_P
SATA_DMA_ACT_CMD_
VIOLATION_N
SATA_DMA_ACT_FIS_COUNT_
VIOLATION_P
SATA_DMA_ACT_FIS_COUNT_
VIOLATION_N
SATA_DMA_ACT_WHEN_
AUTO_ACT_VIOLATION_P
SATA_DMA_ACT_WHEN_
AUTO_ACT_VIOLATION_N
SATA_DMA_IN_CMD_
VIOLATION_P
SATA_DMA_IN_CMD_
VIOLATION_N
SATA_DMA_OUT_CMD_
VIOLATION_P
SATA_DMA_SETUP_FIS_
COUNT_VIOLATION_N
701
Violation
SATA_DMA_TRANSFER_
COUNT_VIOLATION_P
SATA_DMA_TRANSFER_
COUNT_VIOLATION_N
SATA_EX_DIAG_BS_NP_
VIOLATION_P
SATA_EX_DIAG_BS_NP_
VIOLATION_N
SATA_EX_DIAG_BS_P_
VIOLATION_P
SATA_EX_DIAG_BS_P_
VIOLATION_N
SATA_EX_DIAG_GS_NP_
VIOLATION_P
SATA_EX_DIAG_GS_NP_
VIOLATION_N
SATA_EX_DIAG_GS_P_
VIOLATION_P
SATA_EX_DIAG_GS_P_
VIOLATION_N
SATA_FIS_WHEN_SRST_
VIOLATION_P
SATA_FIS_WHEN_SRST_
VIOLATION_N
SATA_LEGACY_QUEUED_
CMD_VIOLATION_P
SATA_LEGACY_QUEUED_
CMD_VIOLATION_N
702
Description
On execution of EXECUTE_DEVICE_
DIAGNOSTIC command from the host,
the device must transmit REG device to
host FIS with bad status as in page: 247
for the non-packet command feature set.
This check fires when the bad status
format is violated.
On execution of EXECUTE_DEVICE_
DIAGNOSTIC command from the host,
the device must transmit REG device to
host FIS with bad status as in page: 247
for the packet command feature set.
This check fires when the bad status
format is violated.
On execution of the
EXECUTE_DEVICE_DIAGNOSTIC
command from the host, the device must
transmit REG device to host FIS with
good status to the host as in page: 246
for non-packet command feature set.
This check fires when the good status
format is violated.
On execution of EXECUTE_DEVICE_
DIAGNOSTIC command from the host,
the device must transmit REG device to
host FIS with good status to the host as
in page: 246 for the packet command
feature set.This check fires when the
good status format is violated.
Violation
Description
SATA_NCQ_CMD_
VIOLATION_P
SATA_NCQ_CMD_
VIOLATION_N
SATA_NCQ_QUEUE_DEPTH_
VIOLATION_P
SATA_NCQ_QUEUE_DEPTH_
VIOLATION_N
SATA_NCQ_REG_D2H_STS_
VIOLATION_P
SATA_NCQ_REG_D2H_STS_
VIOLATION_N
SATA_NCQ_RESP_WO_CMD_
VIOLATION_P
SATA_NCQ_RESP_WO_CMD_
VIOLATION_N
SATA_NCQ_STS_WO_CMD_
VIOLATION_P
SATA_NCQ_STS_WO_CMD_
VIOLATION_N
SATA_NCQ_STS_WO_RESP_
VIOLATION_P
SATA_NCQ_STS_WO_RESP_
VIOLATION_N
SATA_NO_DATA_AFTER_
PIO_SETUP_VIOLATION_P
SATA_NO_DATA_AFTER_
PIO_SETUP_VIOLATION_N
703
Violation
Description
SATA_NON_NCQ_CMD_STS_
VIOLATION_P
SATA_NON_NCQ_CMD_STS_
VIOLATION_N
On reception of legacy
command when NCQ
command is pending the REG
FIS sent by the device in
response must have ERR and
ABRT bits set to 1 and BSY
bit cleared.
SATA_NON_NCQ_WHEN_NCQ_
PENDING_VIOLATION_P
SATA_OTHER_CMD_GS_
VIOLATION_N
SATA_PACKET_CMD_
VIOLATION_P
SATA_NON_NCQ_WHEN_NCQ_
PENDING_VIOLATION_N
SATA_OTHER_CMD_BS_
VIOLATION_P
SATA_OTHER_CMD_BS_
VIOLATION_N
SATA_OTHER_CMD_GS_
VIOLATION_P
SATA_PACKET_CMD_
VIOLATION_N
SATA_PIO_SETUP_FIS_
COUNT_VIOLATION_P
SATA_PIO_SETUP_FIS_
COUNT_VIOLATION_N
704
Violation
Description
SATA_PIO_SETUP_STS_
VIOLATION_P
SATA_PIO_SETUP_STS_
VIOLATION_N
SATA_PIO_TRANSFER_
COUNT_VIOLATION_P
SATA_PIO_TRANSFER_
COUNT_VIOLATION_N
SATA_PKT_CMD_PIO_SETUP_
VIOLATION_P
SATA_PKT_CMD_PIO_SETUP_
VIOLATION_N
SATA_RD_LOG_CMD_STS_
VIOLATION_P
SATA_RD_LOG_CMD_STS_
VIOLATION_N
SATA_REG_D2H_FIS_COUNT_
VIOLATION_P
SATA_REG_D2H_FIS_COUNT_
VIOLATION_N
SATA_REG_D2H_STS_
VIOLATION_P
SATA_REG_D2H_STS_
VIOLATION_N
SATA_REG_H2D_FIS_COUNT_
VIOLATION_P
SATA_REG_H2D_FIS_COUNT_
VIOLATION_N
705
Violation
Description
SATA_REL_BIT_IN_CMD_
VIOLATION_P
SATA_REL_BIT_IN_CMD_
VIOLATION_N
SATA_RESERVED_FIELD_
VIOLATION_P
SATA_RESERVED_FIELD_
VIOLATION_N
SATA_SERV_IN_REG_D2H_
FIS_VIOLATION_P
SATA_SERV_IN_REG_D2H_
FIS_VIOLATION_N
SATA_SERVICE_CMD_
VIOLATION_P
SATA_SERVICE_CMD_
VIOLATION_N
SATA_SET_DEV_FIS_COUNT_
VIOLATION_P
SATA_SET_DEV_FIS_COUNT_
VIOLATION_N
SATA_SRST_BS_NP_
VIOLATION_P
SATA_SRST_BS_NP_
VIOLATION_N
SATA_SRST_BS_P_
VIOLATION_P
SATA_SRST_BS_P_
VIOLATION_N
706
Bad status format violation for On reception of REG device to host FIS
Soft reset protocol of nonwith SRST bit cleared, the device must
packet feature set.
transmit REG device to host FIS with
bad status as in page 244 for the nonpacket command feature set.This check
fires when the bad status format is
violated.
Bad status format violation for On reception of REG device to host FIS
Soft reset protocol of packet
with SRST bit cleared, the device must
feature set.
transmit REG device to host FIS with
bad status as in page 244 for the packet
command feature set.This check fires
when the bad status format is violated.
Violation
Description
SATA_SRST_GS_NP_
VIOLATION_P
SATA_SRST_GS_NP_
VIOLATION_N
SATA_SRST_GS_P_
VIOLATION_P
SATA_SRST_GS_P_
VIOLATION_N
SAPIS Checks
Table 16-9. SAPIS Checks
Check ID
Violation
SATA_COMWAKE_IN_
PARTIAL_VIOLATION_P
SATA_COMWAKE_IN_
PARTIAL_VIOLATION_N
SATA_COMWAKE_IN_
SLUMBER_VIOLATION_P
SATA_COMWAKE_IN_
SLUMBER_VIOLATION_N
SATA_CR_CI_AND_CW_
ACTIVE_VIOLATION_P
SATA_CR_CI_AND_CW_
ACTIVE_VIOLATION_N
Description
707
Violation
Description
SATA_PARTIAL_SLUMBER_
ACTIVE_VIOLATION_P
SATA_PARTIAL_SLUMBER_
ACTIVE_VIOLATION_N
SATA_SAPIS_COMRESET_
COMINIT_DETECT_UNKN_
PSATA_SAPIS_COMRESET_
COMINIT_DETECT_UNKN_N
SATA_SAPIS_COMWAKE_
DETECT_UNKN_PSATA_SAPIS
COMWAKE_DETECT_UNKN_N
Signal COMWAKE_DETECT is
not driven to a valid level.
SATA_SAPIS_K28_5_DETECT_
UNKN_PSATA_SAPIS_K28_5_
DETECT_UNKN_N
SATA_SAPIS_PARTIAL_
UNKN_PSATA_SAPIS_
PARTIAL_UNKN_N
SATA_SAPIS_RX_DATA_
UNKN_PSATA_SAPIS_RX_
DATA_UNKN_N
SATA_SAPIS_RX_DATA_
VALID_UNKN_PSATA_SAPIS_
RX_DATA_VALID_UNKN_N
SATA_SAPIS_RX_LOCKED_
UNKN_PSATA_SAPIS_RX_
LOCKED_UNKN_N
SATA_SAPIS_SLUMBER_
UNKN_PSATA_SAPIS_
SLUMBER_UNKN_N
SATA_SAPIS_TX_DATA_
UNKN_PSATA_SAPIS_TX_
DATA_UNKN_N
SATA_SAPIS_TX_ENABLE_
UNKN_PSATA_SAPIS_TX_
ENABLE_UNKN_N
708
Normal Case
Description
Description
Description
709
710
Corner Case
Description
This gives the total number times partial power down mode
was initiated by the transmission of PMREQp.
This gives the total number times slumber power down mode
was initiated by the transmission of PMREQp.
This gives the total number times partial power down mode
was entered by the transmission of PMACKp.
This gives the total number times slumber power down mode
was entered by the transmission of PMACKp.
This gives the total number of frame transfers that were put
on hold (one statistic for each interface).
Description
Total number of good statuses sent through REG FIS. Number of good statuses send through REG FIS
device to host.
Total number of bad statuses sent through REG FIS.
Description
This gives the total number of times SRST bit was set in
the Reg host to device FIS.
711
Description
This gives the total number of REG FIS with ERR bit
set.
This gives the total number of SET Device bits FIS with
ERR bit set.
This gives the total number of PIO setup FIS with ERR
bit set.
This gives the total number of times REL bit in the REG
FIS set to "1".
712
Description
713
Monitor FAQ
Following are answers to frequently asked questions (FAQ) about the QVL SATA monitor.
1. What are the various interfaces supported by the monitor?
The QVL SATA monitor supports the following interfaces:
o
714
715
Yes, the PACKET_COMMAND_ENABLE parameter must be set to "1" to enable the tracking
of the packet command feature set.
13. Does the monitor support the Legacy queued command feature?
Yes, the LEGACY_QUEUED_COMMAND_ENABLE parameter must be set to "1" to enable the
tracking of the legacy queued commands.
14. Does the monitor support the Native command queuing?
Yes, the NCQ_COMMAND_ENABLE parameter must be set to "1" to enable the tracking of
the NCQ commands.
15. What is the significance of the PORT_MULTIPLIER_ENABLE parameter?
When the monitor is instantiated in a design under test with a SATA compliant port
multiplier device or host interface, this parameter must be set to "1" to indicate the
monitor is instantiated on the port multiplier interface.
16. What is the significance of PORT_SELECTOR_ENABLE parameter?
When the monitor is instantiated in a design under test with a SATA compliant port
selector device or host interface, this parameter must be set to "1" to indicate the monitor
is instantiated on the port selector interface.
17. When is it required to set the ASYNCHRONOUS_SIGNAL_RECOVERY
parameter?
When the monitor is instantiated in a DUT that supports Asynchronous signal recovery
and the monitor is required to track ASR, this parameter has to be set to "1".
18. What is the purpose of the RETRY_INTERVAL parameter?
The default value of this parameter is set to 14999250 (GEN1 clocks = 10ms). In case
the user wants to reconfigure this value, this parameter is provided to override the
default value set in the monitor. This is used for debugging purpose.
19. What are the parameters that need to be configured in the monitor to enable
tracking of the NCQ commands?
The NCQ_COMMAND_ENABLE parameter must be set to "1". Also, configure the
MAX_QUEUE_DEPTH parameter to the maximum allowed. NCQ commands can be
outstanding at a particular instant. If the design under test allows a maximum of 16 NCQ
commands to be outstanding, then set this parameter to 16.
20. What is the significance of the LINK_SIDE parameter in SAPIS monitor?
This parameter indicates whether the monitor is instantiated on the LINK side or the
PHY side of the SAPIS interface. Set this to "0" if the monitor is instantiated on the
PHY side of the SAPIS interface. By default, the monitor is instantiated on the LINK
side of the SAPIS interface.
716
21. The design under test is compliant to the SATA I specification. How do I configure
the monitor?
The parameters NCQ_COMMAND_ENABLE and ASYNC_SIGNAL_RECOVERY must be set to
"0".
717
718
Chapter 17
Serial Parallel Interface (SPI) Monitor
Introduction
The Serial Parallel Interface (SPI) module allows a duplex, synchronous, serial communication
between the MCU and peripheral devices. Software can poll the SPI status flags or the SPI
operation can be interrupt driven. The QVL SPI monitor is designed for checking the SPI
interface.
Reference Documentation
This QVL SPI monitor is modeled from the requirements provided in the following documents:
Supported Features
SPI supports the following features:
Multiple Slave
LSB-First Enable
719
SPI
Master
SPI
Slave
SPI Interface
QVL
QVL
Monitor Connectivity
Connect the SPI Master or Slave monitor pins to internal signals as specified in the pin-out
Table 17-1 and illustrated in Figure 17-2.
Figure 17-2. SPI Monitor Pins Diagram
clk
reset
areset
sck
mosi
ss
miso
active_slave_count
baudrate_divisor
lsbfe
cpol
cpha
SPI Monitor
720
Pins
Description
clk
Reference clock
reset
areset
sck
Serial Clock
mosi
ss
miso
active_slave_count
Description
baudrate_divisor
Baudrate divisor. Sets the baud rate divisor for the externally
generated clock (SCK) from the system clock.
lsbfe
cpol
cpha
Monitor Parameters
The parameters shown in Table 17-2 should be passed with appropriate values to configure the
SPI monitor to track the SPI Master and SPI Slave devices.
Table 17-2. SPI Monitor Parameters
Order Parameters
Default Description
1.
Constraints_Mode
2.
SS_WIDTH
3.
MASTER_MODE
721
Monitor Checks
Table 17-3 shows the monitor checks performed by the SPI monitor.
Table 17-3. SPI Master Checks
Check ID
Violation
Description
SPI_CPHA_CHANGE_DURING_
TRANSFER_P
SPI_CPHA_CHANGE_DURING_
TRANSFER_N
SPI_CPOL_CHANGE_DURING_
TRANSFER_P
SPI_CPOL_CHANGE_DURING_
TRANSFER_N
SPI_LSBFE_CHANGE_DURING_ Transmission abort due to
TRANSFER_P
change in LSBFE during
transfer.
SPI_LSBFE_CHANGE_DURING_
TRANSFER_N
SPI_INVALID_SS_DURING_
TRANSFER_P
SPI_INVALID_SS_DURING_
TRANSFER_N
722
Chapter 18
System Packet Interface Level 4 Phase 2
(SPI4-2)
Introduction
System Packet Interface Level 4 Phase 2 (SPI4-2) is an interface for packet and cell transfer
between a physical layer (PHY) device and a Link layer device for aggregate bandwidths of
OC-192 ATM and Packet over SONET/SDH (POS), as well as 10Gb/s Ethernet applications.
SPI4-2 is the system packet interface for data transfer between the Link layer and the PHY
device. Transmit and Receive refer, respectively, to data flow and associated control/status
information from the Link Layer to PHY, and from the PHY to Link layer devices.
Mentor Graphics (0-In) provides the following two QVL monitors designed for checking SPI42 interface implementations:
In addition to the main specification, the SPI4-2 monitors support the following extensions:
The SPI-4.2 monitors can also be configured to verify POS-PHY L4 interface implementations.
Please refer to the later sections of this chapter for information on configuring the SPI-4.2
monitors for these implementations.
Reference Documentation
System Packet Interface Level 4 (SPI-4) Phase 2: OC-192 System Interface for Physical
and Link Layer Devices; January 2001
723
Receive Monitor
The SPI4-2 Receive interface monitor supports data path and FIFO status interfaces. It provides
programmability for the following:
PHY Layer
SPI4-2
Receive
Monitor
or
LINK Layer
SPI4-2
Receive
Monitor
rdclk
rdat
rctl
PHY Layer
rstat
rsclk
Monitor Connectivity
Connect the SPI4-2 Receive monitor pins to internal signals as specified in the pin out
Table 18-1 and illustrated in Figure 18-2.
724
SPI4-2
Receive Monitor
Description
areset
bandwidth_reprovisioning_enable
calendar_len_x
calendar_len_y
725
726
Pin
Description
calendar_m_x
calendar_m_y
calendar_sequence_x
calendar_sequence_y
Port address sequence in which the FIFO status for all the ports is sent on
the FIFO status interface. The number of slots in a FIFO status sequence
is equal to the number of slots in the calendar sequence.
The order in which port addresses are wired to calendar_sequence_x
(calendar_sequence_y) configures the order in which status information is
sent on the FIFO status interface in a calendar length sequence. That is,
there is an exact one-to-one mapping between calendar_sequence_x order
and the status sequence order. For example, suppose there are four ports,
the calendar length is 6, and the port addresses sequence in which the
FIFO status is sent is 0, 1, 2, 3, 0, 1. Configure these signals as follows:
Status of port addresses 0 and 1 are sent twice on the FIFO status
sequence.
Status of port addresses 2 and 3 are sent only once.
The calendar_sequence_x/ calendar_sequence_y in the monitor
instantiation should be connected as follows:
.calendar_sequence_x (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
.calendar_sequence_y (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
Note that the port address should always be 32-bits wide when it is
connected to the monitor.
control_word_extension_enable
Enables (1) and disables (0) the Payload control word extension feature
discussed in the Appendix E of the reference document. Use this pin only
when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
Note that when the control word extension feature is enabled, the port
address is derived only from the normal control word and the first
extension control word. Subsequent extension control words are userdefined or application-specific, and therefore, are not processed by
the monitor.
data_max_t_x
data_max_t_y
Maximum interval (in RDCLK half clock cycles) within which at least
data_training_sequences_cnt_x number of Training sequences are
expected. Set these parameters to 0 to disable Training sequence on the
data path interface.
data_training_sequences_cnt_x
data_training_sequences_cnt_y
enable_fifo_status_if
Enables(1) and disables (0) the FIFO status interface. By default, tracking
of the FIFO status interface is enabled. Use this pin only when ports are
used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
fifo_max_t_x
fifo_max_t_y
Maximum interval (in RSCLK half clock cycles for LVDS_IO_P mode,
or in RSCLK cycles for LVTTL_IO mode) within which at least one
Training sequence is expected on the FIFO status interface. Set these
parameters to 0 to disable the Training sequence on the FIFO interface.
Description
fifo_valid_sync_or_training_delay
Maximum time (in RSCLK half clock cycles) for the start of the Training
sequence on the FIFO interface when LVDS_IO_P mode is enabled. For
LVTTL mode, fifo_valid_sync_or_training_delay is the maximum time
(in RSCLK cycles) for the start of SYNC pattern on FIFO interface. Use
this pin only when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
l_max_x
l_max_y
Maximum response time (in RDCLK half clock cycles) of the Data path
interface logic to respond to change in FIFO status. Note: l_max_x
(l_max_y) corresponds to the worst case response time after the FIFO
status becomes SATISFIED. Response time is defined as the interval
from reception of status update on the FIFO status channel for a port to its
reflection in the data path interface when payload transfer from that port
is in progress.
lvds_io
Clocking mode for the FIFO status interface. Set to 1'b1 if the FIFO status
is to be updated on both positive and negative edges of RSCLK
(LVDS_IO_P mode). Set to 1'b0 to update status only on the positive
edge of RSCLK (LVTTL_IO mode). Use this pin only when ports are
used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
max_burst_1_x
max_burst_1_y
Maximum number of 16 byte blocks data that the FIFO can accept when
FIFO status channel indicates STARVING.
max_burst_2_x
max_burst_2_y
Maximum number of 16 byte blocks data that the FIFO can accept when
FIFO status channel indicates HUNGRY. Parameter of set X.
max_packet_len_x
max_packet_len_y
min_packet_len_x
min_packet_len_y
port_addresses
Concatenated input of all the port addresses that are to be tracked. Every
port address should be 32-bits wide. Note that all port addresses used in
the design should be connected.
ports_count
Number of ports tracked by the monitor. Use this pin only when ports are
used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
rctl
Receive control, high indicates Control word and low indicates Payload
(Data burst).
rdat
rdclk
reset
rsclk
rstat
Port signals with _x and _y suffixes are configurable parameter signals. These signals
are required to support the Hit-less Bandwidth reprovisioning feature specified in
727
Appendix G of the SPI4-2 specification. Signals with _x belong to parameter set X, and
signals with _y belong to parameter set Y. Parameter set X is selected if the Calendar
Selection Word (sent on the FIFO status interface) value is 2'b01. Parameter set Y is
selected if the Calendar Selection Word value is 2'b10. If your implementation does not
support the bandwidth reprovisioning feature, then use parameter set X to configure the
monitor. You can leave signals of parameter set Y unconnected.
ports_count
lvds_io
fifo_valid_sync_or_training_delay
control_word_extension_enable
bandwidth_reprovisioning_enable
enable_fifo_status_if
The values on these ports can change only during reset and must remain constant until
the next reset.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 0, then the Verilog
parameters listed in Table 18-2 are used to configure the monitor.
Monitor Parameters
The parameters in Table 18-2 configure the SPI4-2 Receive monitor.
Table 18-2. SPI4-2 Receive Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
LINK_SIDE_P
3.
PORTS_COUNT_P
728
Default Description
4.
ENABLE_FIFO_STATUS_IF_P
5.
LVDS_IO_P
6.
FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P
7.
MAX_CALENDAR_LEN_P
256
8.
CONTROL_WORD_
EXTENSION_ENABLE_P
9.
BANDWIDTH_
0
REPROVISIONING_ENABLE_P
10.
NARROW_BAND_
INTERFACE_ENABLE_P
11.
USE_PORTS_TO_
CONFIGURE_P
729
Note that the monitor tracks only the first ports_count number of ports out of
PORTS_COUNT_P number of ports. When you connect the port port_addresses, you must
connect all of the ports in the design. For example, consider a design with four ports (i.e.,
PORTS_COUNT_P is 4). The port_addresses port should be connected as follows:
.port_addresses (addr_1, addr_2, addr_3, addr_4),
If the ports_count port has a value of 2, then the monitor tracks ports with addresses addr_1
and addr_2.
Instantiation Examples
Example 1
Example 18-1 instantiates an SPI4-2 Receive monitor within a Link layer device with the
following configuration:
730
Number of status slots for this port in a FIFO status sequence is 12.
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles. This is the
same for both values of the calendar selection word.
Number of RDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T). This is the same for both values of the calendar selection word.
Length of the FIFO status (CALENDAR_LEN) is set to 12 and the number of FIFO status
sequences within sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to two.
This is the same for both values of the calendar selection word.
Example 18-1. SPI4-2 Receive Monitor Instantiation
qvl_spi4_2_rx_monitor #(
0,
/* Constraints_Mode*/
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
1,
/* ENABLE_FIFO_STATUS_IF_P */
0,
/* LVDS_IO_P */
5,
/* FIFO_VALID_SYNC_OR_TRAINING_DELAY_P */
12,
/* MAX_CALENDAR_LEN_P */
0,
/* CONTROL_WORD_EXTENSION_ENABLE_P */
1,
/* BANDWIDTH_REPROVISIONING_ENABLE_P */
0 )
/* NARROW_BAND_INTERFACE_ENABLE_P */
SPI4_2_RX_MON(
.rdclk
(rdclk),
.rsclk
(rsclk),
.areset
(areset),
.reset
(reset),
.rdat
(rdat),
.rctl
(rctl),
.rstat
(rstat),
.port_addresses
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd6, 32'd7, 32'd8, 32'd9}),
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
.calendar_sequence_x
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd0, 32'd1, 32'd6, 32'd7,
32'd8, 32'd9}),
.l_max_x
(16),
.data_training_sequences_cnt_x(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.max_burst_1_y
(9),
.max_burst_2_y
(7),
.data_max_t_y
(1000),
.calendar_len_y
(12),
.calendar_m_y
(2),
.calendar_sequence_y
({32'd0, 32'd1, 32'd2, 32'd3, 32'd4,
32'd5, 32'd6, 32'd7, 32'd8, 32'd9,
32'd4, 32'd5),
.l_max_y
(16),
.data_training_sequences_cnt_y(3),
.fifo_max_t_y
(500),
.max_packet_len_y
(1000),
.min_packet_len_y
(50) );
731
Example 2
Example 18-2 instantiates an SPI4-2 Receive monitor within a Link layer device with the
following configuration:
The max_burst_2_x (for HUNGRY status) is set to five and max_burst_1_x (for
STARVING status) is set to seven.
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles.
Number of RDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T).
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to 2.
Example 18-2. SPI4-2 Receive Monitor Instantiation
qvl_spi4_2_rx_monitor #(
0,
/* Constraints_Mode */
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
1,
/* ENABLE_FIFO_STATUS_IF_P */
0,
/* LVDS_IO_P */
5,
/* FIFO_VALID_SYNC_OR_TRAINING_DELAY_P */
12,
/* MAX_CALENDAR_LEN_P */
0,
/* CONTROL_WORD_EXTENSION_ENABLE_P */
0,
/* BANDWIDTH_REPROVISIONING_ENABLE_P */
0 )
/* NARROW_BAND_INTERFACE_ENABLE_P */
SPI4_2_RX_MON(
.rdclk
(rdclk),
.rsclk
(rsclk),
.areset
(areset),
.reset
(reset),
.rdat
(rdat),
.rctl
(rctl),
.rstat
(rstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
.calendar_sequence_x
({32'd0, 32'd1, 32'd2,
32'd5, 32'd0, 32'd1,
32'd8, 32'd9}),
.l_max_x
(16),
732
32'd3, 32'd4,
32'd8, 32'd9}),
32'd3, 32'd4,
32'd6, 32'd7,
Example 3
Example 18-3 instantiates an SPI4-2 Receive monitor within a Link layer device with the
following configuration:
The max_burst_2_x (for HUNGRY status) is set to five, and max_burst_1_x (for
STARVING status) is set to seven.
The data path interface response time (L_MAX) is 16 RDCLK half clock cycles.
Number of RDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T).
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within the sync (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set to 2.
LVDS_IO_P, CONTROL_WORD_EXTENSION_ENABLE_P,
BANDWIDTH_REPROVISIONING_ENABLE_P, and ENABLE_FIFO_STATUS_IF_P
are
733
(rstat),
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd6,
32'd8, 32'd9}),
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
.calendar_sequence_x
({32'd0, 32'd1, 32'd2,
32'd4, 32'd5, 32'd0,
32'd6, 32'd7, 32'd8,
.l_max_x
(16),
.data_training_sequences_cnt_x
(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50),
.ports_count
(32'd5),
.lvds_io
(1'b0),
.fifo_valid_sync_or_training_delay(32'd5),
.control_word_extension_enable
(1'b0),
.bandwidth_reprovisioning_enable (1'b0),
.enable_fifo_status_if
(1'b1));
32'd3,
32'd7,
32'd3,
32'd1,
32'd9}),
Monitor Checks
Table 18-3 shows the checks performed by the SPI4-2 Receive monitor.
Table 18-3. SPI4-2 Receive Checks
Check ID
Violation
SPI4_2_RX_00_P
SPI4_2_RX_00_N
SPI4_2_RX_01_P
SPI4_2_RX_01_N
SPI4_2_RX_02_P
SPI4_2_RX_02_N
SPI4_2_RX_03_P
SPI4_2_RX_03_N
734
Description
Violation
Description
SPI4_2_RX_04_P
At least DATA_TRAINING_
SEQUENCES_CNT number of
Training sequences should occur
on the data path interface for
every DATA_MAX_T half clock
cycles.
SPI4_2_RX_04_N
SPI4_2_RX_05_P
SPI4_2_RX_05_N
SPI4_2_RX_06_P
SPI4_2_RX_06_N
SPI4_2_RX_07_P
SPI4_2_RX_07_N
SPI4_2_RX_08_P
SPI4_2_RX_08_N
SPI4_2_RX_09_P
SPI4_2_RX_09_N
SPI4_2_RX_10_P
SPI4_2_RX_10_N
SPI4_2_RX_11_P
SPI4_2_RX_11_N
SPI4_2_RX_12_P
SPI4_2_RX_12_N
735
Violation
Description
SPI4_2_RX_13_P
SPI4_2_RX_13_N
SPI4_2_RX_14_P
SPI4_2_RX_14_N
SPI4_2_RX_15_P
SPI4_2_RX_15_N
SPI4_2_RX_17_P
SPI4_2_RX_17_N
SPI4_2_RX_18_P
SPI4_2_RX_18_N
SPI4_2_RX_19_P
SPI4_2_RX_19_N
SPI4_2_RX_20_P
SPI4_2_RX_20_N
SPI4_2_RX_21_P
SPI4_2_RX_21_N
SPI4_2_RX_22_P
SPI4_2_RX_22_N
736
Violation
Description
SPI4_2_RX_23_P
SPI4_2_RX_23_N
SPI4_2_RX_24_P
SPI4_2_RX_24_N
SPI4_2_RX_25_P
SPI4_2_RX_25_N
SPI4_2_RX_27_P
SPI4_2_RX_27_N
SPI4_2_RX_28_P
SPI4_2_RX_28_N
SPI4_2_RX_29_P
SPI4_2_RX_29_N
SPI4_2_RX_30_P
SPI4_2_RX_30_N
737
Violation
Description
SPI4_2_RX_31_P
SPI4_2_RX_31_N
SPI4_2_RX_32_P
SPI4_2_RX_32_N
SPI4_2_RX_33_P
SPI4_2_RX_33_N
SPI4_2_RX_34_P
SPI4_2_RX_34_N
SPI4_2_RX_35_P
SPI4_2_RX_35_N
SPI4_2_RX_36_P
SPI4_2_RX_36_N
SPI4_2_RX_37_P
SPI4_2_RX_37_N
738
Violation
Description
SPI4_2_RX_38_P
SPI4_2_RX_PARAM_01_P
SPI4_2_RX_PARAM_02_P
SPI4_2_RX_PARAM_06_P
SPI4_2_RX_PARAM_07_P
SPI4_2_RX_PARAM_08_P
SPI4_2_RX_PARAM_09_P
SPI4_2_RX_38_N
SPI4_2_RX_39_P
SPI4_2_RX_39_N
SPI4_2_RX_40_P
SPI4_2_RX_40_N
739
Violation
Description
SPI4_2_RX_PARAM_10_P
DATA_TRAINING_
SEQUENCES_CNT should not
be less than the minimum limit of
1.
SPI4_2_RX_PARAM_11_P
Product of CALENDAR_LEN
and CALENDAR_M should not
be less than 16 when
LVDS_IO_P mode is selected.
SPI4_2_RX_PARAM_12_P
The min_packet_len_x or
min_packet_len_y parameter should
not be specified to be less than 1.
SPI4_2_RX_PARAM_13_P
The max_packet_len_x or
max_packet_len_y parameter value
should not be less than the value of the
respective min_packet_len_x or
min_packet_len_y parameter.
740
The active clock edge for checks SPI4_2_RX_23_P to SPI4_2_RX_32_P, which is the
positive edge of RSCLK. These checks are active only if the
ENABLE_FIFO_STATUS_IF_P parameter is set to 1.
The active clock edge for checks SPI4_2_RX_23_N to SPI4_2_RX_32_P, which is the
negative edge of RSCLK. These checks are active only if the
ENABLE_FIFO_STATUS_IF_P parameter and the LVDS_IO_P parameter are set to 1.
Description
Total number of End of Packets (EOPs) issued with only one byte of
the last word being valid.
Total number of End of Packets (EOPs) issued with both the bytes of
the last word being valid.
Monitor Statistics
Table 18-5 shows the statistics collected by the SPI4-2 Receive monitor.
Table 18-5. SPI4-2 Receive Monitor Statistics
Statistic
Description
Total number of Packets transferred between the PHY device and the
Link layer device.
741
742
Statistic
Description
Total number of bytes transferred between the PHY device and the
Link layer device.
Transmit Monitor
The SPI4-2 Transmit interface monitor supports data path and FIFO status interfaces. It
provides programmability for the following:
PHY Layer
SPI4-2
Transmit
Monitor
or
LINK Layer
SPI4-2
Transmit
Monitor
tdclk
tdat
tctl
PHY Layer
tstat
tsclk
Monitor Connectivity
Connect the SPI4-2 Transmit monitor pins to internal signals as specified in the pin out
Table 18-6 and illustrated in Figure 18-4.
743
SPI4-2
Transmit Monitor
Description
areset
bandwidth_reprovisioning_
enable
Enables (1) and disables (0) the Hit-less Bandwidth Reprovisioning feature
discussed in Appendix G of the reference document. If this pin is set to 1'b0,
then only signals that belong to parameter set X are used by the monitor.
Use this pin only when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
calendar_len_x
calendar_len_y
calendar_m_x
calendar_m_y
744
Description
calendar_sequence_x
calendar_sequence_y
Port address sequence in which the FIFO status for all the ports is sent on
the FIFO status interface. The number of slots in a FIFO status sequence is
equal to the number of slots in the calendar sequence.
The order in which port addresses are wired to calendar_sequence_x
(calendar_sequence_y) configures the order in which status information is
sent on the FIFO status interface in a calendar length sequence. That is,
there is an exact one-to-one mapping between calendar_sequence_x order
and the status sequence order.
For example, suppose there are four ports, the calendar length is 6, and the
port addresses sequence in which the FIFO status is sent is 0, 1, 2, 3, 0, 1. To
configure these signals:
Status of port addresses 0 and 1 are sent twice on the FIFO status
sequence.
Status of port addresses 2 and 3 are sent only once.
The calendar_sequence_x/calendar_sequence_y in the monitor
instantiation should be connected as follows:
.calendar_sequence_x (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
.calendar_sequence_y (
{32'd0,32'd1,32'd2, 32'd3,32'd0,32'd1}),
Note that the port address should always be 32-bits wide when it is
connected to the monitor.
control_word_extension_enable
Enables (1) and disables (0) the Payload control word extension feature
discussed in the Appendix E of the reference document. Use this pin only
when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
Note that when the control word extension feature is enabled, the port
address is derived only from the normal control word and the first
extension control word. Subsequent extension control words are userdefined or application-specific, and therefore, are not processed by the
monitor.
data_max_t_x
data_max_t_y
Maximum interval (in TDCLK half clock cycles) within which at least
data_training_sequences_cnt_x number of Training sequences are expected.
Set these parameters to 0 to disable Training sequence on the data path
interface.
data_training_sequences_cnt_x
data_training_sequences_cnt_y
Number of Training sequences expected on the data path interface for every
data_max_t_x (data_max_t_y) clock edges.
fifo_max_t_x
fifo_max_t_y
Maximum interval (in TSCLK half clock cycles for LVDS_IO_P mode, or
in TSCLK cycles for LVTTL_IO mode) within which at least one Training
sequence is expected on the FIFO status interface. Set these parameters to 0
to disable Training sequence on FIFO interface.
fifo_valid_sync_or_training_
delay
Maximum time (in RSCLK half clock cycles) for the start of the Training
sequence on the FIFO interface when LVDS_IO_P mode is enabled. For
LVTTL mode, fifo_valid_sync_or_training_delay is the maximum time (in
RSCLK cycles) for the start of SYNC pattern on the FIFO interface. Use
this pin only when ports are used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
745
Description
l_max_x
l_max_y
Maximum response time (in TDCLK half clock cycles) of the Data path
interface logic to respond to change in FIFO status.
Note that the l_max_x (l_max_y) corresponds to the worst case
response time after the FIFO status becomes SATISFIED. Response
time is defined as the interval from reception of status update on the
FIFO status channel for a port to its reflection in the data path interface
when payload transfer from that port is in progress.
lvds_io
Clocking mode for the FIFO status interface. Set to 1'b1 if the FIFO status is
to be updated on both positive and negative edges of RSCLK (LVDS_IO_P
mode). Set to 1'b0 to update status only on the positive edge of RSCLK
(LVTTL_IO mode). Use this pin only when ports are used to configure the
monitor (i.e., when USE_PORTS_TO_CONFIGURE_P is set to 1).
max_burst_1_x
max_burst_1_y
Maximum number of 16 byte blocks data that the FIFO can accept when
FIFO status channel indicates STARVING.
max_burst_2_x
max_burst_2_y
Maximum number of 16 byte blocks data that the FIFO can accept when
FIFO status channel indicates HUNGRY. Parameter of set X.
max_packet_len_x
max_packet_len_y
min_packet_len_x
min_packet_len_y
port_addresses
Concatenated input of all the port addresses that are to be tracked. Every
port address should be 32-bits wide. Note that all the port addresses that are
used in the design should be connected.
ports_count
Number of ports tracked by the monitor. Use this pin only when ports are
used to configure the monitor (i.e., when
USE_PORTS_TO_CONFIGURE_P is set to 1).
reset
tctl
Transmit control, high indicates Control word and low indicates Payload
(Data burst).
tdat
tdclk
tsclk
tstat
746
Port signals with _x and _y suffixes are configurable parameter signals. These signals
are required to support the Hit-less Bandwidth reprovisioning feature specified in
Appendix G of the SPI4-2 specification. Signals with _x belong to parameter set X, and
signals with _y belong to parameter set Y. Parameter set X is selected if the Calendar
Selection Word (sent on the FIFO status interface) value is 2'b01. Parameter set Y is
selected if the Calendar Selection Word value is 2'b10. If your implementation does not
support the bandwidth reprovisioning feature, use parameter set X to configure the
monitor. You can leave signals of parameter set Y unconnected.
ports_count
lvds_io
fifo_valid_sync_or_training_delay
control_word_extension_enable
bandwidth_reprovisioning_enable
enable_fifo_status_if
The values on these ports can change only during reset and must remain constant until
the next reset.
When the USE_PORTS_TO_CONFIGURE_P parameter is set to 0, then the Verilog
parameters listed in Table 18-7 are used to configure the monitor.
Monitor Parameters
The parameters in Table 18-7 configure the SPI4-2 Transmit monitor.
Table 18-7. SPI4-2 Transmit Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
LINK_SIDE_P
3.
PORTS_COUNT_P
4.
LVDS_IO_P
747
Default Description
5.
FIFO_VALID_SYNC_OR_
TRAINING_DELAY_P
6.
MAX_CALENDAR_LEN_P 256
7.
CONTROL_WORD_
EXTENSION_ENABLE_P
8.
BANDWIDTH_
REPROVISIONING_
ENABLE_P
9.
NARROW_BAND_
INTERFACE_ENABLE_P
10.
USE_PORTS_TO_
CONFIGURE_P
Note that the monitor tracks only the first ports_count number of ports out of
PORTS_COUNT_P number of ports. When you connect the port port_addresses, you must
connect all of the ports in the design. For example, consider a design with four ports (i.e.,
PORTS_COUNT_P is 4). The port_addresses port should be connected as follows:
port_addresses (addr_1, addr_2, addr_3, addr_4),
If the ports_count port has a value of 2, then the monitor tracks ports with addresses addr_1
and addr_2.
748
Instantiation Examples
Example 1
Example 18-4 instantiates an SPI4-2 Transmit monitor within a Link layer device with the
following configuration:
Number of status slot for this port in a FIFO status sequence is 12.
The max_burst_2_x (for HUNGRY status) is set to five and max_burst_1_x (for
STARVING status) is set to seven. The max_burst_2_y (for HUNGRY status) is set to
seven and max_burst_1_y (for STARVING status) is set to nine.
The data path interface response time (L_MAX) is 16 TDCLK half clock cycles. This is the
same for both values of the calendar selection word.
Number of TDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T). This is the same for both values of the calendar selection word.
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within synchronous (TSTAT = 2'b11) pattern boundary (CALENDAR_M) is set
to 2. This is the same for both values of the calendar selection word.
Example 18-4. SPI4-2 Transmit Monitor Instantiation
qvl_spi4_2_tx_monitor #(
0,
/* Constraints_Mode */
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
0,
/* LVDS_IO_P */
5,
/* FIFO_VALID_SYNC_OR_TRAINING_DELAY_P */
749
32'd3, 32'd4,
32'd8, 32'd9})
32'd3, 32'd4,
32'd6, 32'd7,
32'd3, 32'd4,
32'd8, 32'd9,
Example 2
Example 18-5 instantiates an SPI4-2 Transmit monitor within a Link layer device with the
following configuration:
750
The max_burst_2_x (for HUNGRY status) is set to five, and max_burst_1_x (for
STARVING status) is set to seven.
The data path interface response time (L_MAX) is 16 TDCLK half clock cycles.
Number of TDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T).
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within synchronous (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is set
to 2.
Example 18-5. SPI4-2 Transmit Monitor Instantiation
qvl_spi4_2_tx_monitor #(
0,
/* Constraints_Mode */
1,
/* LINK_SIDE_P */
10,
/* PORTS_COUNT_P */
0,
/* LVDS_IO_P */
5,
/* FIFO_VALID_SYNC_OR_TRAINING_DELAY_P */
12,
/* MAX_CALENDAR_LEN_P */
0,
/* CONTROL_WORD_EXTENSION_ENABLE_P */
0,
/* BANDWIDTH_REPROVISIONING_ENABLE_P */
0 )
/* NARROW_BAND_INTERFACE_ENABLE_P */
SPI4_2_TX_MON(
.tdclk
(tdclk),
.tsclk
(tsclk),
.areset
(areset),
.reset
(reset),
.tdat
(tdat),
.tctl
(tctl),
.tstat
(tstat),
.port_addresses
({32'd0, 32'd1, 32'd2,
32'd5, 32'd6, 32'd7,
.max_burst_1_x
(7),
.max_burst_2_x
(5),
.data_max_t_x
(1000),
.calendar_len_x
(12),
.calendar_m_x
(2),
.calendar_sequence_x
({32'd0, 32'd1, 32'd2,
32'd5, 32'd0, 32'd1,
32'd8, 32'd9}),
.l_max_x
(16),
.data_training_sequences_cnt_x(3),
.fifo_max_t_x
(500),
.max_packet_len_x
(1000),
.min_packet_len_x
(50)),
32'd3, 32'd4,
32'd8, 32'd9}),
32'd3, 32'd4,
32'd6, 32'd7,
Example 3
Example 18-6 instantiates an SPI4-2 Transmit monitor within a Link layer device with the
following configuration:
751
The max_burst_2_x (for HUNGRY status) is set to five and max_burst_1_x (for
STARVING status) is set to seven.
The data path interface response time (L_MAX) is 16 TDCLK half clock cycles.
Number of TDCLK half clock cycles for receiving at least three Training sequences is
1000 (DATA_MAX_T).
Length of the FIFO status (CALENDAR_LEN) is set to 12, and the number of FIFO status
sequences within the synchronous (RSTAT = 2'b11) pattern boundary (CALENDAR_M) is
set to 2.
through ports.
752
32'd3,
32'd7,
32'd3,
32'd1,
32'd9}),
Monitor Checks
Table 18-8 shows the checks performed by the SPI4-2 Transmit monitor.
Table 18-8. SPI4-2 Transmit Checks
Check ID
Violation
SPI4_2_TX_00_P
SPI4_2_TX_00_N
SPI4_2_TX_01_P
SPI4_2_TX_01_N
SPI4_2_TX_02_P
SPI4_2_TX_02_N
SPI4_2_TX_03_P
SPI4_2_TX_03_N
SPI4_2_TX_04_P
SPI4_2_TX_04_N
SPI4_2_TX_05_P
SPI4_2_TX_05_N
Description
753
Violation
Description
SPI4_2_TX_06_P
SPI4_2_TX_06_N
SPI4_2_TX_07_P
SPI4_2_TX_07_N
SPI4_2_TX_08_P
SPI4_2_TX_08_N
SPI4_2_TX_09_P
SPI4_2_TX_09_N
SPI4_2_TX_10_P
SPI4_2_TX_10_N
SPI4_2_TX_11_P
SPI4_2_TX_11_N
SPI4_2_TX_12_P
SPI4_2_TX_12_N
At least DATA_TRAINING_
SEQUENCES_CNT number of
Training sequences should occur
on the data path interface for
every DATA_MAX_T half clock
cycles.
SPI4_2_TX_13_P
SPI4_2_TX_13_N
SPI4_2_TX_14_P
SPI4_2_TX_14_N
754
Violation
Description
SPI4_2_TX_15_P
SPI4_2_TX_15_N
SPI4_2_TX_17_P
SPI4_2_TX_17_N
SPI4_2_TX_18_P
SPI4_2_TX_18_N
SPI4_2_TX_19_P
SPI4_2_TX_19_N
SPI4_2_TX_20_P
SPI4_2_TX_20_N
SPI4_2_TX_21_P
SPI4_2_TX_21_N
SPI4_2_TX_22_P
SPI4_2_TX_22_N
SPI4_2_TX_23_P
SPI4_2_TX_23_N
SPI4_2_TX_24_P
SPI4_2_TX_24_N
755
Violation
Description
SPI4_2_TX_25_P
SPI4_2_TX_25_N
SPI4_2_TX_27_P
SPI4_2_TX_27_N
SPI4_2_TX_28_P
SPI4_2_TX_28_N
SPI4_2_TX_29_P
SPI4_2_TX_29_N
SPI4_2_TX_30_P
SPI4_2_TX_30_N
SPI4_2_TX_31_P
SPI4_2_TX_31_N
SPI4_2_TX_32_P
SPI4_2_TX_32_N
756
Violation
Description
SPI4_2_TX_33_P
SPI4_2_TX_33_N
SPI4_2_TX_34_P
SPI4_2_TX_34_N
SPI4_2_TX_35_P
SPI4_2_TX_35_N
SPI4_2_TX_36_P
SPI4_2_TX_36_N
SPI4_2_TX_37_P
SPI4_2_TX_37_N
SPI4_2_TX_38_P
SPI4_2_TX_38_N
SPI4_2_TX_39_P
SPI4_2_TX_39_N
757
Violation
Description
SPI4_2_TX_40_P
SPI4_2_TX_40_N
SPI4_2_TX_PARAM_01_P
SPI4_2_TX_PARAM_02_P
SPI4_2_TX_PARAM_06_P
SPI4_2_TX_PARAM_07_P
SPI4_2_TX_PARAM_08_P
SPI4_2_TX_PARAM_09_P
SPI4_2_TX_PARAM_10_P
DATA_TRAINING_
SEQUENCES_CNT should not
be less than the minimum limit of
1.
SPI4_2_TX_PARAM_11_P
Product of CALENDAR_LEN
and CALENDAR_M should not
be less than 16 when
LVDS_IO_P mode is selected.
SPI4_2_TX_PARAM_12_P
The min_packet_len_x or
min_packet_len_y parameter should not
be specified to be less than 1.
SPI4_2_TX_PARAM_13_P
The max_packet_len_x or
max_packet_len_y parameter value
should not be less than the value of the
respective min_packet_len_x or
min_packet_len_y parameter.
The active clock edge for checks SPI4_2_TX_23_P to SPI4_2_TX_32_P, which is the
positive edge of TSCLK.
The active clock edge for checks SPI4_2_TX_23_N to SPI4_2_TX_32_P, which is the
negative edge of TSCLK.
Description
Total number of End of Packets (EOPs) issued with only one byte of
the last word being valid.
Total number of End of Packets (EOPs) issued with both the bytes of
the last word being valid.
Number of Data Path Training sequences Total number of training sequences transferred on the data path
interface.
Number of FIFO interface Training
sequences
759
Description
Monitor Statistics
Table 18-10 shows the statistics collected by the SPI4-2 Transmit monitor.
Table 18-10. SPI4-2 Transmit Monitor Statistics
760
Statistic
Description
Total number of Packets transferred between the PHY device and the
Link layer device.
Total number of bytes transferred between the PHY device and the
Link layer device.
Chapter 19
Universal Serial Bus 2.0 (USB)
Introduction
The Universal Serial Bus (USB) is specified to be an industry standard extension to the PC
architecture, with a focus on computer telephony, consumer and productivity appliances. USB
is a cable bus that supports data exchange between a host computer and a wide range of
peripherals. The attached peripherals share USB bandwidth through a host-scheduled, tokenbased protocol. The QVL Universal Serial Bus monitor is designed for checking the USB
protocol implementations.
Reference Documentation
USB 2.0 monitors are compliant with the specifications provided in the following documents:
The USB 2.0 UTMI monitor is compliant with the specifications provided in the following
document:
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification, Version 1.05 - March
29, 2001.
OTG Interface (On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3,
December 5, 2006)
The USB 2.0 ULPI monitor is compliant with the specifications provided in the following
document:
UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1, October 20, 2004
OTG Interface (On-The-Go Supplement to the USB 2.0 Specification, Revision 1.3,
December 5,2006)*
761
Supported Features
The following features are supported by the USB 2.0 monitors:
Control transfers.
Interrupt transfers.
Bulk transfers.
Isochronous transfers.
The USB monitor can be instantiated on the downstream port of the host (root hub), upstream
port of the hub, downstream port of the hub, and upstream port of the device.
Additional features supported by the USB 2.0 UTMI monitor are as follows:
Supports Level 0, 1, 2, 3.
Additional features supported by the USB 2.0 ULPI monitor are as follows:
762
Does not follow the process of device configuration (i.e., the monitors do not identify
the addresses assigned to the devices or device configurations).
Monitor does not support vendor control signals and test modes.
763
USB Host
USB Bus
USB
Monitor
USB Hub
or
USB Hub
USB Bus
USB Host
USB
Monitor
USB Hub
USB Bus
USB
Monitor
USB Device
or
USB Device
USB Hub
USB Bus
USB
Monitor
764
USB 2.0
Monitor
dp
dm
USB Wire
Serial Interface
oe_n
speed
USB Controller
USB
Monitor
Description
address
Address of the device or function. Connect to the address register (register that
holds the assigned address) if the monitor is instantiated on the upstream port
of the device.
areset
clock
Clock input. This clock is used to sample the data on the USB bus. Refer to the
connectivity note 1 at the end of this table.
dm
dp
end_point_config
number_of_active_endpoints
This signal configures the number of active endpoints tracked currently by the
monitor. The value must not be greater than NUMBER_OF_ENDPOINTS
parameter.
oe_n
reset
speed
Connectivity Notes
1. The clock is not a USB interface signal. This signal must be provided from the users
design. The monitor does not perform clock recovery.
765
2. Input address should be connected to the address register of the device if the monitor
is instantiated on the upstream port of the device. If the monitor is instantiated on the
downstream port of the host, hub, or upstream port of the hub, then tie this input to the
address of the device for which transactions needs to be tracked.
3. Input oe_n is an active low input signal. This signal indicates whether host is driving or
device is driving the bus. For example, if the monitor is instantiated on the downstream
port of the host, then a logic low sampled on this signal indicates that the host is driving
the bus. (Ports dp and dm act as the input ports of the transceiver.) A logic high
sampled on this signal indicates that the device is driving the bus. (Ports dp and dm act
as the output ports of the transceiver.)
4. Input end_point_config configures the end points to be tracked. This input follows
the encoding scheme as explained below. For configuring the end points end point
address, transfer type supported by the end point, direction of the end point (IN or
OUT), and maximum packet size supported by the end point need to be specified. Each
end point needs 21-bits for the configuration. The order in which these bits are used is as
follows:
Assuming a 21-bit register for each end point configuration information, various fields
of the register are defined as shown below:
A3 A2 A1 A0 D T2 T1 T0 O1 O0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
o
In this register, the A3 bit is the most significant bit and S0 is the least
significant bit.
A3 A2 A1 A0
The D bit specifies the direction of the end point. When set to 1, the end point
supports only IN transactions. When set to 0, the end point supports only OUT
transactions. This bit should be set to 0 if the end point supports control
transfers.
T2 T1 T0
specifies the transfer type supported by the end point. Allowed values
for these bits are as follows:
0
0
0
1
766
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Isochronous transfer
0
1
0
1
Bits S10 to S0 specify the maximum packet size supported by the end point.
This field represents wMaxPacketSize of configuration information.
Questa Verification Library Monitors Data Book, v2010.2
If there are multiple end points to be tracked by the monitor, then the above specified
encoding information should be provided for each end point. The encoded value of the
end points should be concatenated and wired to the end_point_config input.
For example, suppose the monitor needs to track two end points whose configuration
information is as follows:
end_point_1 = 21'b 0000_0_001_00_0000010000
or
{end_point_2, end_point_1}
Monitor Parameters
Parameters shown in Table 19-2 configures a standard USB 2.0 monitor.
Table 19-2. USB 2.0 Monitor Parameters
Order
Parameter
Default Description
1.
Constraints_Mode
2.
PORT_TYPE
3.
NUMBER_OF_
ENDPOINTS
767
Parameter
Default Description
4.
FRAME_INTERVAL_
COUNT
60000
5.
SOF_JITTER_INTERVAL_
COUNT
30
6.
SEQUENCE_BIT_
TRACKING_ENABLE
7.
PACKET_ISSUE_
CHECK_ENABLE
8.
OTG_DEVICE
9.
HUB_SETUP_INTERVAL
Instantiation Examples
Example 19-1 and Example 19-2 show instantiating the USB 2.0 monitors.
Example 1
This example instantiates a USB monitor on the downstream port of the host.
Example 19-1. USB Monitor on the Downstream Port
qvl_usb_2_0_monitor
#( 0,
/* Constraints_Mode */
0,
/* PORT_TYPE */
768
Example 2
This example instantiates a USB monitor on the upstream port of the high-speed device to track
transactions of four end points. The address of the device is specified through the address input.
Example 19-2. USB Monitor on the Upstream Port
qvl_usb_2_0_monitor
#( 0,
/* Constraints_Mode */
3,
/* PORT_TYPE */
4,
/* NUMBER_OF_ENDPOINTS */
60000,
/* FRAME_INTERVAL_COUNT */
30,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.dp
(dp),
.dm
(dm),
.oe_n
(oe_n),
.speed
(2'b11),
.address
(address),
.end_point_config (end_point_config),
.number_of_active_endpoints (5'b1) );
769
clock
areset
reset
tx_valid
tx_valid_h
tx_ready
data_in_low[7:0]
data_in_high[7:0]
address[6:0]
end_point_config
number_of_active_endpoints
rx_valid
rx_valid_h
rx_active
rx_error
data_out_low[7:0]
data_out_high[7:0]
data_low
data_high
valid_h
USB 2.0
UTMI
Monitor
host_disconnect
dp_pulldown
dm_pulldown
id_pullup
id_dig
a_valid
b_valid
vbus_valid
sess_end
drv_vbus
dischrg_vbus
chrg_vbus
databus16_8
line_state[1:0]
Description
address [6:0]
Address of the device or function. If the monitor is instantiated on the upstream port of
the device, then connect to the address register (register that holds the assigned
address).
areset
clock
Clock input. This clock is used to sample data on the USB bus.
data_in_high [7:0]
8-bit parallel USB data input that transfers the high byte of 16-bit transmit data. This
input is applicable only when databus18_8 is 1. This input is not applicable for fullspeed only and low-speed only devices.
770
Description
data_in_low [7:0]
8-bit parallel USB data input bus. When databus16_8 is 1, this bus transfers the low
byte of the 16-bit transmit data.
data_out_high [7:0]
8-bit parallel USB data output that transfers the high byte of 16-bit receive data. This
input is applicable only when databus16_8 is 1. This input is not applicable for fullspeed only and low-speed only devices.
data_out_low [7:0]
8-bit parallel USB data output bus. When databus16_8 is 1, this bus transfers the low
byte of the 16-bit receive data.
databus16_8
Selects between 8-bit and 16-bit data transfers. This input is not applicable for fullspeed only and low-speed only devices.
end_point_config
line_state [1:0]
number_of_active_
endpoints
This signal configures the number of active endpoints tracked currently by the
monitor. The value must not be greater than NUMBER_OF_ENDPOINTS parameter.
reset
rx_active
Receive active signal. Indicates that the receive state machine is active.
rx_error
Receive error signal. When asserted, indicates that a receive error is detected.
rx_valid
Receive data valid signal. This signal indicates when the data_out bus is valid.
rx_valid_h
Receive data valid high signal. When databus16_8 input is 1, this signal indicates that
the data_out [15:8] bus has valid data. This input is not applicable for full-speed only
and low-speed only devices.
term_select
op_mode [1:0]
This signal is the UTM operational mode input signal. The value of 0 means normal
operation, and a value of 2 means that NRZI encoding and bit stuffing is disabled. This
mode is used during device chirping sequence done during speed negotiation protocol.
suspendm
This signal places the macrocell in low power mode. The value of 0 means low power
mode and a value of 1 means normal operation.
tx_ready
Transmit data ready signal. This signal indicates when the transmit data are loaded into
the transmit holding shift register.
tx_valid
tx_valid_h
Transmit data valid high signal. When databus16_8 is 1, this signal indicates that
data_in [15:8] contains valid transmit data. This input is not applicable for full-speed
only and low-speed only devices.
xcvr_select[0]
Selects between full-speed and high-speed transceivers. A 0 indicates that the highspeed transceiver is selected. A 1 indicates full-speed transceiver is selected. This
input is not applicable for FS only and LS only devices.
data_low [7:0]
771
Description
valid_h
Valid transfer. Only applicable for the 16-bit bidirectional interface (databus16_8 = 1).
If TxValid is high, then this signal is equivalent to TxValidH. If TxValid is low, then
this signal is equivalent to RxValidH.
id_dig
a_valid
b_valid
vbus_valid
sess_end
drv_vbus
dischrg_vbus
chrg_vbus
host_disconnect
This signal is used for all types of peripherals connected to it. It is only valid when
DpPulldown and DmPulldown are 1. The value of 1 indicates that there is no
peripheral connected and a value of 0 means that a peripheral is connected.
dp_pulldown
This signal enables the 15k Ohm pull-down resistor on the DP line. The value of 0
means the Pull-down resistor is not connected to DP and a value of 1 means the Pulldown resistor is connected to DP.
dm_pulldown
This signal enables the 15k Ohm pull-down resistor on the DM line. The value of 0
means the Pull-down resistor is not connected to DM and a value of 1 means the Pulldown resistor is connected to DM.
This signal is used with xcvr_select[0] from level 2 and above. xcvr_select[1:0] selects
between the following modes:
00 : HS transceiver
01 : FS transceiver
10 : LS transceiver (Valid in level 2 and above)
11 : Send a LS packet on a FS bus or receive a LS packet. (Valid only in level 3)
Connectivity Notes
1. Input address should be connected to the address register of the device if the monitor
is instantiated on the upstream port of the device. If the monitor is instantiated on the
downstream port of the host, hub, or upstream port of the hub, then tie this input to the
address of the device for which transactions needs to be tracked.
2. Input end_point_config configures the end points to be tracked. This input follows
the encoding scheme as explained below. For configuring the end points end point
address, transfer type supported by the end point, direction of the end point (IN or
772
OUT), and maximum packet size supported by the end point needs to be specified. Each
end point needs 21-bits for the configuration. The order in which these bits are used is as
follows:
Assuming a 21-bit register for each end point configuration information, various fields
of the register are defined as shown below:
A3 A2 A1 A0 D T2 T1 T0 O1 O0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
o
In this register, the A3 bit is the most significant bit, and S0 is the least
significant bit.
A3 A2 A1 A0
The D bit specifies the direction of the end point. When set to 1, the end point
supports only IN transactions. When set to 0, the end point supports only OUT
transactions. This bit should be set to 0 if the end point supports control
transfers.
T2 T1 T0
specifies the transfer type supported by the end point. Allowed values
for these bits are as follows:
0
0
0
1
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Isochronous transfer
0
1
0
1
Bits S10 to S0 specify the maximum packet size supported by the end point.
This field represents wMaxPacketSize of configuration information.
If there are multiple end points to be tracked by the monitor, then the above specified
encoding information should be provided for each end point. The encoded value of the
end points should be concatenated and wired to the end_point_config input.
For example, suppose the monitor needs to track two end points whose configuration
information is as follows:
end_point_1 = 21'b 0000_0_001_00_0000010000
773
or
{end_point_2, end_point_1}
3. Care should be taken in connecting the clock to the UTMI monitor. There are certain
checks which require that the clock frequency connected to the monitor is in accordance
with the UTMI specifications. It is 30 MHz for a 16-bit interface, and 60 MHz for an
8-bit interface. Not connecting the proper clock can result in violations.
Monitor Parameters
Parameters shown in Table 19-4 configures a USB 2.0 UTMI monitor.
Table 19-4. USB 2.0 UTMI Monitor Parameters
Order Parameter
Default Description
1.
Constraints_Mode
2.
UTMI_LEVEL
3.
PORT_TYPE
4.
UTMI_SIDE
5.
BI_DIRECTIONAL
6.
DEVICE_SPEED
774
Default Description
7.
NUMBER_OF_
ENDPOINTS
8.
FRAME_INTERVAL_
COUNT
7500
9.
SOF_JITTER_INTERVAL_
COUNT
10.
SEQUENCE_BIT_
TRACKING_ENABLE
11.
PACKET_ISSUE_
CHECK_ENABLE
12.
RX_ACTIVE_DEASSERT_
TO_TX_VALID_ASSERT_
DELAY_MIN
13.
RX_ACTIVE_DEASSERT_
TO_TX_VALID_ASSERT_
DELAY_MAX
24
14.
TX_VALID_DEASSERT_
TO_RX_ACTIVE_
ASSERT_DELAY_MIN
15.
TX_VALID_DEASSERT_
TO_RX_ACTIVE_
ASSERT_DELAY_MAX
37
16.
TIME_OUT_COUNT
800
17.
OTG_DEVICE
775
Default Description
18.
HUB_TURNAR_TIMEOUT_
16BIT
45000
19.
HUB_TURNAR_TIMEOUT_
8BIT
90000
20.
HUB_CHIRP_TIMEOUT_
16BIT
1800
21.
HUB_CHIRP_TIMEOUT_
8BIT
3600
22.
TERM_SEL_DEASS_
AFTER_HS_DETECT_
TIMEOUT_16BIT
15000
23.
TERM_SEL_DEASS_
AFTER_HS_DETECT_
TIMEOUT_8BIT
30000
24.
SE0_COUNT_MAX_FULL_
SPEED_REVERSE_8BIT
187500
25.
SE0_COUNT_MAX_FULL_
SPEED_REVERSE_16BIT
93750
26.
SE0_COUNT_MIN_FULL_
SPEED_REVERSE_8BIT
180000
27.
SE0_COUNT_MIN_FULL_
SPEED_REVERSE_16BIT
90000
28.
FULL_SPEED_SE0_RESET_
TIMEOUT_8BIT
150
29.
FULL_SPEED_SE0_RESET_
TIMEOUT_16BIT
75
30.
FULL_SPEED_J_SUSPEND_
TIMEOUT_8BIT
180000
776
Default Description
31.
FULL_SPEED_J_SUSPEND_
TIMEOUT_16BIT
90000
32.
LINE_STATE_DEBOUNCE_
TIMEOUT_8BIT
6000
33.
LINE_STATE_DEBOUNCE_
TIMEOUT_16BIT
3000
34.
CLK_USABLE_TIMEOUT_
8BIT
336000
35.
CLK_USABLE_TIMEOUT_
16BIT
168000
36.
MIN_RESET_INTERVAL_
8BIT
600000
37.
MIN_RESET_INTERVAL_
16BIT
300000
38.
CHIRP_KJ_START_
TIMEOUT_8BIT
6000
Configures the time 100 us in number of clocks for ChirpKJ sequence to start after device Chirp-K in 8-bit UTMI
interface at 60 MHz clock frequency.
39.
CHIRP_KJ_START_
TIMEOUT_16BIT
3000
Configures the time 100 us in number of clocks for ChirpKJ sequence to start after device Chirp-K in 16-bit UTMI
interface at 30 MHz clock frequency.
40.
DEV_CHIRP_K_TIMEOUT_
8BIT
348000
41.
DEV_CHIRP_K_TIMEOUT_
16BIT
174000
42.
DEV_CHIRP_K_DEASS_
TIMEOUT_8BIT
420000
43.
DEV_CHIRP_K_DEASS_
TIMEOUT_16BIT
210000
44.
DEV_CHIRP_K_ASSERT_
TIMEOUT_8BIT
360000
45.
DEV_CHIRP_K_ASSERT_
TIMEOUT_16BIT
180000
777
Default Description
46.
DEV_MIN_REMOTE_
WAKE_UP_COUNT_8BIT
300000
47.
DEV_MIN_REMOTE_
WAKE_UP_COUNT_16BIT
150000
48.
RESUME_K_MIN_ASSERT_
8BIT
60000
49.
RESUME_K_MIN_ASSERT_
16BIT
30000
50.
RESUME_K_MAX_ASSERT_
8BIT
900000
51.
RESUME_K_MAX_ASSERT_
16BIT
450000
52.
RESUME_K_DURATION_
LINE_STATE_8BIT
1200000
53.
RESUME_K_DURATION_
LINE_STATE_16BIT
600000
54.
RESUME_NORMAL_OPER_
TIMEOUT_8BIT
75
55.
RESUME_NORMAL_OPER_
TIMEOUT_16BIT
38
56.
SUSPENDM_DEASSERT_
TO_RESUME_K_ASSERT_
TIMEOUT_8BIT
600000
57.
SUSPENDM_DEASSERT_
TO_RESUME_K_ASSERT_
TIMEOUT_16BIT
300000
58.
HOST_DISCONNECT_
UPDATE_RECOVERY_
TIMEOUT_8BIT
240000
778
Default Description
59.
120000
HOST_DISCONNECT_
UPDATE_RECOVERY_
TIMEOUT_16BIT
Instantiation Examples
Example 19-3 and Example 19-4 show instantiating the USB 2.0 UTMI monitors.
Example 1
This example instantiates a USB monitor to track an 8-bit UTM Level 0 interface, full-speed
only device.
Example 19-3. USB Monitor to Track an 8-bit UTM Interface
qvl_usb_2_0_utmi_monitor
#( 0,
/* Constraints_Mode */
0,
/* UTMI_LEVEL */
3,
/* PORT_TYPE */
0,
/* UTMI_SIDE */
0,
/* BI_DIRECTIONAL */
1,
/* DEVICE_SPEED */
1,
/* NUMBER_OF_ENDPOINTS */
75000,
/* FRAME_INTERVAL_COUNT */
4,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_UTMI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.tx_valid
(TxValid),
.tx_ready
(TxReady),
.data_in_low
(Data_In),
.rx_valid
(RxValid),
.rx_active
(RxActive),
.rx_error
(RxError)
.data_out_low
(Data_Out)
.line_state
(LineState)
.address
(address)
.end_point_config (end_point_config),
.number_of_active_endpoints (5'b1) );
779
Example 2
This example instantiates a USB monitor on the upstream port of a high-speed device to track
transactions of four end points. The address of the device is specified through the address input.
The UTM Level 0 interface is a high-speed/full-speed, 16-bit interface.
Example 19-4. USB Monitor on the Upstream Port
qvl_usb_2_0_utmi_monitor
#( 0,
/* Constraints_Mode */
0,
/* UTMI_LEVEL */
3,
/* PORT_TYPE */
0,
/* UTMI_SIDE */
0,
/* BI_DIRECTIONAL */
0,
/* DEVICE_SPEED */
4,
/* NUMBER_OF_ENDPOINTS */
7500, /* FRAME_INTERVAL_COUNT */
4,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_UTMI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.tx_valid
(TxValid),
.tx_valid_h
(TxValidH),
.tx_ready
(TxReady),
.data_in_low
(Data_In[7:0]),
.data_in_high
(Data_In[15:8]),
.rx_valid
(RxValid),
.rx_valid_h
(RxValidH),
.rx_active
(RxActive),
.rx_error
(RxError),
.data_out_low
(Data_Out[7:0]),
.data_out_high
(Data_Out[15:8]),
.line_state
(LineState),
.xcvr_select
(XcvrSelect),
.term_select
(TermSelect),
.op_mode
(OpMode),
.suspendm
(SuspendM),
.databus16_8
(DataBus16_8),
.address
(address),
.end_point_config (end_point_config),
.number_of_active_endpoints (5'b1) );
780
clock
data[7:0] or
data[3:0]
address[6:0]
reset
USB 2.0
ULPI Monitor
dir
areset
nxt
end_point_config
stp
number_of_active_endpoints
Description
address [6:0]
areset
clock
Clock input. This clock is used to sample data on the ULPI bus.
data[7:0] or data[3:0]
It is bidirectional data bus with option of two bus widths, 8-bits wide and 4-bits
wide. The 8-bit data timed on rising edge of clock. (Optional) 4-bit data timed
on rising and falling edges of clock. In 4-bit data bus, least significant nibble is
transferred first on rising edge of clock. The most significant nibble is
transferred second on the falling edge of clock.
dir
Controls the direction of data bus. A 0 indicates data bus is driven by Link. A
1 indicates data bus is driven by Phy.
end_point_config
number_of_active_endpoints
This signal configures the number of active endpoints tracked currently by the
monitor. The value must not be greater than the NUMBER_OF_ENDPOINTS
parameter.
781
Description
nxt
The Phy asserts nxt to throttle all data types, except register read data and the
RxCMD.
reset
stp
The Link assert stp to signal the end of a USB transmit packet or a register
write operation, and optionally to stop any receive. The stp signal must be
asserted in the cycle after the last data byte is presented on the bus.
Connectivity Notes
1. Input address should be connected to the address register of the device if the monitor is
instantiated on the upstream port of the device. If the monitor is instantiated on the
downstream port of the host, hub, or upstream port of the hub, then tie this input to the
address of the device for which transactions needs to be tracked.
2. Input end_point_config configures the end points to be tracked. This input follows the
encoding scheme as explained below. For configuring the end points end point address,
transfer type supported by the end point, direction of the end point (IN or OUT), and
maximum packet size supported by the end point needs to be specified. Each end point
needs 21-bits for the configuration. The order in which these bits are used is as follows:
Assuming a 21-bit register for each end point configuration information, various fields
of the register are defined as shown below:
A3 A2 A1 A0 D T2 T1 T0 O1 O0 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
o
In this register, the A3 bit is the most significant bit, and S0 is the least
significant bit.
A3 A2 A1 A0
The D bit specifies the direction of the end point. When set to 1, the end point
supports only IN transactions. When set to 0, the end point supports only OUT
transactions. This bit should be set to 0 if the end point supports control
transfers.
T2 T1 T0
specifies the transfer type supported by the end point. Allowed values
for these bits are as follows:
0
0
0
1
0
1
1
0
1
0
1
0
Control transfer
Interrupt transfer
Bulk transfer
Isochronous transfer
782
0
1
0
1
Bits S10 to S0 specify the maximum packet size supported by the end point.
This field represents wMaxPacketSize of configuration information.
If there are multiple end points to be tracked by the monitor, then the above specified
encoding information should be provided for each end point. The encoded value of the
end points should be concatenated and wired to the end_point_config input.
For example, suppose the monitor needs to track two end points whose configuration
information is as follows:
end_point_1 = 21'b 0000_0_001_00_0000010000
or
{end_point_2, end_point_1}
Monitor Parameters
Parameters shown in Table 19-6 configures a USB 2.0 ULPI monitor.
Table 19-6. USB2.0 ULPI Monitor Parameters
Order
Parameter
Default
Description
1.
Constraints_Mode
2.
PORT_TYPE
783
Parameter
Default
Description
3.
ULPI_SIDE
4.
DATA_WIDTH
5.
DEVICE_SPEED
6.
NUMBER_OF_ENDPOINTS
7.
FRAME_INTERVAL_COUNT
7500
8.
SOF_JITTER_INTERVAL_
COUNT
9.
SEQUENCE_BIT_TRACKING_
ENABLE
10.
PACKET_ISSUE_CHECK_
ENABLE
STP_ASSERT_TO_NXT_
ASSERT_DELAY_HS_MIN
15
12.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_FS_MIN
13.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_LS_MIN
77
784
Parameter
Default
Description
14.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_HS_MAX
24
15.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_FS_MAX
18
16.
STP_ASSERT_TO_NXT_
ASSERT_DELAY_LS_MAX
247
17.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_HS_MIN
18.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_FS_MIN
19.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_LS_MIN
77
20.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_HS_MAX
14
21.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_FS_MAX
18
22.
DIR_DEASSERT_TO_NXT_
ASSERT_DELAY_LS_MAX
247
23.
DIR_DEASSERT_TO_DIR_
AND_NXT_ASSERT_DELAY_
HS_MIN
24.
DIR_DEASSERT_TO_DIR_
AND_NXT_ASSERT_DELAY_
FS_MIN
25.
DIR_DEASSERT_TO_DIR_
AND_NXT_ASSERT_DELAY_
LS_MIN
26.
STP_ASSERT_TO_DIR_AND_
NXT_ASSERT_DELAY_HS_
MAX
92
27.
STP_ASSERT_TO_DIR_AND_
NXT_ASSERT_DELAY_FS_
MAX
80
785
Parameter
Default
Description
28.
STP_ASSERT_TO_DIR_AND_
NXT_ASSERT_DELAY_LS_
MAX
718
29.
TIME_OUT_COUNT
800
30.
OTG_DEVICE
31.
HUB_TURNAROUND_
TIMEOUT_MIN
60000
32.
HUB_TURNAROUND_
TIMEOUT_MAX
150000
33.
HUB_CHIRP_K_TIMEOUT
3600
34.
HUB_CHIRP_J_TIMEOUT
3600
35.
HUB_CHIRP_K_MIN
2400
36.
HUB_CHIRP_J_MIN
2400
37.
HUB_CHIRP_KJ_MIN
38.
SE0_COUNT_FULL_SPEED_
REVERSE_ MAX
187500
39.
SE0_COUNT_FULL_SPEED_
REVERSE_MIN
180000
40.
FULL_SPEED_SE0_RESET_
TIMEOUT
150
41.
FULL_SPEED_J_SUSPEND_
TIMEOUT
180000
42.
LINE_STATE_DEBOUNCE_
TIMEOUT
6000
43.
CLK_USABLE_TIMEOUT
336000
786
Parameter
Default
Description
44.
MIN_RESET_INTERVAL
600000
45.
CHIRP_KJ_START_TIMEOUT
6000
46.
TERM_SEL_DEASS_AFTER_
HS_DETECT_TIMEOUT
30000
47.
DEV_CHIRP_K_ASSERT_
TIMEOUT
360000
48.
DEV_CHIRP_K_TIMEOUT
348000
49.
DEV_CHIRP_K_DEASS_
TIMEOUT_MAX
420000
50.
DEV_CHIRP_K_DEASS_
TIMEOUT_MIN
60000
51.
DEV_REMOTE_WAKE_UP_
COUNT_MIN
300000
52.
MAX_SUSPENDM_ASSERT_
INTERVAL
600000
53.
SUSPENDM_DEASSERT_TO_
RESUME_K_ASSERT_
TIMEOUT
600000
54.
RESUME_K_ASSERT_MIN
60000
55.
RESUME_K_ASSERT_MAX
900000
56.
RESUME_NORMAL_
OPERATION_TIMEOUT
80
57.
RESUME_K_DURATION_
LINE_STATE
1200000
58.
5
CLK_DETECT_DIR_
DEASSERTED_SUSPEND_MIN
59.
PRE_PID_LS_SYNC_MIN
20
60.
INIT_SE0_COUNT_DISCONN_
MIN
120000
787
Parameter
Default
Description
61.
DATA_LINE_PULSE_
DURATION_MIN
300000
62.
DATA_LINE_PULSE_
DURATION_MAX
600000
Instantiation Examples
Example 19-5 and Example 19-6 show instantiating the USB 2.0 ULPI monitors.
Example 1
This example instantiates a USB monitor to track a 4-bit ULP interface, full-speed only device.
Example 19-5. USB Monitor to Track an 4-bit ULP Interface
qvl_usb_2_0_ulpi_monitor
#( 0,
/* Constraints_Mode */
3,
/* PORT_TYPE */
0,
/* ULPI_SIDE */
4,
/* DATA_WIDTH */
1,
/* DEVICE_SPEED */
1,
/* NUMBER_OF_ENDPOINTS */
60000,
/* FRAME_INTERVAL_COUNT */
30,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_ULPI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.nxt
(nxt),
.stp
(stp),
.dir
(dir),
.data
(data),
.address
(address)
.end_point_config (end_point_config),
.number_of_active_endpoints (5'd1) );
788
Example 2
This example instantiates a USB monitor on the upstream port of a dual mode high-speed
device to track transactions of four end points. The address of the device is specified through the
address input. The ULP interface is a high-speed, 8-bit interface.
Example 19-6. USB Monitor on the Upstream Port
qvl_usb_2_0_ulpi_monitor
#( 0,
/* Constraints_Mode */
3,
/* PORT_TYPE */
0,
/* ULPI_SIDE */
8,
/* DATA_WIDTH */
0,
/* DEVICE_SPEED */
4,
/* NUMBER_OF_ENDPOINTS */
7500, /* FRAME_INTERVAL_COUNT */
4,
/* SOF_JITTER_INTERVAL_COUNT */
1,
/* SEQUENCE_BIT_TRACKING_ENABLE */
1)
/* PACKET_ISSUE_CHECK_ENABLE */
USB_ULPI_MON (
.clock
(clock),
.areset
(areset),
.reset
(reset),
.nxt
(nxt),
.stp
(stp),
.dir
(dir),
.data
(data),
.address
(address)
.end_point_config (end_point_config),
.number_of_active_endpoints (5'd4) );
789
Monitor Checks
USB 2.0 Standard Monitor Checks
Table 19-7 lists the checks performed by the USB 2.0 standard monitor.
Table 19-7. USB 2.0 Standard Monitor Checks
Check ID
Violation
Description
USB_2_0_ACK_ISSUED_BY_
DEVICE_DURING_IN_XFR
USB_2_0_ACK_ISSUED_BY_
HOST_DURING_NON_IN_XFR
USB_2_0_ACK_RECEIVED_
FOR_IN_TKN
USB_2_0_ADDRESS_
KNOWN_DRIVEN
USB_2_0_BIT_STUFF_ERR_
HOST
USB_2_0_BULK_ISO_ON_
LOW_SPD_BUS
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST
USB_2_0_BIT_STUFF_ERR_
DEVICE
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
790
Violation
Description
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_CLEAR_FEATURE_
HUB_REQUEST_ERR
A CLEAR_FEATURE hub
class request should have
windex of zero and wlength
of zero.
USB_2_0_CLEAR_
FEATURE_REQUEST_
DEVICE_ERR
A CLEAR FEATURE
request (device as recipient)
should have zero value
windex.
USB_2_0_CLEAR_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE
request should have a value
of zero for wlength.
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE (clear
port feature) hub class
request should have wlength
of zero.
USB_2_0_CLEAR_REQUEST_
OTG_ERR
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER
A CLEAR_TT_BUFFER hub class request
hub class request should have should have wlength of zero. This check
wlength of zero.
fires if the wlength field is not zero.
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
USB_2_0_CSPLIT_TO_ISO_
END_POINT
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR
791
Violation
Description
USB_2_0_CTRL_XFR_DATA_
PHASE_LENGTH_ERR_HOST
An isochronous transfer
should always use DATA0
packet id during transmission
of data packets.
USB_2_0_CTRL_XFR_DATA_
PHASE_LENGTH_ERR_
DEVICE
USB_2_0_CTRL_XFR_SEQ_
BIT_ERR_HOST
USB_2_0_CTRL_XFR_SEQ_
BIT_ERR_DEVICE
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_HOST
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_DEVICE
USB_2_0_DATA_CRC_ERR_
HOST
USB_2_0_DATA_CRC_ERR_
DEVICE
USB_2_0_DATA_PID_
ERR_ISO_XFR_HOST
USB_2_0_DATA_PID_
ERR_ISO_XFR_DEVICE
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING
792
Violation
Description
USB_2_0_DEVICE_ISSUED_
TKN
USB_2_0_DM_KNOWN_
DRIVEN
USB_2_0_DP_KNOWN_
DRIVEN
USB_2_0_END_POINT_
CONFIG_KNOWN_DRIVEN
USB_2_0_EXT_TKN_CRC_ERR
USB_2_0_EXT_TKN_PKT_
ILLEGAL_bLinkState
USB_2_0_EXT_TKN_PKT_
ILLEGAL_SUBPID
USB_2_0_EXT_TKN_PKT_
SIZE_ERR
USB_2_0_FRAME_NUMBER_
ERR
USB_2_0_FUNCTION_MAX_
INTER_PKT_DLY_ERR
793
Violation
Description
USB_2_0_FUNCTION_MIN_
INTER_PKT_DLY_ERR
USB_2_0_FUNCTION_
RESPONDS_FOR_ERR_PKT
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
request should have a value
of zero for wvalue, windex,
and a value of one for
wlength.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR
USB_2_0_GET_
INTERFACE_REQUEST_ERR
A GET_INTERFACE
request should have wvalue
of zero and wlength of one.
USB_2_0_GET_INTERFACE_
REQUEST_TO_HUB
GET_INTERFACE request
should not be issued to the
hub.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR
794
Violation
Description
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
A GET_STATUS request
with device as recipient
should have wvalue of zero,
windex of zero, and wlength
of two.
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_ERR
A GET_STATUS request
with nondevice as recipient
should have wvalue of zero
and wlength of two.
USB_2_0_HANDSHAKE_PKT_
IN_ISO_XFR
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST_
USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR
USB_2_0_HOST_ISSUED_
ILLEGAL_HANDSHAKE
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
795
Violation
Description
USB_2_0_HOST_MAX_
INTER_PKT_DLY_ERR
USB_2_0_HOST_MIN_
INTER_PKT_DLY_ERR
USB_2_0_HOST_RESPONDS_
FOR_ERR_PKT
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE
USB_2_0_ILLEGAL_BULK_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for bulk transfer
end points.
USB_2_0_ILLEGAL_CTRL_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for control transfer
end points.
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ
796
Violation
Description
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
Illegal wmaxpacketsize
specified for interrupt
transfer end points.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for isochronous
transfer end points.
USB_2_0_ILLEGAL_SE0_
SIGNALING_HOST
USB_2_0_ILLEGAL_
TOKEN_ON_FULL_SPD_LINK
USB_2_0_IN_END_POINT_
RECEIVED_OUT_TKN
USB_2_0_INT_XFR_DATA_
PID_ERR_HOST
USB_2_0_ILLEGAL_SE0_
SIGNALING_DEVICE
USB_2_0_INT_XFR_DATA_
PID_ERR_DEVICE
USB_2_0_INT_XFR_SEQ_BIT_
ERR_HOST
USB_2_0_INT_XFR_SEQ_BIT_
ERR_DEVICE
797
Violation
Description
USB_2_0_INVALID_
SIGNALING_ON_BUS_HOST
USB_2_0_LPM_DATA0_TKN_
WITHOUT_EXT_TKN
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
Function should
acknowledge with ACK
handshake when setup data is
received without an error.
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
HOST
USB_2_0_NO_RESPONSE_
FOR_PKT_RECEIVED_
WITHOUT_ERR
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
USB_2_0_NON_CONTROL_
ENDPOINT_ZERO
USB_2_0_NON_INTEGRAL_
NUMBER_OF_BYTES_HOST
USB_2_0_INVALID_
SIGNAIGNALING_ON_BUS_
DEVICE
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
DEVICE
USB_2_0_NON_INTEGRAL_
NUMBER_OF_BYTES_DEVICE
798
Violation
Description
USB_2_0_NUMBER_OF_
ENDPOINTS_ERROR
USB_2_0_OE_KNOWN_
DRIVEN
USB_2_0_OUT_ENDPOINT_
RECEIVED_IN_TKN
USB_2_0_PING_
HANDSHAKE_ERROR
USB_2_0_PING_NEXT_
TRANSACTION_ERROR
USB_2_0_PING_NOT_
INITIATED
USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
USB_2_0_PRE_PID_ISSUED
799
Violation
Description
USB_2_0_REQUEST_NOT_
DEFINED
USB_2_0_REQUEST_
RECIPIENT_NOT_DEFINED
Recipient field of
Recipient field of bmrequesttype specified
bmrequesttype is not defined. in the SETUP data should be a defined
value. This check fires if the values are
undefined. This check is active if the
PACKET_ISSUE_CHECK_ENABLE
parameter is 1.
USB_2_0_REQUEST_TYPE_
NOT_DEFINED
USB_2_0_RESET_TT_ERR
USB_2_0_RESPONSE_
FOR_OUT_SETUP_TOKEN
USB_2_0_SET_ADDRESS_
REQUEST_ERR
A SET_ADDRESS request
should have wlength and
windex of zero.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
request should have wlength
and windex of zero.
USB_2_0_SET_FEATURE_
REQUEST_DEVICE_ERR
USB_2_0_SET_FEATURE_
REQUEST_ERR
A SET_FEATURE request
should have wlength of zero.
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR
800
Violation
USB_2_0_SET_
INTERFACE_REQUEST_ERR
USB_2_0_SET_INTERFACE_
REQUEST_TO_HUB
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR
USB_2_0_SETUP_DATA_PID_
ERR
USB_2_0_SETUP_DATA_
SIZE_ERR
USB_2_0_SETUP_TKN_TO_
NON_CTRL_ENDPOINT
USB_2_0_SOF_PKT_ISSUED_
TO_LOW_SPD_DEVICE
SOF packets are to be ignored by the lowspeed devices. However, to defeat illegal
behavior, the monitor tracks whether SOF
packets are issued to low-speed devices.
This check fires if the SOF packets are seen
on the low-speed interface. This check is
active only if the PACKET_ISSUE_
CHECK_ENABLE parameter is 1.
Description
801
Violation
Description
USB_2_0_SOF_PKTS_AT_
IRREGULAR_INTERVALS
USB_2_0_SPEED_KNOWN_
DRIVEN
USB_2_0_SPLIT_PKT_SIZE_
ERR
USB_2_0_SPLIT_TKN_E_BIT_
ERROR
USB_2_0_SPLIT_TKN_S_BIT_
ERROR
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP
802
Violation
Description
USB_2_0_STALL_RECEIVE_
ERR
If STALL handshake is
received during data phase or
status phase of the control
transfer, then successive
access to that control
endpoint should result in the
reception of stall handshake
until the completion of next
setup phase.
USB_2_0_STOP_TT_
REQUEST_ERR
USB_2_0_SYNC_FRAME_
REQUEST_ERR
USB_2_0_SYNCH_FRAME_
REQUEST_TO_HUB
USB_2_0_TKN_CRC_ERR
USB_2_0_TKN_PKT_SIZE_ERR
USB_2_0_TOKEN_BEFORE_
TIMEOUT
803
Violation
Description
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE
804
Check ID
Violation
Description
USB_2_0_UTMI_DATA_
CHANGE_BEFORE_TX_
READY
USB_2_0_UTMI_DATA_
HIGH_KNOWN_DRIVEN
USB_2_0_UTMI_DATA_
IN_KNOWN_DRIVEN
USB_2_0_UTMI_DATA_
LOW_KNOWN_DRIVEN
USB_2_0_UTMI_DATA_
OUT_KNOWN_DRIVEN
USB_2_0_UTMI_
DATABUS16_8_KNOWN_
DRIVEN
USB_2_0_UTMI_ILLEGAL_
RX_VALID
Violation
Description
USB_2_0_UTMI_ILLEGAL_
RX_VALIDH
USB_2_0_UTMI_ILLEGAL_
TX_READY
USB_2_0_UTMI_ILLEGAL_
TX_VALIDH
USB_2_0_UTMI_LINE_
STATE_KNOWN_DRIVEN
USB_2_0_UTMI_NUMBER_
OF_ENDPOINTS_ERROR
USB_2_0_UTMI_INVALID_
CHIRP_SEQUENCE
USB_2_0_UTMI_TIMEOUT_
KJ_CHIRP_DURATION
USB_2_0_UTMI_J_STATE_
DURING_DEV_K_CHIRP
USB_2_0_UTMI_DEV_
INITIATE_WITH_J_DURING_
CHIRP
USB_2_0_UTMI_TERM_SEL_
DEASSERT_TIMEOUT
USB_2_0_UTMI_RX_
ACTIVE_KNOWN_DRIVEN
805
806
Check ID
Violation
Description
USB_2_0_UTMI_RX_
DEASSERT_TO_TX_VALID_
ASSERT_MAX_ERROR
USB 2.0 specifies the maximum interpacket delay when the USB host/device
is required to respond to the packet. The
host/device should start responding
within the specified maximum delay.
This check fires if the maximum interpacket delay is violated.
USB_2_0_UTMI_RX_
DEASSERT_TO_TX_VALID_
ASSERT_MIN_ERROR
USB_2_0_UTMI_RX_
ERROR_KNOWN_DRIVEN
USB_2_0_UTMI_RX_
VALID_ASSERTED_
BEFORE_RX_ACTIVE
USB_2_0_UTMI_RX_
VALID_KNOWN_DRIVEN
USB_2_0_UTMI_RX_VALID_
MORE_THAN_ONE_CLOCK
USB_2_0_UTMI_RX_
VALID_NOT NEGATED
USB_2_0_UTMI_RX_
VALIDH_KNOWN_DRIVEN
USB_2_0_UTMI_
RXERROR_ASSERTED
USB_2_0_UTMI_TERM_
SELECT_KNOWN_DRIVEN
Violation
Description
USB_2_0_UTMI_TX_READY_
ASSERTED_MORE_THAN_
ONE_CLOCK
USB_2_0_UTMI_TX_
READY_KNOWN_DRIVEN
USB_2_0_UTMI_TX_VALID_
DEASSERT_TO_RX_ACTIVE_
ASSERT_MAX_ERROR
USB 2.0 specifies the maximum interpacket delay when the USB host/device
is required to respond to the packet. The
host/device should start responding
within the specified maximum delay.
This check fires if the maximum interpacket delay is violated.
USB_2_0_UTMI_TX_VALID_
DEASSERT_TO_RX_ACTIVE_
ASSERT_MIN_ERROR
USB_2_0_UTMI_TX_
VALID_KNOWN_DRIVEN
USB_2_0_UTMI_TX_
VALID_RX_ACTIVE_
ASSERTED
USB_2_0_UTMI_TX_
VALIDH_KNOWN_DRIVEN
USB_2_0_UTMI_VALIDH_
KNOWN_DRIVEN
USB_2_0_UTMI_XCVR_
SELECT_KNOWN_DRIVEN
USB_2_0_UTMI_INTER_RX_
VALID_DELAY
USB_2_0_UTMI_INTER_TX_
READY_DELAY
807
808
Check ID
Violation
Description
USB_2_0_UTMI_RX_ACTIVE_
DEASSERT_TO_RX_ACTIVE_
ASSERT_ERROR
USB_2_0_UTMI_SUSPENDM_
TERM_SELECT_FS
USB_2_0_UTMI_RX_VALID_
DEASSERT_MORE_THAN_
ONE_CLOCK
USB_2_0_UTMI_TX_READY_
DEASSERT_MORE_THAN_
ONE_CLOCK
USB_2_0_UTMI_TX_VALID_
DEASSERT_TO_TX_READY_
DEASSERT_ERROR
USB_2_0_UTMI_RX_ACTIVE_
RX_VALID_ACTIVITY_
WHILE_TX
USB_2_0_UTMI_TX_READY_
TX_VALID_ACTIVITY_
WHILE_RX
USB_2_0_UTMI_RX_VALID_
ASSERTION_DELAY
USB_2_0_UTMI_TX_READY_
ASSERTION_DELAY
USB_2_0_UTMI_FULL_
SPEED_REVERSAL_ERROR
USB_2_0_UTMI_SUSPENDM_
NEGATION_RESET_ERROR
SuspendM is not
When reset is entered from a suspended
combinatorially negated when state SuspendM is combinatorially
reset is entered from suspended negated.
state.
USB_2_0_UTMI_DEV_CHIRP_
ASSERT_MAX_DELAY
Violation
Description
USB_2_0_UTMI_REMOTE_
WAKE_UP_MIN_DELAY
USB_2_0_UTMI_RESUME_
SIGNAL_ASSERT_MAX_
DURATION_ERROR
USB_2_0_UTMI_DEV_CHIRP_
DEASSERT_MAX_DELAY
USB_2_0_UTMI_CHIRP_KJ_
START_DELAY
USB_2_0_UTMI_REMOTE_
WAKE_UP_MAX_DELAY
USB_2_0_UTMI_RESUME_
SIGNAL_ASSERT_MIN_
DURATION_ERROR
USB_2_0_UTMI_DEV_CHIRP_
SUSPEND_ASSERT_MAX_
DELAY
USB_2_0_UTMI_RESET_I
NTERVAL_MIN_ERROR
USB_2_0_UTMI_SUSPENDM_
ASSERT_MAX_DELAY
USB_2_0_UTMI_SPEED_
MISMATCH_AFTER_RESUME
USB_2_0_UTMI_RESUME_
NORMAL_OPER_MAX_
ERROR
USB_2_0_UTMI_RESUME_K_
DURATION_MIN_ERROR
USB_2_0_UTMI_INVALID_
SIGNALING_ON_LINE_STATE
Invalid LineState.
809
Violation
Description
USB_2_0_UTMI_RX_ACTIVE_
DEASSERT_TO_RX_VALID_
DEASSERT_ERROR
USB_2_0_UTMI_HS_RX_
ACTIVE_ASSERT_TO_RX_
VALID_ASSERT_DELAY
USB_2_0_UTMI_FS_LS_RX_
ACTIVE_ASSERT_TO_RX_
VALID_ASSERT_DELAY
USB_2_0_UTMI_RX_VALIDH_
MORE_THAN_ONE_CLOCK
810
USB_2_0_UTMI_ILLEGAL_
PORT_TYPE_LEVEL_0
USB_2_0_UTMI_DP_
PULLDOWN_VALUE_ERROR
USB_2_0_UTMI_DM_
PULLDOWN_VALUE_ERROR
USB_2_0_UTMI_HOST_
DISCONNECT_XCVR_
SELECT_ERROR
USB_2_0_UTMI_HOST_
DISCONNECT_UPDATE_
ERROR
Early update of
HostDisconnect after reversal
to FS mode.
USB_2_0_UTMI_ILLEGAL_
COMB_OP_MODE_XCVR_
SELECT
USB_2_0_UTMI_ILLEGAL_
XCVR_SELECT
USB_2_0_UTMI_ID_DIG_
KNOWN_DRIVEN
USB_2_0_UTMI_SESS_END_
KNOWN_DRIVEN
Violation
Description
USB_2_0_UTMI_HOST_
DISCONNECT_KNOWN_
DRIVEN
USB_2_0_UTMI_VBUS_
VALID_KNOWN_DRIVEN
USB_2_0_UTMI_AVALID_
KNOWN_DRIVEN
USB_2_0_UTMI_BVALID_
KNOWN_DRIVEN
USB_2_0_UTMI_DRV_VBUS_
KNOWN_DRIVEN
USB_2_0_UTMI_DISCHRG_
VBUS_KNOWN_DRIVEN
USB_2_0_UTMI_DP_
PULLDOWN_KNOWN_
DRIVEN
USB_2_0_UTMI_DM_
PULLDOWN_KNOWN_
DRIVEN
USB_2_0_UTMI_ID_PULLUP_
KNOWN_DRIVEN
USB_2_0_UTMI_END_PREV_
SESS_BEFORE_NEW_SESS_
REQ_ERROR
USB_2_0_UTMI_DEV_
DISCONN_BEFORE_SRP_
ERROR
USB_2_0_UTMI_SRP_AT_
NON_FULL_SPEED
811
Violation
Description
USB_2_0_UTMI_VBUS_AND_
DATA_LINE_PULSING_
ORDER_ERROR
USB_2_0_UTMI_DATA_LINE_
PULSE_DURATION_ERROR
USB_2_0_UTMI_HOST_
RECEIVED_SOF_WITHOUT_
HNP
USB_2_0_UTMI_AVALID_
ASSERT_ERROR
USB_2_0_UTMI_BVALID_
ASSERT_ERROR
USB_2_0_UTMI_ILLEGAL_
LINE_STATE_WHEN_
SESSION_NOT_VALID
Violation
Description
USB_2_0_ACK_ISSUED_BY_
DEVICE_DURING_IN_XFR
USB_2_0_ACK_ISSUED_BY_
HOST_DURING_NON_IN_
XFR
USB_2_0_ACK_
RECEIVED_FOR_IN_TKN
812
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_BULK_ISO_
ON_LOW_SPD_BUS
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST
USB_2_0_CLEAR_FEATURE_
HUB_REQUEST_ERR
A CLEAR_FEATURE hub
class request should have
windex of zero and wlength of
zero.
USB_2_0_CLEAR_FEATURE_
REQUEST_DEVICE_ERR
USB_2_0_CLEAR_FEATURE_
REQUEST_ERR
A CLEAR_FEATURE
request should have a value of
zero for wlength.
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE (clear
port feature) hub class request
should have wlength of zero.
USB_2_0_CLEAR_REQUEST_
OTG_ERR
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER hub
class request should have
wlength of zero.
USB_2_0_CSPLIT_TKN_U_
BIT_ERROR
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
813
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_CSPLIT_TO_
ISO_END_POINT
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_HOST
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_DEVICE
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_DEVICE
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_HOST
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_DEVICE
USB_2_0_DATA_CRC_ERR_
HOST
USB_2_0_DATA_CRC_ERR_
DEVICE
814
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_DATA_PID_ERR_
ISO_XFR_HOST
An isochronous transfer
should always use DATA0
packet id during transmission
of data packets.
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING
USB_2_0_DEVICE_ISSUED_
TKN
USB_2_0_EXT_TKN_CRC_
ERR
USB_2_0_EXT_TKN_PKT_
ILLEGAL_bLinkState
USB_2_0_EXT_TKN_PKT_
ILLEGAL_SUBPID
USB_2_0_EXT_TKN_PKT_
SIZE_ERR
USB_2_0_FRAME_NUMBER_
ERROR
USB_2_0_DATA_PID_ERR_
ISO_XFR_DEVICE
815
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_FUNCTION_
RESPONDS_FOR_ERR_PKT
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
request should have a value of
zero for wvalue and windex,
and a value of one for
wlength.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR
USB_2_0_GET_INTERFACE_
REQUEST_ERR
A GET_INTERFACE request
should have wvalue of zero
and wlength of one.
USB_2_0_GET_INTERFACE_
REQUEST_TO_HUB
GET_INTERFACE request
should not be issued to hub.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
A GET_STATUS request
with device as recipient
should have wvalue of zero,
windex of zero, and wlength
of two.
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_
ERR
A GET_STATUS request
with nondevice as recipient
should have wvalue of zero
and wlength of two.
USB_2_0_HANDSHAKE_
PKT_IN_ISO_XFR
816
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST
USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR
USB_2_0_HOST_ISSUED_
ILLEGAL_HANDSHAKE
USB_2_0_HOST_ISSUED_
TKN_BEFORE_XFR_
COMPLETE
USB_2_0_HOST_RESPONDS_
FOR_ERR_PKT
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE
USB_2_0_ILLEGAL_BULK_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for bulk transfer end
points.
USB_2_0_ILLEGAL_CTRL_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for control transfer
end points.
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
817
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
Illegal wmaxpacketsize
specified for interrupt transfer
end points.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for isochronous
transfer end points.
USB_2_0_ILLEGAL_TOKEN_
ON_FULL_SPD_LINK
USB_2_0_IN_END_POINT_
RECEIVED_OUT_TKN
USB_2_0_INT_XFR_
DATA_PID_ERR_HOST
USB_2_0_INT_XFR_DATA_
PID_ERR_DEVICE
USB_2_0_INT_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_INT_XFR_
SEQ_BIT_ERR_DEVICE
USB_2_0_LPM_DATA0_TKN_
WITHOUT_EXT_TKN
818
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
HOST
USB_2_0_NO_RESPONSE_
FOR_PKT_RECEIVED_
WITHOUT_ERR
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
USB_2_0_NON_CONTROL_
ENDPOINT_ZERO
USB_2_0_OUT_ENDPOINT_
RECEIVED_IN_TKN
Host should not issue IN token Host should not initiate an IN transaction
to OUT only end point.
to an OUT only end point. This check fires
if the host issues IN token to an OUT only
end point. This check is active only when
the address input matches the address
received in the tokens. This check is
enabled only if the PACKET_ISSUE_
CHECK_ENABLE parameter is 1.
USB_2_0_PING_
HANDSHAKE_ERROR
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
DEVICE
819
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_PING_NEXT_
TRANSACTION_ERROR
USB_2_0_PING_NOT_
INITIATED
USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST
USB_2_0_PRE_PID_ISSUED
USB_2_0_REQUEST_
NOT_DEFINED
USB_2_0_REQUEST_
RECIPIENT_NOT_DEFINED
Recipient field of
bmrequesttype is not defined.
USB_2_0_REQUEST_
TYPE_NOT_DEFINED
USB_2_0_RESET_TT_
DESCRIPTOR_REQUEST_
ERR
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
820
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_RESPONSE_FOR_
OUT_SETUP_TOKEN
USB_2_0_SET_ADDRESS_
REQUEST_ERR
A SET_ADDRESS request
should have wlength and
windex of zero.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
request should have wlength
and windex of zero.
USB_2_0_SET_FEATURE_
REQUEST_DEVICE_ERR
USB_2_0_SET_FEATURE_
REQUEST_ERR
A SET_FEATURE request
should have wlength of zero.
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR
USB_2_0_SET_INTERFACE_
REQUEST_ERR
A SET_INTERFACE request
should have wlength of zero.
USB_2_0_SET_INTERFACE_
REQUEST_TO_HUB
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR
USB_2_0_SETUP_DATA_
PID_ERR
USB_2_0_SETUP_DATA_
SIZE_ERR
821
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_SETUP_TKN_TO_
NON_CTRL_ENDPOINT
USB_2_0_SOF_PKT_ISSUED_
TO_LOW_SPD_DEVICE
SOF packets are to be ignored by the lowspeed devices. However, to defeat illegal
behavior, the monitor tracks whether SOF
packets are issued to low-speed devices.
This check fires if the SOF packets are
seen on the low-speed interface. This
check is active only if the PACKET_
ISSUE_CHECK_ENABLE parameter is
1.
USB_2_0_SOF_PKTS_AT_
IRREGULAR_INTERVALS
USB_2_0_SPLIT_PKT_SIZE_
ERR
USB_2_0_SPLIT_TKN_E_
BIT_ERROR
USB_2_0_SPLIT_TKN_S_
BIT_ERROR
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
822
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP
USB_2_0_STALL_
RECEIVE_ERR
If STALL handshake is
received during data phase or
status phase of control
transfer, then successive
access to that control endpoint
should result in reception of
stall handshake until the
completion of the next setup
phase.
USB_2_0_STOP_TT_
REQUEST_ERR
USB_2_0_SYNC_FRAME_
REQUEST_ERR
A SYNCH_FRAME request
should have wvalue of zero
and wlength of two.
USB_2_0_SYNCH_FRAME_
REQUEST_TO_HUB
USB_2_0_TKN_CRC_ERR
USB_2_0_TKN_PKT_SIZE_
ERR
823
Table 19-9. USB 2.0 UTMI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_TOKEN_
BEFORE_TIMEOUT
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE
Violation
Description
USB_2_0_ULPI_ASSERT_STP_
BEFORE_FIRST_BYTE_
CONSUMED
USB_2_0_ULPI_CHIRP_J_
AFTER_DEVICE_CHIRP
824
Violation
Description
USB_2_0_ULPI_DATA_LINE_
PULSE_DURATION_
VIOLATION
USB_2_0_ULPI_DATA_NOT_
THROTTLED
USB_2_0_ULPI_DATA_
UNKNOWN_DRIVEN
USB_2_0_ULPI_DATA_WIDTH_
ERR
USB_2_0_ULPI_DEVICE_
CHIRP_K_TIMEOUT
USB_2_0_ULPI_DEVICE_
CHIRP_MAX_VIOLATION
USB_2_0_ULPI_DEVICE_
CHIRP_MIN_VIOLATION
USB_2_0_ULPI_DEVICE_
CHIRP_SUSPEND_TIMEOUT
USB_2_0_ULPI_DEVICE_
RESUME_INTERVAL_ERR
825
Violation
Description
USB_2_0_ULPI_DIR_
DEASSERTED_REG_READ_
DATA
USB_2_0_ULPI_DIR_
UNKNOWN_DRIVEN
USB_2_0_ULPI_DP_
PULLDOWN_VALUE_ERROR
USB_2_0_ULPI_FS_REVERT_
BACK_ERR
USB_2_0_ULPI_FS_REVERT_
BACK_TIMEOUT
USB_2_0_ULPI_FS_REVERT_
TIMEOUT
USB_2_0_ULPI_HOST_CHIRP_
J_DURATION_ERR
USB_2_0_ULPI_HOST_CHIRP_
K_DURATION_ERR
USB_2_0_ULPI_HOST_CHIRP_
KJ_COUNT_ERR
USB_2_0_ULPI_HOST_
DISCONNECT_IN_NON_
SYNCHRONOUS_MODE
826
Violation
Description
USB_2_0_ULPI_HOST_
DISCONNECT_READ_ERR
USB_2_0_ULPI_HOST_
DISCONNECT_WRITE_ERR
USB_2_0_ULPI_HOST_
DISCONNECT_XCVR_SELECT_
ERROR
USB_2_0_ULPI_HOST_
RECEIVED_SOF_WITHOUT_
HNP
USB_2_0_ULPI_HOST_
RESUME_MIN_ERR
USB_2_0_ULPI_HS_REVERT_
ERR
USB_2_0_ULPI_HUB_CHIRP_
TIMEOUT
USB_2_0_ULPI_INVALID_
LINE_STATE
USB_2_0_ULPI_INVALID_
LINESTATE_BETWEEN_HOST_
CHIRP
USB_2_0_ULPI_INVALID_STP_
ASSERT_FOR_REG_
OPERATION
827
Violation
Description
USB_2_0_ULPI_LINK_
TRANSMIT_ANOTHER_FIRST_
INCOMPLETE
USB_2_0_ULPI_LOW_POWER_
MODE_DIR_ASSERT_ERR
USB_2_0_ULPI_LOW_POWER_
MODE_DIR_ASSERT_
EXPECTED_ERR
USB_2_0_ULPI_LOW_POWER_
MODE_DIR_DE_ASSERTED
USB_2_0_ULPI_LOW_POWER_
MODE_EXIT_COUNT_ERR
USB_2_0_ULPI_LOW_POWER_
MODE_INVALID_DATA2
USB_2_0_ULPI_LOW_POWER_
MODE_NXT_ASSERTED
USB_2_0_ULPI_LOW_POWER_
MODE_STP_ERR
USB_2_0_ULPI_NON_ZERO_
ON_BUSS_DURING_IDLE
USB_2_0_ULPI_NUMBER_OF_
ENDPOINTS_ERROR
828
Violation
Description
USB_2_0_ULPI_NXT_ASSERT_
DURING_READ_DATA
USB_2_0_ULPI_NXT_ASSERT_
DURING_RXERROR
USB_2_0_ULPI_NXT_ASSERT_
OUTSIDE_BYTE_BOUNDARY
USB_2_0_ULPI_NXT_
ASSERTED_DURING_IDLE
USB_2_0_ULPI_NXT_
ASSERTED_MORE_THAN_
ONCE_IN_ONE_BYTE
USB_2_0_ULPI_NXT_BEFORE_
RXACTIVE
USB_2_0_ULPI_NXT_
DEASSERT_EXTENDED_
ADDRESS
USB_2_0_ULPI_NXT_
DEASSERT_REG_WRITE
829
Violation
Description
USB_2_0_ULPI_NXT_
DEASSERTED_FOR_MORE_
THAN_ONE_CYCLE
USB_2_0_ULPI_NXT_DIR_
DEASSERT_AFTER_STP_
ASSERT
USB_2_0_ULPI_NXT_SHOULD_
DEASSERT_AFTER_FIRST_
NOPID
If TX CMD NOPID is
transmitted, then after
indicating nxt high for TX
CMD, nxt should go low for
next byte and then should go
high.
USB_2_0_ULPI_NXT_SHOULD_
FOLLOW_DIR
USB_2_0_ULPI_NXT_TXCMD_
MIS_BEHAVIOUR
Between appearance of TX
CMD on data line and
assertion of nxt there should
be exactly one cycle delay.
USB_2_0_ULPI_NXT_
UNKNOWN_DRIVEN
USB_2_0_ULPI_PHY_ABORT_
LINK_PREVIOUSLY_ABORT
USB_2_0_ULPI_PHY_
TRANSMIT_BEFORE_
SENDING_EOP
830
Violation
Description
USB_2_0_ULPI_PREAMBLE_
ERR
USB_2_0_ULPI_RECEIVE_TO_
RECEIVE_DELAY
USB_2_0_ULPI_RECEIVE_TO_
TRANSMIT_MAX
USB_2_0_ULPI_RECEIVE_TO_
TRANSMIT_MIN
USB_2_0_ULPI_REG_NOT_
WRITE_PERMISSION
USB_2_0_ULPI_REG_READ_
DIR_NOT_ASSERT_AFTER_
ADDRESS
USB_2_0_ULPI_REG_READ_
ILLEGAL_DIR
USB_2_0_ULPI_REG_READ_
RX_ACTIVE
USB_2_0_ULPI_REG_
RESERVED_BITS_READ_ERR
USB_2_0_ULPI_REG_
RESERVED_BITS_WRITE_ ERR
831
Violation
Description
USB_2_0_ULPI_REG_WRITE_
DIR_ASSERTED
USB_2_0_ULPI_REG_WRITE_
END_WITH_STP
USB_2_0_ULPI_REG_WRITE_
NXT_MISBEHAVE
USB_2_0_ULPI_REMOTE_
WAKE_UP_ERR
USB_2_0_ULPI_REMOTE_
WAKE_UP_TIMEOUT
USB_2_0_ULPI_RESERVED_
REG_ADDRESS
USB_2_0_ULPI_RESERVED_
TX_CMD
USB_2_0_ULPI_RESET_
INTERVAL_ERR
USB_2_0_ULPI_RESET_SE0_
ERR
USB_2_0_ULPI_RESUME_
NORMAL_OPERTAION_
VIOLATION
USB_2_0_ULPI_SE0_AFTER_
RESUME_K_VIOLATION
USB_2_0_ULPI_SESS_VALID_
ASSERT_ERROR
832
Violation
Description
USB_2_0_ULPI_SESS_VALID_
SESS_END_MISMATCH
USB_2_0_ULPI_SESSION_END_
LINE_STATE_VIOLATION
USB_2_0_ULPI_SESSION_
INVALID_NORMAL_
OPERATION_GOING
USB_2_0_ULPI_SRP_SPEED_
MISMATCH
USB_2_0_ULPI_STP_ASSERT_
NXT_NOT_DEASSERT
USB_2_0_ULPI_STP_
ASSERTED_MORE_THAN_
ONCE
USB_2_0_ULPI_STP_
UNKNOWN_DRIVEN
USB_2_0_ULPI_SUSPEND_
ASSERT_MAX_ERR
USB_2_0_ULPI_SUSPEND_
SPEED_MISMATCH
USB_2_0_ULPI_SUSPENDM_
TERM_SELECT_FS
833
Violation
Description
USB_2_0_ULPI_TRANSMIT_
TO_RECEIVE_DELAY
USB_2_0_ULPI_TRANSMIT_
TO_TRANSMIT_MAX
USB_2_0_ULPI_TRANSMIT_
TO_TRANSMIT_MIN
USB_2_0_ULPI_VALID_FS_LS_
EOP
USB_2_0_ULPI_VBUS_
PULSING_ORDER_MISMATCH
USB_2_0_ULPI_WRONG_
DATA_ON_BUSS_DURING_
STP_FS_LS
USB_2_0_ULPI_WRONG_
DATA_ON_BUSS_DURING_
STP_HS
USB_2_0_ULPI_WRONG_
DATA_ON_BUSS_DURING_
STP_REG_OPERATION
834
Violation
Description
USB_2_0_ACK_ISSUED_BY_
DEVICE_DURING_IN_XFR
USB_2_0_ACK_ISSUED_BY_
HOST_DURING_NON_IN_
XFR
USB_2_0_ACK_
RECEIVED_FOR_IN_TKN
USB_2_0_BULK_ISO_
ON_LOW_SPD_BUS
USB_2_0_BULK_XFR_
DATA_PID_ERR_HOST
USB_2_0_CLEAR_FEATURE_
HUB_REQUEST_ERR
A CLEAR_FEATURE hub
class request should have
windex of zero and wlength of
zero.
USB_2_0_CLEAR_FEATURE_
REQUEST_DEVICE_ERR
USB_2_0_BULK_XFR_
DATA_PID_ERR_DEVICE
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_BULK_XFR_
SEQ_BIT_ERR_DEVICE
835
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_CLEAR_FEATURE_
REQUEST_ERR
A CLEAR_FEATURE
request should have a value of
zero for wlength.
USB_2_0_CLEAR_PORT_
FEATURE_REQUEST_ERR
A CLEAR_FEATURE (clear
port feature) hub class request
should have wlength of zero.
USB_2_0_CLEAR_REQUEST_
OTG_ERR
USB_2_0_CLEARTT_
REQUEST_ERR
A CLEAR_TT_BUFFER hub
class request should have
wlength of zero.
USB_2_0_CSPLIT_TKN_U_
BIT_ERROR
USB_2_0_CSPLIT_TO_
ISO_END_POINT
USB_2_0_CTRL_XFR_
DATA_PHASE_DIR_ERR
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_HOST
USB_2_0_CTRL_XFR_
DATA_PHASE_LENGTH_
ERR_DEVICE
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_CTRL_XFR_
SEQ_BIT_ERR_DEVICE
836
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_HOST
An isochronous transfer
should always use DATA0
packet id during transmission
of data packets.
USB_2_0_DEVICE_
INITIATED_XFR_WHEN_
HOST_NOT_WAITING
USB_2_0_DEVICE_ISSUED_
TKN
USB_2_0_EXT_TKN_CRC_
ERR
USB_2_0_EXT_TKN_PKT_
ILLEGAL_bLinkState
USB_2_0_EXT_TKN_PKT_
ILLEGAL_SUBPID
USB_2_0_DATA2_MDATA_
FOR_NON_ISO_DEVICE
USB_2_0_DATA_CRC_ERR_
HOST
USB_2_0_DATA_CRC_ERR_
DEVICE
USB_2_0_DATA_PID_ERR_
ISO_XFR_HOST
USB_2_0_DATA_PID_ERR_
ISO_XFR_DEVICE
837
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_EXT_TKN_PKT_
SIZE_ERR
USB_2_0_FRAME_NUMBER_
ERROR
USB_2_0_FUNCTION_
RESPONDS_FOR_ERR_PKT
USB_2_0_GET_
CONFIGURATION_
REQUEST_ERR
A GET_CONFIGURATION
request should have a value of
zero for wvalue and windex,
and a value of one for
wlength.
USB_2_0_GET_HUB_
STATUS_REQUEST_ERR
USB_2_0_GET_INTERFACE_
REQUEST_ERR
A GET_INTERFACE request
should have wvalue of zero
and wlength of one.
USB_2_0_GET_INTERFACE_
REQUEST_TO_HUB
GET_INTERFACE request
should not be issued to hub.
USB_2_0_GET_PORT_
STATUS_REQUEST_ERR
838
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_GET_STATUS_
REQUEST_DEVICE_ERR
A GET_STATUS request
with device as recipient
should have wvalue of zero,
windex of zero, and wlength
of two.
USB_2_0_GET_STATUS_
REQUEST_NON_DEVICE_
ERR
A GET_STATUS request
with nondevice as recipient
should have wvalue of zero
and wlength of two.
USB_2_0_HANDSHAKE_
PKT_IN_ISO_XFR
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_HOST
USB_2_0_HIGH_SPEED_
ENDPOINT ISSUED_ERR
USB_2_0_HOST_ISSUED_
ILLEGAL_HANDSHAKE
USB_2_0_HOST_ISSUED_
TKN_BEFORE_XFR_
COMPLETE
USB_2_0_HOST_RESPONDS_
FOR_ERR_PKT
USB_2_0_HANDSHAKE_
PKT_SIZE_ERR_DEVICE
839
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_HUB_CLASS_
REQUEST_TO_DEVICE
USB_2_0_ILLEGAL_BULK_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for bulk transfer end
points.
USB_2_0_ILLEGAL_CTRL_
XFR_WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for control transfer
end points.
USB_2_0_ILLEGAL_
HANDSHAKE_LPM_REQ
USB_2_0_ILLEGAL_
INTERRUPT_XFR_WMAX_
PACKET_SIZE
Illegal wmaxpacketsize
specified for interrupt transfer
end points.
USB_2_0_ILLEGAL_
ISOCHRONOUS_XFR_
WMAX_PACKET_SIZE
Illegal wmaxpacketsize
specified for isochronous
transfer end points.
USB_2_0_ILLEGAL_TOKEN_
ON_FULL_SPD_LINK
USB_2_0_IN_END_POINT_
RECEIVED_OUT_TKN
840
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_INT_XFR_
DATA_PID_ERR_HOST
USB_2_0_LPM_DATA0_TKN_
WITHOUT_EXT_TKN
USB_2_0_NO_ACK_
HANDSHAKE_FOR_SETUP
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
HOST
USB_2_0_NO_RESPONSE_
FOR_PKT_RECEIVED_
WITHOUT_ERR
USB_2_0_NO_STATUS_
PHASE_AFTER_SETUP_
PHASE
USB_2_0_NON_CONTROL_
ENDPOINT_ZERO
USB_2_0_INT_XFR_DATA_
PID_ERR_DEVICE
USB_2_0_INT_XFR_
SEQ_BIT_ERR_HOST
USB_2_0_INT_XFR_
SEQ_BIT_ERR_DEVICE
USB_2_0_NO_DATA1_PID_
DURING_STATUS_PHASE_
DEVICE
841
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_OUT_ENDPOINT_
RECEIVED_IN_TKN
Host should not issue IN token Host should not initiate an IN transaction
to OUT only end point.
to an OUT only end point. This check fires
if the host issues IN token to an OUT only
end point. This check is active only when
the address input matches the address
received in the tokens. This check is
enabled only if the PACKET_ISSUE_
CHECK_ENABLE parameter is 1.
USB_2_0_PING_
HANDSHAKE_ERROR
USB_2_0_PING_NEXT_
TRANSACTION_ERROR
USB_2_0_PING_NOT_
INITIATED
USB_2_0_PKT_ID_CHK_
FIELD_ERR_HOST
USB_2_0_PRE_PID_ISSUED
USB_2_0_REQUEST_
NOT_DEFINED
USB_2_0_REQUEST_
RECIPIENT_NOT_DEFINED
Recipient field of
bmrequesttype is not defined.
USB_2_0_PKT_ID_CHK_
FIELD_ERR_DEVICE
842
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_REQUEST_
TYPE_NOT_DEFINED
USB_2_0_RESET_TT_
DESCRIPTOR_REQUEST_
ERR
USB_2_0_RESPONSE_FOR_
OUT_SETUP_TOKEN
USB_2_0_SET_ADDRESS_
REQUEST_ERR
A SET_ADDRESS request
should have wlength and
windex of zero.
USB_2_0_SET_
CONFIGURATION_
REQEST_ERR
A SET_CONFIGURATION
request should have wlength
and windex of zero.
USB_2_0_SET_FEATURE_
REQUEST_DEVICE_ERR
USB_2_0_SET_FEATURE_
REQUEST_ERR
A SET_FEATURE request
should have wlength of zero.
USB_2_0_SET_HUB_
FEATURE_REQUEST_ERR
USB_2_0_SET_INTERFACE_
REQUEST_ERR
A SET_INTERFACE request
should have wlength of zero.
USB_2_0_SET_INTERFACE_
REQUEST_TO_HUB
843
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_SET_PORT_
FEATURE_REQUEST_ERR
USB_2_0_SETUP_DATA_
PID_ERR
USB_2_0_SETUP_DATA_
SIZE_ERR
USB_2_0_SETUP_TKN_TO_
NON_CTRL_ENDPOINT
USB_2_0_SOF_PKT_ISSUED_
TO_LOW_SPD_DEVICE
SOF packets are to be ignored by the lowspeed devices. However, to defeat illegal
behavior, the monitor tracks whether SOF
packets are issued to low-speed devices.
This check fires if the SOF packets are
seen on the low-speed interface. This check
is active only if the PACKET_
ISSUE_CHECK_ENABLE parameter is 1.
USB_2_0_SOF_PKTS_AT_
IRREGULAR_INTERVALS
USB_2_0_SPLIT_PKT_SIZE_
ERR
USB_2_0_SPLIT_TKN_E_
BIT_ERROR
844
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_SPLIT_TKN_S_
BIT_ERROR
USB_2_0_SSPLIT_NO_
PAYLOAD_HOST
USB_2_0_STALL_NAK_
HANDSHAKE_FOR_SETUP
USB_2_0_STALL_
RECEIVE_ERR
If STALL handshake is
received during data phase or
status phase of control
transfer, then successive
access to that control endpoint
should result in reception of
stall handshake until the
completion of the next setup
phase.
USB_2_0_STOP_TT_
REQUEST_ERR
USB_2_0_SYNC_FRAME_
REQUEST_ERR
A SYNCH_FRAME request
should have wvalue of zero
and wlength of two.
USB_2_0_SYNCH_FRAME_
REQUEST_TO_HUB
USB_2_0_TKN_CRC_ERR
USB_2_0_SSPLIT_NO_
PAYLOAD_DEVICE
845
Table 19-11. USB 2.0 ULPI Monitor USB 2.0 Checks (cont.)
Check ID
Violation
Description
USB_2_0_TKN_PKT_SIZE_
ERR
USB_2_0_TOKEN_
BEFORE_TIMEOUT
USB_2_0_WMAX_PKT_
SIZE_ERR_HOST
USB_2_0_WMAX_PKT_
SIZE_ERR_DEVICE
846
Corner Case
Description
ACK packets
Bulk transfers
Number of transfers to Bulk end points. This corner case is applicable only
when the monitor is configured to track transactions of a bulk endpoint.
This corner case gives the number of complete bulk transfers addressed to
the device with the address specified at the address input.
Number of Clear Hub Feature requests issued by the host. This statistic is
not applicable when the monitor is instantiated on the upstream port of the
function.
Description
Number of Clear Port Feature requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Number of ClearTT Buffer requests issued by the host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Control transfers
Data packets
ERR packets
Number of Get Hub Descriptor requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Number of Get Hub Status requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Number of Get Port Status requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
IN transactions
Incomplete IN transactions
847
848
Corner Case
Description
Interrupt transfers
Isochronous transfers
NAK packets
NYET packets
OUT transactions
PING packets
Number of PRE PID packets issued. This corner case is applicable only
when the monitor is instantiated on a downstream port of the hub.
Reset TT requests
Resets issued
Number of cycles a reset is issued by the host or Hub. This statistic counts
only resets initiated through SE0 signaling.
Number of Set Hub Descriptor requests issued by host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Number of Set Hub Feature requests issued by the host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Number of Set Port Feature requests issued by the host. This statistic is not
applicable when the monitor is instantiated on the upstream port of the
function.
Setup tokens
SOF packets
STALL packets
Description
Stop TT requests
Time outs
Token packets
Transactions aborted
Monitor Statistics
Table 19-13 shows the statistics maintained by the USB 2.0 monitor.
Table 19-13. USB 2.0 Monitor Statistics
Statistic
Description
Transaction count
No response count
Incomplete transactions
849
850
Appendix 20
QVL Defines
Global Defines
Type
DEFINE
Description
Function
`QVL_ASSERT_ON
`QVL_COVER_ON
`QVL_SV_
COVERGROUP_OFF
`QVL_CW_FINAL_
COVER
`QVL_MW_FINAL_
COVER_OFF
Synthesizable
Logic
`QVL_SVA_INTERFACE
X/Z Values
`QVL_XCHECK_OFF
Coverage
851
QVL Defines
Defines Common to All Assertions
DEFINE
Description
severity_level
`QVL_FATAL
`QVL_ERROR
`QVL_WARNING
Runtime Warning.
`QVL_INFO
`QVL_ASSERT
`QVL_ASSUME
`QVL_IGNORE
`QVL_COVER_ALL
`QVL_COVER_NONE,
`QVL_COVER_SANITY,
`QVL_COVER_BASIC,
`QVL_COVER_CORNER,
`QVL_COVER_STATISTIC
property_type
coverage_level
852
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