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Pulse-Mode
z1
xn
zm
Combinational
logic
y1 yr
Yr Y1
Flip-Flop
memory
Pulse Mode circuit model
Fundamental Mode
z1
xn
zm
Combinational
logic
y1 yr
Yr Y1
Delay, t
berarti klo
awalnya 00 gk
mungkin
inputnya jadi 11
Stable State
PS = present state
NS = next state
PS = NS = Stability
Oscillation
Races
Supply voltage
Temperature, etc.
Race terjadi pada saat transisi dari satu state ke next state KETIKA lebih dari satu variabel next state berubah sebagai respon pada perubahan
Input.
Races
Present State : PS (Y1Y2)
if Y1 changes
first
01
11
if Y2 changes
first
00
10
Desired Next State: NS
Types of Races
Non-Critical
Critical
Races
Present State : PS (Y1Y2)
if Y1 changes
first
01
11
if Y2 changes
first
00
Critical Race
Non-Critical Race
10
Desired Next State: NS
00
Fastest FSM
Economical
input
present
state
next
state
y1
y2
x y y x y
Y1 x , y1 , y2 x y1
x y1 x y1 y2 x y2
Y2 x , y1 , y2 y2 x y
y2 x y1
symbol.
x=0
x=1
Q0
Q0,0
Q1,0
Q1
Q2,0
Q1,0
Q2
Q2,0
Q3,1
Q3
Q0, 0
Q3,1
Intinya kalau FUNDAMENTAL MODE, INPUT HANYA bisa berubah ketika Machine dalam stable state, kalau khasus khusus INPUT yang
berubah hanya satu, maka disebut NORMAL FUNDAMENTAL MODE
Assumptions
States:
y=0=A
y=1=B
x2
y Q
SET
y
Q
CLR
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
z x1 y
S x1 y
R x2 y
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
z x1 y
S x1 y
R x2 y
x1
x2
y
S
R
z
State transition only occurs only if an input pulse occurs
Pulse do not occur simultaneously on two or more input lines, All devices
trigger on the same edge of each pulse
z x1 y
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
S x1 y
R x2 y
R
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
z
y\x1x2
00
01
11
10
R
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
y\x1x2
00
01
11
10
00
00
10
00
01
00
Y/z
y\x1x2
00
01
11
10
z
y\x1x2
00
01
11
10
0 0/0 0/0
1/0
1 1/0 0/0
1/1
Untuk mengisi K-MAP Next state Y, kita lihat karakteristik dari SR LATCH. Karakteristiknya, saat SRnya 00--> Q(t),
Saat SRnya 01--> 0, Saat SRnya 10-->1, saat SRnya 11-->d
States:
y=0=A
y=1=B
x1
x2
Inputs:
[x1,x2] = 00 = I0
[x1,x2] = 10 = I1
[x1,x2] = 01 = I2
z x1 y
y Q
SET
S x1 y
R x2 y
y
Q
CLR
Y/z
y\x1x2
10
Present
State
A/0
A/0
B/0
B/0
A/0
B/0
A/0
B/1
B/1
A/0
00
01
I0
I2
I1
Present
State
x1
x2
Exercise
x
y2
SET
Inputs:
I0 = no pulse on x
I1 = pulse on x
CLR
SET
x
Q
D2 y1 , C2 x
z xy1 y2
xy2
y1
D1 y1 , C1 xy 2
CLR
Inputs:
I0 = no pulse on x
I1 = pulse on x
x
y1
y2
D1=D2
C1
C2
z
Exercise
Karakteristik D Flip-Flop:
Nilai output Q akan sama dengan Nilai input D jika Clock1 = 1 (Negative Edge D Flip-Flop)
-->Jadi, dalam kasus ini D Flip-Flop 1 mendapatkan input not y1 (D1 = not y1), maka Q akan
menghasilkan D1 jika C1, dan menghasilkan not D1 saat C1 not
y1
SET
Y
Q
y2
CLR
SET
CLR
D1 y1 , C1 xy 2
D2 y1 , C2 x
z xy1 y2
C1=xy2
C2=x
Y1 D1C1 y1C1
y1 xy2 y1 (x y2 )
xy1 y2 xy1 y1 y2
Y 2 D2C2 y2C2
xy1 xy2
y1
y1y2\x
00
01
11
10
Y1 D1C1 y1C1
Exercise
Y 2 D2C2 y2C2
D1
C1
y1y2\x
00 1
00 0
01 1
01 0
11 0
10 0
D2
y1y2\x
D1C1
1
y1y2\x
0
0
0
1
1
1
0
0
1
1
Not x or Not y2
Not C1--> 0 1
1 1
1 0
1 0
1 1
Y1
0
00 10 10
00 0
01 10 11
01 0
11 0
11 00 01
11 1
10 0
10 00 00
10 1
C2
y1y2\x 0
y1y2\x 0
00 1
00 0
01 1
01 0
11 0
10 0
D2C2
y1y2\x
y1y2\x
Y2
0
00 10 11
00 0
01 10 11
01 1
11 0
11 00 01
11 1
10 0
10 00 01
10 0
y2
y1y2\x
00
01
11
10
0
0
1
1
0
1
0
1
1
0
y1y2\x
Not x
Not C1--> 0
1
1
1
1
1
0
0
0
0
z
y1y2\x
00
01
11
10
Exercise
Y1
y1y2\x
Y1Y2
y1y2\x
0
0
0
0
0
1
0
0
1
0
Y1 D1C1 y1C1
Y 2 D2C2 y2C2
z xy1 y2
00 0
00 00 01
Y1Y2/z
y1y2\x
01 0
01 01 11
11 1
10 1
Y2
I0
I1
00
00/0
01/0
11 11 00
01
01/0
11/0
10 10 10
11
11/0
00/1
10
10/0
10/0
Y1Y2/z
y1y2\x
00 0
01 1
y1y2\x
00
00/0
01/0
01
01/0
11/0
11 1
11
11/0
00/1
10 0
10
10/0
10/0
Y1Y2/z
y1y2\x
00
01/0
01
11/0
11
00/1
10
10/0
Exercise
y1
y2
SET
Y1Y2/z
y1y2\x
I1
A/0
B/0
B/0
D/0
C/0
C/0
D/0
A/1
I0/0
CLR
SET
I0
I0/0
CLR
I1/1
D
I0/0
I1/0
I1/0
B
I0/0
I1/0
Inti:
State tabel--> minimisasi-->state assignment--> buat persamaan output (z) dan dari
elemen memory dengan mengacu data pada state assignment sebelumnya (Pecah
state assignment tabel ini menjadi bagian-bagianya, yaitu next state dan output)-->
gambar rangkaian.. JANGAN LUPA, KITA BUAT JUGA PERSAMAAN UNTUK
CLOCK KALAU KITA MAKE FLIP-FLOP/LATCH DENGAN CLOCK!!!
Do it yourself
Alur Mendesign :
Buat state tabel,state diagram (Pahami apa yang mau kita desain)--> Klo mungkin, minimisasi
tabel --> Pilih state assignmentnya, lalu buat tabel transisi output--> Pilih elemen memory yang
digunakan--> Tentukan persamaan outputnya (z) dan pers elemen memory--> gambar rangkaiannya.
Persamaan untuk elemen memory bisa
didapat dari hubungan antara present state
dengan Next statenya
Step 1
Dari soal saja sudah terlihat bahwa output z akan sama dengan 1 jika
BERTEPATAN dengan input terakhir (x2) dengan sequence input
x1-x2-x2, maka dia bergantung input dan present state (Mealy
Machine)--> Ingat kembali karakteristik mealy machine (Cara
menggambar state diagram dan state tabelnya).
States
A : indicates that the last input was x1
B : indicates that the sequence x1-x2 occurs
C : indicates that the sequence x1-x2-x2 occurs
Present
State
x1
x2
A/0
B/0
A/0
C/1
A/0
C/0
x1/0
x1/0
A
x1/0
C
x2/0
x2/0
x2/1
Step 2 and 3
x1
x2
00
00/0
01/0
01
00/0
10/1
10
00/0
10/0
Step 4 and 5
Y1
C1
y1y2
Use T-FF: T = 1
Y1Y2/z
y1y2
x1
x2
00
00/0
01/0
01
00/0
10/1
10
00/0
10/0
Y2
x1 x2
y1y2
x1 x2
00
00
01
01
11
11
10
10
y1y2
x1 x2
C2
y1y2
x1 x2
00
00
x1 x2
01
01
00
11
11
01
10
10
11
C1 x1 y1 x2 y2
10
C2 x1 y2 x2 y1
z
y1y2
Dari nilai next state Y1, kita lihat untuk present state y1.
Analisis untuk input x2, saat y1=0, dan Y1nya 0/Q(t)-->
T=0, y1=0 dan Y1nya 1-->T=1, y1=1 dan Y1nya 1/(t)-->
T=0
z x2 y 2
Step 6
C1 x1 y1 x2 y2
C2 x1 y2 x2 y1
z x2 y 2
y1
x1
Q
Q
z
1
x2
Q
Q
y2
Do it yourself
Use SR Latch
Step 1
Present
State
x1
x2
x3
x1
x1
A/0
B/0
x3
x2
x1
x2
x2
D/1
x1,x3
C/0
x3
Step 2 and 3
x1
x2
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
Step 4
Use SR Latch
Y1
y1y2
Untuk S1
Y1Y2
y1 Y1
0--> 0 disini yang perlu
kita lihat adalah Y1 dan S R Q (t+1)
Q(t)
y1 pada tabel Y1 . Karena 0 0
output 0, dan y1 0, maka 0 1
0
pada tabel karakteristik
1 0
1
SR, kemungkinanya
1 1
d
adalah Q(t) dan 0, berarti
dua2nya itu Snya 0. PADA Gunakanlah Gated
tabel karakteristik SR, lihat SR Latch
saja Q(t+1) biar tidak
bingung
S1
R1
x1 x2 x3
y1y2
x1 x2 x3
y1y2
y1y2
x1
x2
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
x 1 x2 x3
00
00
00
S1 x2 y1 y2
01
01
01
11
11
11
R1 x1 y2 x2 y1
10
10
10
Y2
S2
y1y2
x1 x2 x3
R2
y1y2
x1 x2 x3
y1y2
y1
0
0
1
1
Y1
0
1
0
1
S1
0
1
0
d
R1
d
0
1
0
x 1 x2 x3
00
00
00
S 2 x1 y1
01
01
01
11
11
11
R1 x2 y1 x3
10
10
10
Step 5
Y1Y2
y1y2
x1
x2
x3
00
01 00 00
01
01 11 00
11
01 00 10
10
10 00 10
z y1 y 2
Membuat persamaan z disini (Moore
machine) dengan melihat kombinasi y1y2
yang membuat z=1--> karena Moore itu
OUTPUT -nya hanya bergantung dari
present state (y1y2).
Step 6
S1 x2 y1 y2
S 2 x1 y1
R1 x1 y2 x2 y1
R1 x2 y1 x3
z y1 y 2
SET
CLR
x1
x2
S
x3
SET
CLR
Assumptions
z1
xn
zm
Combinational
logic
z g(x , y )
t
Y h( x , y )
t
y1 yr
Yr Y1
Delay, t
t t
Example
x1
Set of equations
z t g ( x1t , x2t , y t ) x1t x2t x2t y t
x2
Y t zt
y
t t
Delay
dt
x1
x2
y
z=Y
t1
t2
t3 t4
t5 t6 t7
Unstable at t3 (y Y)
t5 jga unstable
z tdk ada delay
t8
t9 t10
t11
t12
Tabular Representation
Excitation Table
t t
y\x1x2
00
01
11
10
0 0/0
0/0
1/1
0/0
1 1/1
0/0
1/1
1/1
Tabular Representation
Flow Table
00
01
11
10
0 0/0 0/0
1/1
0/0
1 1/1 0/0
1/1
1/1
y\x1x2
00
01
11
10
a a/0
a/0 b/1
a/0
b b/1
Tabular Representation
perhtikan dr t3 ke t4
perubahan dr unstable
ke stable-> gnti state
Flow Table
y\x1x2
00
t1
a
01
t6
t7
a/0
a/0
t5
b/1
a/0
11
10
t3
t2
b/1
a/0
t4
b/1
b/1
x1
x2
y
z=Y
t1
t2
t3 t4
t5 t6 t7
t8
t9 t10
t11
t12
Example
Step 1
Y1 x y2
Y2
Y2 xy1
Y1
z x y1
Delay
dt
y1
y2
Delay
dt
Example
Step 2
Y1
Y1 x y2
Y2
y1y2\x
y1y2\x
y1y2\x
00
00
00
01
01
01
11
11
11
10
10
10
Y2 xy1
z x y1
Y1 Y2/z
Y1 Y2/z
Y1 Y2/z
y1y2\x
y1y2\x
y1y2\x
00
10/0
01/0
3/0
2/0
3/0
2/0
01
00/0
01/0
1/0
2/0
1/0
2/0
11
00/1
00/0
1/1
1/0
3/1
1/0
10
10/1
00/0
3/1
1/0
1/1
1/0
Example
Timing Diagram
Y1 Y2/z
y1y2\x
00
10/0
01/0
01
00/0
01/0
11
00/1
00/0
10
10/1
00/0
Y1 Y2/z
y1y2\x
y2
00
10/0
01/0
Y1
01
00/0
01/0
11
00/1
00/0
10
10/1
00/0
Y2
z
dt
Example
Step 1
Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.
x1
z1
x2
z2
y1
Delay
dt
Y1
Y1 ( x2 ( x1 y1 )) ( x2 x1 y1 )
x2 ( x1 y1 ) x1 x2 x2 y1
z1 x1 y1
z 2 y1
Example
Step 2 through 5
Let Q0 be state when y1 = 0 and Q1 be state when y1 = 1.
Y1
x1
z1
y1\x1 x2 00 01 11 10
x2
z2
Y1
Input x1,x2
Q0
Q1
01
y1\x1 x2 00 01 11 10
Present
State
00
z1
Delay
dt
y1
11
z2
10
z1z2
y1\x1 x2 00 01 11 10
0
Do it Yourself
x1
x1
R
S
x1
x2
Q1
z
x1
x2
x1
SET
CLR
SET
CLR
x1
Q
Q
Q2
S1 x1Q2
R1 x1Q2
S 2 x1 x2Q1
R1 x1 x2 x1Q1
Present State
(Q1Q2)
00
Excitation
(S1R1,S2R2)
Output
(z)
01
10
11
00
01
10
11
00 00,01
00,01
10,00
10,00
01 00,01
00,01
01,00
01,00
10 00,01
00,10
10,00
10,00
11 00,01
00,10
01,00
01,00
Next State
(Q+1Q+2)
Output
(z)
00
01
10
11
00
01
10
11
00
00
00
10
10
01
00
00
01
01
10
10
11
10
10
11
10
11
01
01
Next State
(Q+1Q+2)
Output
(z)
00
01
10
11
00
01
10
11
00 A
01 B
10 C
11 D
Next State
(Q+1Q+2)
Output
(z)
00
01
10
11
00
01
10
11
Excitation table
Transition Table
State Table
Flow Table
Example
Whenever x1 = 0, z = 0.
The first change to input x2 that occurs while x1 = 1 must cause the
output to become z = 1.
A z = 1 output must not change to z = 0 until x1 = 0.
Example
x1
x2
z
Example
Next State, Output
Present
State
00
a,0
01
10
11
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
c,0
At state (a),
b,0
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
c
d
c,0
d,0
At state (b),
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
At state (c),
d,0
e,1
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
e
f
At state (d),
e,1
f,1
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
-,-
b,-
f,-
e,1
f,1
At state (e),
Example
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
d,-
a,-
-,-
c,0
e,-
-,-
b,-
f,-
d,0
-,-
b,-
f,-
e,1
a,-
-,-
f,1
e,-
At state (f),
Example
Implication chart
Present
State
00
01
10
11
a,0
b,-
c,-
a,-
b,0
a,-
-,-
-,-
d,-
cf
-,-
c,0
e,-
cf
cf
de
de cf
-,-
b,-
f,-
d,0
-,-
b,-
f,-
e,1
cf
de
a,-
-,-
f,1
e,-
de
de
Implication chart
{e,f}
{e,f}
cf
de
{e,f}
{e,f}, {b,d}
cf
cf
de
de cf
{e,f}, {b,d},{a,b},{a,c}
cf
de
de
Implication chart
{e,f}
{e,f}
{a,b}
{e,f}
{a,c}
{e,f}, {b,d}
{b,d}
{e,f}, {b,d},{a,b},{a,c}
{e,f}
x
x
*
x
*
x
Present
State
00
01
10
11
a,0
b,-
c,-
-,-
a,-
b,0
-,-
a,-
-,-
-,-
e
f
Present
State
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
d,-
{b,d} :
,-
,0
,-
,0
c,0
e,-
{e,f} :
,-
,-
,1
,1
b,-
f,-
d,0
-,-
b,-
f,-
e,1
a,-
-,-
f,1
e,-
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
y1\y2
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
: 00
: 11
: 10
Next State
00
01
00,0
10
11
00,0
11,0
11,0
10,1
10,1
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
: 00
00,0
: 11
10,-
: 10
00,-
01
10
11
00,0
11,0
Input 00:
Total State (00,11) (00,00)
Create a cycle
(00,11) (00,10) (00,00)
11,0
10,1
10,1
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
: 00
00,0
10,-
00,0
: 11
10,-
11,0
: 10
00,-
11,-
11
Input 01:
Total State (01,00) (01,11)
Create a cycle
(01,00) (01,10) (01,11)
11,0
10,1
10,1
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
10,-
00,0
: 11
10,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
Input 10:
Total State (10,11) (10,10)
No problem here!
Only 1 bit need to change
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
10,-
00,0
10,-
: 11
10,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
Input 11:
Total State (11,00) (11,10)
No problem here!
Only 1 bit need to change
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
: 00
00,0
: 11
01,-
: 10
00,-
01
00,-
01
10
11
00,0
11,0
11,0
10,1
10,1
Input 00:
Total State (00,11) (00,00)
Create a cycle
(00,11) (00,01) (00,00)
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
01,-
00,0
10,-
: 11
01,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
01
00,-
11,-
Input 01:
Total State (01,00) (01,11)
Create a cycle
(01,00) (01,01) (01,00)
All other inputs are the same as
before!
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
: 00
00,0
: 11
00,-
: 10
00,-
01
00,-
01
10
11
00,0
11,0
11,0
10,1
10,1
Input 00:
Total State (00,11) (00,00)
Non critical race
(00,11) (00,01) (00,00)
(00,11) (00,10) (00,00)
Next State
00
01
10
11
{a,c} :
,0
,-
,0
,-
{b,d} :
,-
,0
,-
,0
{e,f} :
,-
,-
,1
,1
Assignment
: 00
: 11
: 10
Present
State
Next State
00
01
10
11
: 00
00,0
11,-
00,0
10,-
: 11
00,-
11,0
10,-
11,0
: 10
00,-
11,-
10,1
10,1
01
00,-
11,-
Input 01:
Total State (01,00) (01,11)
Non critical race
(01,00) (01,01) (01,11)
(01,00) (01,10) (01,11)
All other input are the same!
Next State
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
Present
State
Next State
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
Next State
Y1Y2,z
y1y2\x1x2
00 01 11 10
00
01
10
11
00
: 00
00,0
10,0
00,0
10,-
01
: 11
10,0
11,0
10,-
11,0
11
: 10
00,0
11,0
10,1
10,1
10
Y1
Y2
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
Y1 x2 y2 x1 y1
Y2 x2 y2 x1 x2 y1
z x1 y1 y2
dibuat dont
care biar bsa
disederhanaka
n
z
x1
Y1
z x1 y1 y2
x2
Y2
y2
Delay
dt
y1
Delay
dt
Y2 x2 y2 x1 x2 y1
z x1 y1 y2
SR Excitation Property
00 SR 0d
01 SR 10
10 SR 01
11 SR d0
Next State
Y1Y2,z
Present
State
y1y2
00
01
10
11
: 00
00,0
10,0
00,0
10,-
: 11
10,0
11,0
10,-
11,0
: 10
00,0
11,0
10,1
10,1
Present
State
y1y2
Next State
(S1R1,S2R2),z
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1
Present
State
y1y2
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1
S1
R1
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
S1 x2
R1 x1 x2 y2
Present
State
y1y2
00
01
10
11
: 00
(0d,0d),0
(10,0d),0
(0d,0d),0
(10,0d),d
: 11
(d0,01),0
(d0,d0),0
(d0,01),d
(d0,d0),0
: 10
(01,0d),0
(d0,10),0
(d0,0d),1
(d0,0d),1
S2
R2
y1y2\x1x2
00 01 11 10
y1y2\x1x2
00 01 11 10
00
00
01
01
11
11
10
10
S 2 x1 x2 y1
R2 x2
x1
x2
z
S
SET
CLR
SET
CLR
Do it yourself
Design a two input (x1, x2) and two output (z1,z2) circuit
where,
00
01
11
10
Present
State
a/00
b/--
-/--
c/--
a/--
b/00
d/--
-/--
a/--
-/--
e/--
-/--
f/--
-/--
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
c/00
a/00
-/--
e/0-
c/00
d/10
g/--
-/--
f/10
d/10
g/10
h/--
e/01
i/--
-/--
h/01
e/01
i/01
a/--
f/10
d/--
-/--
a/-0
f/10
d/10
-/--
a/--
-/--
d/--
g/10
a/-0
-/--
d/10
g/10
a/--
h/01
e/--
-/--
a/0-
h/01
e/01
-/--
a/--
-/--
e/--
i/01
a/0-
-/--
e/01
i/01
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
a/00
-/--
e/0-
c/00
-/--
f/10
d/10
g/10
-/--
h/01
e/01
i/01
a/-0
f/10
d/10
-/--
a/-0
-/--
d/10
g/10
a/0-
h/01
e/01
-/--
a/0-
-/--
e/01
i/01
de
de
d
e
{h,i}
{h,i}
{h,i}{f,g}
{e,h,i}{f,g}
{e,h,i}{d,f,g}
{e,h,i}{d,f,g}{c,h}
{e,h,i}{d,f,g}{c,h}{b,g}
{e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}
h
ab ac tidak bsa
digabung pada
asynchronous,
kurang bc
kaya distrukdis
{h,i}
{h,i}
{h,i}{f,g}
{e,h,i}{f,g}
{e,h,i}{d,f,g}
{e,h,i}{d,f,g}{c,h}
{e,h,i}{d,f,g}{c,h}{b,g}
{e,h,i}{d,f,g}{c,h}{b,g}{a,b}{a,c}
i
b
h
c
g
d
f
2 states
3 states
4
states
Present
State
{a,b}
{d,f,g}
{a,c}
{e,h,i}
Present
State
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
01
11
10
a/00 b/00
-/--
c/00
a/00 b/00
d/-0
-/--
a/00
-/--
e/0-
c/00
-/--
f/10
d/10
g/10
-/--
h/01
e/01
i/01
a/-0
f/10
d/10
-/--
a/-0
-/--
d/10
g/10
a/0-
h/01
e/01
-/--
a/0-
-/--
e/01
i/01
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
Present
State
Assignment:
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
00
01
10
11
00
01
11
10
/00
/00
/-0
/00
/-0
/10
/10
/10
/00
/00
/0-
/00
/0-
/01
/01
/01
PS
(y1 y2)
00
01
00
00/00 00/00
01
00/-0
10
10/00 00/00
11
10/0-
11
10
01/-0
10/00
10/00
Assignment:
00
01
10
11
00
01
11
10
00
01
11
10
00
00
00
01
10
00
00
-0
00
01
00
01
01
01
-0
10
10
10
10
10
00
11
10
00
00
0-
00
11
10
11
11
11
0-
01
01
01
pd asynchronous pakenya sr
synchron pk d flipflop
y1y2
x1x2
00
01
11
10
00
01
11
10
y1y2
00
01
11
10
00
01
Y1 y1 y2 x1 y1 x2 y1 x1 x2 y2
11
Y2 x1 x2 x1 y2 x2 y2
10
Y2
Y1
x1x2
y1y2
x1x2
00
01
11
10
00
01
11
10
z1
y1y2
00
01
11
10
00
01
z1 y1 y2
11
z2 y1 y2
10
z2