Short notes for the questions

1. Familiarization with VLSI Process:

Growing the oxide SiO2 is not the same as Depositing the oxide SiO2.
1(a)(i): The processing step which is used to Grow" an oxide on a Si wafer :
Thermal oxidation .It is used to form SiO2 by reacting the Si substrate atoms with
oxygen or steam Si substrate atoms will be consumed using this process.
(ii): The processing step which is used to Deposit" an oxide on a Si wafer :
Chemical Wafer Deposition (CVD) or Sputtering deposition methods i.e. external
source. In this Processing ,Si substrate atoms will not be consumed to form the
SiO2.
(b)(i) Photo Mask: The glass plate with chromium patterns used in optical
lithography. Chrome regions will block out the light and will not expose the photo
resist .
(ii)Etching Mask: Patterns of materials on the wafer which protects the regions
underneath from being etched. Example: photo resists patterns on an oxide layer.
(iii)Oxidation Mask: Patterns of materials on the wafer which protects the regions
underneath from being oxidized during a thermal oxidation step. Example: Si3N4
patterns on top of Si wafer.
(iv)Implantation Mask: Patterns of materials on the wafer with sufficient physical
thickness to block the penetration of ions during the implantation step. Example:
Thick photo resist or thick oxide patterns on top of wafer.
(c) (i)Process flow sequence of a simple MOSFET using aluminum as the gate
material is below (side view and top view) :

In Lithography, There are total 4 steps are used in this Al-gate process as given
below:
Step1: Pattern thick oxide to define the source/drain area.
Step2: Pattern gate area.
Step3: Pattern contact holes for Al contact to source/drain
Step4: Pattern Al interconnects.
(ii): The photo resist has been stripped before the two step diffusion process which
is used to form the source and drain regions because the source/drain diffusion step
is at ~900

and photo resist cant withstand processing temperature higher

than~180

. The photo resist patterns will be distorted by reflow at moderate

temperature and the resist material will be carbonized at high temperature.

2. Oxidation of Silicon:
2(a): According to the Deal Grove model, oxidation Kinetics starts out Linear and
become parabolic as the oxidation proceeds. This Transition from Linear to
parabolic growth is a gradual in nature and therefore there is no specific thickness
at which an abrupt transition takes place.
1 or when

Taking the values for dry

= 0.619 x

This equation is plotted below along with the

exp

2(b): The transition from linear to parabolic rates occurs when

1 or

When

. In the standard Deal-Grove model, both b and

are

linearly proportional to pressure. This is a consequence of assuming that Henrys

law holds during the oxidant absorption into the oxide and that only a molecular
species is involved in the transport through the oxide and reaction at the Si / SiO2
interface. Thus, a change in pressure will not affect the thickness at which the
transition occurs.
2(c) :

[A] Side: 1100 , 60min in O2 0.11

10 min in steam at 1000

SiO2 .It is equivalent to

[B] Side: 1000 , 30min in steam 0.2

SiO2 grown

Therefore, 1000 , (30+10) min, in steam 0.25

SiO2

grown.

2(d)(i)Given: oxidation process with a linear oxidation constant B/A

=1.2 m=hour and a parabolic oxidation constant B = 0.3
=hour.
So, A=0.25
From the Grove model, we have

= B(t+

Therefore,

Or

=B

From 0.24 =

and 0.133 =

we get

A=0.25

,B/A =1.2 m=hour and B = 0.3

(ii) A=0.25

,B/A =1.2 m=hour and B = 0.3

=hour.
=hour.

From the Deal Grove model, we have

Growth data:
+

= B(t+

[1]

+ 2Ax = B(4+

[2]

Using 2 x [2] [1] gives

X=

+ Ax 3B =0

= 0.508

We then solve for . Using 4 x [1] [2] gives 2Ax =3B

Or
=0.28 hours
From

= B(

, we obtain

= 0.19

2(e)(a)(1):
for 900

+
,

= B(t+

: B = 5600( )/min

(B/A ) = 2( )/min
hence, A= 2800
Therefore , for

= 1000( ),

t=680min

(2) let

be the oxide grown during the steam oxidation step such

that the final oxide thickness

= 5000( ) after dry oxidation

Therefore,
(

+ 2800.(5000) = 5600(680)+

=4700

(3): oxide grown in window area = 1000

New oxide grown in field oxide area = 300

Si step height = (1000-300)/2.16 = 324

3. CVD Deposition :
3(1): At mass transfer limited regime, growth rate =
cm = 0.378

3(2):

So T =

or, 2 x

= 6.3 X

exp

= 0.63

= 1473K =1200

Growth rate (T=1200 ) =

= 3.15 x

cm = 0.189

3(3): At the surface reaction limited regime,

Ln( growth rate ) = const -

= const -

So the slope of Ln( growth rate ) vs. 1000/T is

For the SiH4 curve, the slope (with ln(growth rate)) in the surface
reaction limited regime is
So

= -17.33

= 7.53 x 1000 x k = 1.49eV

4.ETCHING:
cross-sections of the structure with dimension labeled after
etching for
(a) 1 min:

(b) 2min:

(c) 3 min:

Time needed to etch the SiO2 layer = distance to be etched, d

Etch rate.The Sio2 structure on the right has a bigger volume than

the structure on the left. So we are considering the time to etch

the right one only.
d=

= 7.04

So time needed for etching = 7.04/2 =3.52 mins.

4(b)(i)

Metal pitch =

=1

or

X = 0.25
0.5
From eqn.

= x +2 (1- )

0.5 = 0.25 + (0.5)(1- )

= 0.5

The degree of anisotropy:

=0.75

(this could not be achieved

by wet etching).
(ii) If the wet etching is used , we assume the degree of
anisotropy is equal to 0.
Again ,

= x +2 (1- ) =0.25 + (0.5)(1-0)=1.25

The pitch =2x =2.5

5. Ion-Implementation:
5(a):We have an equation relating concentration to peak doping :
C(x) =

exp-

2ln(100) =
Alternatively , we can use the masking formula

+ 3.0

Thus , the oxide Silicon interface lies approximately 3

away

from the peak of the implanted profile. We know the energy of the
phosphorus implant must be at least 30keV to penetrate 50nm.

From a graph of the range of phosphorus we get the value for

= 0.14
Q=

hence the dose can be calculated as :

= 3.5 x

5(b)(i) An NMOS transistor has an n- type source and drain and therefore it needs
an n-type channel to connect the source and the drain when producing drive
current. This requires the p-type substrate ,when the MOSFET is in the off state , it
isolates the source and drain ,to be inverted during the on state when the MOSFET
provides drive current. Under normal operation, a gate positive voltage is applied,
when the switching on the device , producing an inversion layer. More positive
charge in the channel will make the device harder to switch on and shift the
threshold from V to (V+1) Volt , so the channel charge should be boron or indium.
(ii) If the gate oxide is 10nm, the oxide capacitance per unit area is
=

And the

= 345.3nF

shift is given by

1.0 =
Q= 2.16 x