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Data Sheet
FN9251.1
Features
Precision single-phase CORE voltage regulator
- 0.5% system accuracy over temperature
- Enhanced load line accuracy
Thermal monitor
User programmable switching frequency
Differential remote voltage sensing at CPU die
Overvoltage, undervoltage, and overcurrent protection
Pb-free plus anneal available (RoHS compliant)
Ordering Information
PART NUMBER
(NOTE)
PART
MARKING
TEMP
RANGE
(C)
PACKAGE PKG.
(Pb-FREE) DWG. #
ISL6261CRZ
ISL6261CRZ
L40.6x6
ISL6261CRZ-T
ISL6261CRZ
ISL6261CR7Z
L48.7x7
ISL6261IRZ
L40.6x6
ISL6261IRZ-T
ISL6261IRZ
ISL6261IR7Z
ISL6261IR7Z
ISL6261IR7Z-T
ISL6261IR7Z
L48.7x7
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2006. All Rights Reserved. R3 Technology is a trademark of Intersil Americas Inc.
All other trademarks mentioned are the property of their respective owners.
ISL6261
Pinouts
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
ISL6261
(40 LD QFN)
40
39
38
37
36
35
34
33
32
31
FDE
30 VID2
PGD_IN
29 VID1
RBIAS
28 VID0
VR_TT#
27 VCCP
NTC
SOFT
OCSET
24 PHASE
VW
23 UGATE
COMP
22 BOOT
FB
10
21 NC
26 LGATE
DROOP
17
18
19
20
VDD
RTN
16
VSS
VSEN
15
VIN
14
25 VSSP
VSUM
13
VO
12
DFB
11
VDIFF
GND PAD
(BOTTOM)
3V3
CLK_EN#
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
VID2
VID1
VID0
ISL6261
(48 LD QFN)
48
47
46
45
44
43
42
41
40
39
38
37
PGOOD
36 NC
FDE
35 NC
PGD_IN
34 NC
RBIAS
33 NC
VR_TT#
32 NC
NTC
SOFT
OCSET
29 VSSP
VW
28 PHASE
COMP 10
27 UGATE
31 VCCP
GND PAD
(BOTTOM)
30 LGATE
13
14
15
16
17
18
19
20
21
22
23
24
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
NC
NC
25 NC
RTN
NC 12
VSEN
26 BOOT
VDIFF
FB 11
FN9251.1
September 27, 2006
ISL6261
Absolute Maximum Ratings
Thermal Information
JA (C/W)
JC (C/W)
CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with direct attach features. See Tech
Brief TB379.
2. For JC, the case temp location is the center of the exposed metal pad on the package underside.
Electrical Specifications
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
VR_ON = 3.3V
3.1
3.6
mA
VR_ON = 0V
IVDD
I3V3
IVIN
PORr
VDD Rising
4.35
4.5
PORf
VDD Falling
3.85
4.1
-0.5
0.5
VID = 0.5-0.7375V
-8
mV
VID = 0.3-0.4875V
-15
15
mV
RRBIAS = 147k
1.45
1.47
1.49
1.188
1.2
1.212
%Error
(Vcc_core)
RBIAS Voltage
RRBIAS
Boot Voltage
VBOOT
VCC_CORE
(max)
VID = [0000000]
1.5
VCC_CORE
(min)
VID = [1100000]
0.3
VID = [1111111]
0.0
RFSET = 7k,
Vcomp = 2V
333
kHz
200
500
kHz
0.3
mV
dB
fSW
Adjustment Range
AMPLIFIERS
Droop Amplifier Offset
-0.3
AV0
90
FN9251.1
September 27, 2006
ISL6261
Electrical Specifications
PARAMETER
SYMBOL
GBW
MIN
TYP
MAX
UNITS
CL = 20pF
18
MHz
SR
CL = 20pF
5.0
V/s
IIN(FB)
10
150
nA
Soft-start Current
ISS
-46
-41
-36
IGV
|SOFT - REF|>100mV
175
200
225
IC4
DPRSLPVR = 3.3V
-46
-41
-36
IC4EA
DPRSLPVR = 3.3V
36
41
46
IC4EB
DPRSLPVR = 0V
175
200
225
TEST CONDITIONS
SOFT-START CURRENT
RSRC(UGATE)
1.5
ISRC(UGATE)
VUGATE_PHASE = 2.5V
RSNK(UGATE)
1.5
ISNK(UGATE)
VUGATE_PHASE = 2.5V
RSRC(LGATE)
1.5
ISRC(LGATE)
VLGATE = 2.5V
RSNK(LGATE)
0.5
0.9
ISNK(LGATE)
VLGATE = 2.5V
RP(UGATE)
1.1
tPDHU
20
30
44
ns
tPDHL
15
30
ns
0.43
0.58
0.67
BOOTSTRAP DIODE
Forward Voltage
Leakage
VR = 16V
VOL
IPGOOD = 4mA
0.11
0.4
IOH
PGOOD = 3.3V
-1
PGOOD Delay
tpgd
5.5
6.8
8.1
ms
Overvoltage Threshold
OVH
160
200
240
mV
OVHS
1.675
1.7
1.725
10
10.2
3.5
mV
I(Rbias) = 10A
9.8
OC Threshold Offset
-3.5
-360
-300
-240
mV
Undervoltage Threshold
(VDIFF-SOFT)
UVf
LOGIC THRESHOLDS
VR_ON, DPRSLPVR and PGD_IN
Input Low
VIL(3.3V)
VIH(3.3V)
2.3
FN9251.1
September 27, 2006
ISL6261
Electrical Specifications
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
IIL
-1
IIH
IIL_DPRSLP
-1
IIH_DPRSLP
0.45
TEST CONDITIONS
VIL(1.0V)
0.3
VIH(1.0V)
0.7
IIL
-1
IIH
0.45
53
60
67
1.17
1.2
1.25
2.9
3.1
0.18
0.4
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
Over-temperature Threshold
V(NTC) falling
RTT
I = 20mA
VOH
VOL
ICLK_EN# = 4mA
NOTES:
3. Guaranteed by characterization.
4. Guaranteed by design.
tPDHU
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tPDHL
FN9251.1
September 27, 2006
ISL6261
PGOOD
3V3
CLK_EN
DPRSTP#
DPRSLPVR
VR_ON
VID6
VID5
VID4
VID3
40
39
38
37
36
35
34
33
32
31
FDE
30 VID2
PGD_IN
29 VID1
RBIAS
28 VID0
VR_TT#
27 VCCP
NTC
SOFT
OCSET
24 PHASE
VW
23 UGATE
COMP
22 BOOT
FB
10
21 NC
26 LGATE
15
16
VSEN
RTN
DROOP
DFB
VO
17
18
19
20
VDD
14
VSS
13
VIN
12
25 VSSP
VSUM
11
VDIFF
GND PAD
(BOTTOM)
FDE
VW
COMP
The output of the error amplifier.
PGD_IN
Digital Input. Suggest connecting to MCH_PWRGD, which
indicates that VCC_MCH voltage is within regulation.
FB
The inverting input of the error amplifier.
RBIAS
VDIFF
VR_TT#
VSEN
NTC
DROOP
SOFT
A capacitor from this pin to GND pin sets the maximum slew
rate of the output voltage. The SOFT pin is the non-inverting
input of the error amplifier.
RTN
DFB
The inverting input of the droop amplifier.
VO
OCSET
Overcurrent set input. A resistor from this pin to VO sets
DROOP voltage limit for OC trip. A 10A current source is
connected internally to this pin.
FN9251.1
September 27, 2006
ISL6261
VSUM
NC
VIN
VID input with VID0 as the least significant bit (LSB) and
VID6 as the most significant bit (MSB).
VSS
VR_ON
VDD
DPRSLPVR
BOOT
Upper gate driver supply voltage. An internal bootstrap diode
is connected to the VCCP pin.
DPRSTP#
UGATE
The upper-side MOSFET gate signal.
PHASE
The phase node. This pin should connect to the source of
upper MOSFET.
CLK_EN#
VSSP
Digital output for system PLL clock. Goes active 20s after
PGD_IN is active and Vcore is within 10% of boot voltage.
3V3
LGATE
PGOOD
VCCP
FN9251.1
September 27, 2006
DROOP
DFB
VSUM
OCSET
VID6
VID5
VID4
VID3
VID2
VID1
VID0
DAC
VO VSEN RTN
VO
10uA
VR_ON
DROOP
RBIAS
DPRSLPVR DPRSTP#
VO
SOFT
VDIFF SOFT FB
OC
MODE CONTROL
FDE
CLK_EN#
PGOOD
3V3
PGOOD
E/A
COMP
VIN VSOFT
VW
VW
MODULATOR
OC
FLT
FLT
60uA
VIN
VIN
DRIVER
LOGIC
VCCP
1.22V
GND
VSS
PGD_IN
VCCP
VDD
VCCP
VCCP
VSSP
LGATE
PHASE
UGATE
BOOT
VR_TT#
NTC
ISL6261
FN9251.1
September 27, 2006
ISL6261
Simplified Application Circuit for DCR Current Sensing
V+5
V+3.3
Vin
R4
C4
R5
3V3
VDD VCCP
RBIAS
VIN
R6
C8
NTC
C5
UGATE
SOFT
BOOT
Lo
C6
VR_TT#
VR_TT#
PHASE
Vo
VIDs
VID<0:6>
Co
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PGD_IN
MCH_PWRGD
VSSP
CLK_EN#
CLK_ENABLE#
VR_ON
VR_ON
R8
VSUM
PGOOD
IMVP6_PWRGD
VCC-SENSE
VSEN
VSS-SENSE
RTN
R7
C7
C3
C9
R11
C10
DFB
COMP
R12
FB
C1
VDIFF
R1
R10
OCSET
C2
R3
NTC
Network
VO
ISL6261
VW
R2
R9
DROOP
VSS
FN9251.1
September 27, 2006
ISL6261
Simplified Application Circuit for Resistive Current Sensing
V+5
V+3.3
Vin
R4
C4
R5
3V3
VDD VCCP
RBIAS
VIN
R6
C8
NTC
C5
UGATE
SOFT
BOOT
Lo
C6
VR_TT#
VR_TT#
R sen
PHASE
VIDs
VID<0:6>
Vo
Co
DPRSTP#
DPRSTP#
DPRSLPVR
DPRSLPVR
LGATE
FDE
PGD_IN
MCH_PWRGD
VSSP
CLK_EN#
CLK_ENABLE#
VR_ON
VR_ON
IMVP6_PWRGD
PGOOD
VCC-SENSE
R8
VSUM
C9
VSEN
VSS-SENSE
R7
C7
C3
RTN
VO
ISL6261
OCSET
C2
R2
C10
DFB
COMP
R12
FB
C1
R3
VDIFF
R1
R10
R11
VW
DROOP
VSS
10
FN9251.1
September 27, 2006
ISL6261
Theory of Operation
The ISL6261 is a single-phase regulator implementing Intel
IMVP-6 protocol and includes an integrated gate driver for
reduced system cost and board area. The ISL6261 IMVP-6
solution provides optimum steady state and transient
performance for microprocessor core voltage regulation
applications up to 25A. Implementation of diode emulation
mode (DEM) operation further enhances system efficiency.
VDD
VR_ON
100us
Start-up Timing
With the controllers VDD pin voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. In approximately
100s, SOFT and VO start ramping to the boot voltage of
1.2V. At startup, the regulator always operates in continuous
current mode (CCM), regardless of the control signals.
During this interval, the SOFT cap is charged by a 41A
current source. If the SOFT capacitor is 20nF, the SOFT
ramp will be 2mV/s for a soft-start time of 600s. Once VO
is within 10% of the boot voltage and PGD_IN is HIGH for six
PWM cycles (20s for 300kHz switching frequency),
CLK_EN# is pulled LOW, and the SOFT cap is
charged/discharged by approximate 200A and VO slews at
10mV/s to the voltage set by the VID pins. In approximately
7ms, PGOOD is asserted HIGH. Figure 4 shows typical
startup timing.
PGD_IN Latch
It should be noted that PGD_IN going low will cause the
converter to latch off. Toggling PGD_IN wont clear the latch.
Toggling VR_ON will clear it. This feature allows the
converter to respond to other system voltage outages
immediately.
11
2mV/us Vboot
SOFT &VO
~20us
R3
10mV/us
PGD_IN
CLK_EN#
~7ms
IMVP-VI PGOOD
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
Static Operation
After the startup sequence, the output voltage will be
regulated to the value set by the VID inputs per Table 1,
which is presented in the lntel IMVP-6 specification. The
ISL6261 regulates the output voltage with 0.5% accuracy
over the range of 0.7V to 1.5V.
A true differential amplifier remotely senses the core voltage
to precisely control the voltage at the microprocessor die.
VSEN and RTN pins are the inputs to the differential
amplifier.
As the load current increases from zero, the output voltage
droops from the VID value proportionally to achieve the
IMVP-6 load line. The ISL6261 can sense the inductor
current through the intrinsic series resistance of the
inductors, as shown in Figure 2, or through a precise resistor
in series with the inductor, as shown in Figure 3. The
inductor current information is fed to the VSUM pin, which is
the non-inverting input to the droop amplifier. The DROOP
pin is the output of the droop amplifier, and DROOP-VO
voltage is a high-bandwidth analog representation of the
inductor current. This voltage is used as an input to a
differential amplifier to achieve the IMVP-6 load line, and
also as the input to the overcurrent protection circuit.
When using inductor DCR current sensing, an NTC
thermistor is used to compensate the positive temperature
coefficient of the copper winding resistance to maintain the
load-line accuracy.
The switching frequency of the ISL6261 controller is set by
the resistor RFSET between pins VW and COMP, as shown in
Figures 2 and 3.
FN9251.1
September 27, 2006
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
1.5000
0.9750
1.4875
0.9625
0.9500
1.4750
1.4625
0.9375
1.4500
0.9250
1.4375
0.9125
0.9000
1.4250
1.4125
0.8875
1.4000
0.8750
1.3875
0.8625
0.8500
1.3750
1.3625
0.8375
1.3500
0.8250
1.3375
0.8125
0.8000
1.3250
1.3125
0.7875
1.3000
0.7750
1.2875
0.7625
0.7500
1.2750
1.2625
0.7375
1.2500
0.7250
1.2375
0.7125
0.7000
1.2250
1.2125
0.6875
1.2000
0.6750
1.1875
0.6625
0.6500
1.1750
1.1625
0.6375
1.1500
0.6250
1.1375
0.6125
0.6000
1.1250
1.1125
0.5875
1.1000
0.5750
1.0875
0.5625
0.5500
1.0750
1.0625
0.5375
1.0500
0.5250
1.0375
0.5125
0.5000
1.0250
1.0125
0.4875
1.0000
0.4750
0.9875
0.4625
12
FN9251.1
September 27, 2006
ISL6261
TABLE 1. VID TABLE FROM INTEL IMVP-6 SPECIFICATION
(Continued)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Vo (V)
0.4500
0.1625
0.4375
0.1500
0.4250
0.1375
0.4125
0.1250
0.4000
0.1125
0.3875
0.1000
0.3750
0.0875
0.3625
0.0750
0.3500
0.0625
0.3375
0.0500
0.3250
0.0375
0.3125
0.0250
0.3000
0.0125
0.2875
0.0000
0.2750
0.0000
0.2625
0.0000
0.2500
0.0000
0.2375
0.0000
0.2250
0.0000
0.2125
0.0000
0.2000
0.0000
0.1875
0.1750
Control
Signal
Logic
FDE
DPRSLPVR
Forced CCM
0%
0%
33%
Forced CCM
0%
13
OPERATIONAL MODE
VW-COMP WINDOW
VOLTAGE INCREASE
DPRSTP#
FN9251.1
September 27, 2006
ISL6261
High Efficiency Operation Mode
Dynamic Operation
The ISL6261 responds to VID changes by slewing to new
voltages with a dv/dt set by the SOFT capacitor and the logic
of DPRSLPVR. If CSOFT = 20nF and DPRSLPVR = 0, the
output voltage will move at a maximum dv/dt of 10mV/s
for large changes. The maximum dv/dt can be used to
achieve fast recovery from Deeper Sleep to Active mode. If
CSOFT = 20nF and DPRSLPVR = 1, the output voltage will
move at a dv/dt of 2mV/s for large changes. The slow
dv/dt into and out of deeper sleep mode will minimize the
audible noise. As the output voltage approaches the VID
command value, the dv/dt moderates to prevent overshoot.
The ISL6261 is IMVP-6 compliant for DPRSTP# and
DPRSLPVR logic.
PROTECTION ACTIONS
FAULT RESET
Overcurrent fault
120s
Way-Overcurrent fault
< 2s
Immediately
Low-side FET on until Vcore < 0.85V, then PWM tristate, PGOOD latched low (OV-1.7V always)
VDD toggle
Overvoltage fault
(+200mV)
1ms
Undervoltage fault
(-300mV)
1ms
Over-temperature fault
(NTC<1.18)
Immediately
N/A
14
FN9251.1
September 27, 2006
ISL6261
Protection
The ISL6261 provides overcurrent (OC), overvoltage (OV),
undervoltage (UV) and over-temperature (OT) protections as
shown in Table 3.
Overcurrent is detected through the droop voltage, which is
designed as described in the Component Selection and
Application section. The OCSET resistor sets the
overcurrent protection level. An overcurrent fault will be
declared when the droop voltage exceeds the overcurrent
set point for more than 120s. A way-overcurrent fault will be
declared in less than 2s when the droop voltage exceeds
twice the overcurrent set point. In both cases, the UGATE
and LGATE outputs will be tri-stated and PGOOD will go low.
The over-current condition is detected through the droop
voltage. The droop voltage is equal to IcoreRdroop, where
Rdroop is the load line slope. A 10A current source flows out
of the OCSET pin and creates a voltage drop across ROCSET
(shown as R10 in Figure 2). Overcurrent is detected when
the droop voltage exceeds the voltage across ROCSET.
Equation 1 gives the selection of ROCSET.
ROCSET =
I OC Rdroop
(EQ. 1)
10 A
For example: The desired over current trip level, Ioc, is 30A,
Rdroop is 2.1m, Equation 1 gives ROCSET = 6.3k.
Undervoltage protection is independent of the overcurrent
limit. A UV fault is declared when the output voltage is lower
than (VID-300mV) for more than 1ms. The gate driver
outputs will be tri-stated and PGOOD will go low. Note that a
practical core regulator design usually trips OC before it trips
UV.
There are two levels of overvoltage protection and response.
An OV fault is declared when the output voltage exceeds the
VID by +200mV for more than 1ms. The gate driver outputs
will be tri-stated and PGOOD will go low. The inductor
current will decay through the low-side FET body diode.
Toggling of VR_ON or bringing VDD below 4V will reset the
fault latch. A way-overvoltage (WOV) fault is declared
immediately when the output voltage exceeds 1.7V. The
ISL6261 will latch PGOOD low and turn on the low-side
FETs. The low-side FETs will remain on until the output
voltage drops below approximately 0.85V, then all the FETs
are turned off. If the output voltage again rises above 1.7V,
the protection process repeats. This mechanism provides
maximum protection against a shorted high-side FET while
preventing the output from ringing below ground. Toggling
VR_ON cannot reset the WOV protection; recycling VDD will
reset it. The WOV detector is active all the time, even when
other faults are declared, so the processor is still protected
against the high-side FET leakage while the FETs are
commanded off.
I SS
IZ
Internal to
ISL6261
Error
Ampliflier
C SOFT
V REF
FN9251.1
September 27, 2006
ISL6261
10uA
OCSET
R ocset
I phase
OC
VSEN
RTN
1000pF
R par
ESR
R ntc
0~10
Ropn1
R drp1
VO
Cn
R drp2
DROOP
VCC-SENSE
1000pF
330pF
Vo
Co
R series
DFB
Ropn2
DROOP
DCR
Rs
VSUM
Internal to
ISL6261
VSS-SENSE
To Processor
Socket Kelvin
Conections
VDIFF
FIGURE 6. SIMPLIFIED VOLTAGE DROOP CIRCUIT WITH CPU-DIE VOLTAGE SENSING AND INDUCTOR DCR CURRENT SENSING
CSOFT
I GV
=
SLEWRATE
(EQ. 2)
(EQ. 3)
dV soft
dt
I ss
41A
=
= 2.8 mV
s
C SOFT 0.015 F
(EQ. 4)
Selecting Rbias
16
FN9251.1
September 27, 2006
ISL6261
to layouts. The Kelvin sense technique provides for
extremely tight load line regulation at the processor die side.
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes (switching nodes) and other noisy traces. Common
mode and differential mode filters are recommended as
shown in Figure 6. The recommended filter resistance range
is 0~10 so it does not interact with the 50k input resistance
of the differential amplifier. The filter resistor may be inserted
between VCC-SENSE and the VSEN pin. Another option is
to place one between VCC-SENSE and the VSEN pin and
another between VSS-SENSE and the RTN pin. The need of
these filters also depends on the actual board layout and the
noise environment.
Since the voltage feedback is sensed at the processor die, if
the CPU is not installed, the regulator will drive the output
voltage all the way up to damage the output capacitors due
to lack of output voltage feedback. Ropn1 and Ropn2 are
recommended, as shown in Figure 6, to prevent this
potential issue. Ropn1 and Ropn2, typically ranging
20~100, provide voltage feedback from the regulator local
output in the absence of the CPU.
54uA
NTC
V NTC
6uA
Internal to
ISL6261
VR_TT#
SW1
R NTC
SW2
RS
1.23V
1.20V
VR_TT#
(EQ. 5)
Logic_1
In diode emulation mode, the ISL6261 stretches the
switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the
switching loss at light load, which is important in conserving
battery power.
Logic_0
T2
T1
T (oC)
17
FN9251.1
September 27, 2006
ISL6261
The NTC thermistors resistance is approximately given by
the following formula:
NTC
(T ) = R
NTCTo
1
1
b(
)
T
273
To
273
+
+
e
(EQ. 6)
R NTC (T1 ) + Rs =
R NTC (T2 ) + Rs =
1.20V
= 20k
60 A
(EQ. 7)
1.23V
= 22.78k
54 A
(EQ. 8)
(EQ. 9)
2.78k e
RNTCTo =
e
1
b(
)
T2 + 273
b(
1
)
To + 273
(EQ. 10)
1
b(
)
T1 + 273
RNTCTo =
2.78k
1
1 R NTC _ T2
ln(
) + 1 ( 273 + To )
b
R NTCTo
(EQ. 13)
273
(EQ. 14)
R NTC_To = 431k
The NTC thermistor datasheet gives the resistance ratio as
0.03956 at 100C and 0.03322 at 105C. The b value of
4700k in Panasonic datasheet only covers up to 85C;
therefore, using Equation 11 is more accurate for 100C
design and the required NTC nominal resistance at 25C is
438k. The closest NTC resistor value from manufacturers
is 470k. So Equation 12 gives the series resistance as
follows:
(EQ. 11)
Rs =
1.20V
R NTC (T1 ) = 20k R NTC_T1
60 A
18
(EQ. 12)
FN9251.1
September 27, 2006
ISL6261
10uA
Rocset
OCSET
VO
OC
Rs
VSUM
Internal to
ISL6261
DROOP
DFB
Io DCR
Rpar
Rntc
R drp1
VO
Vdcr
Rseries
Cn
R drp2
DROOP
Rn
(Rntc+Rseries) Rpar
Rntc+Rseries+Rpar
G1 (T ) =
V DCR = I o DCR
(EQ. 15)
Rn (T ) =
19
(EQ. 16)
Rn (T )
Rn (T ) + Rs
(EQ. 17)
(EQ. 18)
(EQ. 19)
(EQ. 20)
G 1 (T ) =
G 1 t arg et
(1 + 0.00393* (T 25)
(EQ. 21)
FN9251.1
September 27, 2006
ISL6261
Rdrp1 (R11 in Figure 2) and Rdrp2 (R12 in Figure 2) sets the
droop amplifier gain, according to Equation 22:
k droopamp = 1 +
Rdrp 2
(EQ. 22)
R drp1
Rdrp 2 = (
Rdroop
DCR G1(25 o C )
1) Rdrp1
(EQ. 23)
R drp 2 _ new =
42 mV
( R drp 1 + R drp 2 ) R drp 1
40 mV
Vcore
icore
Icore
Vcore
Vcore
Vcore= IcoreRdroop
FIGURE 10. DESIRED LOAD TRANSIENT RESPONSE
WAVEFORMS
icore
Vcore
Vcore
icore
Vcore
Vcore
(EQ. 24)
R Rs
L
Cn
= n
DCR Rn + Rs
(EQ. 25)
FN9251.1
September 27, 2006
ISL6261
Solving for Cn yields
L
C n = DCR
Rn Rs
Rn + Rs
(EQ. 26)
0.45H
0.0011
= 174nF
Cn =
parallel(7.68k ,3.4k )
(EQ. 27)
Since the inductance and the DCR typically have 20% and
7% tolerance respectively, the L/DCR time constant of each
individual inductor may not perfectly match the RC time
constant of the current sensing network. In mass production,
this effect will make the transient response vary a little bit
from board to board. Compared with potential long-term
damage on CPU reliability, an immediate system failure is
worse. So it is desirable to avoid the waveforms shown in
Figure 11. It is recommended to choose the minimum Cn
value based on the maximum inductance so only the
scenarios of Figures 10 and 12 may happen. It should be
noted that, after calculation, fine-tuning of Cn value may still
be needed to account for board parasitics. Cn also needs to
be a high-grade cap like X7R with low tolerance. Another
good option is the NPO/COG (class-I) capacitor, featuring
only 5% tolerance and very good thermal characteristics. But
the NPO/COG caps are only available in small capacitance
values. In order to use such capacitors, the resistors and
thermistors surrounding the droop voltage sensing and
droop amplifier need to be scaled up 10X to reduce the
capacitance by 10X. Attention needs to be paid in balancing
the impedance of droop amplifier.
21
The user can choose the actual resistor and capacitor values
based on the recommendation and input them in the
spreadsheet, then see the actual loop gain curves and the
regulator output impedance curve.
Caution needs to be used in choosing the input resistor to
the FB pin. Excessively high resistance will cause an error to
the output voltage regulation due to the bias current flowing
in the FB pin. It is recommended to keep this resistor below
3k.
Vrsen = Rsen I o
(EQ. 28)
Rdrp 2
Rdroop = Rsen 1 +
R
drp1
(EQ. 29)
Rdroop
Rdrp 2 = Rdrp1
1
Rsen
(EQ. 30)
FN9251.1
September 27, 2006
VSS
ISL6261
22
FN9251.1
September 27, 2006
ISL6261
10uA
OCSET
Rocset
VO
OC
Rs
VSUM
Internal to
ISL6261
DROOP
DFB
Vrsen
R drp1
VO
I o Rsen
Cn
R drp2
DROOP
FIGURE 14. EQUIVALENT MODEL FOR DROOP CIRCUIT USING DISCRETE RESISTOR SENSING
FIGURE 16. CCM LOAD LINE AND THE SPEC, VID = 1.1V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
FIGURE 18. DEM LOAD LINE AND THE SPEC, VID = 0.7625V,
VIN1 = 8V, VIN2 = 12.6V AND VIN3 = 19V
23
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
5V/div
0.5V/div
10V/div
24
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
5V/div
0.2V/div
0.2V/div
5V/div
5V/div
5V/div
10V/div
5V/div
FIGURE 25. VBOOT TO VID, VIN = 19V, Io = 2A, VID = 1.5V,
Ch1: PGD_IN, Ch2: Vo, Ch3: CLK_EN#,
Ch4: PHASE
5V/div
0.5V/div
7.5ms
5V/div
10V/div
FIGURE 27. CLK_EN AND PGOOD ASSERTION DELAY,
VIN=19V, Io=2A, VID=1.1V, Ch1: CLK_EN#,
Ch2: Vo, Ch3: PGOOD, Ch4: PHASE
25
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
100A/us
50A/us
50A/us
100A/us
26
100A/us
50A/us
FN9251.1
September 27, 2006
ISL6261
Typical Performance (Data Taken on ISL6261 Eval1 Rev. C Evaluation Board) (Continued)
50A/us
100A/us
120us
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporations quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
27
FN9251.1
September 27, 2006
GND_POWER
VSSSENSE
IN
IN
IN
VCORE
IN
VCCSENSE
VCC_PRM
Q5
2N7002
PGOOD
D3
+3.3V
GRN
3 R2 510 J9
1 12 2
1
RED
ON
ON
ON
ON
ON
R4
DROOP
R6
R5
DNP
6.34K
C3
R3
10
9
8
7
6
DPRSLPVR
PSI#
PGD_IN
DPRSTP#
SD05H0SK
FDE
1
2
3
4
5
10K
3
4
5
P6
VW
OCSET
47PF
C12
IN
VSUM
VCC_PRM
330PF
IN
1K
C7
R15
DFB
5.23K
C6
C9
150PF
R12
R11
COMP
SOFT
DNP R8 DNP
R7
P5
+3.3V1
R103
P7
P4
+3.3V
P10
P9
S1
10K
R10
C8
R9
R19
1000PF
C14
464K
IN
IN
IN
IN
OUT
J8
1 2 2 21
10K
R14
0.015UF
C10
DNP
R13
34
2
C2
6.81K
C13
C11
CLK_EN#
PSI#
FDE
+3.3V
PGOOD
DPRSLPVR
OUT
R23
330PF
C18
C20
VDIFF1
41
1
2
3
4
5
6
7
8
9
10
1X3
J10
1
2 21
3 3
RTN
3V3
1UF
C24
J15
1 1 2 2
R30
DNP
C23
EP
FDE
PGD_IN
RBIAS
VR_TT
NTC
SOFT
OCSET
VW
COMP
FB
P23
ISL6261CR
U6
VID2
VID1
VID0
VCCP
LGATE
VSSP
PHASE
UGATE
BOOT
NC
R32
P31
R35
R34
R33
LGATE
GND_POWER
PHASE
UGATE
BOOT
VID6
VID5
VID4
VID3
VID2
VID1
VID0
OUT
OUT
OUT
OUT
OUT
VIN
1 2 2 +5V
J16
IN
IN
IN
IN
IN
IN
IN
10K
R36
IN
J17
2 2 1
+5V
NOTE:
RUN LGATE1 TRACE PARALLEL TO TRACE CONNECTING
PGND1 AND SOURCE OF Q3 AND Q4.
30
29
28
27
26
25
24
23
22
21
P28
P29
VR_ON
DPRSLPVR
DPRSTP#
VSEN
PGD_IN
390PF
2.21K
R25
R24
P12
RBIAS
VR_TT
5.49K
FB
R1 510
SSL_LXA3025IGC
10UF
P3
10K
R18
DNP
1000PF
1000PF
10K
499
C15
147K
10K
R21
R20
P1
R22
P11
0.1UF
C16
P13
DNP
P2
C17
0.12UF
C19
P16
4.53K
R28
R29
0.068UF
C21
P20
P21
DNP
C25
P30 DNP
P14
P15
P18
P17
8200PF
R27
P19
3.57K 10K NTC
R31
P24
C26
10K
R37
C28
P27
P26
PGOOD 40
3V3 39
CLK_EN 38
DPRSTP 37
DPRSLPVR 36
VR_ON 35
VID6 34
VID5 33
VID4 32
VID3 31
VDIFF
VSEN
RTN
DROOP
DFB
VO
VSUM
VIN
VSS
VDD
11
12
13
14
15
16
17
18
19
20
P25
0.22UF
10K
R38
P34
0.01UF
1
2
3
4
5
6
7
U1
14
13
12
11
10
9
8
+3.3V
MST7_SPST
1X3
J19
1
2 21
3 3
ISL6261 EVAL1
CONTROLLER
ENGINEER:
JIA WEI
DRAWN BY:
10K
10K
R45
R44
10K
3
1 S4
+3.3V
R43
5V
VR_ON1
+3.3V
TITLE:
IN
J2
10K
J1
C30
10K
R40
R39
C29
10K
R41
10
1UF
10K
R42
10UF
P33
P32
C27
P8
1UF
10
11
12
13
14
ON
OFF
10
R46
C31
28
10UF
3.3V
100
J4
J3
DATE:
MAR-14-05
SHEET:
1 OF 5
REV:
VR_ON
R47
ISL6261
P22
FN9251.1
September 27, 2006
29
FN9251.1
September 27, 2006
A
BOOT
PHASE
LGATE
IN
IN
IN
UGATE
IN
R48
P36
P35
0.22UF
C1
Q2
Q4
IRF7832
Q3
Q1
IRF7832
IRF7821
IRF7821
VIN
OUT
R49
C33
D2
DNP
DNP
2
C32
1UF
10UF
DNP
C4
J20 4
10UF C5
10UF C5B
R82
J21 4
1
2
56UF
R83
3
1
2
56UF
C34
J5
J6
0.1UF
VSSSENSE
VCCSENSE
VSUM
OUT
P37
P38
R50
R51
P39
IN
IN
DNP
R52
L1
0.45UH
R53
P40
DNP
R54
R60
BUS WIRE
J22 4
3
1
2
J13
C35
7.68K
VCC_PRM
OUT
P41
0.1UF
C91
0.1UF
C42
C45
C39
C43
22UF
C56
C57
22UF
22UF
22UF
C49
330UF
C44
330UF
C55
C90
22UF
C61
330UF
C46
C47
C48
22UF
22UF
22UF
C37
C38
C59
C60
22UF
22UF
C53
C54
22UF
22UF
C36
C40
330UF
330UF
22UF
C41
C52
C89
22UF
22UF
C65
C66
22UF
22UF
22UF
C58
330UF
C64
22UF
C70
OUT
OUT
DATE:
MAR-14-05
SHEET:
2 OF 5
REV:
J14
GND_POWER
22UF
22UF
22UF
C67
22UF
22UF
VCORE
ISL6261 EVAL1
POWER STAGE
ENGINEER:
JIA WEI
DRAWN BY:
22UF
22UF
C68
C69
22UF
TITLE:
C50
C51
22UF
C62
C63
22UF
22UF
22UF
C71
22UF
(Continued)
ISL6261
VCORE
IN
OUT
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AF7
B26
VCCSENSE
VCCA
VCCSENSE
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCCP
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
AF20
AF18
AF17
AF15
AF14
AF12
AF10
AF9
AE20
AE18
AE17
AE15
AE13
AE12
AE10
AE9
AD18
AD17
AD15
AD14
AD12
AD10
AD9
AD7
AC18
AC17
AC15
AC13
AC12
AC10
AC9
AC7
AB20
AB18
AB17
AB15
AB14
AB12
AB10
AB9
AB7
AA20
AA18
G21
J6
J21
K6
K21
M6
M21
N6
N21
R6
R21
T6
T21
V6
V21
W21
A3
A5
A6
A21
A22
A24
A25
B1
B2
B3
B4
B5
B22
B23
B25
C1
C3
C4
C6
C7
C20
C21
C23
C24
C26
D2
D3
D5
D6
D7
D20
D21
D22
D24
D25
E1
E2
E4
E5
E22
E23
E25
E26
F1
F3
F4
F6
F21
F23
F24
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
PSI#
AE6
OUT
AD26
AE2 VID6
AF2 VID5 OUT
AE3 VID4 OUT
AF4 VID3 OUT
AE5 VID2 OUT
OUT
AF5 VID1 OUT
AD6 VID0 OUT
AF26
AF25
AF23
AF22
AF1
AE25
AE24
AE22
AE21
AD24
AD23
AD21
AD20
AD4
AD3
AD1
AC26
AC25
AC23
AC22
AC20
AC5
AC4
AC2
AC1
AB25
AB24
AB22
AB21
AB6
AB5
AB3
AB2
AA26
AA24
AA23
AA21
AA6
SOCKET1
INTEL_IMPV6
COMP3
COMP1
COMP2
COMP0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
PSI
GTLREF
VID6
VID5
VID4
VID3
VID2
VID1
VID0
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
W22
W6
W5
W3
W2
V26
V24
V23
V4
V3
U25
U23
U22
U5
U4
U2
T25
T24
T22
T5
T3
T2
R24
R23
R4
R3
R1
P26
P25
P23
P22
P5
P4
V1
U26
U1
R26
AA4
AA3
AA1
Y26
Y25
Y23
Y22
Y5
Y4
Y2
Y1
W25
W24
A4
A8
A11
A14
A16
A19
A23
A26
B6
B8
B11
B13
B16
B19
B21
B24
C2
C5
C8
C11
C14
C16
C19
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F2
F5
F8
F11
F13
F16
F19
F22
F25
G1
G4
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
ISL6261 EVAL1
SOCKET
ENGINEER:
JIA WEI
DRAWN BY:
TITLE:
GND_POWER
IN
30
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
AE7
SOCKET1
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
S
INTEL_IMPV6
VSSSENSE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
F26
G2
G3
G5
G6
G22
G24
G25
H1
H2
H4
H5
H22
H23
H25
H26
J1
J3
J4
J23
J24
J26
K2
K3
K5
K22
K24
K25
L1
L2
L4
L5
L22
L23
L25
L26
M1
M3
M4
M23
M24
M26
N2
N3
N5
N22
N24
N25
P1
P2
AF24
AF21
AF19
AF16
AF13
AF11
AF8
AF6
AF3
AE26
AE23
AE19
AE16
AE14
AE11
AE8
AE4
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
OUT
AE1
AD25
AD22
AD19
AD16
AD13
AD11
AD8
AD5
AD2
AC24
AC21
AC19
AC16
AC14
AC11
AC8
AC6
AC3
AB26
AB23
AB19
AB16
AB13
AB11
AB8
AB4
AB1
AA25
AA22
AA19
AA16
AA14
AA11
AA8
AA5
AA2
Y24
Y21
Y6
Y3
W26
W23
W4
W1
V25
V22
V5
V2
U24
U21
U6
U3
T26
T23
T4
T1
R25
R22
R5
R2
P24
P21
P6
P3
DATE:
MAR-14-05
SHEET:
3 OF 5
REV:
VSSSENSE
ISL6261
(Continued)
INTEL_IMPV6
SOCKET1
FN9251.1
September 27, 2006
J11
1
+12V
+12V
1UF
Q14
2N7002
LO
VSS
LI
HI
499
R72
HIP2100
VDD
HB
HO
HS
U5
C81
+12V
S5 1
ON
OFF
249
R73
249
R74
BAV99
D1
3
IN
R75
VCORE
Q15
HUF76129D3S
2
3
0.1
R76
C80
R71
3
2
GND_POWER
1
2
4 J23
49.9K
0.12
31
J12
GND_POWER
ISL6261
(Continued)
FN9251.1
September 27, 2006
10UF
1
2
3
4
5
6
7
1
2
3
4
5
6
7
+3.3V
14 14
13 13
12 12
11 11
10 10
9 9
8 8
MST7_SPST
U9
MST7_SPST
14 14
13 13
12 12
11 11
10 10
9 9
8 8
MST7_SPST
U8
R81
14 14
13 13
12 12
11 11
10 10
9 9
8 8
10K
R84
J24
1 2 2 +3.3V_GEY
10K
R85
10K
R86
10K
R87
10K
R88
10K
R89
10K
R90
10K
R91
10K
R92
10K
R93
10K
R94
10K
R95
10K
R96
10K
R97
10K
R98
10K
10K
R100
10K
R99
10K
10K
10K
R101
U7
1
10
10
10
Y4
Y5
Y6
Y7
Y8
A5
A6
A7
A8
GND
HC540
Y7
Y8
A8
GND
Y8
GND
10K
10K
10K
10K
R58
R59
R61
R62
6
Y7
A8
10K
Y6
A7
R57
Y5
10K
Y4
A5
A6
R56
Y3
A4
10K
Y2
A3
R55
Y1
A2
HC540
G2
A1
VCC
Y6
A7
G1
Y5
A6
U4
Y3
Y4
Y2
A3
A5
Y1
A2
A4
G2
A1
VCC
Y3
A4
G1
Y2
A3
U3
Y1
A2
VCC
G2
HC540
U2
A1
G1
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
11
12
13
14
15
16
17
18
19
20
C72
0.1UF
C74
+3.3V_GEY
0.1UF
C73
+3.3V_GEY
0.1UF
+3.3V_GEY
7
28
18
31
30
19
20
21
22
23
24
33
34
8
9
10
11
14
15
16
17
S2
EVQPA
J29
1 1 2 2
EVQPA
PSI#
+3.3V_GEY
PSI# S7
1
J25
1 2 2
EVQPA
LOOP
+3.3V_GEY
DPRSLP
S6
1
MODE TRANS
DNP
+3.3V_GEY
+3.3V_GEY
VDD
VDD
RB0
RB1
RB2
RB3
RB4
RB5
RB6
RB7
NC
NC
RA0
RA1
RA2
RA3
RA4
RA5
OSC1
OSC2
MCLR
1UF
C78
PIC16F874 +3.3V_GEYR69
R104
10K
RC0
RC1
RC2
RC3
RC4
RC5
RC6
RC7
NC
NC
RD0
RD1
RD2
RD3
RD4
RD5
RD6
RD7
RE0
RE1
RE2
VSS
VSS
CLK_EN# R67
+3.3V_GEY
IN
6
29
25
26
27
38
39
40
41
2
3
4
5
12
13
32
35
36
37
42
43
44
1
U10
DNP
R106
10K
R77
AC04
6A
6Y
5A
5Y
4A
4Y
Vcc
1UF
C86
+3.3V
DIRECT
10
11
12
13
14
DELAY
DPRSLPVR
OUT
REV:
TITLE:
ISL6261 EVAL1
GEYSERVILLE TRANSITION GEN.
ENGINEER:
DATE:
MAR-14-05
JIA WEI
DRAWN BY:
SHEET:
5 OF 5
3A
3Y
GND
1A
1Y
2A
2Y
EVQPA
J28
1 2 2
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
U12
HCM49
U11
RESETS8
1
PSI#
DPRSTP#
PGD_IN
VR_ON1
VID0
VID1
VID2
VID3
VID4
VID5
VID6
C85
1
2
3
4
5
6
7
R105
R68
R82
R83
C87
0
DNP
J7
15PF
R63
C75
R64
C76
BAV99
10K
0.1UF
10K
0.1UF
10K
0.1UF
10K
10K
S3
R70 0
R65
C77
R66
R102
C79
3
0.01UF
2
1
C84
15PF
P43
P42
BAV99
R78 0
DNP
1X3
R79 0
C88
P45
P44
1
2 21
3 3
S9
2
1
32
R80 0
DNP
ISL6261
(Continued)
FN9251.1
September 27, 2006
ISL6261
36X 0.50
A
B
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
40
31
30
6.00
4 . 10 0 . 15
21
10
0.15
(4X)
11
20
0.10 M C A B
TOP VIEW
40X 0 . 4 0 . 1
4 0 . 23 +0 . 07 / -0 . 05
BOTTOM VIEW
0 . 90 0 . 1
BASE PLANE
( 5 . 8 TYP )
SEATING PLANE
0.08 C
SIDE VIEW
4 . 10 )
( 36X 0 . 5 )
0 . 2 REF
( 40X 0 . 23 )
0 . 00 MIN.
0 . 05 MAX.
( 40X 0 . 6 )
DETAIL "X"
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
33
FN9251.1
September 27, 2006
ISL6261
44X 0.50
37
6
PIN 1
INDEX AREA
6
PIN #1 INDEX AREA
48
1
7.00
36
4. 30 0 . 15
12
25
(4X)
0.15
13
24
0.10 M C A B
48X 0 . 40 0 . 1
TOP VIEW
( 6 . 80 TYP )
(
0.10 C
BASE PLANE
0 . 90 0 . 1
4 . 30 )
SEATING PLANE
0.08 C
SIDE VIEW
( 44X 0 . 5 )
0 . 2 REF
( 48X 0 . 23 )
( 48X 0 . 60 )
0 . 00 MIN.
0 . 05 MAX.
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal 0.05
4. Dimension b applies to the metallized terminal and is measured
between .015mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
34
FN9251.1
September 27, 2006