Espressif Systems

ESP8266 Application
Design Guide


ESP8266 Features

ESP8266 Schematic

ESP8266 Layout

Test Board

Appendix

Outline
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ESP8266 features

ESP8266 Module device requires only 7 resistors capacitors inductors,

1 passive crystal and 1 flash.

Full internal integrated RF section, with automatic internal calibration

APP code and a reference board available to test frequency and
other RF performance

No special production equipment to test.

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Circuit Power On

first VDDPST (pin 11, pin 17) at Power On

then CHIP_EN (pin 7) at Power On

or VDDPST and CHIP_EN while Power On.

Reference schematic
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Digital and IO supply

Pin 11, Pin 17 - VDDPST

Voltage: 1.8V ~ 3.3V

Reference schematic
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Analog Power

Pin 1, Pin 3, Pin 4, Pin 29, Pin 30

Voltage: 3.0V3.6V

Precautions:
1 All power pins has been connected, with GPIO
all the way to ESP8266, CHIP_EN to control power
2When consider to control CHIP_EN by Reset-IC
use RCR=1k to VCC, C=100nF to GND) circuit.
3Digital power VDDPST and analog power VDDA
can be connected together
4Please do not use on ESP8266 ferrite beads (FB)

Reference schematic
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RF antenna interface

Chip output impedance is 50
,not need to match the chip,but it is
recommended to retain -type matching network for the antenna to match

50

Reference schematic
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SDIO

On SDIO 200
(or less) serial resistors are recommended to reduce noise
no pullups necessary on SDIO

Termination resistors need to be placed near ESP8266

Reference schematic
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CRYSTAL

C1 and C2 can have any value in range of 8pF ~ 12pF
the value is determined by adjusting to the specific needs

WiFi only 20PPM; for WiFi + BT 10PPM crystal

Note: The accuracy of the crystal is

very important! When crystal frequency
offset is out of range, iperf will lead
directly to poor test performance
reducing sensivity

Reference schematic
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CRYSTAL

(this is for Android connected module i think, see Espressif_ESP8089_SDIO_WiFi.zip on my 1drv )

Measuring the actual frequency oscillator (at ESP8266 GPIO0 pin)

Preset:in init_data.conf change test_xtal to 1(default)
after that the GPIO0 will output the actualy crystal frequency
After testchange test_xtal back to 0
Note: Measuring with probes directly at crystal pins will cause deviation.
Steps
(1) adb pull /system/lib/modules/init_data.conf
(2) UltraEdit the init_data.confchange test_xtal=0 to test_xtal=1do not change anything else
(3) adb push init_data.conf /system/lib/modules/init_data.conf
(4) adb shell, go to /system/lib/modules/init_data.conf and change permission in case no read permission
(5) After the test set back the test_xtal=0 to avoid RF interferences caused by clock signal at GPIO0

Reference schematic
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Bluetooth Co-existence

GPIO0/U0RXDcoonected to WLAN_ACTIVE
(WLAN low active)

MTMS: connected to BT_ACTIVE

MTCK: connected to BT_Priority
Connection above for 3-wire Bluetooth protocol

BT_CLK_REQ: Connected to GPIO2

MTDI: connected WIFI_INT, HOST interrupt WIFI

Reference schematic
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Floorplan
ESP
8266

High speed signals between the CPU and DDR will produce HF noise that can interfere with WiFi radio,recommendations:
. a try not to use PCB-board antenna, with external antenna, and the antenna far away from the noise source (CPU + DDR);
. b Floorplan ESP8266 the PCB edge, away from the noise source (CPU + DDR), reduce noise coupling from the position;
. c ESP8266 the RF trace as short as possible;
. d The digital signal space between the CPU and DDR wrap, wrap, or use the shield on both sides, so that the
HF noise is not emitted into the air.
Antenna should be far away from other high-frequency noise sources:
a. LCD b. HDMI c. Camera Sensor d. USB

Reference layout design

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General Guide Lines

4 layers recommended, 1 layer signal, 2 layer GND.

All power supply filter capacitors (except C3) must be as close to the
corresponding IC pin, and with the good ground coupling path.

Trace length from VDD3P3 pins to C3 capacitor (incl. the length of R3)

as much as possible about 6mm

Trace width from VDD33 to VDD3P3_PA_BALUN at least 15mil

No high-speed data traces (SDIO) near crystal; the 26MHz clock traces
as short as possible, good ground plane
(for more check ESP8089_onboard_RK_Platform Design GuideV1.pdfh on my 1drv)

Reference layout design

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RF

RF over controled 50Ohm microstrip trace

RF chip to the antenna can not have a through-hole connection

Reference layout design

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Crystals

close to IC, short traces

no high-speed data traces

(SDIO) near crystal

Reference layout design

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Power traces

thick vias when changing layer,
vias and decoupling caps near IC

Power Amplifier

Peak current(pin 3,4)about 300mA
Note the trace impendance as well.

Reference layout design

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Other

PCB second layer as continuous surface ground plane, do not
allow the power supply nor signal traces walk on that layer

Wi-Fi module need shilding and vias ground plane arround.

Wi-Fi chip antenna can cause damage on touch screen controllers

Reference layout design

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IO_3V3

Power switch

GPIO_control
flash

SD_D2
SD_D3

Power 5V

CHIP_EN SWICH
ANT

SD_CMD

Reset

SD_CLK
SD_D0
SD_D1
serial ports

Test board
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LNA_3V3

PA_3V3

the interface of Demo Board

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MTDO

GPIO0

GPIO2

SDIO / SPI

Uart Download

Flash Boot

GPIO_control
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Appendix

ESP8266 Standlone Mode

Pin

Name

XPD_DCDC

9
10
12
13

MTMS
MTDI
MTCK
MTDO

14

GPIO2

15

GPIO0

18
19
20
21
22
23

SD_DATA_2
SD_DATA_3
SD_CMD
SD_CLK
SD_DATA_0
SD_DATA_1

25

U0RXD

26

U0TXD

level at
power-up

Flash

Deep-Sleep
Wakeup

Yes [0]

SPI

GPIO16 (
HSPICLK
HSPIQ
HSPID
HSPICS

Flash
UART Tx

SPIHD
SPIWP
SPICS0
SPICLK
SPIQ
SPID
Flash
UART Rx

GPIO/I2C

GPIO14 (
GPIO12 (
GPIO13 (
GPIO15 (
GPIO2 ()

Yes [0]

SPICS2

GPIO0 (

Yes
Yes [0]

HSPIHD
HSPIWP

GPIO9 (
GPIO10 ()
No
No
No
No

Yes

GPIO3 (
Yes

SPICS1

GPIO1 ()

1 GPIO
SD_DATA_2 SD_DATA_32 Serial-Flash XPD_DCDC Deep-Sleep GPIO2
U0RXD Flash
GPIO
2GPIO0 GPIO2 U0TXD MTDO
UART Flash GPIO2 U0TXD
MTDO GPIO0
3 GPIO0 GPIO2 U0TXD
UART XPD_DCDC SDIO_DATA_2
SDIO_DATA_3 GPIO
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Appendix

ESP8266 SPI-Slave Mode

Pin

Name

8
9
10
12

XPD_DCDC
MTMS
MTDI
MTCK

13

MTDO

14

GPIO2

15

GPIO0

18

SD_DATA_2

19

SD_DATA_3

20

SD_CMD

21

SD_CLK

22

SD_DATA_0

23
25
26

SD_DATA_1
U0RXD
U0TXD

Flash

Flash

Yes [0]
HSPICLK
HSPIQ
HSPID

GPIO16 (
GPIO14 (
GPIO12 (
GPIO13 (

HSPICS

GPIO15 (

Flash UART Tx

GPIO2 ()

HSPIHD
SPI_SLAVE_CS
HSPIWP
SPI_SLAVE _MOSI

Yes [0]

GPIO0 (

Yes

GPIO9 (

Yes [0]

GPIO10 ()
No

SPI_SLAVE _CLK

No

SPI_SLAVE _MISO

No

Flash UART Rx

Yes
Yes
Yes

No
GPIO3 (
GPIO1 ()

1 GPIO
SD_DATA_2 SD_DATA_3 2 Serial-Flash SD_DATA_3 Firmware
GPIO
2MTDO U0TXD Flash SPI-Slave
Flash UART Flash GPIO2 U0TXD
MTDO GPIO0
3GPIO0 GPIO2 U0TXD UART
XPD_DCDC SDIO_DATA_1 SDIO_DATA_2
SDIO_DATA_3 GPIO
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additional informations on esp8266.com

or on my 1drv: http://1drv.ms/1BUD6Nv

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