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Lesson 6: Exercises

6.1 (a) What do you understand by the term 8-bit ALU, in terms of its inputs, outputs,
and processing, given that it can handle two sets of inputs?
(b) Prepare a possibly complete list of Arithmetic operations and Logical operations,
which can be carried out by the above 8-bit ALU.
(c) Verify your answers for Qn. (a) above, with reference to those for (b) above.

6.2 Consider a 2-input MUX which accepts a 4-bit word on each of its A-leg and B-leg
inputs.
(a) How many input and output lines (data and control) are there for this MUX?
(b) Though theoretically n-to-1 MUX implies any arbitrary values of n, why is it that
n is always restricted to some and not any values?

6.3 We note that a Data Path architecture is based on interconnections of cascaded logic
circuits. An n-level logic circuit means that a signal goes through a maximum of n
number of logic gates. Of course, some signals will go through less number of gates
also, depending on to which gate the signal is the first input. Likewise, we have
different types of logic circuits which introduce different amounts of delay for the
signals going through them. Given that such delays range between 3 and 7 nsecs in
an 8-level logic circuit that implements a CPU data path,
(a) Calculate the maximum clock rate for the CPU,
(b) From the above statements and calculations, list all the steps to be taken for
maximizing the speed of a CPU.

6.4 Assume that a micro-instruction can refer to a maximum of 16 registers on a CPU.


There are two ways of coding this information: one is by including a 4-bit field so
that by decoding it a register can be uniquely identified, and the other is by having a
16-bits field such that only one-of-16 bits when flagged as 1 (called, linear select)
does the unique identification. Discuss the merits and demerits of these two schemes:
Decoding and Linear-select.

6.5 Consider the implementation of the following micro-instruction in state T 1 :


T 1 : A.Bus PC,
which causes the contents of an 8-bit Program Counter to be moved to an 8-bit
Address Register MAR, which in turn places it on the 8-bit Address part of a 16-bit
bus, doing all these in a single state T 1 . If all the registers have Serial-In, Serial-Out,

Parallel-In, and Parallel-Out ports for data signals, and Clear, Preset, In-Enable, and
Out-Enable inputs for control signals,
(a) for this T 1 state operation to be effective, which of the above-mentioned features
will be used?
(b) sketch the schematic of the components and interconnections for this action, and
highlight the data and the control signal paths.

6.6 In a memory-read cycle operation, if a WAIT state is introduced,


(a) identify all the signals that must be extended for correct conclusion of operation
(b) if the CPU can generate the memory address only during one state (that is,
cannot be extended further) what is to be done?
(c) can any of the signals generated by CPU be used to initiate the WAIT state
directly/indirectly? If so, how?
(d) at what time the WAIT state may be precisely terminated?

6.7 With reference to a typical data-path architecture, shown below as Fig. 6.7, the
registers are:
IR = Instruction Register ;
MAR = Memory Address Register ;
AR = Accumulator (earlier referred to as an Internal Register) ;
BR = Buffer Register
;
PC = Program Counter
All the registers have independent input-enable and output-enable signals (indicated
by two arrows on the top of the respective blocks, but labeled only near IR). PC
additionally has an Inc: Increment control input. All the data-path lines, marked
with a \ (slash) symbol, are 8-bits wide (though indicated thus near IR only). IR feeds
a Decoder the output of which generates the necessary control signals.
ALU is the Arithmetic-Logic Unit capable of 8 operations, and so has 3 control
inputs: ALU 0-2. The two Multiplexers A and B have just one control input each, and
depending on whether it is 0/1 the top/bottom leg input is passed on as the output.
The captions in other rectangular boxes just describe the nature of the nearby signals.
Making suitable assumptions, answer the following:
(a) What is the RTL sequence for using the PC contents as the Memory address, to
be used for fetching an instruction word from Memory, and keeping the CPU
ready for fetching the next word also from Memory?
(b) For each step in the above RTL sequence highlight the data path and the relevant
control signals.
(c) Develop the micro-instruction word sequence that will ensure the implementation
of the above RTL sequence.

in

out
Operation
decoded
Control
signals

IR
8

Address out
MAR
In
Data
AR
Out
BR
Inc

Mux A0

PC

ALU 0-2
Mux B0

Fig. 6.7 Archetype data path architecture

6.8 With reference to the Freshman CPU (some design specification details introduced in
Exercises: 2 and 5), assume that it should handle 8-bit words (B 7 B 6 B 5 ..B 1 B 0 ),
(a) develop the typical RTL sequence for each of those 4 commands, for handling
only Immediate Data (that is, when B 5 = 0),
(b) develop a suitable general-purpose data path architecture with which to
implement any of those 4 commands.
(You will have to make appropriate assumptions. Solution for this problem will
help you gain some basic understanding of ISA : Instruction Set Architecture.)