576

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

A High-Voltage Output Driver in a 2.5-V 0.25-m

CMOS Technology
Bert Serneels, Student Member, IEEE, Tim Piessens, Michiel Steyaert, Fellow, IEEE, and
Wim Dehaene, Senior Member, IEEE

AbstractThe design of a high-voltage output driver in a digital

0.25- m 2.5-V technology is presented. The use of stacked devices
with a self-biased cascode topology allows the driver to operate
at three times the nominal supply voltage. Oxide stress and hot
carrier degradation is minimized since the driver operates within
the voltage limits imposed by the design rules of a mainstream
CMOS technology. The proposed high-voltage architecture uses a
switching output stage.
The realized prototype delivers an output swing of 6.46 V to a
50- load with a 7.5-V supply and an input square wave of 10 MHz.
A PWM signal with a dual-tone sinusoid at 70 kHz and 250 kHz
results in an IM3 of 65 dB and an IM2 of 67 dB. The on-resistance is 5.9 .

Index TermsBuffer circuits, CMOS integrated circuits, highvoltage techniques.

I. INTRODUCTION

RIVEN by the ever-growing demand for more computational power, deep-submicron and even nanometer technologies become more and more prominent for digital circuits.
Deep-submicron and nanometer CMOS technologies provide a
solution for the growing integration density of VLSI circuits and
the low-power requirements of complex signal processing applications. Since these technologies require low supply voltages,
the design of analog circuits with high output power demands is
running into its limits.
The objective is to tolerate the high supply voltage with
sufficient lifetime. Two approaches can be used to design
high-voltage tolerant output drivers. The first approach is the
use of customized silicon technologies. These technologies
result in high-voltage tolerant transistors at the cost of a more
expensive process and a degraded performance. Examples
are lightly doped drain (LDD) CMOS technologies and thick
gate-oxide transistors. In a LDD transistor, the electric field
across the channel is lowered by reducing the doping gradient
at the gate edge. The use of a thick gate-oxide transistor can be
seen as a device from a previous generation implemented in a
more advanced technology. The second approach is the use of
alternative circuit topologies and drain-source engineering in a
standard CMOS technology to reliably tolerate the high supply
voltage. An advantage of this approach is that it can be fully
Manuscript received July 28, 2004; revised September 27, 2004.
B. Serneels, M. Steyaert, and W. Dehaene are with the ESAT-MICAS
Laboratory, Katholieke Universiteit Leuven, B-3001 Leuven, Belgium (e-mail:
bert.serneels@esat.kuleuven.ac.be).
T. Piessens is with ICsence, B-3001 Leuven, Belgium (e-mail:
tim.piessens@icsence.com).
Digital Object Identifier 10.1109/JSSC.2005.843599

Fig. 1. Block diagram of the high-voltage output driver.

integrated within a digital technology without extra process

costs. The goal is to find the correct operating point such that
the voltage across the terminals of the transistors is limited.
Examples of this approach can be found in [1][3]. These I/O
circuits use the concept of two stacked devices, with a fixed
bias voltage to tolerate the high supply voltage. However, two
stacked transistors limit the maximum operating voltage, to two
. Ref. [4] presents an
times the nominal supply voltage,
. This topology uses
I/O buffer operating at 2.5 times
stacked transistors with a variable bias voltage. A disadvantage
of this circuit is the large number of stacked devices.
This paper describes a high-voltage output driver in a standard 2.5-V 0.25- m CMOS technology. The presented driver
uses stacked devices with a self-biasing technique [5]. This technique allows the driver to run on three times the nominal supply
voltage with a minimum number of stacked devices. The driver
operates within the electrical design rules of a commercially
available CMOS technology without the use of extra process
steps. Section II gives a system description of the driver. In
Section III, the self-biasing cascode technique is explained for
static and transient operation of the driver. Section IV describes
the design of a high-voltage output driver. Measurement results
are shown in Section V. Finally, in Section VI, conclusions are
given.
II. SYSTEM DESCRIPTION
Fig. 1 shows the block diagram of the high-voltage output
driver. One can distinguish three major parts: a level-shifter, a

0018-9200/$20.00 2005 IEEE

SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m CMOS TECHNOLOGY

p-switch block, and its complementary n-switch block. The pand n-switch blocks consist of a dynamic bias voltage circuit,
stacked output transistors, and a tapered buffer. This structure
can also be seen as a self-biased cascode topology where the
bias voltage of the transistors closest to the output depend on
the output voltage. Since it is a switching type output driver,
all stacked output transistors are either in the cut-off or in the
triode region. To guarantee a minimal lifetime of ten years as described by the electrical design rules of the technology used, the
maximum voltage across the terminals of any transistor is equal
to the nominal supply voltage. This limitation prevents oxide
breakdown and minimizes hot carrier degradation. Since each
switch block consists of three stacked devices the maximum allowable supply voltage of the circuit is three times the nominal
supply voltage. However, transient events prevent having such a
large output voltage. The new high-voltage driver topology offers a significant area reduction compared to a similar output
driver [4] with respect to the output stacked transistors. In [4]
not all of the output stacked transistors are switched from triode
region to cut-off and vice versa. Instead, they are switched from
triode region to a state in which they act as a diode. Therefore,
the voltage drop over these transistors is lower than if they were
in cut-off. This means that more stacked transistors are needed
to tolerate the same supply voltage. Moreover, the width of the
output transistors needs to be increased to achieve a comparable
on-resistance as the presented output driver.
One can derive a simplified formula for the efficiency of the
driver:
(1)
represents the load resistance driven by the
in which
represents the combined on-resistance of
output driver and
the stacked transistors. No dynamic power consumption is taken
into account. This is a reasonable assumption when the on-resistance is rather large. However, for a higher efficiency, dynamic
power consumption becomes a real issue and the efficiency must
, the ratio of
be checked after design. For a desired value of
the width and the length of the stacked output transistors is determined through the simplified formula of the resistance of a
transistor in triode region:
(2)
where is the number of stacked transistors per switch-block.
In this work, is three.
III. SELF-BIASED CASCODE TOPOLOGY
Fig. 2 shows the schematic of the self-biased cascode
topology of the n-switch block. The analysis and operation are
the same for the p-switch block since it is the complement of
the n-block. This topology sets the bias voltage of transistor
in two ways: through a resistive division comprised of
and
, triggered on by
, or by the gate voltage of
which
. For the analysis of the self-biased cascode
passes through
topology, two operating regimes must be considered: static and
transient.

577

Fig. 2. Schematic of the self-biased cascode topology.

Fig. 3. Transfer characteristic of an NMOS switch and the I

a fixed drainsource voltage.

curve for

A. Static Operation
In this section the two static states of the high-voltage
driver (high and low) and the transitions between them will be
discussed. Fig. 3 shows a transfer characteristic of an NMOS

curve for a fixed

transistor used as a switch and its
drainsource voltage. Since in this topology, all transistors are
used as switches, the different regions stated in this figure are
used to clarify the following analysis. A transistor in the cut-off
region corresponds to an open circuit and a transistor in the
triode region corresponds to a short circuit.
First, consider the case in which the output voltage switches
from low to high. In the previous state when the output was low,
, and
were in the triode region and
the transistors
and
were discharged. Initially, tranthe internal nodes
sistor
is in the cut-off region. As a consequence, node
is
and then slowly rises to
due to the
charged to
subthreshold current. To prevent oxide breakdown in
is set at a fixed voltage of
.
is now in the cut-off
region. Consequently, node
is charged to
. The
subthreshold current is again responsible for further charging
. To prevent oxide breakdown, now in
, the maxup to
is
.
is now in the cut-off reimum voltage on
gion. Since
and
both have a voltage drop of
from drain to source, the theoretical maximum output voltage
. During operation however, the drainsource
will be
will be lower than the nominal supply voltage in
voltage of
the high-output state. In this state, the output voltage is given by

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

and
. Fig. 4(b) shows a transient simulation of
division
the gate voltages of the output transistors.
B. Transient Operation

Fig. 4. Transient simulation of the voltage on the terminals of the stacked

output transistors. (a) Drain voltages of M ; M ; and M , (b) Gate voltages
of M ; M ; and M .

the resistive division of the on-resistance of the PMOS output

stacked transistors, which are in the triode region and the load
. This headroom will become useful for tranresistance,
sient operation as will be seen later on. Fig. 4(a) shows a transient simulation of the drain voltages of the output transistors.
is, in this state, given by a resistive division
The voltage on
. This resisbetween the output and the fixed bias voltage of
tive division of
and
is triggered on by
which is in the
and
sets
in the
triode region. The resistive division
cut-off region.
Next, consider the case in which the output switches from
and
were in the
high to low. In the previous state
is set
cut-off region and the output was high. First, transistor
is discharged.
in the triode region. As a consequence, node
was set at
enters the
Since the gate bias of
triode region and its gatesource voltage remains within limits.
is now discharged through
and
. Finally, the
Node
will be larger than its
and the
gatesource voltage of
, its gate
output is discharged. To reduce the oxide stress in
voltage must be lowered from
to
. The gate
is now directly given by the fixed bias voltage of
voltage of
which passes through
.
is in the triode region.
is
now in the cut-off region and consequently breaks the resistive

This section describes the problems and solutions during transient switching of the high-voltage output driver. The most critical transition for the n-switch block is the high-to-low transition
of the output. A low-to-high transition of node switches
from cut-off to the triode region. The faster the transition of ,
enters the triode region and the faster
gets disthe faster
is fixed, its gatesource
charged. Since the gate voltage of
voltage, and as a consequence, its state, is completely determined by the voltage on node . To avoid hot carrier effects in
, resulting from a large drainsource voltage, node
must
be discharged with the same speed as node . This is possible
for a relatively slow transition of . But, for a fast transition,
for entering from cut-off to the triode region
the delay of
results in an overshoot on its drainsource voltage. Therefore,
and
is added to soften the
a low-pass filter comprised of
transitions at . The same problem also occurs with transistor
. The transient event on the terminals of
is solved in two
ways. First, the voltage headroom, originating from the resistive division of the on-resistance with the output load, covers
for the transition into the triode region. Second,
the delay of
is added on top of the already quite large
an extra capacitor
. During a high-to-low transition
gatedrain capacitance of
switches from
of the output, the voltage on node
down to
. Therefore, the switching of node
helps
to discharge the output node due to the strong capacitive coupling. However, during a low-to-high transition of the output,
acts together with
the increased gatedrain capacitance of
and
as a high-pass filter. This results in
the resistances
an overshoot on the steady-state voltage of node . Therefore,
is added which acts as a low-pass filter for the
capacitance
transient overshoot on . The necessary capacitance value of
can be calculated in two ways: the time-domain approach
and the frequency-domain approach.
1) Time Domain: For the time-domain approach, consider
for the
Fig. 5, which shows a model of the bias circuit of
low-to-high transition. The assumption is made that the PMOS
stacked output transistors are already in the triode region and,
as a consequence, they can be represented by their accumulative on-resistance. The same assumption is made for the NMOS
stacked output transistors which are in the cut-off region.
is the voltage across
and
is the voltage across
.
(node ).
These two voltages define the gate voltage of
The electrical network can then be described by the following
system of differential equations:

(3)

(4)

SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m CMOS TECHNOLOGY

579

(13)
From (8), (9), (12), and the initial conditions, the constants
and
can be found:

(14)

Fig. 5. Model of the bias circuit of

for the low-to-high transition.

with
, and
following starting conditions:
In matrix form:

and with the

.

The voltage on node

corresponds with
in this model.
For a positive step function, the exponential terms in the solution
of (9) can lead to an overshoot if the signs of the products
and
are positive. One can see that the exponential term
always has a negative sign. This means
corresponding with
in (9)
that the contribution of this term in the solution of
can never lead to an overshoot on the steady-state solution. The
corresponding with has a negative
exponential term of
holds:
sign if the following condition for
(15)
Which results in
(16)

(5)
or
(6)

One can see from (14) that the exponential term of

corcan even be completely cancelled out if
responding with
is chosen.
2) Frequency Domain: For the frequency-domain approach,
consider the transfer function (TF) from out to in Fig. 5:
(17)

The steady-state solution of this system of differential equations

is the solution of (7):
For dc-operation this becomes
(7)

(18)
Therefore, the steady-state solution is

(8)

and
are the eigenvalues of matrix with their
Assume
and . The global solution of
accompagning eigenvectors
(6) can then be described by the following equation:
(9)
With, after some simplification,

:
(10)
(11)

and
(12)

which is the same as the steady-state solution from the time-domain approach. For the frequency behavior, one must consider
the following pole and zero:
(19)
(20)
A small
results in
which leads to the bode plot
of Fig. 6(a). In this graph, one can see that the gain for high
frequencies is larger than the dc-gain which can lead to voltage
is large
overshoots during transients. On the other hand, if
enough, the situation as shown in Fig. 6(b) is applicable. The
high-frequency gain is now lower than the dc-gain, which results
in a suppression of high-frequency transients. The requirement
can be rewritten as
. After
for a stable voltage on
some calculation, this results in
(21)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 6. Bode plot of the transfer function from out to g . (a) f

f .

> f

. (b) f

<

Fig. 7. Transient simulation of the gate voltage of transistor M for the cases
R C
R C ; R C
R C ; and R C
R C .

which is the same condition as in the time-domain approach (16). Fig. 7 demonstrates the importance of the
analysis results of (16) and (21). It shows a transient simfor three different cases:
ulation of the gate voltage of
and
. One
and
will
can see that the cases
result in a wrong operation point voltage, which causes oxide
.
breakdown in
Fig. 8 shows a simulation of the drainsource to gatesource
and
voltage transfer characteristic of the transistors
as they were defined in Fig. 2. Since the limit of 2.5 V is
only crossed by the drainsource voltage of transistor
in
transient operation, the risk of hot carrier degradation is minimized. The more the curves lean toward the bottom-left corner
of the figures, the lower the risk of hot carriers and vice versa.
This can intuitively be explained by the transistor biasing conditions. A large drainsource voltage creates a large electric field
across the channel resulting in hot carriers. For low gatesource
voltages, the transistor is off, resulting in no current and hence
will suffer the
no hot carriers. One can see that transistor
most hot carrier effects. However, since its drainsource voltage
overshoot during the high-to-low transition is less than 10% of
, thanks to the voltage headroom originating from the
resistive division of the on-resistance with the output load and
its channel is not minimal length, the hot carrier generation in
is kept low. Fig. 8 shows also that the high-to-low transition is more critical than the low-to-high transition, since the

Fig. 8. Simulation of the drain-source to gate-source voltage transfer

characteristic of the transistors: (a) M , (b) M , and (c) M .

high-to-low path leans more to the upper-right corner than the

low-to-high path. Moreover, the voltage overshoot is larger with
high-to-low transitions than with low-to-high transitions. This
can be clearly seen in Fig. 8(c). Fig. 9 shows a transient simuand
lation of the gatedrain voltage of the transistors
. Together with Fig. 8, one can see that the voltages across
each gate oxide never exceed the nominal supply voltage. In this
way, oxide breakdown is prevented and reliability is guaranteed.

SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m CMOS TECHNOLOGY

Fig. 11.

Fig. 9.
;M ;

581

Schematic of the driving circuit for the output transistors.

Transient simulation of the gatedrain voltage of the transistors

and M .

Fig. 12. Efficiency in function ofR .

Fig. 10.

Schematic of the high-voltage output driver.

IV. HIGH-VOLTAGE OUTPUT DRIVER DESIGN

Fig. 10 shows the schematic of the high-voltage
output driver. Three different supply voltages are needed:
and
. From (1) and (2) one can
calculate the width of the output transistors for an efficiency
of 90% and a load resistance of 50 . To reduce the effect of
hot carriers, the electrical field across the channel is lowered
by increasing the channel length. The length was chosen
arbitrarily at 0.8 m. This results in a width of 6.8 mm for
a PMOS output transistor and 1.6 mm for an NMOS output
transistor. These large transistors are driven from one square
wave input signal, which is split into two paths: one for
driving the NMOS transistor and one for driving the PMOS
transistor. Both paths pass through a tapered buffer for driving
the large load capacitance of the output transistors. The
upper path is upconverted to a higher voltage by means of
a simple resistive division between the input signal and the

supply of
. The driving circuit is shown in Fig. 11.
Fig. 12 shows the calculated efficiency of the high-voltage
output driver as a function of its on-resistance. One can see
(or a small width), (1) is applicable. But
that for large
for small
(or a large width) the efficiency drops rapidly,
since the dynamic power consumption becomes important.
After all, large transistors create large parasitics, such as the
n-wellp-substrate capacitance for the PMOS transistors.
The input capacitances of the output transistors also increase
, which leads to larger dynamic power
with decreasing
dissipation. Since these parasitics are known only after design
or even after layout (well capacitances), the efficiency must be
checked to see if the on-resistance is too small. All resistances
in the circuit are chosen high-ohmic to make sure that they do
not affect the static efficiency.
Fig. 13 shows a photograph of the realized prototype. The
area is 2.4 2.4 mm . Much care must be taken in the layout
of the metal layers in order to avoid electromigration. The technology used was a one-poly five-metal (1P5M) 0.25- m twinwell CMOS technology. This permits the connection of the bulk
of every transistor to its source in order to avoid large gatebulk
voltages. A disadvantage of this principle is that it results in substrate currents near each NMOS transistor. Since the substrate is
high-ohmic, special attention went to the prevention of latch-up.
Every transistor is surrounded by a full guard ring to make a
good well contact. Moreover, all NMOS transistors are encircled by an n-well biased at the highest supply voltage and all
PMOS transistors are encircled by a p-well biased at the lowest
supply voltage. In this way, substrate currents are drained by the

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 40, NO. 3, MARCH 2005

Fig. 15. Time-domain measurement with an input square wave of 10 MHz.

Fig. 13.

Chip photograph.

Fig. 16. Distortion measurement with a dual-tone sinusiod at 70 kHz and

250 kHz.

Fig. 14.

Cross section of a (a) PMOS and (b) NMOS transistor.

wells and the interaction between the transistors is minimized.

The output transistors occupy one half of the chip area to lower
the losses due to the substrate currents. A cross section of an
NMOS and a PMOS transistor is shown in Fig. 14.
V. MEASUREMENTS
A prototype has been processed in a mainstream 0.25- m
1P5M twin-well CMOS technology, which has a nominal
supply voltage of 2.5 V. During the measurements, a supply
voltage of 7.5 V was used and the output was loaded with
a resistance of 50 in parallel with a capacitance of 20 pF.
A square wave with a frequency of 10 MHz was applied to

the driver. The result is shown in Fig. 15. An output swing of

6.46 V was measured, which corresponds with an output power
of 208 mW delivered to the load resistance. Since the number of
stacked transistors is minimized for a supply voltage of 7.5 V,
the on-resistance can be as low as 5.9 . The delay through the
driver is 16 ns. Fig. 16 shows the intermodulation distortion
performance by applying a pulse width modulated (PWM)
signal at the input of the chip. The PWM signal was generated
single-bit converter. The input of this
by a fourth-order
converter is a dual-tone sine wave at 70 kHz and 250 kHz.
This distortion measurement is preferred above a harmonic
distortion measurement, since intermodulation products can
generate in-band distortion terms which cannot be filtered off.
An IM3 of 65 dB and an IM2 of 67 dB is obtained.
Still a major issue is whether the high-voltage output driver
is robust against hot carrier effects. In a first test performed in
this area, the driver was operated continuously for more than
two days at a supply voltage of 7.5 V delivering 208 mW in the
50- load resistance. No degradation of the performance was
seen after two days.
Table I summarizes the performance and process specifications.

SERNEELS et al.: A HIGH-VOLTAGE OUTPUT DRIVER IN A 2.5-V 0.25- m CMOS TECHNOLOGY

TABLE I
MEASURED PERFORMANCE AND PROCESS SPECIFICATIONS

583

Tim Piessens was born in Bornem, Belgium, in

1975. He received the Masters degree in electrical
engineering and the Ph.D. degree in electronics from
the Katholieke Universiteit Leuven (K. U. Leuven),
Heverlee, Belgium, in 1998 and 2003, respectively.
From 1998 to 2003, he worked as a Research
Assistant at the ESAT-MICAS Laboratory, K. U.
Leuven, on the development of highly efficient line
drivers for xDSL systems. In 2004, he co-founded
the company ICsense, which is a fabless microelectronics company specialized in integrated sensor
interface systems.

VI. CONCLUSION
In this paper, a 7.5-V output driver in a standard 2.5-V
0.25- m CMOS technology was presented. No extra process
steps were used. This opens the possibility for full integration of
a high-voltage, high-power output stage in a digital low-voltage
technology. The use of stacked devices with a self-biased cascode topology resulted in a reliable, linear high-voltage output
in a 50- load was
buffer. An output swing of about
reached with only three stacked transistors. This minimized the
area and resulted in an on-resistance of only 5.9 .
REFERENCES
[1] M. J. M. Pelgrom and E. C. Dijkmans, A 3=5 V compatible I/O buffer,
IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 823825, Jul. 1995.
[2] G. Singh, A high speed 3.3 V IO buffer with 1.9 V tolerant CMOS
process, in Proc. Eur. Solid-State Circuits Conf., 1998, pp. 128131.
[3] H. Sanchez, J. Siegel, C. Nicoletta, J. Alvarez, J. Nissen, and G. Gerosa,
A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 m 3.5
nm tox 1.8 V CMOS technology, in IEEE ISSCC Dig. Tech. Papers,
1999, pp. 276277.
[4] A.-J. Annema, G. Geelen, and P. de Jong, 5.5 V I/O in a 2.5 V in a 0.25
m CMOS technology, IEEE J. Solid-State Circuits, vol. 36, no. 3, pp.
528538, Mar. 2001.
[5] B. Serneels, T. Piessens, M. Steyaert, and W. Dehaene, A high-voltage
output driver in a standard 2.5 V 0.25 m CMOS technology, in IEEE
ISSCC Dig. Tech. Papers, 2004, pp. 146147.

Bert Serneels (S02) was born in Bonheiden, Belgium, in 1978. He received the Masters degree in
electrical engineering from the Katholieke Universiteit Leuven (K. U. Leuven), Heverlee, Belgium, in
2002.
Currently, he is a Research Assistant at the
ESAT-MICAS Laboratory, K. U. Leuven, where he
is working toward the Ph.D. degree on the design of
highly efficient line drivers for xDSL systems.

Michiel Steyaert (S85A89SM92F04) was

born in Aalst, Belgium, in 1959. He received the
Masters degree in electricalmechanical engineering and the Ph.D. degree in electronics from
the Katholieke Universiteit Leuven (K. U. Leuven),
Heverlee, Belgium, in 1983 and 1987, respectively.
From 1983 to 1986, he obtained an IWNOL fellowship (Belgian National Fundation for Industrial
Research), which allowed him to work as a Research
Assistant at the Laboratory ESAT at K. U. Leuven.
In 1987, he was responsible for several industrial
projects in the field of analog micropower circuits at the Laboratory ESAT as
an IWONL Project Researcher. In 1988, he was a Visiting Assistant Professor
at the University of California, Los Angeles. In 1989, he was appointed by the
National Fund of Scientific Research (Belgium) as Research Associate, in 1992
as a Senior Research Associate, and in 1996 as a Research Director at the Laboratory ESAT, K. U. Leuven. Between 1989 and 1996, he was also a part-time
Associate Professor, and since 1997, he has become an Associate Professor at
the K. U. Leuven. His current research interests are in high-performance and
high-frequency analog integrated circuits for telecommunication systems and
analog signal processing.
Prof. Steyaert received the 1990 and 2001 European Solid-State Circuits Conference Best Paper Award, the 1995 and 1997 ISSCC Evening Session Award,
the 1999 IEEE Circuits and Systems Society GuilleminCauer Award and the
1991 and the 2000 NFWO Alcatel-Bell-Telephone Award for innovative work
in integrated circuits for telecommunications.

Wim Dehaene (S88M97SM04) was born in

Nijmegen, The Netherlands, in 1967. He received
the M.Sc. degree in electrical and mechanical engineering in 1991 from the Katholieke Universiteit
Leuven (K. U. Leuven), Heverlee, Belgium. In
November 1996, he received the Ph.D. degree from
the K. U. Leuven. His thesis was entitled CMOS
integrated circuits for analog signal processing in
hard disk systems.
After receiving the M.Sc. degree, he was a Research Assistant at the ESAT-MICAS Laboratory,
K. U. Leuven. His research involved the design of novel CMOS building
blocks for hard disk systems. The research was first sponsored by the IWONL
(Belgian Institute for Science and Research in Industry and agriculture) and
later by the IWT (the Flemish institute for Scientific Research in the Industry).
In November 1996, he joined Alcatel Microelectronics, Belgium, where he
was a Senior Project Leader for the feasibility, design, and development
of mixed-mode systems-on-chip. The application domains were telephony,
xDSL, and high-speed wireless LAN. In July 2002, he joined the staff of the
ESAT-MICAS Laboratory of the K. U. Leuven where he is now an Associate
Professor. His research is in low-power mixed-mode systems-on-chip. He
teaches several classes on digital circuit and system design.