PIC16F917/916/914/913

12.0

ANALOG-TO-DIGITAL
CONVERTER (A/D) MODULE

The Analog-to-Digital converter (A/D) allows conversion

of an analog input signal to a 10-bit binary representation
of that signal. The PIC16F917/916/914/913 has up to
eight analog inputs, multiplexed into one sample and hold
circuit. The output of the sample and hold is connected to
the input of the converter. The converter generates a
binary result via successive approximation and stores the
result in a 10-bit register. The voltage reference used in
the conversion is software selectable to either VDD or a
voltage applied by the VREF pin. Figure 12-1 shows the
block diagram of the A/D on the PIC16F917/916/914/913.

FIGURE 12-1:

A/D BLOCK DIAGRAM

VDD
VCFG0 = 0
VREF+

RA0/AN0/C1-/SEG12
RA1/AN1/C2-/SEG7
RA2/AN2/C2+/VREF-/COM2
RA3/AN3/C1+/VREF+/COM3(2)/SEG15
RA5/AN4/C2OUT/SS/SEG5

A/D
10

GO/DONE
ADFM

RE0/AN5/SEG21(1)
RE1/AN6/SEG22(1)
RE2/AN7/SEG23(1)

10

ADON
VSS

ADRESH ADRESL

VCFG1 = 0

CHS<2:0>
VREF-

Note 1:
2:

VCFG0 = 1

VCFG1 = 1

These channels are only available on PIC16F914/917 devices.

COM3 available on RA3 only on PIC16F913/916 devices.

2005 Microchip Technology Inc.

Preliminary

DS41250E-page 143

PIC16F917/916/914/913
12.1

A/D Configuration and Operation

There are three registers available to control the

functionality of the A/D module:
1.
2.
3.

ANSEL (Register 12-1)

ADCON0 (Register 12-2)
ADCON1 (Register 12-3)

12.1.1

ANALOG PORT PINS

The ANS<7:0> bits (ANSEL<7:0>) and the TRIS bits

control the operation of the A/D port pins. Set the
corresponding TRIS bits to set the pin output driver to
its high-impedance state. Likewise, set the corresponding ANSEL bit to disable the digital input buffer.
Note:

12.1.2

Analog voltages on any pin that is defined

as a digital input may cause the input
buffer to conduct excess current.

12.1.4

CONVERSION CLOCK

The A/D conversion cycle requires 11 TAD. The source

of the conversion clock is software selectable via the
ADCS bits (ADCON1<6:4>). There are seven possible
clock options:

FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (dedicated internal oscillator)

For correct conversion, the A/D conversion clock

(1/TAD) must be selected to ensure a minimum TAD of
1.6 s. Table 12-1 shows a few TAD calculations for
selected frequencies.

CHANNEL SELECTION

There are up to eight analog channels on the

PIC16F917/916/914/913, AN<7:0>. The CHS<2:0> bits
(ADCON0<4:2>) control which channel is connected to
the sample and hold circuit.

12.1.3

VOLTAGE REFERENCE

There are two options for each reference to the A/D

converter, VREF+ and VREF-. VREF+ can be connected to
either VDD or an externally applied voltage. Alternatively,
VREF- can be connected to either VSS or an externally
applied voltage. VCFG<1:0> bits are used to select the
reference source.

TABLE 12-1:

TAD vs. DEVICE OPERATING FREQUENCIES

A/D Clock Source (TAD)

Device Frequency

Operation

ADCS<2:0>

20 MHz

5 MHz

4 MHz

1.25 MHz

2 TOSC

000

100 ns(2)

400 ns(2)

500 ns(2)

1.6 s

4 TOSC

100

200

ns(2)

ns(2)

s(2)

3.2 s

8 TOSC

001

400 ns(2)

1.6 s

2.0 s

6.4 s

101

(2)

3.2 s

4.0 s

12.8 s(3)

16 TOSC

800 ns

800

8.0 s

25.6 s(3)

12.8 s(3)

16.0 s(3)

51.2 s(3)

s(1,4)

s(1,4)

2-6 s(1,4)

32 TOSC

010

1.6 s

6.4 s

64 TOSC

110

3.2 s

A/D RC
Legend:
Note 1:
2:
3:
4:

x11

2-6

s(1,4)

1.0

2-6

(3)

2-6

Shaded cells are outside of recommended range.

The A/D RC source has a typical TAD time of 4 s for VDD > 3.0V.
These values violate the minimum required TAD time.
For faster conversion times, the selection of another clock source is recommended.
When the device frequency is greater than 1 MHz, the A/D RC clock source is only recommended if the
conversion will be performed during Sleep.

DS41250E-page 144

Preliminary

2005 Microchip Technology Inc.

PIC16F917/916/914/913
12.1.5

STARTING A CONVERSION

The A/D conversion is initiated by setting the

GO/DONE bit (ADCON0<1>). When the conversion is
complete, the A/D module:
Clears the GO/DONE bit
Sets the ADIF flag (PIR1<6>)
Generates an interrupt (if enabled)
If the conversion must be aborted, the GO/DONE bit
can be cleared in software. The ADRESH:ADRESL
registers will not be updated with the partially complete
A/D
conversion
sample.
Instead,
the
ADRESH:ADRESL registers will retain the value of the
previous conversion. After an aborted conversion, a
2 TAD delay is required before another acquisition can
be initiated. Following the delay, an input acquisition is
automatically started on the selected channel.
Note:

The GO/DONE bit should not be set in the

same instruction that turns on the A/D.

FIGURE 12-2:

A/D CONVERSION TAD CYCLES

TCY TO TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11
b9

b8

b7

b6

b5

b4

b3

b2

b1

b0

Conversion Starts
Holding Capacitor is Disconnected from Analog Input (typically 100 ns)
Set GO/DONE bit

12.1.6

ADRESH and ADRESL registers are loaded,

GO/DONE bit is cleared,
ADIF bit is set,
Holding Capacitor is Connected to Analog Input

CONVERSION OUTPUT

The A/D conversion can be supplied in two formats: left

or right shifted. The ADFM bit (ADCON0<7>) controls
the output format. Figure 12-3 shows the output
formats.

FIGURE 12-3:

10-BIT A/D RESULT FORMAT

ADRESH

(ADFM = 0)

ADRESL

MSB

LSB

bit 7

bit 0

bit 7

10-bit A/D Result

(ADFM = 1)

bit 0
Unimplemented: Read as 0

MSB
bit 7

LSB
bit 0

Unimplemented: Read as 0

2005 Microchip Technology Inc.

Preliminary

bit 7

bit 0

10-bit A/D Result

DS41250E-page 145

PIC16F917/916/914/913
REGISTER 12-1:

ANSEL ANALOG SELECT REGISTER (ADDRESS: 91h)

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

R/W-1

ANS7(2)

ANS6(2)

ANS5(2)

ANS4

ANS3

ANS2

ANS1

ANS0

bit 7
bit 7-0:

bit 0

ANS<7:0>: Analog Select bits(2)

Select between analog or digital function on pins AN<7:0>, respectively.
1 = Analog input. Pin is assigned as analog input.(1)
0 = Digital I/O. Pin is assigned to port or special function.
Note 1: Setting a pin to an analog input automatically disables the digital input circuitry,
weak pull-ups, and interrupt-on-change if available. The corresponding TRIS bit
must be set to Input mode in order to allow external control of the voltage on the pin.
2: ANS<7:5> on PIC16F914/917 only; forced 0 on PIC16F913/916.
Legend:

REGISTER 12-2:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

- n = Value at POR

1 = Bit is set

0 = Bit is cleared

x = Bit is unknown

ADCON0 A/D CONTROL REGISTER (ADDRESS: 1Fh)

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

ADFM

VCFG1

VCFG0

CHS2

CHS1

CHS0

GO/DONE

ADON

bit 7

bit 0

bit 7

ADFM: A/D Result Formed Select bit

1 = Right justified
0 = Left justified

bit 6

VCFG1: Voltage Reference bit

1 = VREF- pin
0 = VSS

bit 5

VCFG0: Voltage Reference bit

1 = VREF+ pin
0 = VDD

bit 4-2

CHS<2:0>: Analog Channel Select bits

000 =
001 =
010 =
011 =
100 =
101 =
110 =
111 =

Channel 00 (AN0)
Channel 01 (AN1)
Channel 02 (AN2)
Channel 03 (AN3)
Channel 04 (AN4)
Channel 05 (AN5)
Channel 06 (AN6)
Channel 07 (AN7)

bit 1

GO/DONE: A/D Conversion Status bit

1 = A/D conversion cycle in progress. Setting this bit starts an A/D conversion cycle.
This bit is automatically cleared by hardware when the A/D conversion has completed.
0 = A/D conversion completed/not in progress

bit 0

ADON: A/D Conversion Status bit

1 = A/D converter module is operating
0 = A/D converter is shut off and consumes no operating current
Legend:

DS41250E-page 146

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

- n = Value at POR

1 = Bit is set

0 = Bit is cleared

Preliminary

x = Bit is unknown

2005 Microchip Technology Inc.

PIC16F917/916/914/913
REGISTER 12-3:

ADCON1 A/D CONTROL REGISTER 1 (ADDRESS: 9Fh)

U-0

R/W-0

R/W-0

R/W-0

U-0

U-0

U-0

U-0

ADCS2

ADCS1

ADCS0

bit 7

bit 0

bit 7

Unimplemented: Read as 0

bit 6-4

ADCS<2:0>: A/D Conversion Clock Select bits

000 = FOSC/2
001 = FOSC/8
010 = FOSC/32
x11 = FRC (clock derived from a dedicated internal oscillator = 500 kHz max)
100 = FOSC/4
101 = FOSC/16
110 = FOSC/64

bit 3-0

Unimplemented: Read as 0
Legend:
R = Readable bit

W = Writable bit

U = Unimplemented bit, read as 0

- n = Value at POR

1 = Bit is set

0 = Bit is cleared

2005 Microchip Technology Inc.

Preliminary

x = Bit is unknown

DS41250E-page 147

PIC16F917/916/914/913
12.1.7

CONFIGURING THE A/D

EXAMPLE 12-1:

After the A/D module has been configured as desired,

the selected channel must be acquired before the
conversion is started. The analog input channels must
have their corresponding TRIS bits selected as inputs.
To determine sample time, see Section 19.0 Electrical
Specifications. After this sample time has elapsed, the
A/D conversion can be started.
These steps should be followed for an A/D conversion:
1.

2.

3.
4.
5.

6.
7.

Configure the A/D module:

Configure analog/digital I/O (ANSEL)
Configure voltage reference (ADCON0)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON1)
Turn on A/D module (ADCON0)
Configure A/D interrupt (if desired):
Clear ADIF bit (PIR1<6>)
Set ADIE bit (PIE1<6>)
Set PEIE and GIE bits (INTCON<7:6>)
Wait the required acquisition time.
Start conversion:
Set GO/DONE bit (ADCON0<1>)
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
(with interrupts disabled); OR
Waiting for the A/D interrupt
Read A/D Result register pair
(ADRESH:ADRESL); clear bit ADIF if required.
For next conversion, go to step 1 or step 2 as
required. The A/D conversion time per bit is
defined as TAD. A minimum wait of 2 TAD is
required before the next acquisition starts.

DS41250E-page 148

A/D CONVERSION

;This code block configures the A/D

;for polling, Vdd reference, R/C clock
;and RA0 input.
;
;Conversion start and wait for complete
;polling code included.
;
BSF
STATUS,RP0
;Bank 1
MOVLW B01110000
;A/D RC clock
MOVWF ADCON1
BSF
TRISA,0
;Set RA0 to input
BSF
ANSEL,0
;Set RA0 to analog
BCF
STATUS,RP0
;Bank 0
MOVLW B10000001
;Right, Vdd Vref, AN0
MOVWF ADCON0
CALL
SampleTime
;Wait min sample time
BSF
ADCON0,GO
;Start conversion
BTFSC ADCON0,GO
;Is conversion done?
GOTO
$-1
;No, test again
MOVF
ADRESH,W
;Read upper 2 bits
MOVWF RESULTHI
BSF
STATUS,RP0
;Bank 1
MOVF
ADRESL,W
;Read lower 8 bits
MOVWF RESULTLO

Preliminary

2005 Microchip Technology Inc.

PIC16F917/916/914/913
12.2

A/D Acquisition Requirements

For the A/D converter to meet its specified accuracy,

the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 12-4. The
source impedance (RS) and the internal sampling
switch (RSS) impedance directly affect the time
required to charge the capacitor CHOLD. The sampling
switch (RSS) impedance varies over the device voltage
(VDD), see Figure 12-4. The maximum recommended impedance for analog sources is 10 k.

EQUATION 12-1:

As the impedance is decreased, the acquisition time

may be decreased. After the analog input channel is
selected (changed), this acquisition must be done
before the conversion can be started.
To calculate the minimum acquisition time,
Equation 12-1 may be used. This equation assumes
that 1/2 LSb error is used (1024 steps for the A/D). The
1/2 LSb error is the maximum error allowed for the A/D
to meet its specified resolution.
To calculate the minimum acquisition time, TACQ, see
the PICmicro Mid-Range MCU Family Reference
Manual (DS33023).

ACQUISITION TIME

T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + [ ( Temperature - 25C ) ( 0.05s/C ) ]
Where CHOLD is charged to within 1/2 lsb:

1
V AP P LIED 1 ------------ = V C HOLD
2047

;[1] VCHOLD charged to within 1/2 lsb

----------

RC
V AP P LIED 1 e = V CHOLD

T C

;[2] VCHOLD charge response to VAPPLIED

---------

1
RC
V AP P LIED 1 e = V A PP LIE D 1 ------------
2047

Tc

;combining [1] and [2]

Solving for TC:

T C = C HOLD ( R IC + R SS + R S ) ln(1/2047)
= 10pF ( 1k + 7k + 10k ) ln(0.0004885)
= 1.37 s
Therefore:
T ACQ = 2S + 1.37S + [ ( 50C- 25C ) ( 0.05S /C ) ]
= 4.67S

Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.

2005 Microchip Technology Inc.

Preliminary

DS41250E-page 149

PIC16F917/916/914/913
FIGURE 12-4:

ANALOG INPUT MODEL

VDD
RS

VT = 0.6V

ANx
CPIN
5 pF

VA

RIC 1k

Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
= 10 pF

I LEAKAGE
500 nA

VT = 0.6V

VSS

6V
5V
VDD 4V
3V
2V

Legend: CPIN
= Input Capacitance
VT
= Threshold Voltage
I LEAKAGE = Leakage current at the pin due to
various junctions
RIC
= Interconnect Resistance
SS
= Sampling Switch
CHOLD
= Sample/Hold Capacitance (from DAC)

12.3

A/D Operation During Sleep

The A/D converter module can operate during Sleep.

This requires the A/D clock source to be set to the
internal oscillator. When the RC clock source is
selected, the A/D waits one instruction before starting
the conversion. This allows the SLEEP instruction to be
executed, thus eliminating much of the switching noise
from the conversion. When the conversion is complete,
the GO/DONE bit is cleared and the result is loaded
into the ADRESH:ADRESL registers. If the A/D

FIGURE 12-5:

RSS

5 6 7 8 9 10 11
Sampling Switch
(k)

interrupt is enabled, the device awakens from Sleep. If

the GIE bit (INTCON<7>) is set, the program counter is
set to the interrupt vector (0004h). If GIE is clear, the
next instruction is executed. If the A/D interrupt is not
enabled, the A/D module is turned off, although the
ADON bit remains set.
When the A/D clock source is something other than
RC, a SLEEP instruction causes the present conversion
to be aborted, and the A/D module is turned off. The
ADON bit remains set.

A/D TRANSFER FUNCTION

Full-Scale Range

3FFh
3FEh
3FDh
3FCh
3FBh

1/2 LSB Ideal

004h
003h
002h
001h
000h

Full-Scale
Transition

Analog Input
1/2 LSB Ideal

Zero-Scale

DS41250E-page 150

Center of
Full-Scale Code

Zero-Scale
Transition

Preliminary

VREF

A/D Output

1 LSB Ideal

2005 Microchip Technology Inc.

PIC16F917/916/914/913
12.4

Effects of Reset

A device Reset forces all registers to their Reset state.

Thus, the A/D module is turned off and any pending
conversion is aborted. The ADRESH:ADRESL
registers are unchanged.

TABLE 12-2:
Addr

Name

SUMMARY OF A/D REGISTERS

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Value on:
POR, BOR

Value on
all other
Resets

05h

PORTA

RA7

RA6

RA5

RA4

RA3

RA2

RA1

RA0

xxxx xxxx

uuuu uuuu

09h

PORTE

RE3

RE2

RE1

RE0

---- xxxx

---- uuuu

0Bh/
8Bh

INTCON

GIE

PEIE

T0IE

INTE

RBIE

T0IF

INTF

RBIF

0000 000x

0000 000x

EEIF

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

0Ch

PIR1

1Eh

ADRESH

Most Significant 8 bits of the left justified A/D result or 2 bits of the right justified result

0000 0000

0000 0000

xxxx xxxx

uuuu uuuu

1Fh

ADCON0

ADFM

VCFG1

VCFG0

CHS2

CHS1

CHS0

GO/DONE

ADON

0000 0000

0000 0000

85h

TRISA

TRISA7

TRISA6

TRISA5

TRISA4

TRISA3

TRISA2

TRISA1

TRISA0

1111 1111

1111 1111

89h

TRISE

TRISE3

TRISE2

TRISE1

TRISE0

---- 1111

---- 1111

8Ch

PIE1

EEIE

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

0000 0000

0000 0000

91h

ANSEL

ANS7

ANS6

ANS5

ANS4

ANS3

ANS2

ANS1

ANS0

1111 1111

1111 1111

9Eh

ADRESL

9Fh

ADCON1

Legend:

Least Significant 2 bits of the left justified A/D result or 8 bits of the right justified result

ADCS2

ADCS1

ADCS0

xxxx xxxx

uuuu uuuu

-000 ----

-000 ----

x = unknown, u = unchanged, - = unimplemented read as 0. Shaded cells are not used for A/D module.

2005 Microchip Technology Inc.

Preliminary

DS41250E-page 151