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Bharadwaj Amrutur
ECE Dept.
IISc Bangalore.
Outline
References:
Topics
Memory hierarchy
Cache
Main Memory
Disk
Virtual memory
Power considerations
Multi-core considerations
MemOp
Processor
Address
Memory
WriteData
ReadData
The Gap
CPU
Moores Law
100
10
1
Less Law?
Proc
60%/yr.
Processor-Memory
Performance Gap:
(grows 50% / year)
DRAM
DRAM
7%/yr.
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993
1994
1995
1996
1997
1998
1999
2000
Performance
1000
From Kubiatowicz/UCB
Caches
Processor Registers
L1 $
Bigger
Faster
L2 $
Main Memory (DRAM)
Disk
5
PCB
Chip/
Package
<1mm
Chip
Proc
16-128 64-bit
Regs
Few mm
4KB-32KB
L1 $
1MB - 8MB
L2 $
128MB - 4GB
Many Inches
80GB-few TB
Disk
Memory Hierarchy
Exercise
Which is better?
Register File
RWL0
WWL0
Read
Decoder
Write
Decoder
RWL31
W63
W0
Read
Address
R0
WWL31
R63
Write
8
Address
Register File
Wire dominated
Register file cell can be 10x bigger than SRAM cell
(used in L1/L2 cache)
Unlike caches
Power cost
Cache concept
Main Memory
Cache
10
ALU ops
MemAccess
CPU time =IC
CPI Aluops
AMAT Cycletime
Instr
Inst
Average Memory Access Time (AMAT) is given as:
AMAT=HitTimeMissRateMissPenalty
HitTime and MissPenalty are in number of clock cycles
IC is Instruction Count in the program
To reduce AMAT, reduce HitTime, MissRate and MissPenalty
HitTime is usually the lowest possible of 1 cycle
MissPenalty is a function of the upper levels of the memory hierarchy
MissRate is a function of Cache Size & Associativity
which also impacts Cycletime : Hence an optimization problem
11
Exercise
12
Cache issues
What to do on a write?
13
Main Memory
0 1 2 3 4 5 6 7 8 9 10 111213 14 15
Cache
0 1 2 3
The main memory
blocks which map
to specific cache blocks
are:
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
Main Memory
0 1 2 3 4 5 6 7 8 9 10 111213 14 15
Cache
0 1 2 3
The main memory
blocks which map
to specific cache blocks
are:
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
Main Memory
0 1 2 3 4 5 6 7 8 9 10 111213 14 15
31
0
Tag
Cache Tag
CacheIndex ByteSel
Cache Data
0 1 2 3
The main memory
blocks which map
to specific cache blocks
are:
0
4
8
12
1
5
9
13
2
6
10
14
3
7
11
15
16
Tag
Decoder
Data
=
Hit/Miss
What is missing?
31
0
Tag
CacheIndex ByteSel
17
Valid
Tag
Decoder
Data
=
Hit/Miss
31
0
Tag
CacheIndex ByteSel
18
Main Memory
0 1 2 3 4 5 6 7 8 9 10 111213 14 15
Set 0 Set 1
Cache
0 1 2 3
The main memory
blocks which map
to specific cache blocks
are:
0
4
8
12
2
6
10
14
1
5
9
13
3
7
11
15
19
Main Memory
0 1 2 3 4 5 6 7 8 9 10 111213 14 15
Set 0 Set 1
Cache
0 1 2 3
The main memory
blocks which map
to specific cache blocks
are:
0
4
8
12
2
6
10
14
1
5
9
13
3
7
11
15
20
0
CacheIndex ByteSel
Tag
Valid
Decoder
Tag
Data
Valid
Decoder
Tag
Tristate Driver
Hit/Miss_Set0
Exercises:
a) Complete the wiring
b) How do you generate the final Hit/Miss signal
c) Extend the design to a Fully Associative Cache
d) What happens to MissRate with associativity
e) What happens to MissRate with size
f) What happens to cycle time with Associativity and Size?
Data
Tristate Driver
Hit/Miss_Set1
21