14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum

FPGA Realization of Space-Vector Pulse Width Modulation for a 3-Level

Inverter
Muhamed Shereef1 , Shiny.G2
Power Electronics Research Laboratory
Dept. of Electronics and Communication Engineering
College of Engineering Trivandrum, Kerala, India
srfmlp@gmail.com1

Abstract
A simplified space-vector pulse width modulation
(SVPWM) scheme for a 3-level inverter is presented. The
method involves the mapping of reference vector in the
space vector diagram of 3-level inverter to a 2-level inverter.
60 coordinate system is used to represent space vectors instead of using cartesian coordinate system. In 60 coordinate system only integer coordinates are involved. So the
computational complexity is reduced. The proposed scheme
is simulated and verified using Xilinx system generator software.

1. Introduction
Multilevel inverters are widely used in industrial drive
applications due to their ability to produce waveforms with
improved harmonic spectrum [1, 2]. Multi level inverters
can produce variable voltages and frequencies from discrete
voltage levels using pulse width modulation (PWM) strategies. Several techniques have been developed for the implementation of PWM [3, 4]. The two main methods are Sine
triangle Pulse width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM) [5, 6]. SPWM is
the simple and widely used scheme which generates PWM
signals by comparison of level shifted triangular carrier signals with a sinusoidal reference waveform [7, 8]. SVPWM
involves synthesising of reference sinusoidal voltage by
switching amoung the nearest three voltage spacevectors.
SVPWM is the best technique to implement PWM due to
following advantages. 1) higher o/p voltage for the same
dc-bus voltage 2) lower switching losses and 3) Better harmonic performance.
Implementation of SVPWM scheme involves 1.sector
identification 2.determination of nearest voltage space vectors to be switched 3.determination of duration of each
switching voltage space vectors 4.determination of an op-

timum switching sequence. A new approach for sector

identification using fractal concept is proposed in [9]. The
scheme in [9] uses cartesian coordinate system for the representation of space vectors. SVPWM scheme based on 60
coordinate system has been proposed in [10, 11, 12, 13].
For the implementation of SVPWM techniques Digital
Signal Processors (DSP) are widely used [14].But DSP executes control procedures sequentially using their mathematically oriented resources. So the mutual influences of
various control procedures should no longer be neglected
in high sampling rate applications. But differ from DSP
FPGA can execute control procedures concurrently. Due
to its powerful calculation ability and flexibility, FPGA is
considered as an appropriate solution to boost system performance of a digital controller including an SVPWM algorithm [15, 16, 17].
This paper proposes the implementation of SVPWM algorithm for a 3-level inverter based on 60 coordinate system using FPGA. As compared to cartesian coordinate system the representation of space vector using 60 coordinate
system greately reduces computational complexity since
only integer coordinates are involved.

2. Proposed Scheme
SVPWM involves synthesising of reference sinusoidal
voltage(Vref ) by switching amoung the nearest three voltage space vectors. In the proposed work 60 coordinate
system is used to represent the space vectors. Suppose
Va , Vb and Vc represents the instantaneous amplitudes of
three phase reference sinusoid, 60 coordinates (m, n) of
Vref can be found using the equations given below,
Vm = Va Vb

(1)

Vn = Vb Vc

(2)

(m, n) coordinates are normalized using the division by

Vdc /(l 1). Where Vdc is the d.c link voltage and l is the

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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum

number of levels of inverter. Space vector representation

of a 3-level inverter using 60 coordinate system is shown
Figure. 1

Table 1. Sector identification (1=Satisfy, 0=Notsatisfy, =Dont

care)

Sector
1
2
3
4
5
6

Vmm 0
1
0
0
0
1
1

Vnm 0
1
1
1
0
0
0

|Vmm | |Vnm |

0
1

0
1

Determination of sub hexagon to which Vref belongs.

Mapping of Vref into the inner hexagon.
Find the sector of inner hexagon to which the mapped
reference vector Vrefm belongs.
Determination of duration of switching voltage space
vectors.
Determination of an optimum switching sequence.
Determination of actual switching vectors by adding
the switching vector corresponds to the sub hexagon
center.

Figure 1. Space vector representation of a 3-level inverter in 60

coordinate system

The space vector diagram of a three-level inverter can

be viewed as the composition of one inner hexagon and
six outer sub hexagons that are the space vector diagrams
of conventional two-level inverters. Each of these six sub
hexagons, constitutes the space vector diagram of a 3-level
inverter, centers on the six apexes of the inner hexagon. Figure. 2 shows the sub hexagon centers of 3-level inverter.

2.1. Sub Hexagon Center Identification

Sub hexagon center closest to the tip of Vref is determined by comparing (m, n) coordinates of Vref with each
sub hexagon center. Comparison is done by calculating
the distance from (m, n) coordinates of Vref to each sub
hexagon center using the equation
p
d = (Vm Vmh )2 + (Vn Vnh )2 + (Vm Vmh )(Vn Vnh )
(3)
where Vmh & Vnh are the corresponding sub hexagon center. The sub hexagon center with least value of d is selected.

2.2. Mapping to 2-level space vector

The hexagon center closest to the tip of Vref is subtracted from the respective (m, n) coordinates of Vref . Suppose Vref is located in sub hexagon with center B as in
Figure. 3 then the new coordinates of mapped reference
vector(Vref m ) can be calculated as

Figure 2. Space vector of a 3-level inverter showing Sub hexagon

centers

Steps involved in the implementation of SVPWM are

Vmm = Vm 0

(4)

Vnm = Vn 1

(5)

The sector to which the Vref m belongs can be found using Table. 1
Once the sector of operation is identified phase voltage switching timings of switching vectors can be found
as in Table. 2. It should be ensured the selected vectors are
switched in an optimum sequence so that only one switching occurs when the inverter changes its state.

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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum

FPGA. Coupled with a capability for implementing highly

parallel arithmetic architectures, this makes the FPGA ideally suited for creating high-performance PWM controllers.
Though VHDL provides many high level abstractions and
language constructs for simulation, its synthesizable subset
is far too restrictive for system design. System Generator
is a software tool for modeling and designing FPGA-based
DSP systems in Simulink. The tool presents a high level abstract view of a DSP system, yet nevertheless automatically
maps the system to a faithful hardware implementation. The
most significant is that System Generator provides these services without substantially compromising either the quality
of the abstract view or the performance of the hardware implementation.

3.1. System Generator

Figure 3. Mapping of Vref in to inner hexagon

Table 2. Equations for determining T1 and T2 for a two level inverter

Sector
1
2
3
4
5
6

T1
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm

T2
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )
Ts Vnm
Ts Vmm
Ts (Vmm + Vnm )

2.3. Generation of Actual Switching Vector

Actual switching vector is generated by adding back the
hexagon center to the calculated switching vectors as shown
in Figure. 4.

Simulink provides a powerful high level modeling environment for DSP systems, and consequently is idely used
for algorithm development and verification. System Generator maintains an abstraction level very much in keeping
with the traditional Simulink block sets, but at the same time
automatically translates designs into hardware implementations that are faithful, synthesizable, and efficient [18].
The implementation is faithful in that the system model
and hardware implementation are bit-identical and cycleidentical at ample times defined in Simulink. The implementation is made efficient through the instantiation of intellectual property (IP) blocks that provide a range of functionality from arithmetic operations to complex DSP functions [18]. These IP blocks have been carefully designed
to run at high speed and to be area efficient. In System
Generator, the capabilities of IP blocks have been extended
transparently and automatically to fit gracefully into a system level framework. For example, although the underlying IP blocks operate on unsigned integers, System Generator allows signed and unsigned fixed point numbers to be
used, including saturation arithmetic and rounding. Userdefined IP blocks can be incorporated into a System Generator model as black boxes which will be embedded by the
tool into the HDL implementation of the design.

4. Modeling with system genereator

Figure 4. Generation of Actual switching vector

3. FPGA Implementation
Field-Programmable Gate Arrays (FPGAs) have become
key components in implementing high performance digital
signal processing (DSP) systems [17]. The memory bandwidth of a modern FPGA far exceeds that of a microprocessor or DSP running at clock rates two to ten times that of the

Before developing the hardware circuit for power, control and isolation circuit based on the FPGA, the entire
system is generated with the aid of simulation package
simulink/system generator for FPGA in order to verify the
pulses and the patterns of the output pulses. The creation of
a DSP design begins with a mathematical description of the
operations needed and concludes with a hardware realization of the algorithm [18]. The hardware implementation is
rarely faithful to the original functional description instead
it is faithful enough. The challenge is to make the hardware
area and speed efficient while still producing acceptable re-

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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum

Table 3. Status of the top switches of each Inverter during different

Voltage levels (For A-phase)

Inverter-1
OFF
OFF
ON

Inverter-2
OFF
ON
ON

VA0 O
0
Vdc /2
Vdc

Realized switching level

0
1
2

Figure 6. Simulation model

Figure 5. 3-level Inverter by Cascading two 2-level Inverters

sults. In a typical design flow, a flow supported by System

Generator the following steps occur:
1. Describe the algorithm in mathematical terms
2. Realize the algorithm in the design environment, initially using double precision

Figure 7. Switching signals generated for 2-level operation: Top 3traces for Inverter-1 & Lower 3-traces for Inverter-2 (Modulation
index 0.25)

3. Trim double precision arithmetic down to fixed point

4. Translate the design into efficient hardware
Step 4 is error prone because it can be difficult to guarantee the hardware implements the design faithfully. System
Generator eliminates this concern by automatically generating a faithful hardware implementation.

5. Simulation and Results

5.1. 3-Level Inverter Configuration
3-Level Inverter is achieved by cascading two 2-level Inverters having same D.C link voltage of Vdc /2 as shown in
Figure. 5.
VAO , VBO and VCO represents the pole voltages of
Inverter-1. VA0 O , VB 0 O and VC 0 O represents pole voltages
of Inverter-2. Status of the top switches of the individual inverters during different voltage levels is shown in Table. 3. In case of 2-level operation ie, the reference vector
(Vref ) is in the inner hexagon, only inverter-2 is switched
and inverter-1 is clamped to zero level.

5.2. Modeling Using System Generator

The proposed algorithm is generated in front end with
the aid of system generator editor, and the sampling fre-

Figure 8. Switching signals generated for 3-level operation: Top 3traces for Inverter-1 & Lower 3-traces for Inverter-2 (Modulation
index 0.75)

quency is set to 5kHz. The entire system is shown in Figure 6.

Switching pulses generated for a modulation index of
0.25, i.e. corresponds to 2-level operation, are shown in
Figure 7. As seen, in 2-level operation, only inverter-2
is switched and inverter-1 is clamped to zero level. The
switching pulses generated for 3-level operation (modulation index = 0.75) are shown in Figure 8. Both the inverters
switch equally during 3-level operation.

6. Conclusion
This paper proposes a method for the implementation of
SVPWM in FPGA. Since the SVPWM method is based on
the 60 coordinate system instead of cartesian coordinate
system computational complexity is greatly reduced. The
scheme is simulated for a 3-level inverter. 3-level inverter is

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14th National Conference on Technological Trends | 30 - 31, August 2013 | College of Engineering Trivandrum

realised by cascading two 2-level inverters.

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