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Technical Brief
December 2003
TB417.1
Author: Doug Mattingly
Assumptions
Output Filter
The output filter consists of the output inductor and all of the
output capacitance. It is important to include the DC
resistance (DCR) of the output inductor and the total
Equivalent Series Resistance (ESR) of the output capacitor
bank. The input to the output filter is the PHASE node and
the output is the regulator output. Figure 3 shows the
equivalent circuit of the output filter and its transfer function.
LO
Introduction
Synchronous and non-synchronous buck regulators have
three basic blocks that contribute to the closed loop system.
These blocks consist of the modulator, the output filter, and
the compensation network which closes the loop and
stabilizes the system.
ERROR
AMPLIFIER
+
REFERENCE
OUTPUT
OUTPUT
FILTER
MODULATOR
VOUT
DCR
PHASE
CO
ESR
GAIN
FILTER
1 + s ES R C OUT
= ---------------------------------------------------------------------------------------------------------------------------------------2
1 + s ( ESR + DCR ) C
+s L
C
OUT
OUT
OUT
Modulator
The modulator is shown in Figure 2. The input to the
modulator is the output of the error amplifier, which is used
to compare the output to the reference.
VIN
The transfer function for the output filter shows the well
known double pole of an LC filter. It is important to note that
the ESR of the capacitor bank and the DCR of the inductor
both influence the damping of this resonant circuit. It is also
important to notice the single zero that is a function of the
output capacitance and its ESR.
DRIVER
OSC
PWM
COMPARATOR
VOSC
LO
PHASE
+
OUTPUT OF
ERROR AMPLIFIER
E/A
OUTPUT
DRIVER
DCR
VOUT
+
CO
ESR
V
1 + s ESR C
IN
OUT
GAINOPENLOOP = ---------------------- --------------------------------------------------------------------------------------------------------------------------------------V
2
OSC 1 + s ( ESR + DCR ) C
+s L
C
OUT
OUT
OUT
V IN
GAIN MODULATOR = ---------------------V OSC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
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FESR
FLC
-20dB/DEC
FREQUENCY (Hz)
Type II Compensation
Figure 6 shows a generic Type II compensation, its transfer
function and asymptotic Bode plot. The Type II network
helps to shape the profile of the gain with respect to
frequency and also gives a 90o boost to the phase. This
boost is necessary to counteract the effects of the resonant
output filter at the double pole.
If the output voltage of the regulator is not the reference
voltage then a voltage programming resistor will be
connected between the inverting input to the error amplifier
and ground. This resistor is used to offset the output voltage
to a level higher than the reference. This resistor, if present,
has no effect on the compensation and can be ignored.
2. Pick a gain (R2/R1) that will shift the Open Loop Gain up
to give the desired bandwidth. This will allow the 0dB
crossover to occur in the frequency range where the
Type II network has a flat gain. The following equation will
calculate an R2 that will accomplish this given the system
parameters and a chosen R1.
F ESR 2 DBW V OSC
R 2 = ----------------- ----------------- ---------------------- R 1
V IN
F LC F ESR
Figure 8 shows the asymptotic Bode gain plot and the actual
gain and phase equations for the Type II compensated
system. It is recommended that the actual gain and phase
plots be generated through the use of commercially
available analytical software. Some examples of software
that can be used are Mathcad, Maple, and Excel. The
asymptotic plot of the gain and phase does not portray all
the necessary information that is needed to determine
stability and bandwidth.
The compensation gain must be compared to the open loop
gain of the error amplifier. The compensation gain should
not exceed the error amplifier open loop gain because this is
the limiting factor of the compensation. Once the gain and
phase plots are generated and analyzed, the system may
need to be changed somewhat in order adjust the bandwidth
or phase margin. Adjust the location of the pole and/or zero
to modify the profile of the plots.
If the phase margin proves too difficult to correct, then a
Type III system may be needed.
C1
C2
R2
1
s + ------------------
R C
2
2
1
= -------------------- -------------------------------------------------------GAIN
TYPEII
R C
C +C
1
1
1
2
s s + --------------------------------
R C C
2
1
2
R1
VOUT
GAIN (dB)
REFERENCE
-20dB/DEC
VCOMP
1
------------------------------2 R 2 C 2
1
-------------------------------------------------- C1 C2
2 R ----------------------
2 C + C
1
2
1
------------------------------2 R 1 C 1
R2
20 log ------R
1
FREQUENCY (Hz)
0
-20dB/DEC
FREQUENCY (Hz)
PHASE
-30
90o PHASE
BOOST
-60
-90
VIN
DRIVER
OSC
PWM
COMPARATOR
VOSC
LO
PHASE
CO
C1
C2
VOUT
DCR
ESR
DRIVER
R2
R1
VCOMP
REFERENCE
1
s + ------------------
V IN
1 + s ESR C OUT
R 2 C 2
1
= -------------------- -------------------------------------------------------- ---------------------- ---------------------------------------------------------------------------------------------------------------------------------------GAIN
SYSTEM
V
2
R1 C1
C
+
C
2
1
2
ERROR AMP
DC GAIN
GAIN (dB)
OPEN LOOP
ERROR AMP GAIN
GAIN BANDWIDTH
PRODUCT
0.1FLC
0.5 FSW
0
-20dB/DEC
MODULATOR
& FILTER GAIN
CONVERTER
GAIN
FLC
FESR
BANDWIDTH
COMPENSATION
GAIN
FREQUENCY
GAIN dB(f) = GAIN MODULATOR + GAIN FILTER + GAIN TYPEII
PHASE(f) = PHASE MODULATOR + PHASE FILTER + PHASE TYPEII
V IN
Where: GAIN
----------------------
MODULATOR = 20 log V
OSC
GAIN FILTER = 10 log 1 + ( 2f ESR C OUT )
2
2
2
+ ( 2f ( ESR + DCR ) C
10 log 1 ( 2f ) L
OUT )
OUT C OUT
2f ESR + DCR C
OUT
PHASE FILTER = atan [ 2f ESR C OUT ] + atan ---------------------------------------------------------------------2
2f L OUT C OUT 1
C1 C2 2
20 log [ 2f R ( C + C ) ] 10 log 1 + 2f R ----------------------
1
1
2
2
C 1 + C 2
C1 C2
o
PHASE TYPEII = 90 + atan [ 2f R 2 C 2 ] atan 2f R2 ----------------------
C 1 + C 2
GAIN
TYPEII
= 10 log 1 + ( 2f R C )
2
2
1
C 2 = -------------------------------- R 2 FLC
4. Calculate C1 by placing the first pole at the ESR zero
frequency:
C2
C 1 = --------------------------------------------------------------------2 R 2 C 2 F ESR 1
5. Set the second pole at half the switching frequency and
also set the second zero at the output filter double pole.
This combination will yield the following component
calculations:
R1
R 3 = -----------------------------F SW
-------------------- 1
2 F LC
1
C 3 = ---------------------------------- R 3 FSW
C3
R3
VOUT
C2
R2
R1
REFERENCE
VCOMP
1
1
s + ------------------- s + ------------------------------------
R C
( R 1 + R 3 ) C 3
R +R
2
2
1
3
GAIN
- ----------------------------------------------------------------------------------------TYPEIII = ---------------------------R R C
C +C
1
3
1
1
2
1
s s + ----------------------------- s + ------------------
R C
R
3
3
2
1
2
1
--------------------------------------------------2 ( R 1 + R 3 ) C 3
1
-------------------------------------------------- C1 C2
2 R ----------------------
2 C + C
1
2
GAIN (dB)
1
------------------------------------------------- R 1 R 3 C 1
2 --------------------------------
R1 + R3
R2
20 log ------R1
FREQUENCY (Hz)
0
1
------------------------------2 R 2 C 2
1
------------------------------2 R 3 C 3
180
PHASE
90
180o PHASE
BOOST
FREQUENCY (Hz)
-90
OSC
PWM
COMPARATOR
VOSC
LO
PHASE
CO
C1
C2
VOUT
DCR
ESR
DRIVER
C3
R2
R3
R1
VCOMP
REFERENCE
1
1
s + ------------------- s + ---------------------------------------
V IN
1 + s ESR C OUT
R1 + R3
R 2 C 2
( R1 + R3 ) C3
= -------------------------------- ------------------------------------------------------------------------------------------------ ---------------------- ---------------------------------------------------------------------------------------------------------------------------------------GAIN
SYSTEM
V OSC
2
R1 R3 C1
C1 + C2
1
1 + s ( ESR + DCR ) C OUT + s L OUT C OUT
s s + -------------------------------- s + --------------------
R 2 C 1 C 2
R 3 C 3
.
FZ1=0.5FLC
FP1=FESR
FZ2=FLC
FP2=.5FSW
ERROR AMP
DC GAIN
CONVERTER
GAIN
GAIN (dB)
OPEN LOOP
ERROR AMP GAIN
GAIN BANDWIDTH
PRODUCT
-20dB/DEC
MODULATOR
& FILTER GAIN
COMPENSATION
GAIN
FESR
FLC
BANDWIDTH
FREQUENCY
GAIN dB(f) = GAIN MODULATOR + GAIN FILTER + GAIN TYPEIII
PHASE(f) = PHASE
Where:
MODULATOR
+ PHASE
FILTER
V IN
GAIN MODULATOR = 20 log ----------------------
V OSC
+ PHASE
TYPEIII
2
2
2
+ ( 2f ( ESR + DCR ) C
10 log 1 ( 2f ) L
OUT )
OUT C OUT
TYPEIII
= 10 log 1 + ( 2f R C )
2
2
C1 C2 2
20 log [ 2f R ( C + C ) ] 10 log 1 + 2f R ----------------------
1
1
2
2 C + C
1
2
2
2
+ 10 log 1 + ( 2f ( R + R ) C ) 10 log 1 + ( 2f R C )
1
3
3
3
3
C1 C2
o
PHASE TYPEIII = 90 + atan [ 2f R 2 C 2 ] atan 2f R 2 ---------------------- + atan [ 2f ( R 1 + R 3 ) C 3 ] atan [ 2f R 3 C 3 ]
C 1 + C 2
FIGURE 11. TYPE III COMPENSATED NETWORK
Converter Parameters
Input Voltage:
Output Voltage:
Controller IC:
Osc. Voltage:
Switching Frequency:
Total Output Capacitance:
Total ESR:
Output Inductance:
Inductor DCR:
Desired Bandwidth:
VIN
VOUT
IC
VOSC
fSW
COUT
ESR
LOUT
DCR
DBW
5V
3.3V
ISL6520A
1.5V
300kHz
990F
5m
900nH
3m
90kHz
The dive in the phase is so sharp that the 90o phase boost of
the Type II network does not compensate the phase enough
to have sufficient phase margin. At approximately 6kHz, the
phase margin goes below 45o and never recovers. There is
nothing more that the Type II system can do to improve the
phase. The Phase of the compensation is at its peak when
the phase of the filter is at its minimum.
Another problem with the Type II compensation network in
this example is that the compensation gain intersects and
then exceeds the gain of the error amplifier open loop gain.
As the open loop gain of the error amplifier is the limiting
factor to the compensation gain, the actual gain and phase is
affected by the limit and will not exceed it.
Due to these issues, a Type III network will need to be
implemented to compensate for the phase properly.
The guidelines for the Type III network were then followed to
produce the following component values:
R1 = 4.12k (chosen as the feedback component)
R2 = 20.863k
R3 = 151.85
C1 = 0.2587nF
C2 = 2.861nF
C3 = 6.987nF
Again, these calculated values need to be replaced by
standard resistor values before the gain and phase plots can
be plotted and examined.
R1 = 4.12k
R2 = 20.5k
R3 = 150
C1 = 0.22nF
C2 = 2.7nF
C3 = 6.8nF
The gain plot of the Type III compensated system in Figure
13 looks very good. The gain rolls off at -20dB/decade from
low frequency all the way to the 0dB crossover with a small
perturbation from the LC filter double pole resonant point.
The phase plot shows a system that is unconditionally
stable.
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
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8
100
ERROR AMP
OPEN LOOP
80
GAIN
COMPENSATION
60
GAIN
COMPENSATION
GAIN ENCROACHING
ON ERROR AMP
Gain [dB]
40
20
0
BANDWIDTH
-20
SYSTEM
GAIN
-40
-60
10
100
1000
10000
100000
1000000
Frequency
0
COMPENSATION
PHASE
-20
SYSTEM
PHASE
-40
Phase [degrees]
-60
-80
MODULATOR
& FILTER
-100
PHASE
-120
-140
45 PHASE
MARGIN
-160
-180
10
100
1000
10000
100000
Frequency
1000000
100
ERROR AMP
80
OPEN LOOP
GAIN
60
40
COMPENSATION
GAIN
20
BANDWIDTH
0
-20
SYSTEM
GAIN
-40
-60
10
100
1000
10000
100000
1000000
70
COMPENSATION
PHASE
MODULATOR & FILTER
20
PHASE
-30
SYSTEM
PHASE
-80
-130
45 PHASE
MARGIN
-180
10
100
1000
10000
100000
10
1000000