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Introduction
As the first step in a netlist-to-GDSII design flow, floorplanning presents the SoC designer with challenges and
opportunities that affect the rest of the design flow, from block implementation, to chip assembly and top-level
closure. It is particularly important in hierarchical floorplanning to quickly solve macro and IO pad placement,
accurately estimate timing, power and area, create top-level power networks, and to efficiently partition the design.
Floorplanning for large, complex ICs and SoCs depends on a high capacity solution that allows early timing
estimations in a multi-mode, multi-corner (MCMM) context, supports all varieties of multi-Vdd flows, and offers
wide flexibility between automatic and manual placements of all floorplan objects.
In this paper, we review floorplanning challenges and show how the Olympus-SoC implementation system
comprehensively addresses all those challenges to produce the best floorplan in the shortest time.
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Floorplanning Challenges
Each design project has different challenges and goals, but there are some issues that commonly arise for physical
design teams.
Figure 1. Sub-optimal IO placements can lead to long paths over macros. In the design shown, the IOs should be
placed on the bottom left side to have better access to the logic pins. Changing the IO placements can be
tedious, particularly if the problem is not discovered until later in the design flow.
creating multiple power grids, and in inserting the special cells such as switches, level shifters, retention registers,
and always-on buffers. Poorly shaped regions and broken logical hierarchy contribute to delayed schedules and
suboptimal timing, power, and area.
Once the regions are determined, the region/partition pins are assigned. The challenge is to create pin placements
that satisfy any number of design criteria, but most importantly the timing requirements between blocks for all
corner/mode scenarios. Typically, pin assignments are based on wire length only, as determined by Steiner-based
estimations. Poor pin assignments can wreak havoc on inter-partition timing paths, and lead to costly ECOs
between the block level and chip level late in the design cycle.
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Figure 2. The IO Constraints Editor facilitates pin constraint editing with cross-probing, robust filtering, and
flylines. IO ports can be automatically aligned, and Olympus-SoC can infer constraints based on current
placements.
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As the floorplan, or even the block implementation, progresses and more detailed information is available,
designers often find that the pin assignments need adjustment. Rather than re-assigning all pins, Olympus-SoC
supports incremental pin assignment. Designers can specify which pins to re-assign, while keeping the rest of the
pins fixed.
After placing the IO signal pins, Olympus-SoC will place the IO filler cells and power/ground pads. The IO
placements can then be written out in industry-standard formats for use by board, package, or top-level SoC
planning purposes. This link between board, package, and SoC becomes more important at 45 nm and below
because of tighter design constraints and more pad-limited designs.
Figure 3. The large macros in this screen capture have already been aligned with just a few button clicks. Using the
Matrix align and space capability, all the smaller macros can be instantly arranged into a matrix with specified
spacing between them. Multiple macros can also be grouped and moved as a single object.
hierarchy, or manually shaped, facilitated by colorized logic groupings. Regions can also be manually moved,
resized, reshaped, or split into smaller regions. Egresses (bumps) and ingresses (notches) are created by adding or
deleting rectangles from the existing regions.
As regions are hardened into partitions, Olympus-SoCs fast timing-driven prototype placement and global routing
predicts where routes will cross the partition boundaries, and assigns partition pins based on that. The placement
and routing engines support multi-mode, multi-corner constraints, so pin assignments are optimized based on
timing and wire length that will satisfy all mode/corner scenarios.
Figure 4. With the Multi-Voltage browser, the power domains and the cells assigned to each domain can be
easily navigated. Items selected in the browser are highlighted in the chip view for cross-probing operation.
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Regardless of the number of voltage domains, Olympus-SoC can create and connect all power routing at block or
top level. Rings, stripes, and vias are automatically generated based on user configuration and connected to follow
pins. Users can manually choose which vias to use or let Olympus-SoC determine the correct vias, either from
among defined LEF vias or by generating them using the default via generation rules in the LEF file. Users can also
specify which kind of power connections to make: stripe-to-stripe, stripe-to-macro, and stripe-to-cell. Olympus-SoC
has the ability to create multiple power networks for multi-vdd designs.
Short jogs
eliminated
Figure 5. Layer promotion is a technique used by Olympus-SoC to reduce resistance in top-level routing.
Another option available in Olympus-SoC to stretch capacity and save on runtime is to selectively turn off some
levels of logical hierarchy with regard to timing. That allows Olympus-SoC to access the relevant physical
information, but not spend computational resources on extraction and timing of those modules. Olympus-SoC is
unique in the level of flexibility offered in both flat and hierarchical flows. Olympus-SoC also offers capabilities like
SyncOpt, which automatically updates all occurrences of a block when a change is made to any of its instances.
Many IC flows also call for some amount of automatic or manual detail routing and wire editing of critical nets. For
manual editing, the Olympus-SoC wire editor provides a robust and intuitive environment, supporting automatic
preferred-layer routing, via creation, and non-adjacent layer wire creation.
Olympus-SoC also provides real-time, interactive DRC, giving instant feedback for all objects being manipulated, as
illustrated in Figure 6.
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Figure 6. Manual wire editing with interactive DRC checking gives instant feedback on common design rule
violations as wires are drawn or moved.
Conclusion
Floorplanning is the foundation of a quality IC implementation. The decisions made regarding IO pad placement,
macro placement, partitioning, pin assignment, and power planning ripple through the place-and-route flow.
Designers need solutions that can handle extremely large data sets, design variability and complexity, in addition to
enabling fast, high-quality floorplanning.
Olympus-SoC has a complete floorplanning solution with a flexible tool infrastructure and large capacity. It
generates high-quality floorplans and accurate early estimations of design constraints based on MCMM timing.
Flexible support for mixed-level hierarchy throughout the flow keeps ECOs to a minimum and maintains physical
and logical convergences between top and block levels. Olympus-SoC is a complete, tapeout-proven, netlist-toGDSII solution for very large, advanced-node SoCs.
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