Circuit Schematic

The figure above is a typical two-stage CMOS operational amplifier.

The first stage has a p-channel differential input pair with a nchannel current mirror active load.
Devices

Length

Width

Multiplier

Mp1

1m

2m

16

Mp2

1m

2m

16

Mn3

1m

2m

Mn4

1m

2m

Mp5

1m

2m

32

Mp6

1m

2m

64

Mn7

1m

2m

16

Mp8

1m

2m

Mp9

1m

2m

Mn10

1m

2m

Mn11

1m

2m

Mn12

1m

2m

Mn13

1m

2m

Mp14

1m

2m

16

Mn15

1m

2m

Mn16

1m

2m

MCr

1m

2m

16

MCc

2m

2m

56

Tesbench
Gain, Gain BW & Phase Margin

Floor Plan

Slewrate

Stick Diagram
Metal 1
Metal 2
Metal 3
Metal 4
Polysilicon
Power Rail
Via

PMOS Booster Mp6

Differential Piar Mp1 & Mp2

Current Bias Mp5

Mp8 & Mp9

Mp14

NMOS Booster Mn7

Mn15

NMOS Current Mirror Mn10 & Mn11

Mn16

Compensation Resistor

Current Mirror Mn3 & Mn4

NMOS Current Mirror Mn12 & Mn13

Layout View

The figure shows a layout of a Two-Stage Operational Amplifier. The

first gain stage is a differential-input single-ended output stage
which is constructed by Mp5, Mp1, Mp2 Mn3, Mn4. The second-stage is a
common-source gain and constructed by Mp6 and Mn7 known as our
boosters to amplify the signal.

Simulation and Verification

Design Rule Check:

Layout Versus Schematic:

Layout Parasitic Extraction:

Pad and Core Layout View

Pre and Post Simulation Results

PRESIM
POSTSIM

RESULTS

PRESIM

POSTSIM

GAIN

84.3dB

84.6dB

PRESIM

POSTSIM

RESULTS
GAIN BW
PHASE MARGIN

PRESIM
11.8MHz
60

POSTSIM
8.24MHz
60

POSTSIM

PRESIM

RESULTS

PRESIM

POSTSIM

SLEWRATE

2.1 V/s

1.26 V/s

Pre and Post Simulation of FF, TT, and SS

FF
TT
SS

RESULTS
Gain

FF
76.1dB

TT
84.6dB

SS
78.9dB

FF
TT
SS

RESULTS
Gain BW
Phase Margin

FF
14.8MHz
61

TT
8.21MHz
60

SS
4.84MHz
60

TT

FF

SS

RESULTS
Slew Rate

FF
2.14 V/s

FF
TT
SS

TT
1.26 V/s

SS
1.42 V/s

Conclusion
Basic layout rules and procedures are very important to speed up
the process of layouting. Minimum rule, metals and vias, capacitor and
resistor types are all essential in the process of Operational
Amplifier Layout.
Routing between devices are recommended to be thick to avoid
electromigration in such a way that the current density is matched
with the thickness of the metal. 45 degrees routing is encouraged and
is a good layout practice. As much as possible, routing must be done
with the shortest distance especially in direct routing with global
nets. T Routes are discouraged to avoid eddy currents to occur in
corners which will result to current unable to flow properly.
Guard ring of 5 to 10 array of contacts is encouraged in dealing
with operational amplifiers layout. This is for better noise immunity
and optimum performance.

ECE 127
Introduction to Digital
VLSI Design
Two Stage Operational Amplifier

Guinomla, Harris W.