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INTERNATIONAL JOURNAL
OF TECHNOLOGY
January-June 2015
Vol. 6, No. 1
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Design and Implementation of Inset feed Square Patch Micro strip Antenna
Array for WLAN Application Using Dielectric Substrate
Priya Upadhyay, Dr. Ranjit Singh and Arundhati Tiwari
50
55
Published by:
ISSN 0975-9514
Vice Chancellor
Uttrakhand Technical University
Dehradun (Uttrakhand)
Shri S. N. Gupta
Prof. M. L. Kothari
Department of Electrical Engineering
Indian Institute of Technology
New Delhi
Patron-in-Chief
Dr. R. K. Agarwal
Director
Ajay Kumar Garg Engineering College
Ghaziabad
Editorial Team
Editor-in-Chief: Dr. Ranjit Singh
Editor: Dushyant S. Chauhan
Secretary General
NGN Forum (India)
New Delhi
Vol. 6, No. 1
ISSN 0975-9514
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16
21
26
31
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39
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Editor-in-Chief
Dr. Ranjit Singh
55
Patron-in-Chief
Our Vision
To introduce undergraduate and postgraduate courses for all
engineering branches and award of Ph.D degree. To be one of
the best engineering colleges in the country
and to be a deemed university.
Our Mission
We strive to provide and maintain academic environment and systems, enabling
maximum learning to produce competent professionals. We also aim at
achieving this through transparent academic and administrative policies
in the college. We intend to provide conducive atmosphere
for research, development and consultancy services to
our faculty at national and international level.
Disclaimer
The views expressed by the authors do not necessarily represent those of the Editor or Publisher, or the
management of the Ajay Kumar Garg Engineering College. Though every care has been taken to avoid errors,
this journal is being published on the condition and understanding that all the information provided herein is
merely for reference and must not be taken as having authority of or binding in any way on the authors, editor
and publisher who do not owe any responsibility for any damage or loss to any person, for the result of any action
taken on the basis of this work. The publisher shall be obliged if mistakes are brought to their notice.
ii
I. INTRODUCTION
THERE are different digital logic integrated circuits available
in the market. These can be used in designing circuits by circuit
designers. But as systems become complex, there may be some
functions that cannot be performed by these readily available
ICs. Hence the use of VHDL for circuit design comes in handy
[1]. VHDL is a high level programming language which is
powerful in programming Programmable Logic devices such
as field programmable gate arrays, generic array logic (GAL)
and Programmable array logic [2],[3]. For the programmable
logic devices to be programmed the codes must pass through
stages such as synthesis, timing simulations, place and route
and bit file generation [4]. This work will be based on design
on an FPGA. The advantage of designing digital circuits used
for instrumentation and control using it is that the circuits can
be modified even after reaching the market due to the
reprogrammability of FPGAs thereby enhancing rapid
prototyping [5]. There are many manufacturers of FPGA such
as Xilinx; Inc, Altera Corporation, Perfect Parts Corporation,
Achronix Semiconductor Corporation, Atmel Corporation [6],
[7] etc. FPGAs contain programmable logic elements called
Logic elements LEs and a hierarchy of reconfigurable
interconnects that allow Les to be connected physically [5].
In this work, a Spartan-3 FPGA development board is used.
The designed circuit has the following features:
The Alarm: The alarm has a switch setalm. When the button
is set, user can set and adjust the alarm setting using sethr,
setmin and inct. At the time when the alarm set time
becomes equal to the clock time, an output pulse is sent out.
This is dependant on whether a 24 hours or 12 hours format is
selected. User adjusts it by taking into consideration which
time format is used at a particular moment.
II. METHODOLOGY
The codes for the functionalities mentioned earlier were written
in eight different files and were assigned names listed below:
1.
Tb_toplevel.vhd
2.
Toplevel.vhd
3.
Clockdivider.vhd
4.
Clock.vhd
5.
Alarm.vhd
6.
Stop.vhd
7.
Date.vhd
8.
Scan4digit.vhd
III. RESULTS
V. REFERENCES
[1].
Used Available
124
98
3,840
[2].
Utilization
[3].
3%
[4].
26
444
3,840
259
1,920
13%
259
259
100%
259
0%
3,840
12%
[5].
[6].
11%
Logic Distribution
444
41
35
173
20%
Number of BUFGMUXs
37%
[7].
[8].
IV. CONCLUSION
The Digital Clock was designed by first creating VHDL codes
and synthesizing them using Xilinx ISE 8.2i software. The codes
passed synthesis and a bit file was generated. The bit file was
programmed onto a Spartan-3 development kit and tested for
functionality. The circuit performed the desired functions.
Design statistics also showed that the FPGA resources were
highly utilized and therefore the design is economical. This
proves how FPGAs are desirable when dealing with complex
systems.
I. INTRODUCTION
QUEUING theory had its beginning in the research work of a
Danish engineer named A. K. Erlang. In 1909 Erlang
experimented with fluctuating demand in telephone traffic.
Eight years later, he published a report addressing the delays
in automatic dialing equipment. At the end of World War II,
Erlangs early work was extended to more general problems
and to business applications of waiting lines.
L =W (Littles Law)=/-
L = Lq +/
W = Wq +1/=L/
U= /
I=1-u=1-/
P0= (1-/)
Pn= (/) n.p0== [(/)n](1-/)
Month
Time spent
No of customers
served per a day
1618
1306
January 1, 2014
2103
No. of respondents
Percentage
January 3, 2014
1295
5-20 minutes
10%
January 5, 2014
1388
21-36 minutes
10%
January 6, 2014
1134
37-52 minutes
12
24%
Total
8844
Opinion
No of respondents
Percentage
Yes
16
32%
No
34
68%
Total
50
100%
Opinion
No of respondents
Percentage
Yes
15
30%
No
35
70%
Total
50
100%
Selected day
December 24
157
December 28
153
January 1
167
January 3
144
January 5
156
January 6
141
Total
918
(mean service rate per hour) = 1474 + 211 = 1685 = 177/ hr.
9.5
9 .5
=177/8= 22.14 customers served in each window /hr. or mean
service rate for each server per hour
=22.14 Customers served per hour in each window
=153 Average customers arrive at the service station in an
hour
C= 8 Number of servers
The average time that the customer spends in the queue system
is 0.2804 hr. or 17 minute.
IV. SUGGESTIONS
Suggestions: Based on the analysis of the study, the following
suggestions are given for improvement of efficiency and quality
of service to customers of the bank.
Bank should enrich employees job by making them multiskilled, through continuous training so as to enable them
to eliminate unnecessary counter-check handoffs.
V. CONCLUSION
Based up on the above discussion it can be concluded that,
for rendering better services to the bank customers modern
models should be adopted. The average waiting time per
customer in a system as well as in the queue were found about
32 minutes and about 29 minutes respectively, however 2
servers added in the bank, the average waiting time per
customer in the system and queue were found about
3.18minutes and 0.4896 minutes respectively. Customer
satisfaction is the significant factor for any industry and more
to service industry to which all banks belong. Therefore the
application of queuing analysis has proved that the adoption
of it in the day to day operational activities of the bank will
satisfy the customers. Satisfied customers will result in desired
growth for the bank and for economy of the country.
Lq
Wq
PW
82.32
75.41
32.28m
29.52m
0.9859
42.9
35.99
17m
14.4m
0.6026
8.16
1.25
3.18m
0.4896m
0.38
VI. REFERENCES
[1].
[2].
[3].
[4].
[5].
[6].
[7].
I. INTRODUCTION
THIS research is to design and develop the Hybrid method
of automatically filling the chemical liquid into bottles using
PLC&SCADA and show its visualization on SCADA screen.
10
11
The components of the drive system are broken into four major
categories: source power, rectifier, dc bus, and inverter. Other
components exits such as resolver and encoder feedback
devices, tachometers, sensors, relays and help supplement
the system.
VII. METHODOLOGY
This department of the plant works on distribution of any kind
of chemical liquid into different tank to a main two buffer
storage tank. This distribution takes place automatically using
the Programmable Logic Controller (PLC).
12
Figure 4. Screen shot of SCADA software of manufacturing department of the chemical liquid.
Figure 5. Screen shot of the SCADA software of the automatically filling of the chemical liquid into the bottles.
The motor continues to run even when the bottle moves away
from the first sensors range, i.e. the output of the motor is
latched as explained in the ladder logic section of PLC. When
sensor 2 senses the bottle, it also gives a high output to the
13
PLC. The PLC instructs the inverter to stop the motor. The
high output bit of sensor 2 is also given to the timer for the
solenoid valve. The timer used is TON. It counts for a predefined
value of time (18 sec). It gives two outputs, Enable output and
done output. The Enable output remains high while the timer
is counting and the output goes high after the timer has finished
counting. The Enable output of TON is given to the solenoid
valve, and so the solenoid valve is open for the predefined
value of time (18 sec). The Done output bit is used to turn ON
the motor again in the running . And this all the process are
repeat again and half the bottles fill again to in front of the
second chemical tank and the bottles full filled and the done
output bit is used to turn on the induction motor again. All
this are described in this ladder programming of the PLC.
IX. CONCLUSION
This paper presents a automated liquid filling to bottles of
using PLC and SCADA. A total control is made in a filling is
achieved. The present system will provides a great deal of
applications in the field of automation, especially in mass
production industries where there are large number of
components to be processed and handled in a short period of
time and theres need for increased production. The
programming to this system developed is flexible, quickly and
easily. This will increase the total production output; this
increase in production can yield significant financial benefits
and savings. This concept can be used in beverage and food
industries, milk industries, medicine industries, mineral water,
chemical product industries and manufacturing industries. The
Figure 6. PLC ladder program for filling of the chemical liquid into the bottles.
14
[8].
X. REFERENCES
[1].
[2].
[3].
[4].
[5].
[6].
[7].
[9].
[10].
[11].
[12].
[13].
15
I. INTRODUCTION
FRICTION stir welding is a solid state joining process using a
rotating tool moving along the joint interface, generating heat
and resulting in a re-circulating plasticized material flow near
the tool surface. This plasticized material is subjected to
extrusion by the tool probe rotational and linear movements
leading to the formation of stir zone. This stir zone formation is
affected by the material flow behavior under the action of
rotating tool. It was developed in England by The Welding
Institute (TWI) in 1991 [1]. The friction stirring tool consists of
a pin, or probe, and a shoulder as shown in Fig.1. Contact of
the pin with the workpiece creates frictional and deformational
heating and softens the workpiece material; contacting the
shoulder to the workpiece increases the workpiece heating,
expands the zone of softened material, and constrains the
deformed material. Naturally, there are important effects to the
tool during welding: abrasive wear, high temperature and
dynamic effects. Therefore, the good tool materials have the
following properties: good wear resistance, high temperature
strength, temper resistance, and good toughness.
16
Tool geometry
Tool geometry affects the heat generation rate, traverse force,
torque and the thermo-mechanical environment experienced
by the tool. The flow of plasticised material in the workpiece is
affected by the tool geometry as well as the linear and rotational
motion of the tool. Important factors are shoulder diameter,
shoulder surface angle, pin geometry including its shape and
size, and the nature of tool surfaces [12]. It was also observed
from the previous data that the friction stir weld tool geometry
has a significant effect on the weldment reinforcement, micro
hardness, and weld strength.
Shoulder diameter
In order to determine the optimum tool geometry, the two
components of the torque are plotted in Fig. 4 for various
shoulder diameters. As the shoulder diameter increases, the
sticking torque, increases, reaches a maximum and then
decreases [4]. This behavior, which shows that two main factors
affect the value of the sticking torque. First, the strength of the
material, shear stress decreases with increasing temperature
due to an increase in the shoulder diameter. Second, the area
18
Tool cost
While the energy cost for the FSW of aluminium alloys is
significantly lower than that for the fusion welding processes
[25] the process is not cost effective for the FSW of hard
alloys. Tools made of pcBN are often used for the welding of
hard materials. However, pcBN is expensive due to high
temperatures and pressures required in its manufacture [12].
Santella et al [22] did an approximate cost benefit analysis for
FSW with a pcBN tool versus resistance spot welding (RSW)
of DP 780 steel. The equipment and utility costs for FSSW
were assumed to be 90 and 30% respectively of the costs in
RSW; however, they did not report the dollar amounts of these
costs. They further assumed that a typical RSW tool tip lasts
5000 welds and costs $0.65 per tip [12]. Considering the costs
involved with equipment, utility and the tool, they estimated
that in order for the FSSW to be cost competitive with respect
to RSW, each FSSW tool, costing ~$100, needs to make 26 000
spot welds. Since the cost of each pcBN tool was significantly
greater than $100 and typical tool life was between 500 and
1000 welds, they suggested lowering tool costs as an important
need. Feng et al [24] produced over 100 friction stir spot welds
on dual phase steel (ultimate tensile strength 600 MPa) and
martensitic steel (ultimate tensile strength 1310 MPa) without
noticeable degradation of the pcBN tool. The costs of Si3N4
and TiB2 tools were less than 25% of the cost of pcBN tools
[22]. Tools of WRe or WLa alloys are relatively less
expensive than that of pcBN tool but suffer considerably more
19
[1].
20
Department of Mechanical Engineering, Jamia Millia Islamia, New Delhi 110025 India
Department of Mechanical Engineering, Aligarh Muslim University, Aligarh 202002 India
1
zafer.amu@gmail.com, 2aalikhan.me@amu.ac.in, 3msuhaib@jmi.ac.in
I. INTRODUCTION
THE AIM of this paper is to develop an algorithm that can be
used to determine the natural frequency by knowing the
response and the system parameter using Volterra series. Such
analysis have attracted considerable attention in the recent
past, partly due to growing awareness of the significance of
the Random nature of forces produced by during operation.
Indirect estimation of excitation force using model co-ordinate
transformation has been carried out by De Sanghere et.al. [1],
classification of different force identification problem has been
carried out by Stevens [2]. A study for finding inverse method
for estimation of impulsive loads has been conducted by Ma
et.al. [3]. A non-linear vibration problem of estimating the
external forces for a single degree of freedom system using
conjugate gradient method has been developed by Huang [45].
21
(1)
(2)
22
V. COMPUTER SIMULATION
The input identification procedure is illustrated through
numerical simulation of the response for the non-dimensional
coupled equation (3) and (4). The forcing functions chosen for
response simulation are normalized zero mean random forces,
and
. The excitation forces are simulated through
random number generating subroutines and are normalized
with respect to their maximum values. The governing equations
are then numerically solved using a fourth order Runge-Kutta
method, to obtain the responses in and directions (
and )
from equations (3) and (4). Using FFT the power spectrum of
the response averaged over the ensemble of 2000 samples is
determined.
F211i(=
())0.094358
))
(yxf
Owing to the statistical nature of the problem, the procedure is
illustrated for various sets of direct and coupled stiffness and
damping parameters. The case studied for a particular set of
stiffness as well as damping parameter have been designed to
find the natural frequency of the system using the algorithm
developed.
23
: Case 1.
: Case 1.
24
VIII. REFERENCES
[1].
25
I. INTRODUCTION
READOUT circuits for photon counting image sensors are
based on analog and digital circuits, such as the Medipix 2 [1].
Photon-counting pixels contain complex circuitry, which means
that the pixel design is mainly driven by area, power
consumption and mixed mode design constraints. In photon
counting pixel readout of X-rays if a pixel does not have
excellent X-ray sensitivity, a low energy threshold and a low
noise contribution, then attempts to correct intensity
measurements may fail because small changes in threshold
can lead to significant alteration in detection efficiency.
Because small variations in threshold make it very difficult to
avoid missing counts. To solve this problem four discriminators
per pixel instead of double discriminators are used. For low
discriminator level, the circuit consists of sum circuit and two
comparators, one of the comparator work as a threshold
correction. For high discriminator level, the circuit consists of
two comparators and (AND gate). For improving threshold
uniformity, the circuit is equipped with two 5-bits analog to
digital converters DACs. One of the DAC is used to bias the
feedback transistors of the preamplifier and the shaper. The
second DAC set the threshold voltages ThLL, ThLH, ThHL, and
ThHH in the comparators see (Figure 1).
II. METHODOLOGY
A block diagram of the circuit architecture of Photon counting
26
27
28
Figure 11. Simulation result of the circuit with offset input signal.
29
[6].
[7].
[1]
IV. CONCLUSION
In this paper we have introduced architecture for a photon
counting pixel detector readout with threshold correction for
the comparators is implemented as a solution for the missing
counting of the signal due to the offset problem. The additional
circuits needed for this architecture, leads to an increase in
power consumption and in circuit area. It is implemented in a
120nm CMOS process and the presented results are based on
simulations.
[2]
[3]
[4]
V. REFERENCES
[1].
[2].
[3].
[4].
[5].
30
I. INTRODUCTION
THE fast growth of the economy in the past 10 years has
placed increasing importance on physical infrastructure such
as electricity, railways, roads, ports, airports, irrigation, water
supply and sanitation.They are important for economy as far
as growth is concerned. The current target growth rate of
economy can only be sustained if this infrastructure deficit is
overcome and adequate investment takes place in support of
higher growth for an improved quality of life, both for urban as
well as rural communities. A competitive market alone cannot
assure the required infrastructure facilities and services. This
often justifies for government involvement by directly
providing infrastructure services through Public Sector
Undertakings.
31
It is risk-adjusted valuation
32
c.
d.
e.
33
(source:http://www.treasury.wa.gov.au/)
V. CONCLUSION
Public Sector Comparator (PSC) calculation is one of the most
useful tools used to perform value for money calculation for
making the decision between the PPP procurement route or
conventional procurement options. However due to its
hypothetical nature of valuation throughout the life cycle of
the project, the merit of PSC is still a debated issue. Much
work still needs to be done in all the areas such as to reduce
the gap in the valuation of projects by understanding the risks
in the project, closing the gap between hypothetical
assumption of vfm and to assess how close the value of vfm
can be with real value of the project. The public sector
comparator should be used with other similar tools to provide
better results. This is due to the fact that some of the factors
which are used for value for money comparison are more
qualitative than quantitative for which data is used based on
certain assumptions.
Merit of PSC as a tool for value for money: As per U.K. Audit
Commission report (2003 p. 37) the PSC has lost the confidence
of many people, and risks being seen more as a hoop to jump
through on the way to government funding than a valuable
exercise that can help ensure better VFM.
Value for money test is sometimes problematic. In particular,
it is difficult to factor in the cost of things going wrong over
the total life of the project. More generally, the public sector
comparator is necessarily hypothetical, so its credibility is
difficult to test.
As per report from Public Accounts Committee Publications
(UK):
The use of public sector comparators has been the subject of
considerable debate about their reliability, accuracy and
relevance in the contexts in which they have come to be used.
They have observed many cases where the public sector
comparator has been incorrectly used as a pass or fail test. In
these cases the desire to show that the PFI deal is "cheaper"
than the public sector comparator has led to manipulation of
34
[5].
[6].
[7].
[8].
VI. REFERENCES
[1].
[2].
[3].
[4].
http://www.eib.org/epec/g2g/i-project-identification/12/124/
index.htm
The Value for Money Analysis:A Guide for More Effective
PSC and PPP Evaluation: by Dawn Bidne, Amber Kirby,
Lucombo J. Luvela, Benjamin Shattuck, Sean Standley, and
Stephen Welker
http://www.unescap.org/resources/guidebook-public-privatepartnership-infrastructure
http://www.ncppp.org/wp-content/uploads/2013/03/PS051012ValueForMoney-paper.pdf
35
II. METHODOLOGY
Step I: Galvanostatic Charge/ Discharge cycling was performed
on a capacitor, using an Arbin BT2000 multi channel battery
testing instrument along with its Arbin MITS Pro Software.
The galvanostatic current was set at 50mA. The results below
were obtained from the experiment.
I. INTRODUCTION
AS A result of the rapid development in technology and the
availability of portable devices, researches on energy storage
devices are under process in order to obtain storage devices
that have higher energy density as well as higher power
density. Batteries have higher energy density but with lower
power density. In the case of supercapacitors, the reverse is
the case [1]. Thus present researches are on how to improve
the energy density of supercapacitors so that it can replace
batteries in some applications [2]. The Ragone Plot below shows
the various forms of energy storage devices, their energy
density and power density.
37
[5].
[6].
IV. CONCLUSION
In this paper it has been shown that current, voltage and
frequency affect the value of the capacitance of a
supercapacitor. In order for users of such products to make
proper choices, manufacturers of supercapacitors include more
information in their datasheets regarding this issue.
V. REFERENCES
[1].
[2].
[3].
[4].
38
Ripple Carry Adders have most compact design but they are
having slow speed of operation. Whereas, the Carry Look
Ahead Adder has fast speed but it consumes more area. Carry
Select Adder solves both the problem as generated by that of
the Ripple Carry Adder and Carry Look Ahead Adder. A CarrySelect Adder can be structured by using a single Ripple-Carry
Adder and an add-one circuit rather than using the dual RippleCarry Adders.Based on the area, delay and power consumption
requirements, several adder structures have been proposed. A
multiplexer-based add-one circuit is proposed to reduce the
area with less speed penalty. This acts as the sum for each bit
position in an adder which is generated serially only after the
previous bit position has been summed and a carry is
propagated to the next position.
I. INTRODUCTION
IN recent years, the increasing demand for high-speed
arithmetic units in micro-processors, image processing units
and DSP chips has paved the path for development of highspeed adders as addition is an important operation in almost
every arithmetic unit, and it too acts as the general building
block for synthesis of all other arithmetic computations. If we
have to increase the portability of systems as well as the
reliability of the battery, area and power are the critical aspects
which are generally considered. In digital adders and
corresponding circuit designs, the speed of addition has
somerestrictions by the time required to propagate a carry
through the adder. The designs of area and high-speed data
path logic systems arethe most important areas of research&
study in VLSI system design. In electronic system and
applications adders are mostly used. As we know that in
39
attain low power dissipation and high speed. Ripple Carry Adder
consists of cascaded N single bit full adders. Output carry,
i.e. Cout of previous adder becomes the input carry of next full
adder. Therefore, the carry of this adder traverses longest path
called worst case delay path through N stages. Figure 1 shows
the block diagram of Ripple Carry Adder (RCA). Now, as the
value of N increases, delay of adder increases linearly. So,
RCA has the slowest speed amongst all adders because of
large propagationdelay, but it occupies the least area. Now
CSLA provides a way to get around this linear dependency to
anticipate all possible values of input carry i.e. 0 and 1 and
evaluate the result in advance. Once the original value of carry
is known, result can be selected using the multiplexer stage.
So,the conventional CSLA makes use of dual RCAs to
producethe partial sum and carry by taking the input carry Cin
= 0 and Cin = 1, then the final sum and carry are selected by
multiplexers. Figure 2 shows the 16-bit SQRT. CSLA.The Sqrt.
CSLA is area consuming due to the use of dual RCAs.
Ripple Carry Adder has the lowest speed among the fast adders.
The CSLA is used to find out all possible values of input carry
i.e. 0 and 1 and calculates the result in advance. The result is
passed through a select line by the multiplexer. The CSLA
generallyuses dual RCAs to generate partial sum and carry by
considering Cin=0 and Cin=1 then the final sum and carry is
selected by using multiplier. In regular CSLA area consumed is
more due to the use of dual RCAs. The basic idea of this study
is to use Binary to excess-1 converter (BEC) rather than that of
RCA with Cin=1 to reduce the area and power. The advantage
of BEC is that it requires less number of logic gates than that of
the N bit full adders. To reduce the delay, N bit ripple carry
adders are replaced with N+1 bit BEC.So, the newly modified
Sqrt. CSLA is area consuming than regular CSLA.
40
assuming Cin = 0and the other RCA produce carry and sum and
sum assuming Cin= 1 [3]. This conventional carry select adder
has less carry propagation delay than conventional RCA adder
but increases the complexity due to dual RCA structure. A
carry select adder generating carry of block with carry in as1
from the block with carry in as 0 was proposed by Tyagi.[13] in
1990. Later in 1998, Chang and Hsiao[10] proposed a carry
select adder consisting of single ripple carry adder. This was a
real start in the carry select adder history.In 2001 a further
modified carry select adder with increased delay but reduced
area and power was givenby Kim and Kim [11]. Here the RCA
section with Cin = 1 was replaced using an add one circuit
using multiplexer (MUX). Later in the year 2005 a further modified
carry select adder which reduces the area and power
consumption was proposed by Amelifard, Fallah and
Pedram[12]. It reduces the gap between carry select adder and
ripple carry adder.
Later a Sqrt. CSLA was proposed which helps in implementing
large bit width adders with less delay. In this system the CSLAs
with increasing bit widths are cascaded with each other. It
helps in minimizingthe overall adder delay. A BEC based CSLA
was further proposed byRamkumar and Kittur[1] which had
fewer resources than conventional CSLA but with more delay.
A CBL (common Boolean logic) based CSLA[10] was also
proposed which requires less logic resources but CPD(carry
propagation delay) was similar to that of RCA. A CBL based
Sqrt. CSLA [11] was also proposed but the design requires
more logic resource and delay than BEC based Sqrt. CSLA.
41
Half Adders are used to add two one bit binary numbers. It is
also possible to structure a logical circuit using multiple full
adders to add N-bit binary numbers. Each full adder inputs
aCin, which is the Cout of the previous adder. This kind of adder
is a ripple carry adder, since each carry bit ripples to the
next full adder. The first (and only the first) full adder may be
replaced by a half adder.
The Carry Select Adders are divided into two types: Uniform
sized adders and variable sized adders. When thebit length is
equally divided it is stated as an uniform sized adder. It is also
called as the linear Carry Select Adder. In variable sized adders
the bit lengths are generally unequally divided. It is also called
42
of this task is to use BEC instead of the RCA with Cin=1 in order
to reduce the area and increase the speed of operation in the
regular CSLA to obtain modified CSLA. To replace the n-bit
RCA, n+1 bit BEC logic is required as shown in Figure 10.
Figure 11 shows the BEC using carry out.
The next figure i.e. Figure 9 illustrates how the basic function
of the CSLA is obtained by using the 4-bit BEC together with
the Mux. One input of the 8:4 mux gets as it input (B3, B2, B1,
and B0) and another input of the mux is the BEC output. This
produces the two possible partial results in parallel and the
mux is used to select either the BEC output or the direct inputs
according to the control or carry signal Cin.
Figure 12. Connection of RCA, BEC and Sum & Carry Block
43
Binary Logic
B0 B1 B2 B3
Excess-1 Logic
E0 E1 E2 E3
0000
0001
0001
0010
0010
0011
0011
0100
0100
0101
0101
0110
0110
0111
0111
1000
1000
1001
1001
1010
1010
1011
1011
1100
1100
1101
1101
1110
1110
1111
1111
0000
VIII. CONCLUSION
Power, delay and area are the main performance parameters of
CSLA and the reduction of these parameters is the challenging
issue of todays VLSI research. Many methods and techniques
have been proposed to design fast, compact and less power
consuming CSLA. But as we can analyze from the recent
method proposed that there is a trade-off between area
consumption and delay of CSLA. Therefore, there is a scope
to make CSLA more delay and area efficient by optimizing the
circuit. The overall improvement in Modified CSLA shows
better results in terms of area power and delay. Hence, proposed
modified CSLA is being used for power and area efficient
devices.
IX. ACKNOWLEDGEMENT
Authors thank Ajay Kumar Garg Engineering College for
providing facilities.
X. REFERENCES
[1].
[2].
44
B. Ramkumar and H.M. Kittur, 2012, Low-power and areaefficient carry-select adder, IEEE Transactions on Very Large
Scale Integration (VLSI) System. vol. 20, no. 2, pp. 371375.
J. Kinniment, 1996, An evaluation of asynchronous addition,
IEEE transaction on Very Large Scale Integration (VLSI)
Systems, vol.4, pp.137-140.
[4].
[5].
[6].
[7].
[8].
[9].
[10].
[11].
[12].
[13].
45
I. INTRODUCTION
FIELD-PROGRAMMABLE gate arrays (FPGAs) are
semiconductor devices containing programmable logic
elements (LEs) and a hierarchy of reconfigurable interconnects
to realize any complex combinational or sequential logic
functions. Hardware implemented in an FPGA can be
reconfigured by programming the logic elements and
interconnections for specific applications, even after the
product has been installed in the field. Todays FPGAs consist
of configurable embedded static random-access memories
(SRAMs), high speed transceivers, high-speed input/output
(I/O) elements, network interfaces, and even hard-embedded
processors
46
and A and fc, and 0 are the amplitude and frequency of the
sinusoidal carrier signal.
0<t<T
47
48
[4]
[5]
[6]
[7]
V. CONCLUSION
The choice of digital modulation scheme significantly affects
the characteristics and resulting physical realization of
communication system. This work describes the Concepts and
simulations to Methods of hardware implementations of all
the main digital modulation schemes used such as BASK,
BFSK, and BPSK. It elaborates the simulation to synthesis of
digital modulation schemes using the MATLAB/Simulink
program and its implementation in a XILINXs Spartan- III kit.
VII. REFERENCES
[2]
[3]
VI. ACKNOWLEDGEMENT
Authors are grateful to HoD, ECE, AKGEC for providing the
Deptt Lab facilities to undertake the research work.
[1]
49
Number of elements : 4
Input impedance : 50
VSWR: 1 1.4.
I. INTRODUCTION
ANTENNA is one of the important elements of a wireless
communications system. Wireless technology provides less
expensive alternative and a flexible way for communication.
Communication plays a vital role in the worldwide society nowa-days and the communication systems are rapidly switching
from wired to wireless. Accordingly, antenna design has
become one of the most active fields in the communication
studies.
50
The radiating patch and the feed lines are usually photo etched
on the dielectric substrate. Micro strip antenna consists of
very small conducting patch built on a ground plane separated
by dielectric substrate. The conducting patch, theoretically,
can be designed of any shape like square, triangular, circular,
or rectangular. However rectangular and circular configurations
are the most commonly used. Micro strip antenna has a
drawback of small bandwidth and low gain. The bandwidth
can be increased by cutting slots and stacking configuration
and Gain can be increased by using different patch elements in
an array to achieve optimum radiation characteristics.
51
V. DESIGN EQUATIONS
For an efficient radiation, the practical width of the patch can
be calculated by using the following.
W = 1/(2ro o)z/(r+1)
W = 29mm
Length of the antenna (L)
The radiation patterns at the center frequency 2.4GHz, for Sband is plotted as shown in Fig 4.
L = 0.49X0.123/ 4.2
L = 29mm
Free space wavelength (0)
0= C/F
0 = 0.125 mm
Effective Dielectric Constant (re)
= 4.18 mm
Guide wavelength (g)
= 0 /eff
= 6.1 mm
nret
VSWR
The value of voltage standing wave ratio (VSWR) should be
in the range between 1 and 2. The acceptable VSWR is 1.5.
Figure 5 shows below that the value of VSWR is close to the
ideal value of 1 and 2:1 VSWR Bandwidth = 0.89796 with the
measurements that are provided as shown in figure 5.
52
VII. CONCLUSION
This paper presents the design and performance analysis of
Micro strip Phased Array Antenna for WLAN Application.
Physical patch dimensions were calculated in HFSS. Antenna
simulator software was used to evaluate performance of the
patch. The selected patches were arranged in planner array
form for WLAN application. 4 patch elements were selected to
achieve high gain and good efficiency. This proposed antenna
model is found to be cost effective, features high efficiency for
applications in 2.45GHz frequency range. The optimum design
parameters were used to achieve the compact dimensions and
high radiation efficiency. It provides a gain of 16.31 dBi, 95.6
percent efficiency and VSWR < 2 is achieved over the complete
frequency band with linear polarization of antenna in the desired
part of the beam.
3D Polar Plots
The antenna should not have the side lobes and back lobes
ideally. We cannot remove them completely but we can minimize
them. Micro strip antennas can provide directivity in the range
of 14 dB as shown in figure 6.
VIII. ACKNOWLEDGMENT
The authors acknowledge Ajay Kumar Garg Engineering
College, Ghaziabad for providing inspiring and propitious
academic ecosystem and facilities.
IV. REFERENCES
[1]
[2]
Figure 6. 3D polar plot.
[3]
Return Loss
The S11 parameter for the proposed antenna was calculated
and the simulated return loss results are shown in Figure below.
The value of return loss is -16 dB in this proposed antenna.
The achieved return loss value is small enough and frequency
is very closed enough to the specified frequency band for 2.45
GHz WLAN applications. Return loss as shown in Fig: 7.
[4]
[5]
[6]
53
[10]
[11]
[12]
[13]
[14]
[15]
[16].
54
I. INTRODUCTION
MOLECULAR weight is an important parameter characterizing
a polymer sample. The molecular weight can be determined by
chemical or physical analysis which include functional group
analysis, by measurement of the colligative properties, light
scattering, ultracentrifugation or measurement of viscosity of
dilute solution. All methods except the last one are absolute.
The viscosity method is an indirect method but its value lies
in its simplicity and that it can be applicable to a large group of
polymer systems. All the physical methods require solubility
of the polymer and extrapolation to infinite dilution [1].
II. THEORY
When adjacent layers of a fluid move with relative velocity,
forces known as viscous forces come into play to reduce their
relative motion. When we consider a fluid whose upper layer
is moving with a velocity u in a fixed direction then a state will
be reached when the lower most layer is at rest and the
intermediate layers move with velocity less than u as shown in
Figure 1.
55
IV. CONCLUSION
It has been shown that the new method of measuring the MarkHauwink parameters yields results close to the values obtained
by other methods. The method described in this paper has a
positive future in context of determining the molecular mass of
a given polymer which is important as a quality control in
various polymer industries.
V. ACKNOWLEDGEMENTS
The authors thank Prof. P.K. Sharda, HOD Applied Science for
many fruitful discussions. The authors thank the facilities
provided by the chemistry lab of Ajay Kumar Garg Engineering
College, especially the Lab assistant Mr. Manoj Kumar.
VI. REFERENCES
B) Measurement of K
The data presented in ref[4] is used to verify equation (14) of
the appendix which is meant to calculate K. The table of ref [4]
which is used in the following calculation is reproduced here.
[1].
[2].
[3].
[4].
VII. APPENDIX
The derivation of important formulae which extract the Mark
Hauwink parameters from viscosity data alone:
Section a) The Mark Hauwink equation relates the intrinsic
viscosity of a polymer solution with its average molecular mass
through a set of parameters (a and K) which are dependent on
the nature of the polymer and the solvent. The Mark Hauwink
equation reads:
(3)
Dividing (1) by (2) we get:
[] = KMa
(4)
The quantity on the left hand side is called the intrinsic viscosity
and M on the right hand side is the average molecular mass of
the given sample of polymer. K and a are the Mark Hauwink
parameters.
(6)
[1] = KM1a
(6) becomes our governing equation to determine the parameter
a.
Now the solution is masticated for some given time so that the
polymer in the solution breaks down and its average molecular
mass reduces. Let the reduced average molecular mass be called
M2. The intrinsic viscosity of the masticated solution is also
extracted in the same way by experimenting on the new
solution. Let the new viscocity be called [2]. Then from the
Mark Hauwink equation:
[2] = KM2a
The original solution is made in duplicate. Now the two
solutions (Original +Masticated) are mixed together. Let the
total mass of the polymer before dissolution be TM. Then the
average molecular mass of the polymer in the solution is TM
divided by the no. of polymer molecules. Thus:
(7)
Let the values of a and K at temperature T1 and T2 be a1, a2, K1
and K2 respectively.
Then from (7):
(1)
(8)
And
.
(9)
We can get K2-K1 from the above equation (8).
57
(10)
And so:
(11)
(12)
And:
(13)
Which gives on simplification :
(14)
Equation (14) becomes the master equation for determining K.
The viscosities are measured and from it, the as are calculated
in the manner described in previous section.
58
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An Efficient Carry Select AdderA Review
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FPGA Implementation of Digital Modulators
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Design and Implementation of Inset feed Square Patch Micro strip Antenna Array for WLAN .....
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A Novel Method of Extracting Mark-Hauwink-Sakurada Parameters from Viscosity Data
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