Title: Image Rejection Wifi Receiver for 802.

11g

Group Members:
Lawrence Kaplan
Wilson Liang
Mark McSharry

Date: 6/11/2013

I Introduction
In our project, we followed the receiver architecture specified in the assignment as shown in Figure 1. In
addition, we have voltage regulators to tap out specific voltages needed for proper circuit performance, and
current sources used in the baseband amplifier stage. We used a cascaded LNA with input and output
matching networks, followed by a balun to split the RF signal into I and Q rails. We used a passive
differential input mixer with differential LO. We chose our LO to be 2.38Ghz to have an IF frequency of
20Mhz. After the down conversion, we used a passive LPF to filter out all the unwanted harmonics. After
filtering, the IF signal is amplified again and the I path is created by I = I+ -I- and the Q path is created by Q =
Q++Q-. The I and Q are then shifted to be 180o out of phase and added together to cancel out the image.

Figure 1: Image Rejection Receiver Chain

The simulations for ft and fmax for simple 10um device is shown in Figure s.

Figure 2: Ft and Fmax curves for 10um device

II Design
LNA
For our LNA design, we chose to utilize the common-source amplifier that we had previously utilized for the
homework shown in Figure 3. We chose this design to maximize the gain. We opted to include a commondrain stage at the output to help improve the stability of our circuit. To begin with, we used non-ideal
inductors at the gate and the source of the LNA to bias the input. We sized the source-degenerative inductor
to match the real part of the input impedance to 50; we then sized the gate inductor to the correct value
such that were able to nullify the imaginary component of the input impedance. Next, we added a matching
network to the output of our LNA, so as to match the output impedance to 50. To calculate the necessary
values of L and C, we found the real and imaginary parts of the output impedance and used Q to find the
correct inductor and capacitor sizes. Lastly, we added a blocking capacitor to the output of the LNA (after the
matching network) to block any DC signal from the LNA, as we had designed the mixer to be a passive
mixer with no DC bias (we did eventually change this misconception and opted to bias the passive mixer as

you will see later). Once we had completed the LNA design, we ran the following Cadence simulations: gain,
NF, IIP3, return loss, and stability for the amplifier by itself. Figures 4-6 show the LNA gain, noise figure,
and stability plotted over temperature, respectively. Figures 7-9 show the LNA IIP3 at -20C, 27C, 60C,
respectively. Lastly, Figure 10 shows the return loss over temperature.

Figure 3: LNA Circuit

Figure 4: LNA Gain vs Temp

Figure 5: LNA Noise Factor

Figure 6:LNA Stability

Figure 7:LNA IIP3 curve, T=-20C

Figure 8:LNA IIP3 curve, T=27C

Figure 9:LNA IIP3 curve, T=60C

Figure 10: LNA Return Loss

Mixer
For our mixer design, we elected to create a passive mixer shown in Figure 11. We envisioned that we could
get enough gain from our LNA and baseband amplifier stages, so we were willing to take the hit on the
convergence loss that the mixer brings to the chain. We were very attracted to the passive mixer design
because of the minimal power draw and simplistic layout. At first, we simply took the passive mixer design
that had been presented to us in lecture and used that in our receiver chain. After running the conversion gain
simulation, we found that we were around -12dB of convergence gain. This number seemed a little lower
than our intuition indicated, so we re-visited the convergence gain calculations for a simple passive mixer.
The hand analysis we performed showed that GC = 2/ -4dB. This shows that, at worst, our conversion gain
should be -7dB or -8dB. After some discussion (thank you Professor!), we decided bias the gates of each of
the transistors with ~vt, allowing the transistors to be easily switched on and off. After implementing this
change, we found our conversion gain to be as good as -7dB with an optimal bias voltage. Once we had
completed the mixer design, we ran the following Cadence simulations: conversion gain, NF, and IIP3.
Figures 12-13 show the conversion gain and noise figure plotted over temperature, respectively. Figures 1416 show the mixer IIP3 at -20C, 27C, 60C, respectively.

Figure 11: Passive Mixer

Figure 12: Mixer Conversion Gain

Figure 13: Mixer Noise Figure

Figure 14:Mixer IIP3, T=-20C

Figure 15:Mixer IIP3, T=27C

Figure 16: Mixer IIP3, T=60C

Low-Pass Filter
For our LPF design, we used an RC filter shown in Figure 17. When simulating a one stage RC filter, the
attenuation levels were not rolling off fast enough, so we continued adding stages until we got the desired
response. After a few iterations, we found that 8 stages were enough to get the desired response. We believe
this filter should be improved upon since non-ideal resistors in the models will give us loss in the pass band.

Figure 17: RC LPF Circuit

Polyphase Filter
The inputs to the passive mixer were generated from the single allotted sine wave source. The mixer
required four separate input signals: VLO+, VLO-, V90+, and V90-. VLO+ and VLO- were 180 out of phase from
one another. V90+ and V90- were also 180 out of phase from one another, and additionally were 90out of
phase from VLO+ and VLO-, respectively. To accomplish the required phase shifts, we used two 45 shifting
blocks in conjunction with an RC polyphase Shifter. The 45 shifting blocks were used to create VLO+ and
VLO-. These were then fed into the polyphase to generate V90+ and V90-. In order to properly size the
polyphase shifter at the single frequency of operation we used the following formula.

At 2.38 GHz and R = 100, this corresponds to a capacitance of 633.146 F. The circuit layout can be seen in
Figure 18, while the output waves can be seen in Figure 19.

Figure 18: Polyphase Filter Circuit

Figure 19:Output waveforms of the Polyphase Filter.

Voltage Regulator
The voltage regulator was used to generate an 800mV supply line. We were allotted two DC supplies, which
we used for VDD and a 600mV bias. We required a third supply at 800mV to bias several transistors.
Rather than build a mirror for each bias, we elected to build a single supply that could be tapped for all the
800mV biases. In the end this saved on power consumption, as the regulator was designed with three low
current paths from VDD to ground. Had we built a mirror for each bias we would have likely doubled this
power consumption, and in the process decreased our Figure of Merit. Also, because the regulator was
designed entirely from transistors it is not affected much by changes in temperature, as a resistive mirror
would be. To generate the appropriate output voltage, the values of the transistors were adjusted. The
second level, PMOS on the far right is the dominant controller of the V800m bias as seen in Figure 20.

Figure 20: Voltage Regulator Circuit

Baseband Amplifier
The Baseband Amplifier was designed with power consumption in mind. To this end, we developed an
amplifier with the maximum amount of gain from a single stage. An initial attempt at a single-ended design
did not have enough bandwidth. and rather than add an additional stage, we elected to create the fully
differential amplifier seen in Figure 21. The load resistors increase our output resistance, thereby increasing
gain. However, in order to obtain a gain of about 15dB, the resistor would need to be sized so large that it
would drop our entire supply voltage across it. To prevent this, we added bleed transistors in parallel with
each resistor. This allowed for a large output resistance, while keeping the output bias at approximately
VDD/2.

Figure 21: Baseband Amplifier Circuit

The baseband amplifier was simulated with a 50 load. It was found that the amplifier gain was
significantly impacted by this load (Vout < 1mV). The output was therefore increased to 10k. The gain and
bandwidth values seen in Figure 22 are for this load resistance. For 27C and 60C, the amplifier has a gain
of 12-13dB and a bandwidth of 750-900MHz. However, at -20C the gain decreases to -5dB. This is likely

due to the non-idealities of the load resistors as show. If the resistor value were to increase significantly, the
output bias could be driven to ground.

Figure 22:Gain and Bandwidth for the Baseband Amplifier terminated with 10k.
The IIP3 was also simulated at the previously mentioned temperatures. The curves can be seen in Figures
23-25. All three curves fit well, and have IIP3 values in the range of -6 to -11dBm. The simulation at -20C
has a non-linear component for input power between -10 and -20dBm.

Figure 23: Baseband IIP3, T=-20C

Figure 24:Baseband IIP3, T=20C

Figure 25: Baseband IIP3, T=60C

III Combination Results

From the individual simulations, we calculated the projected receiver performance since we had cadence
crash and disk issues even after deleting all of our old files.
This architecture is designed for image rejection, so we expect a high image rejection ratio although we were
unable to simulate.
Below are the summarized results for our receiver performances:

LNA

Gain
(dB)
19.37

IIP3
(dBm)
-12

Mixer

-9

7.7

Baseband
Amp

12.9

-11

N/A

Total

23.27

-16.4

2.2

NF (dB)
1.1

SFDR = (2/3)( IIP3TOT MDS) = (2/3)(-16.4dBm (-80dBm)) = 42.4dBm

PDC = 14.8mW = 11.7 dBm
FOM = GTOT * (SFDR) / PDC = 23.3dB + 42.4dBm 11.7dBm = 54 dB

IV Conclusion
Although our receiver did not work as a whole, we learned and appreciated the difficulty in designing a
receiver chain. The individual building blocks of our receiver show promising results. If we could get this
receiver working and tuned it properly, we believe that we can meet the specs based on our theoretical
calculations. Future improvements to this receiver includes an on chip local oscillator, new filter design that
requires less stages and better stop-band attenuation.