Mark N.

Egbers
325 Van Ness Ave., Santa Cruz, CA 95060
831.325.4038
mrkegbers@gmail.com

OBJECTIVE

Electrical Design Engineer, Project Leader / Manager

SUMMARY

Engineer/Manager with long history of success contributing to reliable, best-in-class Integrated Circuit
(IC) Design and IC Stacked-Die Package Design. Designed and/or managed over 400 successful
projects to date. Project management from original customer request for quote (RFQ) through release
to manufacturing. Adept at gathering and translating complex requirements into viable solutions. Excel
at collaborating across departments, coordinate with staff and managers to complete projects on time
and within budget. Customers included tier 1 DRAM and NAND Flash manufacturers.
Skills include: Engineering team and project management, digital and analog IC circuit and logic
design, package design, signal integrity analysis, circuit simulation, thermal analysis, customer
technical applications support, ISO9001 qualified design standards and documentation.
Tools include: Cadence SigXPlorer, Verilog, AutoCAD, ICAP/4 SPICE, Polar 2D Field Solver

CAREER HISTORY
5/1998 –11/2008
Vertical Circuits, Inc. Scotts Valley, CA

Chief Design Engineer

Design of industry leading density stacked DRAM, NAND Flash, SRAM, and ASIC devices including
LGAs, BGAs, and TSOPs. Responsible for project management, RDL (Re-Distribution metal Layer)
design on top of existing ICs to bring the base die pads to the periphery to allow vertical interconnection
along the side(s) of the die stack to the substrate for stacked die packages. Extracted the parasitic
electrical parameters and performed SI (Signal Integrity) simulation and analysis to meet industry
leading JEDEC DDR DRAM and NAND Flash ONFI standards.
Provided design and applications engineering technical customer support including architecture system
design for 2, 4, 8, and 16 high stacked die devices and thermal analysis for the stacked die packages.
Provided test, manufacturing, product, and reliability engineering support including ISO 9001 qualified
design standards and documentation.

2/1990-4/1998
GEC Plessey Semiconductor, Inc. San Jose/Scotts Valley, CA

Northwest Design Center Manager 1994-1998

Responsible for managing the principal US ASIC design center. Complete design engineering project
responsibility from pre-sales to production release. Hands on” design engineering manager. Strong
pre-sales engineering customer support and board level design consulting including advanced industry
standard inter-tool CAD design methodology, ASIC power dissipation, required power supply pinning
and placement, analog cell design support and development, and internal clock design methodology.
 Scotts Valley Design Center Manager 1990-1994
Managed large design engineering team supporting direct and turnkey customer ASIC designs from
pre-sales through production release supporting digital and mixed-mode CMOS and bipolar designs
including high volume PC, disk drive, and automotive high-quality conscious customers.

Ferranti Interdesign Scotts Valley, CA 7/1988-2/1990

New Product Development Manager, CMOS Semicustom

Developed the very successful digital “MH” and analog/digital “MA” series of gate arrays. Performed
circuit design and layout, cell library design and layout, SPICE models, design and test methodology.
Wrote comprehensive design manuals allowing customers to design, simulate and layout their own
digital or mixed mode ASICs.

Interdesign Inc. Scotts Valley, CA 10/1982-7/1988

Applications Engineering Manager, 1985-1988

Customer applications pre-sales design support for digital and analog/digital CMOS ASICs.
Member of the Technical Staff, 1982-1985

Turnkey CMOS ASIC designs from customer specifications.

Gould SEL Computer Systems Sunnyvale, CA 11/1980- 9/1982

Member of the Technical Staff

Complete circuit design and project responsibility for a full custom NMOS instruction unit for a 16 bit
minicomputer.
Provided transistor and layout design support for an internal CAD team as they developed the
DRACULA DRC/ERC/LVS IC design verifications software. This group later became ECAD and
ultimately merged with CADENCE.

Perkin Elmer Data Systems Santa Cruz, CA 6/1978-8/1980

Member of the Technical Staff

Complete circuit design and project responsibility for a full custom NMOS instruction unit for a 16 bit
minicomputer.

Texas Instruments, Inc. Houston, TX 6/1973-6/1978

Project Design Engineer and Engineering Technician/Co-op

Circuit design and layout- RAM/EPROM memory chip, SR50 Scientific calculator chipset, and single
chip 4-function calculator.

EDUCATION
BSEE, University of Houston Houston, TX 1976
US citizen