Name:_____________________________________________

Matric No:__________________

INTERNATIONAL ISLAMIC UNIVERSITY MALAYSIA

MID-TERM EXAMINATION
SEMESTER III, 2008/2009 SESSION
KULLIYYAH OF ENGINEERING
Course Code : ECE 1231

Course Title: Electronics

Time

Date

: 8:30 pm-10:00 pm
Duration

: 04-June-2009

: 1 Hour 30 Minutes

INSTRUCTIONS TO CANDIDATES

DO NOT OPEN UNTIL YOU ARE ASKED TO DO SO

Do not use your own sheet.

A total mark of this examination is 60.
This examination is worth 30% of the total assessment.
Answer ALL questions.

Any form of cheating or attempt to cheat is a serious offence

which may lead to dismissal.

Marks
Marks
Obtained

Question
1
15

Question
2
15

Question
3
15

Question
4
15

Total
Marks
60

Midterm Examination

Semester III 2008/2009

Q.1 [15 marks]

(a) The electron concentration in silicon at T = 300 K is n0 = 51015 cm-3 and the intrinsic
carrier concentration is ni = 1.51010 cm-3. Determine the hole concentration. Is the
material n-type or p-type?
(4 marks)

(b) A gallium arsenide pn junction has a diode current of ID = 12 mA when biased at VD =

1.10 V. Determine the reverse-bias saturation current. Using the result of the previous
part, determine the diode current when the diode is biased at VD = 1.0 V.
(5 marks)

Midterm Examination

Semester III 2008/2009

(c) The diode cut-in voltage is V = 0.7 V in the two circuits shown in Fig. 1 (c). Find I and
V0 in each of the circuits.
(6 marks)

Fig. 1 (c)

Midterm Examination

Semester III 2008/2009

Q.2 [15 marks]

(a) The input signal voltage to the half-wave rectifier circuit in Fig. 2 (a) is
I 80 sin[ 2 (60)t ] V and the transformer turns ratio is N1/N2 = 6. If V = 0.7 V and rf
= 0, determine (i) the peak diode current for R = 10 K and (ii) the average value of the
output voltage.
(5 marks)

Fig. 2 (a)

Midterm Examination

Semester III 2008/2009

(b) In the voltage regulator circuit in Fig. 2 (b), V I 20 V, VZ 10 V, Ri 200 , and

R L 250 . Determine I L , I Z , and I I .
(6 marks)

Fig. 2 (b)

(c) The diodes in the circuit in Fig. 2 (c) have piecewise linear parameters of V 0.7 V and
r f 0 . Determine the output voltage VO and the diode currents I D1 and I D 2 for the
input: V1 = V2 = 10 V.
(4 marks)

Midterm Examination

Fig. 2 (c)

Semester III 2008/2009

Midterm Examination

Semester III 2008/2009

Q.3 [15 marks]

(a) For the diode clipper circuit in Fig. 3 (a), plot O versus time over two periods for
sinusoidal input signal. Assume V 0 .
(5
marks)

Fig. 3 (a)

(b) A diode clamper circuit with sinusoidal input signal is shown in Fig. 3 (b). Assume
V r f 0 . Plot (i) the capacitor voltage versus time and (ii) the output voltage versus
time.
(6 marks)

Fig. 3 (b)

Midterm Examination

Semester III 2008/2009

(c) Consider the diode AND logic circuit in Fig. 3 (c). Assume V 0.6 V for each diode.
Determine the output VO for: (i) V1 V2 0 ; (ii) V1 0 , V2 5 V; (iii) V1 5 V,
V2 0 ; (iv) V1 V2 5 V.
(4 marks)

Fig. 3 (c)