Академический Документы
Профессиональный Документы
Культура Документы
The main difference between the Full Adder and the previous Half Adder is that a full
adder has three inputs. The same two single bit data inputs A and B as before plus an
additional Carry-in (C-in) input to receive the carry from a previous stage as shown below.
Then the full adder is a logical circuit that performs an addition operation on three binary
digits and just like the half adder, it also generates a carry out to the next addition column.
Then a Carry-in is a possible carry from a less significant digit, while a Carry-out represents
a carry to a more significant digit.
Truth Table
C-in
Sum
C-out
+)
CO
0+0=0
0+1=1
1+0=1
1 + 1 = 0 with a Carry of 1
Inputs
Outputs
CO
Figure 7: A 4-bit Ripple Adder constructed with four Basic Full Adders
Addition between two Multi-bit Binary Numbers P and Q is done by adding the bits successively, starting from the
Least Significant Bit (LSB), i.e. P0 + Q0. Any Carry bit from previous bits is added to the sum of the next consecutive
bits, Figure 8.
P0 = 20 = 1
P1 = 21 = 2
P2 = 22 = 4
P3 = 23 = 8
P4 = 24 = 16
The formula for converting a 5-bit Binary Number P2 (P4 P3 P2 P1 P0) to its corresponding Decimal Number P 10 is:
P10 = P4 x 24 + P3 x 23 + P2 x 22 + P1 x 21 + P0 x 20
The CO bit of a 4-bit Full Adder is equivalent to the 4th significant bit and its weight is 16 (2 4 = 16).
The largest decimal sum that can be obtained from a 4-bit Full Adder is 31 (2 4+1 - 1 = 31).
Half Adder:
Half adder is simple example of combinational logic circuit with 2 logic gates. This digital circuit performs
addition operation between two binary numbers. The half adder operation needs two inputs: augend and
addend bits and provides two outputs sum(s) and carry(c).
In order to get the simplified Boolean equations for sum and carry we use K- map. The below figure
shows you how to get logic functions for sum and carry from truth table.
Full Adder:
Full adder is digital circuit used to calculate the arithmetic sum of three bits. Full adder is little difficult to
implement than half adder. Full adder consists of three inputs and 2 outputs. The first 2 inputs are
augend and addend and 3rd input is the carry of previous digit operation. The first two inputs are denoted
by A and B, carry of previous operation is denoted by Cin.
Now let us see how to get the Boolean functions for sum and carry from the truth table using K map.
Half adder
Last Updated on March 29, 2012 by admin in Digital Electronics with 14 Comments
To understand what is a half adder you need to know what is an adder first. Adder
circuit is a combinational digital circuit that is used for adding two numbers. A typical
adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the
output. Typically adders are realized for adding binary numbers but they can be also
realized for adding other formats like BCD (binary coded decimal, XS-3 etc. Besides
addition, adder circuits can be used for a lot of other applications in digital electronics
like address decoding, table index calculation etc. Adder circuits are of two types:
Half adder ad Full adder. Full adder s have been already explained in a previous
article and in this topic I am giving stress to half adders.
Half adder is a combinational arithmetic circuit that adds two numbers and produces
a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum
bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From
this it is clear that a half adder circuit can be easily constructed using one X-OR gate
and one AND gate. Half adder is the simplest of all adder circuit, but it has a major
disadvantage. The half adder can add only two input bits (A and B) and has nothing
to do with the carry if there is any in the input. So if the input to a half adder have a
carry, then it will be neglected it and adds only the A and B bits. That means the
binary addition process is not complete and thats why it is called a half adder. The
truth table, schematic representation and XOR//AND realization of a half adder are
shown in the figure below.