Physical Verification Signoff for DDR IP

using PVS
Tobing Soebroto,
Cadence IP Group
Presented at Signoff Summit
Nov 21, 2013

Agenda

1. Cadence IP Factory
2. Signoff Challenges
3. Why PVS for Physical Verification

4. Conclusions

2013 Cadence Design Systems, Inc. All rights reserved.

Growing IPG with the Best

Acquisition of
key IP
Tensilica joins IPG

Expansion to
existing Analog
Team

Cosmic joins IPG

Denali joins Cadence Systems

Evatronix to join IPG

Pre - 2013

Q2 2013

Building a
comprehensi
ve
ecosystem
partners,
customers,
foundries,
design
houses, etc.
Q3+ 2013

Denali acquisition - strong memory IP and models

Analog team expands analog capabilities
IP acquisition provides key mobile IP technology
Tensilica adds innovative and system level IP to portfolio
Cosmic expands AMS IP and provides key mobile IP
Evatronix will complement USB and memory IP offering

2013 Cadence Design Systems, Inc. All rights reserved.

Cadence Confidential

Cadence IP Factory
Next Gen SoCs
DRAM

NAND

PCIe

Ethernet

USB

MIPI

AMS

Ctrl.+PHY

Ctrl.+PHY

Ctrl.+PHY

MAC+PCS+PHY

Ctrl.+PHY

Ctrl.+PHY

Analog Mixed
Signal

DDR1/2

ONFi 1/2/3

Gen1

10/100 MAC

USB 2

DSI

ADC/DAC

USB 3

CSI

AFE

USB OTG

SLIMbus

SENSORS

USB Hub

DigRF

PLL/DLL

HSIC

BIF

PVT mon

USB 2 PHY

D-PHY

SERDES

USB 3 PHY

M-PHY

Power
Mgmt

DDR3

1G MAC

Toggle 1/2
Gen2

DDR4

10G MAC

Async
LPDDR1/2
LPDDR3

LPDDR4

SDIO
Device
SD/SDIO
Host
1/2/3/3.2/4

Gen3

Gen3

AVB
MMC/eMMC

HMC

100G MAC

L1 substate

Wide I/O
Wide I/O 2

40G MAC

M-PCIe

4.2/4.4/5.0

UHS I/II

Auto
Ethernet
PCIe PHY

2013 Cadence Design Systems, Inc. All rights reserved.

10GKR

Cadence DDR PHY IP

Silicon proven, highest performance PHY
Robust PHY IP ready for system integration

First to market DDR2400, WideIO, LPDDR4

Complete jitter analysis and char. reports
Verified with leading memory models
System Design-In Kit : PCB modeling: SI/PI analysis

HS PHY

Scalable to 3200 performance

Per bit de-skewing, per rank leveling
DDR3/4/3L, LPDDR2/3/4 support
DDR2400 silicon characterization

DFI 2.1/3.1 Interface

Delay line
on DQS

Synthesizable
PHY logic

Per-bit DQ
Delay line

LP PHY

Up to 1600 performance
Lowest power/area, integrated hard controller
DDR2/3/3L LPDDR2/3 support
High volume production

IO Pads

IP around your chip, not other way round

8 bit hardened slices + IO + PLL integration ready
Flexible IO ordering, bump pitch, form factor
Custom, fully hardened PHY option

2013 Cadence Design Systems, Inc. All rights reserved.

DRAM interface

HS PHY

Motivation to Develop IPs Early

With shorter design cycle, IP is a key component of the
design realization
Foundry
Foundries like to work with IP companies and make available the
widest range of IP to win new design customers

Cadence IP Group
Be first to market with differentiated IP
Cover a broad range of customer needs
Get as many customers fast

2013 Cadence Design Systems, Inc. All rights reserved.

Signoff Challenges to Overcome

Foundry:
The IP has to developed early and be available to customers, before
the new designs come for production
This requires the infrastructure to be ready early for IP companies,
like rule decks, techfiles, PDKs,

Cadence IP Group
IP products support multiple new foundries
Tools used must support leading edge technologies/process nodes
for example, TSMC 16FF technologies
Must help to improve productivity and achieve fastest time to market
Design impact needs to be understood
Mixed Signal flows
Reduce debugging time
Reduce Iterations/loops to signoff
7

2013 Cadence Design Systems, Inc. All rights reserved.

Primary Requirement: Rule Deck Availability

PVS History and Status

Previously
PVS rule decks were available by request to the foundry
and Cadence foundry team

Now
PVS is available online at selected foundries early with
other signoff tools

Decision:
PVS is our plan of record where decks are available and
has been used on numerous tapeouts

2013 Cadence Design Systems, Inc. All rights reserved.

Mixed Signal Design Challenges

Mixed verilog and schematic view
We liked the tight integration of PVS
in Virtuoso
No translation of Verilog to CDL. Verilog is
read directly.
No manual translation of dfII to CDL.
No need prepare mapping for probing in
dfII.
No need to merge netlists.
No need to create scripts.
Batch oriented
submission

PVS GUI
submission
9

Convert Verilog
to CDL

Convert dfII to CDL

+ mapping

One pass submission

2013 Cadence Design Systems, Inc. All rights reserved.

Merge netlists

Significant gain for mixed analog/digital schematics

Reduced Probing Time

Probing from error report to dfII.

Mixed Signal Designs input

schematic is mix of dfII,
Verilog and CDLs:
PVS LVS Debug
Environment eases probing
by providing:

Probing from error report to Verilog

From error report to dfII.

From error report to Verilog

From error report to
CDL/SPICE

10

2013 Cadence Design Systems, Inc. All rights reserved.

Probing from error report to CDL/SPICE

PVS ISL Facilitates One-Pass Short Isolation

Debugging Time savings
Conventional way
of debug
Hundreds shapes
of net 122 to
investigate

PVS ISL reduced the

number of shapes to
debug to ~10 and
exactly pointed to the
short.

11

2013 Cadence Design Systems, Inc. All rights reserved.

We start Debugging While Run is in Progress

As soon as first results are available

Conventional way of debug: thousands shapes of ground net gnd to

investigate.
PVS ISL reduced number of shapes to debug to ~30 and exactly points
to short.

12

2013 Cadence Design Systems, Inc. All rights reserved.

Conclusion
PVS is the plan of record for Cadence IP group
PVS has many technologies which ease and fasten signoff
time to tapeout
In-design applications which reducing debugging time
Timing aware dummy metal fill
Interactive DRC with IPVS
Advanced node technology support

Cadence IP group have completed numerous production

tape-outs with PVS

13

2013 Cadence Design Systems, Inc. All rights reserved.