MLR

Institute of Technology

Laxma Reddy Avenue, Dundigal, Quthbullapur (M), Hyderabad 500 043

ELECTRONICS AND COMMUNICATION ENGINEERING

COURSE DESCRIPTION FORM

I.

Course Title
Course Code

DIGITAL DESIGN USING VERILOG HDL

Regulation
Course Structure

R13-JNTUH
Lectures
5

Course Coordinator
Team of Instructors

Ms.A.Deepthi, Assistant Professor

A40410
Tutorials
1

Practicals
-

Credits
4

Ms.A.Deepthi Assistant Professor,;

Mr. M.Srikanth, Assistant Professor

COURSE OVERVIEW:
As the size and complexity of digital systems increase, more computer aided design (CAD) tools are
introduced into the hardware design process. Early simulation and primitive hardware generation tools have
given way to sophisticated design entry, verification, high-level synthesis, formal verification, and
automatic hardware generation and device programming tools. Growth of design automation tools is
largely due to hardware description languages (HDLs) and design methodologies that are based on these
languages. Based on HDLs, new digital system CAD tools have been developed and are now widely used
by hardware designers. At the same time research for finding better and more abstract hardware languages
continues. One of the most widely used HDLs is the Verilog HDL. Because of its wide acceptance in
digital design industry, Verilog has become a must-know for design engineers and students in computerhardware-related fields.

II.

PREREQUISITE(S):

Level
UG

Credits
4

Periods / Week
5

Prerequisites
Switching Theory and Logic Design

Good logical skills and logical analysis

III.

MARKS DISTRIBUTION:
Sessional Marks (25 Marks)

University Total
End Exam Marks
Marks
75
100

Mid Semester Test

There shall be 2 midterm examinations.
Each midterm examination consists of subjective type and Objective type tests.
The subjective test is for 10 marks, with duration of 1 hour.
The objective type test is for 10 marks with duration of 20minutes.
It consists of 10 Multiple choice and 10 fill in the blanks.
The student has to answer all the questions and each carries half mark.
First midterm examination shall be conducted for the first two and half units of
syllabus and second midterm examination shall be conducted for the remaining
portion.
Five marks are earmarked for assignments.
Marks shall be awarded considering the average of two midterm examinations in
each course reason whatsoever, will get zero marks(s).
IV.

EVALUATION SCHEME:
Mid Semester Test

25 marks

End Semester Examination

75 marks

S. No
1
2
3
4
5

V.

Component
I Mid examination
I assignment
II Mid examination
II Assignment
External examination

Duration
80 minutes
-80 minutes
-3
hours

Marks
20
05
20
05
75

COURSE OBJECTIVES:
1.

To understand the constructs and conventions of the Verilog HDL programming.

2.

To understand the structural, register-transfer level (RTL), and algorithmic levels of abstraction for
modeling digital hardware systems.

3.

To design and modeling of combinational and sequential digital systems (Finite State Machines).

4.

To understand and apply the concept of test-benches to create testing behavioral environments for
simulation based verification.

5.

To study advanced features of verilog HDL and apply them to design complex real time digital
systems.

VI.

VII.

COURSE OUTCOMES:
1.

Able to design, simulate, and synthesize computer hardware using the Verilog hardware description
language.

2.

Able to develop program codes for gate level and data flow modeling of combinational and sequential
logic using Verilog HDL in any problem identification, formulation and solution.

3.

Able to develop program codes for behavioral modeling of combinational and sequential logic using
Verilog HDL in any problem identification, formulation and solution.

4.

Able to develop program codes for circuit level modeling using Verilog HDL

5.

Able to design complex state machines (present in all practical computers) that are functional.

HOW COURSE OUTCOMES ARE ASSESSED:

Program Outcomes
A

An ability to apply the knowledge of mathematics, science, and

engineering to solve Electronics and communications engineering
problems.

Proficiency
assessed by
Assignments

An ability to design and conduct engineering experiments, as well as to

analyze and interpret data.

Assignments

--

An ability to design and construct a hardware and software system,

component, or process to meet desired needs, within realistic
constraints.

Level

An ability to function on multi disciplinary teams.

D

Designing,
Exercises

E
F

An ability to identify, formulate and solve engineering problems.

An understanding of professional, social and ethical responsibility.

Designing .

--

An ability to communicate effectively.

--

The broad education necessary to understand the impact of engineering

solutions in a global, economic, environmental, and societal context.
An ability to recognize the need for and an ability to
engage in life long learning.

Prototype

Models
--

Document
Preparation,

Presentation
Assignments

An ability to gain knowledge of contemporary issues.

An ability to use the techniques, skills, and modern engineering tools

necessary for engineering practice.

Assignments

Graduates are able to participate and succeed in competitive

examination like GRE, GATE, TOEFL, GMAT etc.

The use of current application softwares; the design and use of circuits;
and the analysis, design, testing, and documentation of Analog and
Digital circuits for the use in Communications engineering.
M

Presentation

Assignments

The basic knowledge of electronics, electrical components, computer

architecture
and
applications
of
microcomputer
systems,
communications needed in data transport.
N
N = None

VIII.

S = Supportive

H = Highly Related

SYLLABUS:
UNIT - I

INTRODUCTION TO VERILOG:
Verilog as HDL, Levels of design Description, Concurrency, Simulation and Synthesis, Functional
verification, System Tasks, Programming Language Interface (PLI), Module, Simulation and Synthesis
Tools, Test Benches.
LANGUAGE CONSTRUCTS AND CONVENTIONS:
Introduction, Keywords, Identifiers, White Space Characters, Comments, Numbers, Strings, Logic Values,
Strengths, Data Types, Scalars and Vectors, Parameters, Operators.
UNIT - II

GATE LEVEL MODELING:

Introduction, AND Gate Primitive, Module Structure, Other Gate Primitives, Illustrative Examples, TriState gates, Array of Instances of Primitives, Design of Flip Flops with gate primitives, Delays,
Strengths and contention Resolution, Net Types, Design of Basic Circuits.
MODELING AT DATA FLOW LEVEL:
Introduction, Continuous Assignment Structures, Delays and Continuous Assignments, Assignment to
vectors, Operators.
UNIT - III

BEHAVIORAL MODELING:
Introduction, Operations and Assignments, Functional Bifurcation, Initial Construct, Always Construct,
assignments with Delays, Wait Construct, Multiple Always Blocks, Designs at Behavioral Level, Blocking
and Non-Blocking Assignments, The case statement, Simulation Flow if and if-else constructs, assign
deassign construct, repeat construct, for loop, the disable construct, while loop, forever loop, parallel
blocks, force-release construct, Event.
UNIT - IV
SWITCH LEVEL MODELLING:
Basic Transistor Switches, CMOS Switch, Bi directional Gates, Time Delays with Switch Primitives,
Instantiations with Strengths and Delays, Strength Contention with Trireg Nets.
SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES:
Parameters, Path Delays, Module Parameters, System Tasks and Functions, File Based Tasks and
Functions, Compiler Directives, Hierarchical Access, User-defined Primitives (UDP).

UNIT V

SEQUENTIAL CIRCUIT DESCRIPTION:

Sequential Models Feedback Model, Capacitive Model, Implicit Model, Basic Memory
Components, Functional Register, Static Machine Coding, Sequential Synthesis
Component Test and Verification: Test bench Combinational Circuit Testing, Sequential
Circuit Testing, Test bench Techniques, Design Verification, Assertion Verification.

TEXT BOOKS:
1. T. R. Padmanabhan and B. Bala Tripura Sundari, Design through Verilog HDL Wiley, 2009.(T1)
nd
2. Zainalabdien Navabi, Verilog Digital System Design, TMH, 2 Edition (T2)
REFERENCE BOOKS:

1. Fundamentals of Digital Logic design with Verilog Design Stephen Brown and Zvonko
nd
Vranesic, TMH, 2 Edition, 2010. (R1)
2. Advanced Digital Logic Design using Verilog, State Machine & Synthesis for FPGA Sunggu
Lee, Cengage Learning, 2012 (R2)
nd
3. Verilog HDL Samir Palnitkar, 2 Edition, Pearson Education, 2009. (R3)
4. Advanced Digital Design with Verilog HDL Michael D. Ciletti, PHI, 2005 (R4)
IX.

COURSE PLAN:
At the end of the course, the students are able to achieve the following course learning outcomes:
Lecture
Course Learning
Topics to be covered
Reference
No.
Outcomes
1-3
Outline the importance of Introduction To Verilog, Need of
T1:1
HDL in VLSI domian
VLSI and HDLs
4
Identify the various
Verilog as HDL, Levels of design
T1:2.1-2.2
design styles in Verilog
Description
5-7
List and Memorize the
Concurrency, Simulation and
T1: 2.3features of Verilog HDL.
Synthesis Functional, Verification,
2.10
System Tasks, Programming
Language Interface (PLI), Module,
Simulation and Synthesis Tools,
Test Benches.
8-11
Indicates the constructs
Introduction, Keywords, Identifiers, T1: 3.2
inVerilog HDL
White Space Characters,
3.14
Comments, Numbers, Strings,
Logic Values, Strengths, Data
Types, Scalars and Vectors,
Parameters, Operators.
12
Discuss the constructs for Introduction, AND Gate Primitive,
T1: 4.1

Lecture
No.

Course Learning
Outcomes
gate level modelling

13-15
16

Designs gate level models

Discuss tri state gates

17-19

Designs flip flop using

Verilog
Lists various delays in
gate level modelling
Designs Verilog modules
Identify assignment
statements in data flow
model along with delays
and vectors. Lists various
operators
Design data flow models
Identify the important
features of behavioral
modeling

20-21
22-24
25-27

28-30
30-31

32-33
34

35-36
37

38
39-40

41

42-44
45-47

48

49-50

51 -52

Designs Verilog modules

Lists the delay features of
behavioral modelling,
wait construct
Designs Verilog modules
Differentiate blocking
and non-blocking
statement
Illustrate Case construct
and simulation flow
Illustrate if, assigndeassign, repeat, for,
disable, while, forever
constructs
Illustrate parallel blocks,
force- release and event
constructs
Designs Verilog modules
Outline basic switches in
Verilog with delays,
strength contention

Discuss parameter and

path delay in behavioral
modeling
Lists system tasks and
functions in Verilog

Demonstrate UDPs

Topics to be covered

Reference

Module Structure, Other

Gate
Primitives
Illustrative Examples,
Tri-State Gates, Array of Instances
of Primitives
Design of Flip Flops with gate
primitives
Delays, Strengths and Contention
Resolution, Net Types
Design of Basic Circuits.
Introduction, Continuous
Assignment Structures, Delays and
Continuous Assignments,
Assignment to Vectors. Operators
( Unary, Binary, ternary)
Examples
Introduction, Operations and
Assignments, Functional
Bifurcation, Initial Construct,
Always Construct
Examples
Assignments with Delays, Wait
Construct, Multiple Always Blocks

4.4

Designs at Behavioral Level

Blocking and Non-Blocking
Assignments,

T1: 7.10
T1: 7.11

The case statement, Simulation

Flow
if and if-else constructs, assign
deassign construct, repeat
construct, for loop, the disable
construct, while loop, forever loop
parallel blocks, force-release
construct, Event.

T1: 7.12

Exercises

T1: 8.12

Basic Transistor Switches, CMOS

Switch, Bi directional Gates,
Time
Delays with
Switch
Primitives, Instantiations
with
Strengths
and Delays, Strength
Contention with Trireg Nets.
Parameters, Path Delays, Module
Parameters

T1: 10.2
10.7

T1: 4.5
T1: 4.6
4.7
T1: 5.2
T1: 5.35.5
T1: 5.6
T1: 6.2
6.5

T1: 6.6
T1: 7.1
7.5

T1: 7.6
T1: 7.7
7.9

T1: 8.2
8.8
T1 : 8.9
8.11

T1: 11.2
11.4

System Tasks and Functions, File T1: 11.5

Based
Tasks and
Functions, 11.8
Compiler Directives, Hierarchical
Access
User-defined Primitives (UDP).
T1: 9.4

Lecture
No.
53-54

55-56
57-58
59-60
61-62
63

64
65

X.

XI.

Course
Code
A40410

Topics to be covered

Demonstrate memory
design in Verilog
Discuss various
functional register
Illustrate Static machine
coding
Explain sequential
synthesis
Model Test benches for
both combinational and
sequential circuits
Describe test bench
techniques
Describe design
verification and assertion
verification

Reference

Sequential Models Feedback

Model, Capacitive Model, Implicit
Model
Basic Memory Components

T2: 5.1

Functional Register

T2: 5.3

Static Machine Coding

T2: 5.4

Sequential Synthesis

T2: 5.5

Test bench Combinational Circuit

Testing, Sequential Circuit Testing

T2: 6.1

Test bench Techniques

T2: 6.2

Design Verification,Assertion
Verification

T2:
6.4,6.5

MAPPING COURSE OBJECTIVES

PROGRAMME OUTCOMES:

Course
Outcomes

1
2
3
4
5

Course Learning
Outcomes
Classify sequential
models

LEADING

TO

THE

T2: 5.2

ACHIEVEMENT

OF

Program Outcomes

MAPPING COURSE OUTCOMES LEADING TO THE ACHIEVEMENT OF PROGRAMME

OUTCOMES:

II-II SEMESTER

M N

Digital design using verilog HDL

CO1: Able to design, simulate, and
synthesize computer hardware using the
Verilog hardware description language.
CO2: Able to develop program codes
for gate level and data flow modeling of
combinational and sequential logic
using Verilog HDL in any problem
identification, formulation and solution

CO3: Able to develop program codes

for
behavioral
modeling
of
combinational and sequential logic
using Verilog HDL in any problem
identification, formulation and solution

CO4: Able to develop program codes

for circuit level modeling using Verilog
HDL

CO5: Able to design complex state

machines (present in all practical
computers) that are functional.