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F0064

Load Control
Input
Master clock generator synchronizes all
subsystems of a sequential circuit

Shift Register and Counter

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Page 1 of 25

F0064

Load Control
Input
Load control input using the clock and the
associated timing diagram

LOAD
 the control signal that will determine whether
the subsystem where the CLOCK is connected
to needs to function

Shift Register and Counter

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Page 2 of 25

F0064

Load Control
Input
Load control input using the input X1

 the figure shows how a logic 1 at the LOAD will


allow the input X1 to be processed by
subsystem A during each clock transition

Shift Register and Counter

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F0064

Register and
Shift Registers
Register
 a flip-flop structure that handles multiple bits of
data at any one time

 called a 4-bit parallel register or buffer


register
 used in most computers as high-speed
temporary data storage
Detailed implementation using flip-flops

Shift Register and Counter

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F0064

Register and
Shift Registers

schematic symbol

alternative manner of representing the


implementation


another way of drawing the register using the


same set of flip-flops but written horizontally
simplifies the correspondence between the flipflops outputs and the way the output is written
from the least significant bit (LSB) to the most
significant bit (MSB)

Shift Register and Counter

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Page 5 of 25

F0064

Register and
Shift Registers

 shows how optional inputs of flip-flops may be


used
 inputs: CLEAR and PRESET


modifies the state of the associated flip-flop


instantaneously

Shift Register and Counter

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F0064

Parallel Register
with Load Control
 the LOAD input dictates when the register may
allow data from its inputs to be transferred and
stored

Parallel/buffer register with load control input


Shift Register and Counter

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F0064

Shift Register
 capable of shifting or rotating the binary
information stored in the register
 has the capability of shifting stored bits to the
left or to the right for every clock pulse
 used in microcomputer serial communications
to transfer information

A simple shift-left and shift-right register using D


flip-flops
Shift Register and Counter

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Page 8 of 25

F0064

Shift Register
Summary of the input and output of the shift register:
Initial state

Q = 0000

1st rising edge:


2nd rising edge:

Q = 0001
Q = 0011

SERIAL IN = 1
SERIAL IN = 1

SERIAL OUT = 0
SERIAL OUT = 0

3rd rising edge:

Q = 0111

SERIAL IN = 1

SERIAL OUT = 0

4th rising edge:


Successive rising edges:

Q = 1111
Q = 1111

SERIAL IN = 1
SERIAL IN = 1

SERIAL OUT = 1
SERIAL OUT = 1

when the SERIAL IN=0, the output of the register:


Initial state
1st rising edge:

Q = 1111
Q = 1110

SERIAL IN = 0

SERIAL OUT = 1

2nd rising edge:


3rd rising edge:

Q = 1100
Q = 1000

SERIAL IN = 0
SERIAL IN = 0

SERIAL OUT = 1
SERIAL OUT = 1

4th rising edge:


Successive rising edges:

Q = 0000
Q = 0000

SERIAL IN = 0
SERIAL IN = 0

SERIAL OUT = 0
SERIAL OUT = 0

Serial Loading

 the method of storing a word of information

Shift Register and Counter

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Page 9 of 25

F0064

Shift Register
When the stored data in the register is Q=1111 and
SERIAL IN=0 at all times, the output will be:
Initial state

Q = 1111

1st rising edge:


2nd rising edge:
3rd rising edge:
4th rising edge:
Successive rising edges:

Q = 0111
Q = 0011
Q = 0001
Q = 0000
Q = 0000

Shift Register and Counter

SERIAL IN = 0
SERIAL IN = 0
SERIAL IN = 0
SERIAL IN = 0
SERIAL IN = 0

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Page 10 of 25

F0064

Shift Register
Example 1:
Get the output of the following shift register
after with the following conditions:

(a)

shift-left, Q=0000, SERIAL IN sequence is


0,0,0,1,0,1,1; after 7 cycles
(b) shift-left, Q=00001111, SERIAL IN alternating 0
and 1; after 10 cycles
Solution:
(a) initial Q = 0000
cycle 1
Q = 0000
cycle 2
Q = 0000
cycle 3
Q = 0000
cycle 4
Q = 0001
cycle 5
cycle 6
cycle 7

Shift Register and Counter

Q = 0010
Q = 0101
Q = 1011

SERIAL IN = 0
SERIAL IN = 0
SERIAL IN = 0
SERIAL IN = 1
SERIAL IN = 0
SERIAL IN = 1
SERIAL IN = 1

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Page 11 of 25

F0064

Shift Register
Solution (cont.):
(b) initial

Q = 00001111

cycle 1
cycle 2
cycle 3
cycle 4
cycle 5
cycle 6
cycle 7
cycle 8

Q = 00011110
Q = 00111101
Q = 01111010
Q = 11110101
Q = 11101010
Q = 11010101
Q = 10101010
Q = 01010101

SERIAL IN = 0
SERIAL IN = 1
SERIAL IN = 0
SERIAL IN = 1
SERIAL IN = 0
SERIAL IN = 1
SERIAL IN = 0
SERIAL IN = 1

cycle 9
cycle 10

Q = 10101010
Q = 01010101

SERIAL IN = 0
SERIAL IN = 1

Shift Register and Counter

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Page 12 of 25

F0064

Shift Register
Example 2:
Design an alternative implementation of the
shift-left register using JK flip-flops.

Solution:
The basic operation of the 4-bit shift (left)
register that is made using D flip-flops is as
follows:
1. D0 takes in new value from SERIAL IN
2. D1 takes old value of D0; D2 takes D3; etc.
JK flip-flops function table:

Shift Register and Counter

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Page 13 of 25

F0064

Shift Register
 A 4-bit shift-left register using JK flip-flops

Shift Register and Counter

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Page 14 of 25

F0064

Shift Registers
with Load Control
 gates and feedback are also used to allow for
increased control over the operation of the shift
register
Shift register with load control input

Shift Register and Counter

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Page 15 of 25

F0064

Counters
 are essentially registers that go through a
sequence of states whenever input pulses are
applied
 can be used to measure time or frequency (and
period)
 handle binary numbers and are called binary
counters
Two types of counters:
Synchronous


the flip-flops are timed using a common clock


pulse

Asynchronous


each of the outputs of the flip-flops is used to


trigger the other flip-flops

Shift Register and Counter

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Page 16 of 25

F0064

Ripple Counter
 a simple type of counter that is usually
implemented with T flip-flops or JK flip-flops
 the inputs of the CLK are derived from the
outputs of the flip-flops used

A 3-bit ripple counter using JK flip-flops


A ripple counter using JK flip-flops:
1. The CLK is triggered during high-to-low logic
transitions.

2. The flip-flop that corresponds to the LSB is the


JK flip-flop that is directly connected to the
input. Each subsequent flip-flop corresponds to
a higher bit.
3. Since the inputs J and K of all the flip-flops are
tied together, each flip-flop will merely toggle
(negate its input) when triggered.
Shift Register and Counter

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Page 17 of 25

F0064

Ripple Counter

A 3-bit ripple counter using T flip-flops

This figure shows how some authors want to


present it so that the outputs are read from the
MSB to the LSB.

Shift Register and Counter

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Page 18 of 25

F0064

Ripple Counter

Timing diagram of the ripple counter

Ripple counter counting sequence

Shift Register and Counter

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Page 19 of 25

F0064

Synchronous
Counters

Ring counter with pre-load pulse


 resembles the shift register using D flip-flops
with the difference that the output from the MSB
is fed back0 to the LSB input
Ring Counter
 the action of going back to the beginning

Shift Register and Counter

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Page 20 of 25

F0064

Synchronous
Counters

Sequence of states

Shift Register and Counter

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Page 21 of 25

F0064

Synchronous
Counters
Using the D flip-flops to get the state equation
directly from the state table, follow the steps below:
Step 1: Get the sum of minterms expression
DQ2 (Q2, Q1, Q0) = (3, 4, 5, 6)
DQ1 (Q2, Q1, Q0) = (1, 2, 5, 6)
DQ0 (Q2, Q1, Q0) = (0, 2, 4, 6)
Step 2: Simplify using K-map method

Shift Register and Counter

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F0064

Synchronous
Counters
Step 2: Simplify using K-map method (cont.)

Shift Register and Counter

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Page 23 of 25

F0064

Synchronous
Counters
The simplified equation:
DQ2 = Q2Q1Q0 + Q2Q1 + Q2Q0
DQ1 = Q1Q0 + Q1Q0

DQ0 = Q0
Step 3: Draw the logic diagram

Shift Register and Counter

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Page 24 of 25

F0064

Synchronous
Counters
Partial state table alongside excitation table

Shift Register and Counter

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Page 25 of 25