How to find T States of 8085 Microprocessor.

How To Calculate Timing States In 8085 Microprocessor

CLK:-The clock is the machine clock it goes up and low.
A15-A8 :-These are the higher order address lines store only address,Here we put the
higher order address.
AD7-AD0 :-These are the lower order address lines.This is a multi plexed Address/Data
bus.Firstly we store lower order address in this and after that we put data in it.
ALE :- It is a positive going pulse which indicates that the bits on AD7-AD0 are address
bits.This latches lower order bus and generate to seperate 8 address lines.
IO/M bar:-These are the status signals .Different signals give different results.

Opcode fetch (IO/M bar=0,S1=1,S0=1)

Memory Read (IO/M bar=0,S1=1,S0=0)
Memory Write (IO/M bar=0,S1=0,S0=1)
I/O Read (IO/M bar=1,S1=1,S0=0)
I/O Write (IO/M bar=1,S1=0,S0=1)
Interrupt Accow. (IO/M bar=1,S1=1,S0=1)
So this is the description of the timing diagram.Now we will know how to find the T
states.

So for any instruction LDA,MVI,MOV ......etc.we have to fetch the operation code,for
this the microprocessor goes to the memory location where it will find the machine code
for that opcode.From this whatever has been there on the address goes through data bus
to the instruction decoder which decodes the signal.
Lets take an example
MVI A,32H is the instruction.
So ,memory location 5000 in Hexa & machine code which is there for MVI is
00111110(assume only) ,ie 3E in Hexa.
For op code fetch the status signals are(IO/M=0,S1=1,S0=1),it places the memory
address from program counter on the address bus and increment the program counter to
5001.Thus,50 H goes to higher order bus and 00H goes to lower order bus.The Ale signal
goes high during T1 which latches
the lower order bus.At T2 the 8085 asserts RD bar signal,which enables the memory,and
the memory places the byte 3E on the data bus.Then 8085 places opcode in the
instruction register and disables RD bar signal.The fetch cycle is completed in T3
state.During T4 state 8085 decodes the opcode.
and finds out second byte to read.After the T3 state,the contents of the bus A15-A8 are
unspecified and AD7-AD0 goes high impedance.
For opcode fetch 4T states required.
After the opcode fetch 8085 goes again to the memory and places the next address 5001
on the address bus and increments the program counter.The second signal identifies as
memory read thus,the status signals are (IO/M=0,S1=1, S0=0),the same thing happen as
it has been for opcode accept the decode.So for reading 3T states are required.
AS general rule :If there is 1 byte instruction we will require minimum 4T states.
If there is 2 byte instruction we will require minimum 7T states.
If there is 3 byte instruction we will require minimum 10T states.
For opcode fetch 4T states.
read 3T state.
write 3T state.
Thus in above example which is 2 byte instruction we will require 4T states for opcode
fetch and then 3T states for reading the data.Thus total 7T states.