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Advance ‡ 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance ‡ 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance ‡ 4Gb: x4, x8, x16 DDR4 SDRAM Features

DDR4 SDRAM

MT40A1G4

MT40A512M8

MT40A256M16

Features

• V DD = V DDQ = 1.2V ±60mV

• V PP = 2.5V, –125mV/+250mV

• On-die, internal, adjustable V REFDQ generation

• 1.2V pseudo open-drain I/O

• T C of 0°C to 95°C

– 64ms, 8192-cycle refresh at 0°C to 85°C

– 32ms at 85°C to 95°C

• 16 internal banks (x4, x8): 4 groups of 4 banks each

• 8 internal banks (x16): 2 groups of 4 banks each

• 8n-bit prefetch architecture

• Programmable data strobe preambles

• Data strobe preamble training

• Command/Address latency (CAL)

• Multipurpose register READ and WRITE capability

• Write and read leveling

• Self refresh mode

• Low-power auto self refresh (LPASR)

• Temperature controlled refresh (TCR)

• Fine granularity refresh

• Self refresh abort

• Maximum power saving

• Output driver calibration

• Nominal, park, and dynamic on-die termination (ODT)

• Data bus inversion (DBI) for data bus

• Command/Address (CA) parity

Table 1: Key Timing Parameters

• Databus write cyclic redundancy check (CRC)

• Per-DRAM addressability

• Connectivity test (x16)

• Post package repair (PPR) and soft post package re- pair (sPPR) modes

• JEDEC JESD-79-4 compliant

Options 1

• Configuration

Marking

1 Gig x 4

512 Meg x 8

256 Meg x 16

• FBGA package (Pb-free)

1G4

512M8

256M16 2

– 78-ball (9mm x 11.5mm) – x4, x8

HX

– 96-ball (9mm x 14mm) – x16

HA

• Timing – cycle time

– 0.833ns @ CL = 16 (DDR4-2400)

-083E 3

– 0.833ns @ CL = 17 (DDR4-2400)

-083

– 0.937ns @ CL = 14 (DDR4-2133)

-093F 3

– 0.937ns @ CL = 15 (DDR4-2133)

-093E

– 1.071ns @ CL = 13 (DDR4-1866)

-107E

• Operating temperature

– Commercial (0° T C 95°C)

None

– Revision

:A

Notes:

1. Not all options listed can be combined to define an offered product. Use the part catalog search on http://www.micron.com for available offerings.

2. Not available on Rev. A.

3. Restricted and limited availability.

Speed Grade

Data Rate (MT/s)

Target t RCD- t RP-CL

t RCD (ns)

t RP (ns)

CL (ns)

-083E 1 , 2 , 3 , 4

2400

16-16-16

13.32

13.32

13.32

-093F 1 , 2 , 3

2133

14-14-14

13.13

13.13

13.13

-093E 1 , 2

2133

15-15-15

14.06

14.06

14.06

-107E 1

1866

13-13-13

13.92

13.92

13.92

Notes:

1. Backward compatible to 1600, CL = 11 (-125E).

2. Backward compatible to 1866, CL = 13 (-107E).

3. Backward compatible to 2133, CL = 15 (-2133).

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

1

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

‡Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change by Micron without notice. Products are only warranted by Micron to meet Micron's production data sheet specifications.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

4. Backward compatible to 2133, CL = 14 (-2133).

Table 2: Addressing

Parameter

1024 Meg x 4

512 Meg x 8

256 Meg x 16

Number of bank groups

4

4

2

Bank group address

BG[1:0]

BG[1:0]

BG0

Bank count per group

4

4

4

Bank address in bank group

BA[1:0]

BA[1:0]

BA[1:0]

Row addressing

64K (A[15:0])

32K (A[14:0])

32K (A[14:0])

Column addressing

1K (A[9:0])

1K (A[9:0])

1K (A[9:0])

Page size 1

512B / 1KB 2

1KB

2KB

Notes:

1. Page size is per bank, calculated as follows:

Page size = 2 COLBITS × ORG/8, where COLBIT = the number of column address bits and ORG = the number of DQ bits.

2. Die revision dependant.

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

2

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Contents

General Notes and Description Description General Notes Definitions of the Device-Pin Signal Level Definitions of the Bus Signal Level Ball Assignments Ball Descriptions Package Dimensions State Diagram Functional Description RESET and Initialization Procedure Power-Up and Initialization Sequence RESET Initialization with Stable Power Sequence Uncontrolled Power-Down Sequence Programming Mode Registers Mode Register 0 Burst Length, Type, and Order CAS Latency Test Mode Write Recovery(WR)/READ-to-PRECHARGE DLL RESET Mode Register 1 DLL Enable/DLL Disable Output Driver Impedance Control ODT R TT(NOM) Values Additive Latency Write Leveling Output Disable Termination Data Strobe Mode Register 2 CAS WRITE Latency Low-Power Auto Self Refresh Dynamic ODT Write Cyclic Redundancy Check Data Bus Target Row Refresh Mode Mode Register 3 Multipurpose Register WRITE Command Latency When CRC/DM is Enabled Fine Granularity Refresh Mode Temperature Sensor Status Per-DRAM Addressability Gear-Down Mode Mode Register 4 Post Package Repair Mode Soft Post Package Repair Mode WRITE Preamble READ Preamble READ Preamble Training Temperature-Controlled Refresh Command Address Latency

16

16

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17

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PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

3

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Internal V REF Monitor Maximum Power Savings Mode Mode Register 5 Data Bus Inversion Data Mask CA Parity Persistent Error Mode ODT Input Buffer for Power-Down CA Parity Error Status CRC Error Status CA Parity Latency Mode Mode Register 6

t CCD_L Programming V REFDQ Calibration Enable V REFDQ Calibration Range V REFDQ Calibration Value Truth Tables NOP Command DESELECT Command DLL-Off Mode DLL-On/Off Switching Procedures DLL Switch Sequence from DLL-On to DLL-Off DLL-Off to DLL-On Procedure Input Clock Frequency Change Write Leveling DRAM Setting for Write Leveling and DRAM TERMINATION Function in that Mode Procedure Description Write-Leveling Mode Exit Command Address Latency Low-Power Auto Self Refresh Mode Manual Self Refresh Mode Multipurpose Register MPR Reads MPR Readout Format MPR Readout Serial Format MPR Readout Parallel Format MPR Readout Staggered Format MPR READ Waveforms MPR Writes MPR WRITE Waveforms MPR REFRESH Waveforms Gear-Down Mode Maximum Power-Saving Mode Maximum Power-Saving Mode Entry Maximum Power-Saving Mode Entry in PDA CKE Transition During Maximum Power-Saving Mode Maximum Power-Saving Mode Exit Command/Address Parity Per-DRAM Addressability V REFDQ Calibration V REFDQ Range and Levels V REFDQ Step Size V REFDQ Increment and Decrement Timing

51

51

53

54

55

55

55

55

55

55

56

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57

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PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

V REFDQ Target Settings

115

Connectivity Test Mode

117

Pin Mapping

117

Minimum Terms Definition for Logic Equations

118

Logic Equations for a x4 Device, When Supported

118

Logic Equations for a x8 Device, When Supported

119

Logic Equations for a x16 Device

119

CT Input Timing Requirements

119

Post Package Repair and Soft Post Package Repair

121

Post Package Repair

121

PPR Row Repair

121

PPR Row Repair - Entry

121

PR Row Repair – WRA Initiated (REF Commands Allowed)

122

PPR Row Repair – WR Initiated (REF Commands NOT Allowed)

123

sPPR Row Repair

125

PPR/sPPR Support Identifier

126

Target Row Refresh Mode

127

ACTIVATE Command

128

PRECHARGE Command

129

REFRESH Command

129

Temperature-Controlled Refresh Mode

131

TCR Mode – Normal Temperature Range

131

TCR Mode – Extended Temperature Range

131

Fine Granularity Refresh Mode

133

Mode Register and Command Truth Table

133

t REFI and t RFC Parameters

133

Changing Refresh Rate

136

Usage with TCR Mode

136

Self Refresh Entry and Exit

136

SELF REFRESH Operation

138

Self Refresh Abort

140

Self Refresh Exit with NOP Command

141

Power-Down Mode

143

Power-Down Clarifications – Case 1

148

Power-Down Entry, Exit Timing with CAL

149

ODT Input Buffer Disable Mode for Power-Down

152

CRC Write Data Feature

154

CRC Write Data

154

WRITE CRC DATA Operation

154

DBI_n and CRC Both Enabled

155

DM_n and CRC Both Enabled

155

DM_n and DBI_n Conflict During Writes with CRC Enabled

155

CRC Simultaneous Operation Restrictions

155

CRC Polynomial

155

CRC Combinatorial Logic Equations

155

Burst Ordering for BL8

156

CRC Data Bit Mapping

157

CRC Enabled With BC4

158

CRC with BC4 Data Bit Mapping

158

CRC Equations for x8 Device in BC4 Mode with A2 = 0 and A2 = 1

161

CRC Error Handling

162

CRC Write Data Flow Diagram

164

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4gb_ddr4_dram.pdf - Rev. A 9/14 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Data Bus Inversion

165

DBI During a WRITE Operation

165

DBI During a READ Operation

166

Data Mask

167

Programmable Preamble Modes and DQS Postambles

168

WRITE Preamble Mode

168

READ Preamble Mode

171

READ Preamble Training

171

WRITE Postamble

172

READ Postamble

172

Bank Access Operation

174

READ Operation

178

Read Timing Definitions

178

Read Timing – Clock-to-Data Strobe Relationship

179

Read Timing – Data Strobe-to-Data Relationship

180

t LZ(DQS), t LZ(DQ), t HZ(DQS), and t HZ(DQ) Calculations

181

t RPRE Calculation

183

t RPST Calculation

184

READ Burst Operation

185

READ Operation Followed by Another READ Operation

187

READ Operation Followed by WRITE Operation

192

READ Operation Followed by PRECHARGE Operation

198

READ Operation with Read Data Bus Inversion (DBI)

201

READ Operation with Command/Address Parity (CA Parity)

202

READ Followed by WRITE with CRC Enabled

203

READ Operation with Command/Address Latency (CAL) Enabled

204

WRITE Operation

206

Write Timing Definitions

206

Write Timing – Clock-to-Data Strobe Relationship

207

Write Timing – Data Strobe-to-Data Relationship

209

WRITE Burst Operation

212

WRITE Operation Followed by Another WRITE Operation

214

WRITE Operation Followed by READ Operation

220

WRITE Operation Followed by PRECHARGE Operation

224

WRITE Operation with WRITE DBI Enabled

227

WRITE Operation with CA Parity Enabled

229

WRITE Operation with Write CRC Enabled

230

Write Timing Violations

235

Motivation

235

Data Setup and Hold Violations

235

Strobe-to-Strobe and Strobe-to-Clock Violations

235

ZQ CALIBRATION Commands

236

On-Die Termination

238

ODT Mode Register and ODT State Table

238

ODT Read Disable State Table

239

Synchronous ODT Mode

240

ODT Latency and Posted ODT

240

Timing Parameters

240

ODT During Reads

242

Dynamic ODT

243

Functional Description

243

Asynchronous ODT Mode

246

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4gb_ddr4_dram.pdf - Rev. A 9/14 EN

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Electrical Specifications

247

Absolute Ratings

247

DRAM Component Operating Temperature Range

247

Electrical Characteristics – AC and DC Operating Conditions

248

Supply Operating Conditions

248

Leakages

248

V REFCA Supply

249

V REFDQ Supply and Calibration Ranges

249

V REFDQ Ranges

250

Electrical Characteristics – AC and DC Single-Ended Input Measurement Levels

251

RESET_n Input Levels

251

Command/Address Input Levels

252

Data Receiver Input Requirements

254

Connectivity Test (CT) Mode Input Levels

257

Electrical Characteristics – AC and DC Differential Input Measurement Levels

261

Differential Inputs

261

Single-Ended Requirements for CK Differential Signals

262

Slew Rate Definitions for CK Differential Input Signals

263

CK Differential Input Cross Point Voltage

264

DQS Differential Input Signal Definition and Swing Requirements

265

DQS Differential Input Cross Point Voltage

267

Slew Rate Definitions for DQS Differential Input Signals

267

Electrical Characteristics – Overshoot and Undershoot Specifications

269

Address, Command, and Control Overshoot and Undershoot Specifications

269

Clock Overshoot and Undershoot Specifications

270

Data, Strobe, and Mask Overshoot and Undershoot Specifications

271

Electrical Characteristics – AC and DC Output Measurement Levels

271

Single-Ended Outputs

271

Differential Outputs

273

Reference Load for AC Timing and Output Slew Rate

274

Connectivity Test Mode Output Levels

275

Electrical Characteristics – AC and DC Output Driver Characteristics

277

Output Driver Electrical Characteristics

277

Output Driver Temperature and Voltage Sensitivity

280

Alert Driver

280

Electrical Characteristics – On-Die Termination Characteristics

281

ODT Levels and I-V Characteristics

281

ODT Temperature and Voltage Sensitivity

282

ODT Timing Definitions

283

DRAM Package Electrical Specifications

286

Thermal Characteristics

290

Current Specifications – Measurement Conditions

291

I DD , I PP , and I DDQ Measurement Conditions

291

I DD Definitions

292

Current Specifications – Patterns and Test Conditions

296

Current Test Definitions and Patterns

296

I DD Specifications

305

Current Specifications – Limits

306

Speed Bin Tables

308

Refresh Parameters By Device Density

313

Electrical Characteristics and AC Timing Parameters

314

Options Tables

325

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

7

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

List of Figures

Figure 1:

78-Ball x4, x8 Ball Assignments

18

Figure 2:

96-Ball x16 Ball Assignments

19

Figure 3:

78-Ball FBGA – x4, x8

23

Figure 4:

96-Ball FBGA – x16

24

Figure 5:

Simplified State Diagram

25

Figure 6:

RESET and Initialization Sequence at Power-On Ramping

30

Figure 7:

RESET Procedure at Power Stable Condition

31

Figure 8:

t MRD Timing

33

Figure 9:

t MOD Timing

33

Figure 10:

DLL-Off Mode Read Timing Operation

62

Figure 11:

DLL Switch Sequence from DLL-On to DLL-Off

64

Figure 12:

DLL Switch Sequence from DLL-Off to DLL-On

65

Figure 13:

Write-Leveling Concept, Example 1

67

Figure 14:

Write-Leveling Concept, Example 2

68

Figure 15:

Write-Leveling Sequence (DQS Capturing CK LOW at T1 and CK HIGH at T2)

70

Figure 16:

Write-Leveling Exit

71

Figure 17:

CAL Timing Definition

72

Figure 18:

CAL Timing Example (Consecutive CS_n = LOW)

72

Figure 19:

CAL Enable Timing – t MOD_CAL

73

Figure 20:

t MOD_CAL, MRS to Valid Command Timing with CAL Enabled

73

Figure 21:

CAL Enabling MRS to Next MRS Command, t MRD_CAL

74

Figure 22:

t MRD_CAL, Mode Register Cycle Time With CAL Enabled

74

Figure 23:

Consecutive READ BL8, CAL3, 1 t CK Preamble, Different Bank Group

75

Figure 24:

Consecutive READ BL8, CAL4, 1 t CK Preamble, Different Bank Group

75

Figure 25:

Auto Self Refresh Ranges

78

Figure 26:

MPR Block Diagram

79

Figure 27:

MPR READ Timing

85

Figure 28:

MPR Back-to-Back READ Timing

86

Figure 29:

MPR READ-to-WRITE Timing

87

Figure 30:

MPR WRITE and WRITE-to-READ Timing

88

Figure 31:

MPR Back-to-Back WRITE Timing

89

Figure 32:

REFRESH Timing

89

Figure 33:

READ-to-REFRESH Timing

90

Figure 34:

WRITE-to-REFRESH Timing

90

Figure 35:

Clock Mode Change from 1/2 Rate to 1/4 Rate (Initialization)

93

Figure 36:

Clock Mode Change After Exiting Self Refresh

93

Figure 37:

Comparison Between Gear-Down Disable and Gear-Down Enable

94

Figure 38:

Maximum Power-Saving Mode Entry

95

Figure 39:

Maximum Power-Saving Mode Entry with PDA

96

Figure 40:

Maintaining Maximum Power-Saving Mode with CKE Transition

96

Figure 41:

Maximum Power-Saving Mode Exit

97

Figure 42:

Command/Address Parity Operation

98

Figure 43:

Command/Address Parity During Normal Operation

100

Figure 44:

Persistent CA Parity Error Checking Operation

101

Figure 45:

CA Parity Error Checking – SRE Attempt

101

Figure 46:

CA Parity Error Checking – SRX Attempt

102

Figure 47:

CA Parity Error Checking – PDE/PDX

102

Figure 48:

Parity Entry Timing Example – t MRD_PAR

103

Figure 49:

Parity Entry Timing Example – t MOD_PAR

103

Figure 50:

Parity Exit Timing Example – t MRD_PAR

103

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Figure 51:

Parity Exit Timing Example – t MOD_PAR CA Parity Flow Diagram PDA Operation Enabled, BL8 PDA Operation Enabled, BC4 MRS PDA Exit V REFDQ Voltage Range Example of V REF Set Tolerance and Step Size V REFDQ Timing Diagram for V REF,time Parameter V REFDQ Training Mode Entry and Exit Timing Diagram V REF Step: Single Step Size Increment Case V REF Step: Single Step Size Decrement Case V REF Full Step: From V REF,min to V REF,max Case V REF Full Step: From V REF,max to V REF,min Case V REFDQ Equivalent Circuit Connectivity Test Mode Entry PPR WRA – Entry PPR WRA – Repair and Exit PPR WR – Entry PPR WR – Repair and Exit sPPR – Entry, Repair, and Exit t RRD Timing t FAW Timing REFRESH Command Timing Postponing REFRESH Commands (Example) Pulling In REFRESH Commands (Example) TCR Mode Example 1 4Gb with Fine Granularity Refresh Mode Example OTF REFRESH Command Timing Self Refresh Entry/Exit Timing Self Refresh Entry/Exit Timing with CAL Mode Self Refresh Abort Self Refresh Exit with NOP Command Active Power-Down Entry and Exit Power-Down Entry After Read and Read with Auto Precharge Power-Down Entry After Write and Write with Auto Precharge Power-Down Entry After Write Precharge Power-Down Entry and Exit REFRESH Command to Power-Down Entry Active Command to Power-Down Entry PRECHARGE/PRECHARGE ALL Command to Power-Down Entry MRS Command to Power-Down Entry Power-Down Entry/Exit Clarifications – Case 1 Active Power-Down Entry and Exit Timing with CAL REFRESH Command to Power-Down Entry with CAL ODT Power-Down Entry with ODT Buffer Disable Mode ODT Power-Down Exit with ODT Buffer Disable Mode CRC Write Data Operation CRC Error Reporting CA Parity Flow Diagram 1 t CK vs. 2 t CK WRITE Preamble Mode 1 t CK vs. 2 t CK WRITE Preamble Mode, t CCD = 4 1 t CK vs. 2 t CK WRITE Preamble Mode, t CCD = 5

104

Figure 52:

105

Figure 53:

107

Figure 54:

107

Figure 55:

108

Figure 56:

109

Figure 57:

111

Figure 58:

112

Figure 59:

113

Figure 60:

114

Figure 61:

114

Figure 62:

115

Figure 63:

115

Figure 64:

116

Figure 65:

120

Figure 66:

123

Figure 67:

123

Figure 68:

124

Figure 69:

124

Figure 70:

126

Figure 71:

128

Figure 72:

128

Figure 73:

130

Figure 74:

130

Figure 75:

130

Figure 76:

132

Figure 77:

135

Figure 78:

136

Figure 79:

139

Figure 80:

140

Figure 81:

141

Figure 82:

142

Figure 83:

144

Figure 84:

145

Figure 85:

145

Figure 86:

146

Figure 87:

146

Figure 88:

147

Figure 89:

147

Figure 90:

148

Figure 91:

148

Figure 92:

149

Figure 93:

150

Figure 94:

151

Figure 95:

152

Figure 96:

153

Figure 97:

154

Figure 98:

163

Figure 99:

164

Figure 100:

168

Figure 101:

169

Figure 102:

170

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4gb_ddr4_dram.pdf -

Rev. A 9/14 EN

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Figure 103:

1 t CK vs. 2 t CK WRITE Preamble Mode, t CCD = 6

170

Figure 104:

1 t CK vs. 2 t CK READ Preamble Mode

171

Figure 105:

READ Preamble Training

172

Figure 106:

WRITE Postamble

172

Figure 107:

READ Postamble

173

Figure 108:

Bank Group x4/x8 Block Diagram

174

Figure 109:

READ Burst t CCD_S and t CCD_L Examples

175

Figure 110:

Write Burst t CCD_S and t CCD_L Examples

175

Figure 111:

t RRD Timing

176

Figure 112:

t WTR_S Timing (WRITE-to-READ, Different Bank Group, CRC and DM Disabled)

176

Figure 113:

t WTR_L Timing (WRITE-to-READ, Same Bank Group, CRC and DM Disabled)

177

Figure 114:

Read Timing Definition

179

Figure 115:

Clock-to-Data Strobe Relationship

180

Figure 116:

Data Strobe-to-Data Relationship

181

Figure 117:

t LZ and t HZ Method for Calculating Transitions and Endpoints

182

Figure 118:

t RPRE Method for Calculating Transitions and Endpoints

183

Figure 119:

t RPST Method for Calculating Transitions and Endpoints

184

Figure 120:

READ Burst Operation, RL = 11 (AL = 0, CL = 11, BL8)

185

Figure 121:

READ Burst Operation, RL = 21 (AL = 10, CL = 11, BL8)

186

Figure 122:

Consecutive READ (BL8) with 1 t CK Preamble in Different Bank Group

187

Figure 123:

Consecutive READ (BL8) with 2 t CK Preamble in Different Bank Group

187

Figure 124:

Nonconsecutive READ (BL8) with 1 t CK Preamble in Same or Different Bank Group

188

Figure 125:

Nonconsecutive READ (BL8) with 2 t CK Preamble in Same or Different Bank Group

188

Figure 126:

READ (BC4) to READ (BC4) with 1 t CK Preamble in Different Bank Group

189

Figure 127:

READ (BC4) to READ (BC4) with 2 t CK Preamble in Different Bank Group

189

Figure 128:

READ (BL8) to READ (BC4) OTF with 1 t CK Preamble in Different Bank Group

190

Figure 129:

READ (BL8) to READ (BC4) OTF with 2 t CK Preamble in Different Bank Group

190

Figure 130:

READ (BC4) to READ (BL8) OTF with 1 t CK Preamble in Different Bank Group

191

Figure 131:

READ (BC4) to READ (BL8) OTF with 2 t CK Preamble in Different Bank Group

191

Figure 132:

READ (BL8) to WRITE (BL8) with 1 t CK Preamble in Same or Different Bank Group

192

Figure 133:

READ (BL8) to WRITE (BL8) with 2 t CK Preamble in Same or Different Bank Group

192

Figure 134:

READ (BC4) OTF to WRITE (BC4) OTF with 1 t CK Preamble in Same or Different Bank Group

193

Figure 135:

READ (BC4) OTF to WRITE (BC4) OTF with 2 t CK Preamble in Same or Different Bank Group

194

Figure 136:

READ (BC4) Fixed to WRITE (BC4) Fixed with 1 t CK Preamble in Same or Different Bank Group

194

Figure 137:

READ (BC4) Fixed to WRITE (BC4) Fixed with 2 t CK Preamble in Same or Different Bank Group

195

Figure 138:

READ (BC4) to WRITE (BL8) OTF with 1 t CK Preamble in Same or Different Bank Group

196

Figure 139:

READ (BC4) to WRITE (BL8) OTF with 2 t CK Preamble in Same or Different Bank Group

196

Figure 140:

READ (BL8) to WRITE (BC4) OTF with 1 t CK Preamble in Same or Different Bank Group

197

Figure 141:

READ (BL8) to WRITE (BC4) OTF with 2 t CK Preamble in Same or Different Bank Group

197

Figure 142:

READ to PRECHARGE with 1 t CK Preamble

198

Figure 143:

READ to PRECHARGE with 2 t CK Preamble

199

Figure 144:

READ to PRECHARGE with Additive Latency and 1 t CK Preamble

199

Figure 145:

READ with Auto Precharge and 1 t CK Preamble

200

Figure 146:

READ with Auto Precharge, Additive Latency, and 1 t CK Preamble

200

Figure 147:

Consecutive READ (BL8) with 1 t CK Preamble and DBI in Different Bank Group

201

Figure 148:

Consecutive READ (BL8) with 1 t CK Preamble and CA Parity in Different Bank Group

202

Figure 149:

READ (BL8) to WRITE (BL8) with 1 t CK Preamble and CA Parity in Same or Different Bank Group

202

Figure 150:

READ (BL8) to WRITE (BL8 or BC4: OTF) with 1 t CK Preamble and Write CRC in Same or Different

Bank Group

203

Figure 151:

READ (BC4: Fixed) to WRITE (BC4: Fixed) with 1 t CK Preamble and Write CRC in Same or Different

Bank Group

204

Figure 152:

Consecutive READ (BL8) with CAL (3 t CK) and 1 t CK Preamble in Different Bank Group

204

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Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

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Figure 153:

Consecutive READ (BL8) with CAL (4 t CK) and 1 t CK Preamble in Different Bank Group

205

Figure 154:

Write Timing Definition

206

Figure 155:

Clock-to-Data Strobe Relationship

208

Figure 156:

Rx Compliance Mask

209

Figure 157:

V CENT_DQ V REFDQ Voltage Variation

209

Figure 158:

Rx Mask DQ-to-DQS Timings

210

Figure 159:

Rx Mask DQ-to-DQS DRAM-Based Timings

211

Figure 160:

Example of Data Input Requirements Without Training

212

Figure 161:

WRITE Burst Operation, WL = 9 (AL = 0, CWL = 9, BL8)

213

Figure 162:

WRITE Burst Operation, WL = 19 (AL = 10, CWL = 9, BL8)

214

Figure 163:

Consecutive WRITE (BL8) with 1 t CK Preamble in Different Bank Group

214

Figure 164:

Consecutive WRITE (BL8) with 2 t CK Preamble in Different Bank Group

215

Figure 165:

Nonconsecutive WRITE (BL8) with 1 t CK Preamble in Same or Different Bank Group

216

Figure 166:

Nonconsecutive WRITE (BL8) with 2 t CK Preamble in Same or Different Bank Group

216

Figure 167:

WRITE (BC4) OTF to WRITE (BC4) OTF with 1 t CK Preamble in Different Bank Group

217

Figure 168:

WRITE (BC4) OTF to WRITE (BC4) OTF with 2 t CK Preamble in Different Bank Group

218

Figure 169:

WRITE (BC4) Fixed to WRITE (BC4) Fixed with 1 t CK Preamble in Different Bank Group

218

Figure 170:

WRITE (BL8) to WRITE (BC4) OTF with 1 t CK Preamble in Different Bank Group

219

Figure 171:

WRITE (BC4) OTF to WRITE (BL8) with 1 t CK Preamble in Different Bank Group

220

Figure 172:

WRITE (BL8) to READ (BL8) with 1 t CK Preamble in Different Bank Group

220

Figure 173:

WRITE (BL8) to READ (BL8) with 1 t CK Preamble in Same Bank Group

221

Figure 174:

WRITE (BC4) OTF to READ (BC4) OTF with 1 t CK Preamble in Different Bank Group

222

Figure 175:

WRITE (BC4) OTF to READ (BC4) OTF with 1 t CK Preamble in Same Bank Group

222

Figure 176:

WRITE (BC4) Fixed to READ (BC4) Fixed with 1 t CK Preamble in Different Bank Group

223

Figure 177:

WRITE (BC4) Fixed to READ (BC4) Fixed with 1 t CK Preamble in Same Bank Group

223

Figure 178:

WRITE (BL8/BC4-OTF) to PRECHARGE with 1 t CK Preamble

224

Figure 179:

WRITE (BC4-Fixed) to PRECHARGE with 1 t CK Preamble

225

Figure 180:

WRITE (BL8/BC4-OTF) to Auto PRECHARGE with 1 t CK Preamble

225

Figure 181:

WRITE (BC4-Fixed) to Auto PRECHARGE with 1 t CK Preamble

226

Figure 182:

WRITE (BL8/BC4-OTF) with 1 t CK Preamble and DBI

227

Figure 183:

WRITE (BC4-Fixed) with 1 t CK Preamble and DBI

228

Figure 184:

Consecutive Write (BL8) with 1 t CK Preamble and CA Parity in Different Bank Group

229

Figure 185:

Consecutive WRITE (BL8/BC4-OTF) with 1 t CK Preamble and Write CRC in Same or Different Bank

Group

230

Figure 186:

Consecutive WRITE (BC4-Fixed) with 1 t CK Preamble and Write CRC in Same or Different Bank

Group

231

Figure 187:

Nonconsecutive WRITE (BL8/BC4-OTF) with 1 t CK Preamble and Write CRC in Same or Different

Bank Group

232

Figure 188:

Nonconsecutive WRITE (BL8/BC4-OTF) with 2 t CK Preamble and Write CRC in Same or Different

Bank Group

233

Figure 189:

WRITE (BL8/BC4-OTF/Fixed) with 1 t CK Preamble and Write CRC in Same or Different Bank Group

234

Figure 190:

ZQ Calibration Timing

237

Figure 191:

Functional Representation of ODT

238

Figure 192:

Synchronous ODT Timing with BL8

241

Figure 193:

Synchronous ODT with BC4

241

Figure 194:

ODT During Reads

242

Figure 195:

Dynamic ODT (1 t CK Preamble; CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

244

Figure 196:

Dynamic ODT Overlapped with R TT(NOM) (CL = 14, CWL = 11, BL = 8, AL = 0, CRC Disabled)

245

Figure 197:

Asynchronous ODT Timings with DLL Off

246

Figure 198:

V REFDQ Voltage Range

249

Figure 199:

RESET_n Input Slew Rate Definition

252

Figure 200:

Single-Ended Input Slew Rate Definition

253

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

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Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Figure 201:

DQ Slew Rate Definitions

254

Figure 202:

Rx Mask Relative to t DS/ t DH

256

Figure 203:

Rx Mask Without Write Training

257

Figure 204:

TEN Input Slew Rate Definition

258

Figure 205:

CT Type-A Input Slew Rate Definition

258

Figure 206:

CT Type-B Input Slew Rate Definition

259

Figure 207:

CT Type-C Input Slew Rate Definition

260

Figure 208:

CT Type-D Input Slew Rate Definition

260

Figure 209:

Differential AC Swing and “Time Exceeding AC-Level” t DVAC

261

Figure 210:

Single-Ended Requirements for CK

263

Figure 211:

Differential Input Slew Rate Definition for CK_t, CK_c

264

Figure 212:

V IX(CK) Definition

264

Figure 213:

Differential Input Signal Definition for DQS_t, DQS_c

265

Figure 214:

DQS_t, DQS_c Input Peak Voltage Calculation

266

Figure 215:

V IXDQS Definition

267

Figure 216:

Differential Input Slew Rate and Input Level Definition for DQS_t, DQS_c

268

Figure 217:

ADDR, CMD, CNTL Overshoot and Undershoot Definition

269

Figure 218:

CK Overshoot and Undershoot Definition

270

Figure 219:

Data, Strobe, and Mask Overshoot and Undershoot Definition

271

Figure 220:

Single-ended Output Slew Rate Definition

272

Figure 221:

Differential Output Slew Rate Definition

274

Figure 222:

Reference Load For AC Timing and Output Slew Rate

275

Figure 223:

Connectivity Test Mode Reference Test Load

275

Figure 224:

Connectivity Test Mode Output Slew Rate Definition

276

Figure 225:

Output Driver: Definition of Voltages and Currents

277

Figure 226:

Alert Driver

280

Figure 227:

ODT Definition of Voltages and Currents

281

Figure 228:

ODT Timing Reference Load

283

Figure 229:

t ADC Definition with Direct ODT Control

284

Figure 230:

t ADC Definition with Dynamic ODT Control

285

Figure 231:

t AOFAS and t AONAS Definitions

285

Figure 232:

Thermal Measurement Point

290

Figure 233:

Measurement Setup and Test Load for I DDx , I DDPx , and I DDQx

292

Figure 234:

Correlation: Simulated Channel I/O Power to Actual Channel I/O Power

292

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Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

List of Tables

Table 1:

Key Timing Parameters

1

Table 2:

Addressing

2

Table 3:

Ball Descriptions

20

Table 4:

State Diagram Command Definitions

26

Table 5:

Address Pin Mapping

35

Table 6:

MR0 Register Definition

35

Table 7:

Burst Type and Burst Order

37

Table 8:

Address Pin Mapping

39

Table 9:

MR1 Register Definition

39

Table 10:

Additive Latency (AL) Settings

41

Table 11:

TDQS Function Matrix

42

Table 12:

Address Pin Mapping

43

Table 13:

MR2 Register Definition

43

Table 14:

Address Pin Mapping

46

Table 15:

MR3 Register Definition

46

Table 16:

Address Pin Mapping

49

Table 17:

MR4 Register Definition

49

Table 18:

Address Pin Mapping

53

Table 19:

MR5 Register Definition

53

Table 20:

Address Pin Mapping

56

Table 21:

MR6 Register Definition

56

Table 22:

Truth Table – Command

58

Table 23:

Truth Table – CKE

60

Table 24:

MR Settings for Leveling Procedures

68

Table 25:

DRAM TERMINATION Function in Leveling Mode

68

Table 26:

Auto Self Refresh Mode

77

Table 27:

MR3 Setting for the MPR Access Mode

79

Table 28:

DRAM Address to MPR UI Translation

79

Table 29:

MPR Page and MPRx Definitions

80

Table 30:

MPR Readout Serial Format

82

Table 31:

MPR Readout – Parallel Format

83

Table 32:

MPR Readout Staggered Format, x4

84

Table 33:

MPR Readout Staggered Format, x4 – Consecutive READs

84

Table 34:

MPR Readout Staggered Format, x8 and x16

85

Table 35:

Mode Register Setting for CA Parity

100

Table 36:

V REFDQ Range and Levels

110

Table 37:

V REFDQ Settings (V DDQ = 1.2V)

116

Table 38:

Connectivity Mode Pin Description and Switching Levels

118

Table 39:

PPR MR0 Guard Key Settings

122

Table 40:

DDR4 PPR Timing Parameters

125

Table 41:

DDR4 sPPR Timing Parameters

126

Table 42:

DDR4 Repair Mode Support Identifier

126

Table 43:

MAC Encoding of MPR Page 3 MPR3

127

Table 44:

Normal t REFI Refresh (TCR Disabled)

131

Table 45:

Normal t REFI Refresh (TCR Enabled)

132

Table 46:

MRS Definition

133

Table 47:

REFRESH Command Truth Table

133

Table 48: t REFI and t RFC Parameters

134

Table 49:

Power-Down Entry Definitions

143

Table 50:

CRC Error Detection Coverage

155

PDF: 09005aef84af6dd0

4gb_ddr4_dram.pdf - Rev. A 9/14 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2014 Micron Technology, Inc. All rights reserved.

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features
Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance

4Gb: x4, x8, x16 DDR4 SDRAM Features

Advance 4Gb: x4, x8, x16 DDR4 SDRAM Features

Table 51:

Table 52:

Table 53:

Table 54:

Table 55:

Table 56:

Table 57:

Table 58:

Table 59:

Table 60:

Table 61:

Table 62:

Table 63:

Table 64:

Table 65:

Table 66:

Table 67:

Table 68:

Table 69:

Table 70:

Table 71:

Table 72:

Table 73:

Table 74:

Table 75:

Table 76:

Table 77:

Table 78:

Table 79:

Table 80:

Table 81:

Table 82:

Table 83:

Table 84:

Table 85:

Table 86:

Table 87:

Table 88:

Table 89:

Table 90:

Table 91:

Table 92:

Table 93:

Table 94:

Table 95:

Table 96:

Table 97:

Table 98:

Table 99:

Table 100:

Table 101:

Table 102:

CRC Data Mapping for x4 Devices, BL8 CRC Data Mapping for x8 Devices, BL8 CRC Data Mapping for x16 Devices, BL8 CRC Data Mapping for x4 Devices, BC4 CRC Data Mapping for x8 Devices, BC4 CRC Data Mapping for x16 Devices, BC4 DBI vs. DM vs. TDQS Function Matrix DBI Write, DQ Frame Format (x8) DBI Write, DQ Frame Format (x16) DBI Read, DQ Frame Format (x8) DBI Read, DQ Frame Format (x16) DM vs. TDQS vs. DBI Function Matrix Data Mask, DQ Frame Format (x8) Data Mask, DQ Frame Format (x16) CWL Selection DDR4 Bank Group Timings Termination State Table Read Termination Disable Window ODT Latency at DDR4-1600/-1866/-2133/-2400/-2666/-3200

Dynamic ODT Latencies and Timing (1 t CK Preamble Mode and CRC Disabled) Dynamic ODT Latencies and Timing with Preamble Mode and CRC Mode Matrix Absolute Maximum Ratings Temperature Range Recommended Supply Operating Conditions V DD Slew Rate Leakages

V REFDQ Specification

V REFDQ Range and Levels RESET_n Input Levels (CMOS) Command and Address Input Levels: DDR4-1600 Through DDR4-2400 Single-Ended Input Slew Rates DQ Input Receiver Specifications Rx Mask and t DS/ t DH Without Write Training TEN Input Levels (CMOS) CT Type-A Input Levels CT Type-B Input Levels CT Type-C Input Levels (CMOS) CT Type-D Input Levels Differential Input Swing Requirements for CK_t, CK_c Minimum Time AC Time t DVAC for CK Single-Ended Requirements for CK CK Differential Input Slew Rate Definition Cross Point Voltage For CK Differential Input Signals at DDR4-1600 through DDR4-2400 Cross Point Voltage For CK Differential Input Signals at DDR4-2666 through DDR4-3200 Differential Input Swing Requirements for DQS_t, DQS_c Cross Point Voltage For Differential Input Signals DQS DQS Differential Input Slew Rate Definition Differential Input Slew Rate and Input Levels for DQS_t, DQS_c ADDR, CMD, CNTL Overshoot and Undershoot/Specifications CK Overshoot and Undershoot/ Specifications Data, Strobe, and Mask Overshoot and Undershoot/ Specifications Single-Ended Output Levels

157

157

158

158

159

160

165

165

165

166

166

167

167

167

169

174

239

239

240

243

244

247

247

248

248

248

250

251

251

252

253

255