IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO.

2, FEBRUARY 2008

497

16 PLL Transmitter With a Loop-Bandwidth

Calibration System

Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, and
Satoshi Tanaka, Member, IEEE

16

AbstractWe developed a
PLL transmitter with a linear
charge pump and a new loop-bandwidth calibration system that
can calibrate loop bandwidth accurately in a very short time.
The calibration system uses a double integration technique that
integrates the transient signal at the voltage-controlled oscillator
output during the response to a step wave input to the divider.
In our
PLL transmitter for GSM phones, the calibration
system keeps the loop bandwidth within 2% and the calibration
time is about 25 s. To improve the GSM spectrum, we developed
a charge pump that reduces a spike noise and the asymmetry
of the charge and discharge characteristics. The phase error of
PLL transmitter with the charge pump
modulation in the
and calibration system was kept within 2 degrees rms, and after
calibration the 400-kHz offset noise level of the spectrum mask
was 64 dBc.

16

16

Index Terms
width.

16 PLL, fractional-

PLL, GSM, loop band-

I. INTRODUCTION

OW NOISE and low power consumption are the most

important features of radio frequency integrated circuits
(RF-ICs) used in mobile phones. Offset PLL transmitters have
been widely used in GSM phones because of their low noise
PLL transmitters have been studied
performance, and
because they can provide the same noise performance while
PLL transmitters, however, are
using less power [1], [2].
sensitive to variation of loop bandwidth or loop gain. When the
loop bandwidth is smaller than designed, the phase error of the
modulation is degraded because less of the spectrum can be
used for the signal. When the loop bandwidth is greater than the
designed bandwidth, on the other hand, the noise performance
(e.g., the 400-kHz and the 20-MHz offset noise performance)
is degraded because the phase noise and the quantization noise
PLL
increase. Loop-bandwidth calibration methods for
transmitters have therefore been studied extensively [4][10].
Loop bandwidth varies because of variations in process, temperature, voltage, and carrier frequency. The frequency of the
voltage-controlled oscillator (VCO) in a GSM phone needs to
be changed for frequency hopping. Since the sensitivity of a
VCO depends on the control voltage, it is generally different
at different frequencies. Because the loop bandwidth thus
Manuscript received March 12, 2007; revised September 20, 2007.
Y. Akamine, M. Kawabe, K. Hori, T. Okazaki, and S. Tanaka are with Hitachi,
Ltd., Kokubunji, Tokyo 185-8601, Japan (e-mail: yukinori.akamine.uy@
hitachi.com).
M. Kasahara is with the Renesas Technology Corp., Kokubunji, Tokyo 1858601 Japan.
Digital Object Identifier 10.1109/JSSC.2007.914325

Fig. 1.

16 PLL transmitter.

varies in every transmission burst, we have developed a

PLL transmitter that has an improved charge-pump circuit and
can correct the loop bandwidth in the short time before every
transmission burst.
This paper is organized as follows. Section II introduces
PLL transmitters, Section III describes our loop-bandwidth calibration system and its operation sequence, and Section IV describes our new charge-pump circuit that eliminates the dead
zone for small phase differences and ensures that the charge and
discharge currents are symmetrical. Section V presents the results we obtained when evaluating a prototype of our new
PLL transmitter, and Section VI concludes the paper with a brief
summary.
II.

PLL TRANSMITTERS

The
PLL transmitter (Fig. 1) has been studied extensively
because of its low noise performance and low power requirements. Binary digital data from baseband LSIs is lead to the
Gaussian filter that generates the frequency signal for GMSK
modulator, which
modulation. That signal is input to the
generates the value of the divide ratio of a fractional- PLL.
Then the VCO of the fractional- PLL generates the GMSKmodulated signal when the divide ratio is changed by the
modulator.
PLL transmitter requires only one VCO, its
Because the
current consumption is low and its chip size is small. Its loop
bandwidth, however, must be about 100 kHz because the phase
noise level of the PLL is almost impossible to achieve at less
than the GSM standard 400-kHz offset noise level. The
PLL transmitter is also sensitive to the variation of loop bandwidthwhich changes with voltage, process, temperature, and
frequency hoppingbecause the loop bandwidth is smaller than
the modulation signal bandwidth. We therefore developed a new
loop-bandwidth calibration method.

0018-9200/$25.00 2008 IEEE

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008

Fig. 3. Third order loop filter.

Fig. 2. Simulated phase error.

III. LOOP-BANDWIDTH CALIBRATION SYSTEM

A. Impact of Loop Gain Error on

PLL Transmitters

Fig. 2 shows the simulated result of the phase error of the

modulation signal at GSM standard [3] when the loop gain of
the
PLL error is at the designed value. The horizontal axis
in Fig. 2 is the loop gain error at the designed value, and the
vertical axis is the rms phase error of the modulated signal. The
phase error specified in the GSM standard [3] is less than 5 degrees rms. The simulated phase error shown in Fig. 2, however,
moduincludes only the effects of the phase noise of the
lator and loop gain error but should include the effects of other
factors such as jitter and thermal noise. To compensate for these
effects, the specified phase error should be less than one degree
rms. Therefore, the loop gain error should be less than 5% for
our specifications. Because the loop gain error due to process
variation is generally more than 5%, a loop-bandwidth calibration system is necessary.

Fig. 4. Impact of

N , Kv, Icp and Ct variation.

B. Factors Causing Loop Gain Variation

The loop gain

of a PLL can be expressed as follows:

(1)

is the transfer function of the loop filter,

is the
where
is the charge-pump current, and
is the
divide ratio,
VCO sensitivity. When the third-order lag-lead filter shown in
Fig. 3 is used, the transfer function of the loop filter can be expressed as shown in (2) at the bottom of the page,where
,
, and
. The frequency characteristics of
are shown in Fig. 4. The point
-versus-frequency curve crosses the axis
at which the
is well known as the unity-gain frequency and in general PLL
design is the same as the loop bandwidth. The variation factors
are ,
,
, and the resistance and capacitance
in
(Fig. 5). Since
in
, ,
,
values determining

Fig. 5. Variation factors on

16 PLL transmitter.

and
always appear together as a product independent of the
, and
frequency, we can minimize the variation due to , ,
by changing only one of these factors. The variation in ,
,
, and
makes the curve in Fig. 4 shift in the vertical
direction.
In our calibration system, we can reduce the variation of loop
. In general, the integrated resisgain by optimizing only
tances and capacitances have almost the same variation ratio.
That is, the variation of resistance and capacitance shifts the

(2)

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PLL TRANSMITTER WITH A LOOP-BANDWIDTH CALIBRATION SYSTEM

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D. Relation Between Loop Gain and Accumulation Result

When we use the third-order lag-lead filter, the closed-loop
of a PLL can be expressed as shown in
transfer function
,
(3) at the bottom of the page, where
, and
. When we consider the
impulse or step response of a PLL, the effects of the third-order
and fourth-order terms in the denominator of (3) are so small
that they can be ignored. We then get the following equation:
Fig. 6. Step response wave form of closed PLL.

poles and zeros of

and shifts the curve in Fig. 4 in the
can
horizontal direction. Our calibration system optimizing
-versus-frequency curve only vertically, but this
shift the
is sufficient for calibrating the loop bandwidth.
(4)
C. Step Response of a PLL
The proposed loop-bandwidth calibration system uses the
step response of a closed PLL. The response of the VCO when
the step wave is input to the divider in the PLL is shown in
Fig. 6. The step response of the VCO is fast and some ringing
occurs when the gain of the PLL is high, but the step response is
slow when the gain of the PLL is low. The proposed calibration
system uses those characteristics. The conceptual sequence is
as follows.
In the lock state of PLL, the frequency of the VCO is integrated over time. After the lock state, a step input for calibration is applied and the frequency of the VCO is integrated over
time. The difference between these integrations during the lock
state and step-input state is shown in Fig. 6 as a shaded area.
The shaded area has a difference between high loop gain and
low loop gain. The integration period should be enough long to
yield a large difference between the low and high loop gains.
The integrated values under the lock and step-input states are
then integrated once more over time. This is a double integration
over time. Finally our calibration system calculates the double
integration difference between the lock and step-input states.
The double integration yields a difference between the high and
low loop gains that is larger than that yielded by the first integration, so we can determine the loop gain more accurately by
using the double-integration technique. Another advantage of
double integration is that the calculated double integration results have a linear relationship to 1/(loop gain) that makes the
logic of detecting the loop gain easier.

where

,
, and
. When we consider the impulse
response, we should use the Laplace transform. By Laplace
transformation of (4), we get the impulse response of (4) as the
following equation:

(5)

To calculate a step response we can use the convolution

between the impulse response and the step. We get the following equation as the convolution between (5) and the
, the divider should be
step. To step the VCO output by
. So a
step is used in (6) shown at the
stepped by
,
bottom of the next page, where
,
, and step
. Now, we can get the (6) as the
frequency step at the VCO output, when the step for calibration is the input from the divider. In the proposed calibration

(3)

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Fig. 7. New loop bandwidth calibration system for

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008

16 PLL transmitter.

system, double integration is used at the VCO output. The

double integration of (6) can be expressed as follows:
Fig. 8. Transient signal at each part.

(7)
where
,
, and
.
and can be calculated from the condition in the integration and
. If the duration
double integration which should be zero at
of the step input for calibration is long enough, the period of
double integration in (7) can be approximated as from zero to
infinity. We then get the following equation:

where
(8)
In this equation we can see that the double integration of the step
.
response is proportional to
E. New Loop-Bandwidth Calibration System
Our loop-bandwidth calibration system for
shown in Fig. 7.

PLLs is

PLL transmitter for calibraThe additional blocks of the

tion are the register for the step wave, the 16-bit ECL counter at
the VCO output, the 24-bit accumulator, and the control logic
for the charge-pump current. These can be implemented as
simple digital circuits. The sequence of the calibration system
is as follows.
PLL should be in the lock state. Then the
First, the
16-bit ECL counter at the VCO output counts up the values
of VCO frequency integrated over time. These counted values
are sampled by the crystal clock at 26 MHz and then the
sampled values are integrated by the 24-bit accumulator. These
integrated values at the accumulator are the values of VCO
frequency double-integrated over time. The double-integrated
values are memorized at the resistor as ACC1 (Fig. 8).
Second, the step wave stored in the register is applied to the
modulator in the lock state of the
PLL. Then, in the
same sequence as in the lock state, the counter and the accumulator integrate the VCO output signal. The double-integrated
value in the step-wave-input state should be stored in the resistor
as ACC2 (Fig. 8).
Finally, the control logic for the charge-pump current calculates the difference between the double-integrations of the lock
and step-input states (ACC2 ACC1), which depends on the
loop gain of the PLL. As described in the Section III-D, the relation between ACC2 ACC1 and 1/loop gaini.e., the reciprocal of (1)is almost linear, so the control logic for the chargepump current can be implemented by fairly simple circuits.

(6)

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Fig. 9. Synchronization of the calibration system.

Fig. 8 shows the waveforms at each part of the calibration

process. The waveform of Fig. 8(a) is a step signal that is fed
modulator. The waveform shown in Fig. 8(b) indiinto the
cates the VCO-output frequency under the step response. The
waveforms under the step response differ between high and low
loop gain. When the loop gain is high, the step response is fast.
Regarding the step, we should take care of the following two
things.
1) The transient response of step happens in a short time, such
as a few microseconds.
2) The input step should be small to keep the lock and remove
variation in locking voltage.
the impact of the
The waveform shown in Fig. 8(c) indicates the counter-output
value. The counted value is the result of integrating the VCO
frequency over time. If we use the counted value for a calibration, there is a problem in the accuracy to detect the difference
between low and high loop gain. For example, the step transient
is supposed as 10 s and the 1-MHz step is supposed to input in
902 MHz at VCO-output. When the counter operates under the
902 MHz and 903 MHz at VCO-output for 10 s, the counted
values are 9020 and 9030 respectively. Then, we can notice that
the difference between high and low loop gain in step must be
).
less than only 10 (
To improve the accuracy with which the difference between
low and high loop gains is determined, an accumulator is added
at the counter output. The waveform shown in Fig. 8(d) is the
result of the double-integration of the VCO output frequency
over time.
In the case of double integration, the accumulator can detect
the transient of the counted value more accurately. As described,
the difference of the counted values, which means the integrated
result, is less than only 10. However, the double integration can
have about 10 chances to detect the timing at when the difference of counted values between low and high loop gain happens during the count of around 9000. That is, the accumulator
output signal can indicate the difference between low and high
loop gains more accurately.
F. Synchronization of Calibration System
Synchronization is necessary if our calibration system is to
determine the loop gain accurately because the system is sensitive to the phase of VCO at the start of the calibration. It is therefore necessary to synchronize the reference signal to sample the

counted value, the VCO output signal, and the reset signal as
shown in Fig. 9.
IV. CHARGE-PUMP CIRCUIT
When a PLL uses an integer divider, the phase detector
and the charge pump operate under conditions in which in
the locking state there is a small phase difference between
the divider output and the reference signal. The nonlinearity
of a charge pump far from a small phase difference has no
sensitivity because it operates only under a small phase error.
The nonlinearity around a small phase differencei.e., the
dead zone of the phase detector and charge pump is well
known and causes spurious noise. But because this spurious
noise can be decreased using a loop filter, nonlinearity of the
phase detector or charge pump is basically not an issue with an
integer PLL.
PLL or fractional PLL, however, the
When we use a
phase of the divider output alternatively repeats a little faster and
slower than the phase of the reference signal in the lock state.
Then nonlinearity of the charge pump around a small phase
difference not only generates spurious noise but also causes
PLL
phase noise degradation. Phase noise degradation in a
degrades the modulation spectrum, so the phase detector and
PLL must have quite linear characterischarge pump for a
tics around a small phase difference.
Fig. 10 shows the dead zone and asymmetry between the
charge and discharge currents in a charge pump. These phenomena degrade the modulation spectrum. According to our
simulation results, if the asymmetry between the charge and discharge on the charge pump is 1%, the modulation spectrum of
GSM is degraded by about 10 dB from the ideal spectrum.
The phase-detector and charge-pump generally used are
shown in Fig. 11. The phase detector is made up of two
flip-flops and a NAND circuit. The flip-flops are reset by the
feedback signal via the NAND circuit, so the feedback delay
makes the dead zone. And the spike noise at the reset timing
causes phase noise degradation. The spike noise happens because of the delay of resetting the flip-flops, during which delay
the switches for charge and discharge are ON at the same time.
A well known way method to avoid the asymmetry between the charge (pMOS) and discharge (nMOS) operations
is to use same size nMOS for both [13]. Fig. 12(a) shows
the chargepump circuit usually used to make charging and

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Fig. 10. No linearity on charge pump.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008

and the spike noise can be reduced by the operational amplifier.

The asymmetry, spike noise, and dead-zone problems should
be solved at same time, however, to keep the good modulation
spectrum of GSM.
We therefore developed the charge-pump circuit shown in
Fig. 13. When each of the nMOS current sources is the same
. Therefore, the charge and discharge
size,
operations are symmetrical because
.
The slave charge pump can reduce the spike noise of the phase
detector at the reset timing. The slave charge pump input is connected to the reset of the phase detector. When the reset of
the phase detector is high level, the slave charge pump enables I2
on the nMOS side. Ib should then be the same as I2 because the
operation amplifier decides the bias level of the pMOS. When
.
reset is low, the slave charge pump enables I1, and
When
, Ib is always the same
, except at
the time of switching. The switching of the slave charge pump
at also reset can compensate for the spike noise of the master
charge pump. Our charge pump can be made using simple circuits on a small chip.
V. PROTOTYPE DEVELOPMENT AND EVALUATION RESULTS
A.

Fig. 11. Phase detector.

Fig. 12. Known charge-pump circuit.

discharging more symmetrical. The charge current is translated

via a pMOS current mirror. The current consumption of this
circuit, however, is twice that of the charge-pump circuit shown
in Fig. 11.
Spike noise is usually avoided by using the charge-pump circuit shown in Fig. 12(b) [13][15]. When both P and N switches
are ON, the charge pump outputs the spike noise. In this circuit the slave charge pump can keep the voltage at charge-pump
output when both P and N in the master charge pump are ON,

PLL Transmitter

PLL transmitter we made (Fig. 14) conThe prototype

sists of a 0.25- m SOI BiCMOS circuits and a FPGA. The
modulation block, and
FPGA comprises a GMSK filter, a
a calculator to control charge-pump current. The fractionalPLL was fabricated using 0.25- m SOI BiCMOS technology.
PLL transmitter is as follows.
The operation of the
Data for transmission is supplied to this system in a binary
data format at 270.83 kHz and then filtered by a Gaussian
filter on an FPGA to generate a GMSK-modulated signal.
The Gaussian filter output has a 16-bit data structure and the
sampling rate is 6.5 MHz. Frequencychannel-selection data is
then added and the signal is fed into the third-order MASH
modulator. The input signal of the
modulator is a 24-bit
modulator
one, and the sampling rate is 26 MHz. The
shapes noise in order to decrease the quantization noise in the
signal band. This shaped signal is given to the divider in a
fractional- PLL at a sampling rate of 26 MHz. This divider is
an A/B-counter type (i.e., a pulseswallow-counter type) and
consists of ECL circuits. The VCO output provides a GSM
modulation spectrum.
The linearity of the charge pump in the fractional- PLL
needs to be good. Our charge pump assures that the chargecurrent and discharge-current characteristics are symmetrical
(within 10%) over the entire range of the charge pumps operation voltages (Fig. 15).
The 16-bit ECL counter and 24-bit accumulator for loopbandwidth calibration are on the BiCMOS chip, and the chargepump current-control logic and step-wave register are on the
FPGA. In this prototype, the third-order loop filter is outside
of the chip.
B. Calibration System Evaluation Results
The results of evaluating the double-integration of the loopbandwidth calibration system are shown in Fig. 16. The accu-

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PLL TRANSMITTER WITH A LOOP-BANDWIDTH CALIBRATION SYSTEM

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Fig. 13. New charge pump circuit.

Fig. 14. Block diagram of

16 PLL transmitter with loop bandwidth calibration system.

Fig. 15. Double-Integration evaluation result.

mulator integrates 260 points of counter-output, with a 26-MHz

sampling clock, in the lock and step-input states. This system
takes approximately 25 s for the calibration (excluding the
lock-up time of the PLL). The vertical axis in Fig. 16 is the
value determined by subtracting the double-integrated value in
the lock state from the double-integrated value in the step-input
state, and the horizontal axis is the reciprocal of the loop gain

Fig. 16. Charge and discharge current under each register value.

normalized by the most suitable value of loop gain (i.e., the designed loop gain). The ideal normalized 1/(loop gain) changes
step per step of increased double-inteapproximately
gration, and the double-integration result is always within
of the ideal line. This means that 1/(loop gain) can be deter. That is, the
mined to within 2% accuracy
calibration accuracy of loop bandwidth is 2%.

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Fig. 17. Dependency on output voltage.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 2, FEBRUARY 2008

Fig. 18. Transient characteristic.

The calibration accuracy depends on the loop bandwidth and

the sampling clock for the double-integration. In this prototype,
the designed loop bandwidth is around 100 kHz and the sampling clock is 26 MHz. When the loop bandwidth is larger but
the sample clock is the same, the calibration accuracy is degraded because of the faster PLL response. Therefore, the sampling clock should be faster to maintain calibration accuracy.
C. Charge Pump Evaluation Results
Fig. 17 shows the charge pump evaluation result for each
register value. Our charge pump can set the current using a
6-bit register. The register decides the Vbias of current source
of the pMOS in Fig. 12. The charge-pump current can be set
from 400 A to 1620 A in 20- A steps. The charge and discharge currents were measured when the charge pump output
was 1.4 V.
The dependence of the charge and discharge currents on the
charge-pump output voltage is shown in Fig. 15. In this case, the
register value of the charge pump was 55. The locking voltage at
the output of the charge pump depends on the offset frequency
of the VCO. Our VCO can select the most suitable
and
offset frequency automatically. When the VCO is in use, the
voltage at the output of the charge pump in the lock state is
always between 0.8 V and 1.8 V and the error between charge
current and discharge current is less than 1%.
The dead zone of the charge pump is problematic with the
PLL, and the results of evaluating the dynamic
conventional
operation of our charge pump are shown in Fig. 18. Note that
there is no dead zone and that the charge and discharge characteristics are almost symmetrical.
D. GMSK Modulation and Phase Error
PLL transWe adapted our calibration system to the
mitter. Fig. 19 shows the spectrum of GMSK modulation for
GSM at the power amplifier (PA) output when the PA output
is 35.1 dBm. The modulation spectrum is measured after the
loop-bandwidth calibration. The 400-kHz offset noise level is
64 dBc at a PA output that has 4-dB margins at the GSM standard [3]. But we noticed that the noise of the FPGA, which is
on the same board as BiCMOS IC, increases the phase noise of
PLL and degrades the 400-kHz offset noise level.
the
The phase error at GSM standard is sensitive to the loop gain,
but our calibration system can choose the most suitable value

Fig. 19. Spectrum at PA output.

Fig. 20. Charge pump current versus phase error of GMSK modulation.

for the charge-pump current. Fig. 20 shows results of the evaluation of the rms value of the phase error at the GSM standard
[3] when the charge-pump current was changed manually. The
phase error shown in Fig. 20 was measured at the PA output
when the power there was 35.1 dBm. The vertical axis in Fig. 20
is phase error at the GSM standard. and the horizontal axis
is the charge pump current. The charge-pump current can be
set from 400 A to 1620 A in 20- A steps. The most suitable charge-pump current was 1040 A, where the phase error
was 2.0 degrees rms (Fig. 20). Our loop-bandwidth calibration

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TABLE I
LOOP BANDWIDTH CALIBRATION SYSTEM

TABLE II

16 PLL TRANSMITTER
Fig. 21. Die photograph.

VI. CONCLUSION

Fig. 22. Photograph of evaluation board.

system is always able to set the charge-pump current at most

PLL transsuitable current after the calibration, and our
mitter with the loop-bandwidth calibration system can always
hold the phase error to 2 degrees rms or less.
E. Evaluation Board
Fig. 21 is a die photograph of BiCMOS IC that we developed
as a prototype. It was fabricated using 0.25- m SOI BiCMOS
technology and included a VCO, a divider, a phase detector, a
charge pump, a 16-bit ECL counter, and a 24-bit accumulator.
The power level at the VCO output was 3 dBm. The current
consumption was 65 mA (85 mA during calibration) at 2.7 V.
Fig. 22 is a photograph of the evaluation board that included
an FPGA, a power amplifier, and a BiCMOS-IC. The FPGA
included a GMSK filter ROM, a CIC interpolator, a third-order
MASH, a step register for the calibration, and a charge-pump
controller.

PLL transBecause the loop bandwidth in a conventional

mitter varies and the characteristics of the charge pump in that
transmitter are nonlinear, we developed a loop-bandwidth calibration system and a more linear charge pump. The calibration
system used the characteristics of the step response of a PLL
and has simple counter and accumulator circuits. The calibration time is only 25 s, and this system can calibrate the most
suitable bandwidth of a PLL before every transmit burst. The
loop gain is determined to an accuracy within 2%. Our charge
pump made the charge and discharge currentvoltage characteristics symmetrical and eliminated the dead zone.
PLL transmitter, with the charge
We made a prototype
pump and the loop-bandwidth calibration system, for GSM 850,
900, DCS 1800 and PCS 1900 mobile phones. After calibration
the phase error at the GSM standard was less than 2 degrees rms.
The 400-kHz offset noise level at the PA output was 64 dBc,
that is, 4-dB margins from GSM specification. The 20-MHz
offset level at the VCO output was 162 dBc/Hz.
ACKNOWLEDGMENT
The authors would like to thank to K. Watanabe and S. Tanaka
of Renesas Technology Corporation and the RF-IC team of
Takasaki Renesas Technology Corporation.

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[14] M. Johnson and E. Hudson, A variable delay line PLL for CPU-coprocessor synchronization, IEEE J. Solid-State Circuits, vol. 23, no.
5, pp. 12181223, Oct. 1988.
[15] I. A. Young, J. K. Greason, and K. L. Wong, A PLL clock generator
with 5 to 110 MHz of lock range for microprocessors, IEEE J. SolidState Circuits, vol. 27, no. 11, pp. 15991607, Nov. 1992.

Kazuyuki Hori was born in Osaka, Japan, in 1967.

He received the B.E. degree in electrical engineering
and the M.E. degree in informatics from the Tokyo
Institute of Technology, Japan, in 1990 and 1992.
In 1992, he joined the Central Research Laboratory
of Hitachi, Ltd., Tokyo, Japan, and has been engaged
in the development of RF power amplifier linearizers.

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Yukinori Akamine was born in 1974 in Siga Prefecture, Japan. He received the B.S. and M.S. degrees
from Waseda University, Japan, in 1997 and 2000.
He joined the Central Research Laboratory of
Hitachi, Ltd., Tokyo, Japan, in 2000 and has been
engaged in the development of mobile phone RF-ICs
for GSM, EDGE, and WCDMA standards. His
current interest is analog and digital techniques for
digital interface RF-ICs.

Manabu Kawabe was born in Osaka, Japan, in

1960. He received the B.E. and M.E. degrees in
electronics engineering from Kobe University, Japan,
in 1982 and 1984.
In 1984, he joined the Communication Systems
Laboratories of Oki Electric Industry, Ltd., Tokyo,
Japan. In 1997, he joined the Central Research Laboratory of Hitachi, Ltd., Tokyo, Japan, and has been
engaged in the development of radio communication
systems.

Takao Okazaki was born in Hiroshima, Japan, in

1957. He received the B.E. and M.E. degrees in mechanical engineering and the B.S. degree in physics
from Tokyo Institute of Technology, Japan, in 1979,
1981, and 1984, respectively.
In 1984, he joined Micro Device Division, Hitachi,
Ltd., Tokyo, Japan. Since then, he has been engaged
in the development of mixed-signal LSIs.

Masumi Kasahara was born in Gunma, Japan.

In 1979, he joined Hitachi, Ltd., where he was
engaged in the development of analog mixed LSIs.
In 2003, Semiconductor group of Hitachi, Ltd.
became Renesas Technology Corporation. Since
then, he has been engaged in the development of RF
communication LSIs.

Satoshi Tanaka (M93) was born in 1960 in Kyoto

Prefecture, Japan. He received B.S. and M.S. degrees
from Waseda University, Japan, in 1983 and 1985,
respectively.
Since 1985, he has worked at the Central Research Laboratory of Hitachi, Ltd. He has been
engaged in research and development efforts devoted
to mixed analog and digital LSIs for VCRs and
TV sets, low-voltage high-frequency analog RF
ICs for paging receivers, low-noise amplifiers for
magneto-optical disks, digital signal processors
for magnetic recording systems, low-voltage low-power logic circuit design
techniques, and GaAs MMICs and PAs for mobile communication systems.
From September 1995 to November 1996, he was a visiting researcher at the
Electrical Engineering Department, UCLA, where he was engaged in research
on CMOS RF circuit design techniques. Since 1996, he has been developing RF
CMOS circuits for paging receivers, RF ID tag systems, and BiCMOS RFICs
for GSM and W-CDMA applications. His current interest is circuit techniques
for RF power amplifier module and related system design.
Mr. Tanaka was a member of the technical program committee of the IEEE
BCTM from 2000 to 2005 and since 2005 has been a member of the technical
committee of the IEEE ISSCC. He is a member of the IEEE and IEICE.