Design of a 1 Volt, 1.

86 mW Folded-Cascode
Even Harmonic Mixer with DC Offset Analysis
T K Bhattacharyya
Advanced VLSI Design Laboratory, Indian Institute of Technology, Kharagpur, West Bengal, India 721302

In implementing RF transceivers, low power consumption is one of the most challenging

requirements due to the battery lifetime. Low power design has gained tremendous significance in recent times,
particularly with the introduction of newer standards like ZigBee (based on IEEE 802.15.4) which aim at the
design of portable battery operated systems. In this work, the design of a low power, low voltage, high linearity
and good DC offset rejection even harmonic mixer for 1 volt, low IF receivers, compliant with the IEEE
802.15.4 protoco has been achieved. The novelty of this work lies in the thorough analysis of DC offset and its
definition with regard to this particular topology, a more accurate method of simulation and measurement of 1dB compression point and good IIP3(1.12dBm), conversion gain and linearity with a power consumption as
low as1.86mW. The phenomenon of DC offset, its characterization and measurement techniques, specifically for
an even harmonic Mixer architecture have been analyzed in detail.
Keywords : Homodyne architecture, LO self-mixing , Even harmonic mixers, DC offset .

INTRODUCTION
The use of direct- downconversion techniques is a promising approach for highly integrated wireless receivers due to their potential for a
low-power cost effective solution for fully monolithic operation. Their potential for broadband operation is especially important for future
wireless communication applications, where a combination of digital cellular, GPS, and WLAN applications are required in a single
portable device. However, their application has been limited by the menagerie of dynamic range limitations associated with the conversion
of an RF signal directly to baseband. In particular, distortion, noise, and local oscillator (LO) self-mixing are some of the most important
drawbacks . LO self-mixing is a troublesome problem with traditional homodyne approaches, because any signal at the LO frequency
including the LO appearing at the input terminals downconverts to dc. The magnitude of this signal can be measured and periodically
subtracted from the mixer output , but its value varies with time in an unpredictable mannerlimiting the effectiveness of the
compensationand it necessarily subtracts from the available dynamic range of the circuit. The folded cascode even-harmonic doublebalanced mixer architecture that has been designed operates at 1 V supply with a power consumption of less than 2 Watts . The detailed
circuit topology and constraints for low power design , and, measurement and methods to quantify DC offset have been described in detail
in the next sections .Finally , a performance summary of the achieved parameter values has been presented.
1.SYSTEM ARCHITECTURE
1.1 NEED FOR AN EVEN HARMONIC MIXER
In spite of the various advantages of Homodyne architecture, it suffers from certain problems that arise primarily due to conversion to
the base band directly and the far greater susceptibility of signal corruption at near DC levels, an issue which does not arise in
heterodyne receivers. These problems inherent to Direct Conversion mixers have been described in brief here :
DC offset : The root of the DC offset lies to the fact that the RF signal and the LO are at the same frequency and the RF-to-LO
isolation provided by the mixer is never infinite. The LO leakage finds its way into the RF path. It mixes with the LO signal itself to
create a DC offset at the baseband. This phenomenon is called self-mixing. Hence, components at zero and 2*LO frequency are
generated as shown .

FIGURE1

The problem of offset is exacerbated if the self-mixing varies with time. This occurs when the LO signal leaks to the antenna and is
radiated and subsequently reflected back from moving objects back to the receiver. Then it will be difficult to distinguish the time
varying offset from the actual signal.
The DC offset cannot be removed by using a high pass filter, because the desired signal will also then be filtered out. The problem of
DC offset has been the major obstacle in the success of homodyne architecture and thus needs proper attention. It has been
described in detail later with reference to the design.
Noise: Noise performance in homodyne receivers is evaluated in two distinct ways. One is the typical additive noise described by the
noise figure and the other is the baseband low frequency flicker noise. Since the signal is directly down-converted to baseband, flicker
noise becomes an in-band phenomenon that needs to be considered.
1.2 CONCEPT OF EVEN HARMONIC MIXING
The even harmonic mixing technique reduces the effect of the DC offset by a significant amount. The basic principle is to operate
the LO at half the incoming RF carrier frequency. Suppose RF carrier frequency is . Then the local oscillator operates at half of the
incoming RF frequency i.e. at / 2. Any leakage of local oscillator signal component back into the LNA can effectively be filtered out
now. This is called sub harmonic mixing. Because in this case, the LO frequency is half of that of the RF (i.e. an even sub-multiple of
RF), it is also known as even-harmonic mixing.
But for direct conversion to take place, LO signal frequency should be equal to the RF frequency. Hence, twice the applied LO
frequency is generated by a switching network within the circuit so that direct conversion operation can take place.
2.CHOICE OF TOPOLOGY
The choice of topology involves many constraints and tradeoffs .
An even -harmonic scheme has been used to obtain a relatively simple architecture for low-IF applications There are several key
performance parameters for a mixer. Higher gain, higher linearity, lower noise figure, high isolation between LO and RF ports, low
power consumption are desired. These parameters are difficult to obtain simultaneously. The mixer operates at 1 Volt. This imposes a
stringent voltage headroom constraint. Better linearity can be achieved by maintaining a larger overdrive, which again necessitates the
use of higher supply voltage. The gain of a mixer can be increased by increasing the bias current , but it will increase the power
consumption. This requires a cascode at the input stage to minimize LO-RF leakage. But use of a cascode worsens voltage headroom
problem.
Thus a trade off is necessary, particularly in todays scenario where low supply voltage and improved battery life dominate the design
optimizations. In this work, the design objective was to obtain primarily a high linearity and good DC offset rejection and isolation ,
while consuming as little power as possible.
A 1-Volt double-balanced folded cascode even-harmonic mixer with good linearity and isolation has been designed in this work in
0.18 . CMOS technology. On-chip and off-chip Inductance versions of the same design have been explored.
3. CIRCUIT DESCRIPTION
The Circuit of the even harmonic mixer designed has been designed for a low IF band upto 1 MHz. The salient features of the design
are :
1 It is a multiplier based mixer and comprises essentially of three stages : The transconductance stage (for RF ) ,the switching
stage ( for LO) and the Output Stage. Each of these have been explained in detail later

1
2

The mixer operates at 1 volt power supply.

A cascode structure is used for the RF input stage as it has very high output impedance and thus provides better isolation
between RF and LO ports. Moreover, the gate being at a fixed potential provides an AC ground for any feedthrough signal.
However, this increases the voltage headroom constraint in the design.
3 The mixer structure is fully differential and symmetric ;it is a double-balanced mixer circuit. Double Balanced Mixers are
used to prevent the LO products from reaching the output. It essentially consists of two single-balanced circuits with the RF
transistors connected in parallel. This configuration provides a high degree of LO-IF isolation easing filtering requirements at
the output. Double Balanced mixers are less susceptible to noise than the single-balanced mixers because of the differential
RF signal.
4 Inductive degeneration has been added to the RF stage . This is better than resistive degeneration because there is no DC
voltage drop and increased impedance at high frequencies helps filter out the undesired high frequency components. It
provides voltage gain due to resonance with Cgs (discussed later) and improves linearity.
5 The RF and the LO stages are folded with respect to each other to deal with the voltage
6
headroom constraint(we have to keep all devices in saturation during operation with a supply
7
voltage of 1 Volt).
8 Thus for proper operation, we must bias the RF and LO transistors properly so that the overdrive
9
voltage is small and all the transistors operate in saturation. The reduced overdrive somewhat
10 reduces the linearity of the mixer.
1 The inductors L1 and L2 which provide bias current have been designed as both off-chip and on-chip ; with each
configuration having its characteristic pros and cons. This issue has been discussed later in detail .
2 The generation of twice the LO frequency is achieved by means of quadrature LO signals at 0,90,180 and 270 degrees. The
switching network effectively produces a switching at twice the applied LO frequency.
3 Multiplication of the RF signal with the LO signal generates two components- one at frequency (RFLO) and the other
at (RF +LO). Since the desired IF is the first one,we use an RC filter in the IF stage,
4 This is a low IF topology and combines the advantages of both types of receivers, IF and direct down-conversion. In a low
IF receiver, the filter following the mixer can be of a much lower quality factor, as compared to a high IF case. This leads to
easier design of filter and improved integration. The advantage of a low IF filter compared to a homodyne receiver is also
obvious. The DC offset problem is not that severe because the wanted signal is not situated around DC.
5
In simple terms, the design can be viewed as a time-varying mildly non-linear circuit in which the flow of one signal is controlled
by the time-variation of the other one. The controlling signal is the LO (Local Oscillator) while the stimulus is the RF signal and
the desired output is the intermediate frequency (IF) waveform.

CIRCUIT TOPOLOGY (FIGURE2)

TRANSCONDUCTANCE STAGE

SWITCHING STAGE
3.1 CHOICE OF INDUCTANCE
Two basic schemes have been designed, the circuit topology being the same. The difference lies in the implementation of the inductor
in the tank stage as an on-chip or off-chip component and the corresponding constraints associated with each case.
The off-chip scheme implies that the inductor in the transconductance stage tank circuit has been implemented off-chip .This offers
the flexibility of being able to select a larger Q value (of about 20 ) for the inductor and consequently a higher conversion gain. The
inductance value is taken to be 70 nH initially and later reduced to 20nH.
In the on-chip scheme, the design of high quality integrated inductors is a key point in the realization of radio frequency selective
amplifiers/filters, LNA and Voltage-Controlled Oscillators. Inductors in the range of 1 nH to 8 nH can be integrated and they are
commonly realized as spirals using the top metal layer. In this implementation, the losses are of three types : finite conductivity of the
metal , electric coupling with the substrate and magnetic coupling with the substrate. The Q-factor degrades due to each of these
losses. An efficient solution to reduce magnetic losses in standard CMOS processes has not been found yet.
Thus , with an on-chip inductor stage , we have the advantage of better integration . However, the problem with the on-chip case is
that we have is that the 5nH inductor has an associated series resistance of 7ohms(for a Q of 4).
The tank circuit is tuned to resonance at the RF frequency (901MHz) so that maximum current can flow to the switching stage.

AC MODEL OF THE MIXER (FIGURE 3)

Denoting the tank stage as ZT , the transconductance stage as G m and replacing the switches by their on-state resistance and associated
parasitic capacitance , the ac model of the mixer can be represented as shown in Figure 3.
4.DC OFFSET IN EVEN HARMONIC MIXERS: AN ANALYSIS
This analysis is aimed at the techniques used for the measurement of DC offset in mixers and also at developing what DC offset
rejection specifically means in the context of an even harmonic direct conversion mixer.
4.1THE GENERALIZED DEFINITION
DC offset is a measure of the imbalance of the mixer. For an ideal mixer, the DC offset is zero. DC offset defines the IF voltage output
when the mixer is used as a phase detector and only the LO signal is applied; the RF-port is terminated in 50 ohms.
The basic concept upon which phase detection rests is that the application of two identical frequency, constant amplitude signals to a
mixer results in a dc output which is proportional to the phase difference between the two signals. Thus, in this case the voltage at the
IF port will be dc and will vary as the cosine of the phase difference between the LO and RF signals. DC offset varies with mixerinduced phase shift of the signals due to circuit imbalance. We can observe how these characteristics may change as various elements
affecting mixer performance are changed (e.g., frequency, LO and RF drive levels, load resistance, and temperature).
If only one signal (LO or RF) is applied to the mixer, the dc offset is then simply the dc component of that portion of the applied
signal which is measured at the output port, implying that dc offset is inversely related to isolation.
4.2 DIRECT LO FEEDTHROUGH
The isolation between the LO port and the inputs of the mixer is not perfect, and a finite amount of feed through, which is known as
LO Leakage exists from the LO port to the other mixer inputs. The leakage signal is reflected back at the outputs of LNA (ignoring
the feed through from LNA outputs to its inputs) and now mixed with the original LO signal, thus producing a DC component at the
output of the mixer. Coupling of LO to the LNA and RF ports causes static offset. DC offset is thus generated due to LO selfmixing. Also, when LO couples to the antenna, and gets reflected back, a dynamic time-varying offset may be created.
4.3 HOW CAN THIS OFFSET BE QUANTIFIED
So, the DC offset at the mixer output due to self-mixing Vself can be expressed as:
where

Vleak = Leaked LO signal voltage

Ramp

= Reflection factor at LNA output port

Glo bb

Vself Vleak Ramp Glo bb

= Conversion gain of the mixer from LO-signal frequency to base band.

Ramp

is varied depending on the electromagnetic environment of the antenna and the reverse and/or forward gains of the
RF amplifier. The LNA gain is often switched depending on received signal strength. Thus, the self-mixing output is not a stable dc
offset.
The output voltage itself cannot be a direct measure for the self-mixing , Attenuator following the mixer may make the offset small but
does not improve the ratio of the desired signal to the undesired signal. Instead; the equivalent RF signal amplitude V eq at the mixer
input should be used as a measure of self-mixing.

Veq Vleak Ramp

where

Grf bb

In a typical direct converter case,

Globb
Grf bb

and

Ramp

of -14 dB, we obtain a

Veq

Glo bb
Grf bb

is the conversion gain from received signal frequency to baseband.

is unity since LO frequency is same as received signal frequency. For a

Vleak of -50 dBm,

of -64dBm. It is preferred that the reflected signal should be less than -100dBm.

To achieve this figure of -100dBm, there are two options in mixer design :

Reduce

Vleak to Reduce

Glo bb
Grf bb

EVEN HARMONIC MIXER CASE

Conversion gain ratio is the most important factor for overcoming self-mixing problem.
To isolate the desired RF signal and the reflected LO signal, it is desirable that the LO frequency be different from the desired signal
frequency. In an even harmonic mixer, the LO operates at half the RF frequency. The self-mixing output is a product of the LO signal

and the leaked- and-reflected LO signal. Ideally,

principle.

Glo bb
Grf bb

is zero for an EHM and hence it is free from LO self-mixing problem, in

Also, a double-balanced fully differential architecture is effective for reducing leak . The folded cascode topology offers high Output
impedance and thus reduces the leakage of LO to the input RF port (which leads to self-mixing).
LO Leakage arises from many factors, such as substrate coupling, asymmetry of the circuit etc.
4.4 RESULTS :
MEASUREMENT OF LO LEAKAGE :
The LO leakage can be obtained by disconnecting RF signals and only injecting LO Signals to the mixer. The RF port is terminated in
a 50 Ohms resistance through a balun. The measured values are inversely related to RF-LO, IF-LO ,RF-2LO and IF-2LO isolation as
shown in the figure 4 .

MEASUREMENT OF LO LEAKAGE
SNo.

LO signal

LO

RF port

IF port

level(mV)

Frequency

signal

signal

1.

400m

450 MHz

89.446 nV

14.775 V

2.

400m

900 MHz

61.22 nV

1.279V

3.

200m

450 MHz

34.7 nV

2.793 V

4.

100m

450 MHz

11.16nV

327.72nV

FIGURE4

amp
Worst case calculation of Veq : In the worst case calculation we assume the reflection coefficient
to be unity .The actual DC
offset would become about 10dB smaller than this measured result.
1 The LO leakage level at the RF input port is measured(as above).
2 Then a simulated reflection signal is applied, which is the same as the LO leakage level measured above with a 1 MHz
offset.
3 The output signal level at 1 MHz can then be obtained.

Thus , we can obtain the LO-signal amplitude dependence of Veq,the measure of self-mixing.
A frequency offset of 1 MHz was introduced to isolate self-mixing from other dc offsets and to make the measurement independent of
the phase of the reflected signal.
DC OFFSET CANCELLATION
The DC offset cancellation performance due to self-mixing can be quantified as:
DC Offset Cancellation = GRF / GLO
where GRF is the conversion gain of the mixer when the input is at the RF frequency and LO is half of the input RF frequency and GLO
is the conversion gain of the mixer when the RF input is at the QVCO frequency. This definition can be correlated to the definition for
calculation of DC offset voltage described previously. Here, GRF / GLO term appears instead of the reciprocal as here we are trying to
quantify cancellation instead of calculation of the actual offset.In order to determine the DC Offset rejection, we first find out G RF /
GLO. It is observed that when RF is at 451 MHz. the output observed at the IF port is not a pure signal at 1 MHz. We obtain the DFT
coefficients of the output signal for computation of GLO.
DC OFFSET CANCELLATION MEASUREMENT

4.5 SUMMARY

SNO

RF freq.
(MHz)

LO freq.
(MHz)

DFT coefficient
(1MHz)

DC offset
cancellation

1.

901

450

3.28 e-3

94.8574 dB

2.

451

450

5.929e-8

3.

901

450

3.572e-3

62.33 dB

4.

451

450

2.73 e-6

(with 1%gm
mismatch)

The measurement of DC offset can be done in many ways. However, all the proposed techniques are derived from the measurement of
the LO leakage signal at the input port which leads to self-mixing .In other words, the better the port-to-port isolation the better is
the DC offset rejection. Hence , GRF / GLO factor is directly proportional to Offset cancellation and inversely proportional to DC
offset value. Also, there are various factors that contribute to DC offset, self-mixing being a prominent one. It is difficult to clearly
obtain the offset due to each of these factors separately.
5.LINEARITY MEASUREMENT AND ANALYSIS
Research in non-linear high frequency circuits has a dual focus. The first is on the design of non-linear circuits, in which non-linearity
is exploited for some particular function. Among these circuits are the frequency multipliers and mixers .The second focal point is on
the deleterious effects of the undesired non linearity .The analysis and optimization of such systems is complicated by the complex
nature of the signals they must accommodate ;viewed in the frequency spectra these signals have multiple frequency components ,or
continuous spectra. Our primary concern here is to understand and quantify those non-linearities associated with a mixer which limit
its performance.

FIGURE 6

Ignoring dynamic effects, we can model an actual mixer as non-linearities around an ideal mixer.
1 Non-linearity A can be characterized by gain compression and IIP3.It can hamper the rejection of interferers.
2 Non-linearity B will change the spectrum of the LO signal. It is not of much concern, because LO Input is a square wave itself.
3 Non-linearity C will cause self-mixing of the IF output. It can be avoided by using a linear load such as a resistor.
5.1 NOVEL METHOD OF MEASUREMENT OF 1-dB COMPRESSION POINT :
The 1-dB compression point is an important measure of circuit linearity .Here, we describe a method for its measurement . The mixer
unit is simulated in two different configurations.
In the first one, a differential input V1 is applied to the mixer unit and the output IF amplitude is monitored after a transient
simulation. Also, in the second one, input V2 is also applied differentially to the mixer unit such that V1/V2 = 10 or in terms of input.
power , input(2) is less than input(1) by 20 dBm.A Voltage-controlled Voltagesource (VCVS) which provides a voltage gain of
8.912,is applied at the output (equivalently 19dB) .Thus, the output power level in configuration(2) will be 1 dBm lesser. Hence,
ideally the output in configuration (2) should be less than configuration (1) by 1dB( assuming perfectly linear behavior, the input is
20dB less in second case and then a voltage gain of 19dB is provided).However, due to actual circuit behavior , as the input power
amplitude will increase, at the 1- dB compression point , the transient output curves of circuit (1) and (2) will exactly coincide. This
implies that the output of configuration (1) has fallen 1-dB below its value (as expected from linear behavior) and hence coincides
with the output of configuration(2), (which is still linear as the signal amplitude is quite small : V2 being one-tenth of V1). The onedB compression point measurement is thus carried out by running a transient simulation on both these configurations and comparing
the output signals obtained at each power input level until they exactly overlap at the 1- dB point.
5.2RESULTS
a) for gm stage 1(on-chip):
At each applied input power level(V1 and V2) , the output signal amplitudes are monitored. At input level corresponding to -8.48dBm
, the two output signals obtained are :

FIGURE 7

Where the two curves represent the transient output IF signal (at 1MHz) obtained from the two configurations. For an input at 901
MHz, the output signal amplitudes are same for - 8.4dBm input to configuration 1 and a -28.4 dBm input to configuration 2.
b)for off-chip Mixer unit (with L = 20nH)
The measured 1- dB compression point is -11dBm .
Thus , the on-chip design developed in this work has a 1-dB compression point of -8.4dBm and an IIP3 of +1.2dBm .
CONCLUSION :

In this work , the design focus has been primarily on two factors. Firstly, an folded cascode EHM architecture suitable for
low power, low voltage and good linearity operation has been conceived and designed. Moreover, a detailed analysis if DC offset and
its characterization has been carried out. It is believed that the analysis of DC offset presented in this work will help in developing a
clearer understanding of this phenomenon in EHM architectures, and establishing more definitive methodologies for its measurement
and comparison; which will hence give a better direction to the attempts at minimizing its impact and facilitate research on low
voltage, low power, good linearity EHM designs with much more standard techniques of DC offset characterization, understanding
and improvement.
BRIEF LITERATURE REVIEW :
[1] is the one of the latest published works on Even harmonic Mixers. This EHM possesses a conversion gain of 8.3 dB,third -order
input intercept point of 0.03dbm at a supply voltage of 0.9 volts. The power consumption of the proposed Mixer is about 4.95 mW at
an IF frequency of 500KHz.

Our design has a conversion gain of 5dB(without matching) , a third order intercept point of +1.12 dbm nearly, supply voltage of 1
volt and a power consumption of 1.863 mW.
[2]The measured results reveal that the proposed mixer possesses single-end conversion gain of 8 dB and third-order input intercept
point (IIP3) of -3.8 dBm, respectively, under the supply voltage of 1.8 V and LO power of 4 dBm. The power consumption of the
proposed mixer is about 1.4 mW at 900 MHz.
[3]This proposed mixer operates at 3 Volt, has a IIP3 of -8dbm and a dc current consumption of 4.6mA.
Also ,it has been implemented in 0.35 micron SiGe BiCMOS process. Hence, detailed comparison is not relevant here.
[4.]This mixer design is aimed at good DC offset cancellation , but the supply voltage is 3V.
Moreover, it is not a cascode scheme for the RF stage and the LO stage is not folded with respect to the RF stage. Hence, the topology
is quite different.
REFERENCES :
[1] Ming-feng huang ,Chung J.Kuo, members IEEE, "A 5.25 GHz CMOS Folded-Cascode Even Harmonic Mixer for Low Voltage
Applications " IEEE 2006
[2] Proceedings of the 2004 International Symposium on Low Power Electronics and Design, "A CMOS Even Harmonic Mixer with
Current
Reuse
For
Low
Power
Applications "
Ming-Feng
Huang,
Shuenn-YuhLee, Chung J. Kuo, National Chung Cheng University, Taiwan
[3].M.Goldfarb, E.Balboni and J.Cavey , "Even harmonic double-balanced active mixer for use in direct conversion receivers" IEEE
solid state-circuits ,oct.2003
IEEE Radio Frequency Integrated Circuits Symposium .
[4] S.J Fang, S.T Lee and D.J Allstot ,"A 2 GHz CMOS even harmonic mixer for direct conversion receivers" in proc. IEEE Int. Sym.
Circuits Syst., vol4, 2002.
[5]Kalle Kivekas ,Aarno Parssinen ,Kari A.I Halonen , Characterization of IIP2 and
DC-Offsets in Transconductance Mixers; IEEE Transactions on circuits and systems-II ,Vol. 48, No 11 ,November 2001.