Академический Документы
Профессиональный Документы
Культура Документы
Department of
DIPLOMA IN ELECTRONICS & COMMUNICATION ENGINEERING
2014-15
Name : ________________________________
Regd. No. : _____________________________
Class : ________________________________
Year : _________________________________
Department of DECE
EXP. NO.
PAGE
NO.
INDEX
Construct and verify the truth tables of NAND and NOR latches
10
11
12
13
14
Design and simulate half adder,full adder circuits using workbench software
etc,,
Department of DECE
REG NO:
YEAR:
EXPERIMENT NAME
DATE
7
8
STAFF
SIGNAT
URE
REMARKS/
GRAD
E
10
11
12
13
14
Department of DECE
DATE:
VCC = + 5V
14
13
12
11
13
10
12
11
C
8
10
B
6
GND
1
74LS08
Department of DECE
AND GATE
OR - Gate Symbol
NOT Gate:
When in put variable A is low the output of a NOT gate is High. The logic symbol of
NOT Gate is shown in Fig .The IC 74LS04 is a single in put NOT Gate IC and it consists of 6NOT gates. The IC has 14 pins constructed in Dual in Line package(DIP) as shown in Fig. The
truth table of NOT Gate is as shown in Fig.
Department of DECE
13
12
11
10
GND
1
NAND Gate:
The outputs of all NAND gates are high if any of the inputs are low. The logic
symbol of NAND Gate is shown in Fig .The IC 74 LS00 is a two input NAND Gate IC. It
consists 4 NAND gates built in. The truth table of NAND Gate is as shown in Table.
NOR Gate:
The outputs of all NOR gates are low if any of the inputs are high. The logic symbol
of NOR Gate is shown in Fig. The IC 74 LS02 is two in-put NOR Gate IC it consists of 4 NOR
gates. The truth table of NOR Gate is as shown
Department of DECE
EXOR Gate:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not
both, of its two inputs are high. . The logic symbol of EXOR Gate is shown in Fig .The IC
74LS04 is a single in put EXOR Gate IC and it consists of 4- EXOR gates. The truth table of
EXOR Gate is as shown in Table.
Department of DECE
Construct the circuit on breadboard for each Gate as shown in figures by inserting the
appropriate IC.
2.
Check the combinations of various inputs as shown in truth tables for each Gate.
3.
If the input is low connect input to Ground, which indicates logic 0.
4.
If input is high or logic 1 then connect the input to the power supply.
5.
When output is high the LED will glow which indicates output as high, if the LED is not
glowing then the output is low.
OBSERVATIONS:
Truth Table for NOT Gate
A
X=
0
1
B
0
1
0
1
X=
RESULT:
Successfully checked and verified the operation of Basic Logic Gates through the truth
table.
Signature of Staff Member
Department of DECE
DATE:
Department of DECE
PROCEDURE:
1. Construct the circuit on breadboard for each Gate as shown in figures by inserting the
appropriate IC.
2. Check the combinations of various inputs as shown in truth tables for each Gate.
3. If the input is low connect input to Ground, which indicates logic 0.
4. If input is high or logic 1 then connect the input to the power supply.
5. When output is high the LED will glow which indicates output as high, if the LED is not
glowing then the output is low.
OBSERVATIONS:
B
0
1
0
1
A
0
0
1
1
X = A*B
B
0
1
0
1
X = A+B
Successfully realized Boolean expressions using AND-OR-NOT Gates, NAND and NOR
gates and verified the operation through the truth tables.
Signature of Staff Member
Department of DECE
10
DATE:
REALISATION OF HALF ADDER
AIM:
To construct and check the truth tables for Half-Adder.
APPARATUS REQUIRED:
COMPONENTS:
1.
2.
3.
4.
IC 7408
IC 7486
LED - 2 nos
330 resistor-2 nos
EQUIPMENT:
1. Power supply
2. Bread Board.
3. Connecting wires
THEORY:
HALF ADDER:
LOGIC SYMBOL:
A
S = AB+ AB
HA
C = AB
The combinations for the sum and carry are written by the formula are given as.
S = AB+ AB
C = AB
PROCEDURE:
1.
2.
3.
4.
5.
6.
7.
8.
Connect the logic circuit diagram of Half adder on bread board as shown in figures.
Give power supply to pin no. 14 of each IC.
Ground the pin no 7 of each IC.
Connect LEDs as an out put for sum, carry, difference and barrow.
Connect a 330 resistor in series with each LED.
Check the truth table for all combinations.
When output is high the LED will glow, indicates logic 1.
When output is low the LED will not glow, indicates logic 0
Department of DECE
11
CIRCUIT DIAGRAM:
TRUTH TABLE
A
0
0
1
1
B
0
1
0
1
S C C
PROCEDURE:
1 Connect the logic circuit diagram of Half adder on bread board as shown in figures.
2 Give power supply to pin no. 14 of each IC.
3 Ground the pin no 7 of each IC.
4 Connect LEDs as an out put for sum, carry, difference and barrow.
5 Connect a 330 resistor in series with each LED.
6 Check the truth table for all combinations.
7 When output is high the LED will glow, indicates logic 1.
8 When output is low the LED will not glow, indicates logic 0
RESULT:
Successfully constructed the Half-adder circuit using ICs and verified truth table.
DATE:
12
IC 7408
IC 7486
LED - 2 nos
330 resistor-2 nos
EQUIPMENT:
4. Power supply
5. Bread Board.
6. Connecting wires
THEORY:
The Full Adder circuit is used to add three binary digits. The two outputs are sum- S and
carry-C. The three inputs are input A, input B and carry input C. The outputs are sum S and
carry out X. The construction of Full adder using two EX-OR Gates, two AND Gates and one
OR Gate is as shown in fig-3. The IC numbers are 7486, 7408 and 7432.
LOGIC SYMBOL:
The combinations for the sum and carry are written by the formulae are given as.
S = ABC + ABC+ ABC + ABC
X = AB + BC + AC
Sum- S
A
B
Full-Adder
Carry -X
Department of DECE
13
Department of DECE
14
RESULT:
Successfully constructed the Full-adder circuit using ICs and verified truth table.
Department of DECE
15
EXP NO: 5
Department of DECE
16
TRUTH TABLE:
INPUTS
R
0
0
1
1
S
0
1
0
1
OUTPUTS
NOT Q
OUTPUTS
NOT Q
2.NOR LATCH:
TRUTH TABLE:
INPUTS
R
0
0
1
1
S
0
1
0
1
PROCEDURE:
Department of DECE
17
RESULTS:
EXP NO: 6
DATE:
18
IC 7400
IC 7410
IC 7476
IC 7474
LED 2 no.s
Single lead probes.
EQUIPMENT:
1. Flipflop trainer kit
2. Connecting wires/patch chords.
THEORY:
A flip-flop has two stable states. One of the stable states is known as SET or LOGIC 1 where
as the other stable is called RESET, CLEAR or LOGIC 0. It stores a binary digit either 0 or 1.
Types of flip-flops:
1) SR flip flop
2) JK flip flop
3) D flip- flop
4) T flip-flop
S-R Flip-flop
. When S=1 and R=0 after applying of clock pulse Q=1 and = 0,this state is know as set
condition. When S=0 and R=1 when clock pulse is high Q=0 and = 1,this is reset condition.
For the combination S=0 and R=0 the outputs will be the previous outputs only. The combination
S=1 and R=1 are not applied because the outputs will be toggling mode i.e. Outputs are not
stable.
S
Q
CLK
FF
Q
JK Flip-flop
The construction of JK flip-flop using NAND gates is shown in fig-.
When clock is applied if J=1 and K=0 then the outputs Q=1 and =0 this condition is called as
SET. If J=0 and K=1 then the outputs Q=0 and =1 this is called as reset condition. The truth
table for the J-K flip flop is shown below. The JK flip flop can also be constructed by using an IC
74LS76. The Pin Description for IC 7476 are shown below:
Department of DECE
19
FF
Q
D Flip-flop
The Logic symbol of D flip-flop is shown in fig 9. When clock is applied if D=1 then the
outputs Q=1 and =0. If D=0 then the outputs Q=0 and =1. The truth table for the D flip
flop is shown below. The D flip flop IC number is 74LS76. The Pin Description for IC 7476 are
shown below:
D
Q
CLK
FF
Q
FIG 9. D- FLIP-FLOP
T Flip-flop
WORK PROCEDURE:
1. Connections are made as per the logic symbols
2. Connect the logic input to input switches and logic outputs to o/p switches provided on the
FlipFlop Trainer kit
3. Apply clock iput to the pulser of trainer kit.
4. Set the synchronous inputs Reset/Clear and set/preset to logic 1 throughout the experiment
for all the flipflops
5. Switch on the trainer kit
6. Apply various combination of
inputs
TRUTH TABLE FOR
according to the truth tables and
observe
the
condition of LEDs
JK MASTER SLAVE FLIP FLOP
7. Hence verify the truth tables for
all flipflops.
J
K
Q
n+1
OBSERVATIONS:
Department of DECE
0
200
1
1
0
1
0
Qn+1
Qn+1
Qn+1
RESULT:
Successfully constructed various flip-flops and verified their truth tables.
Department of DECE
21
DATE:
COUNTERS
AIM:
To construct and check the Decade counter, Ripple counter and binary counters using
and IC 7493.
IC 7490
APPARATUS REQUIRED:
COMPONENTS:
1.
2.
3.
4.
5.
IC 7490
IC 7493
Resistors - 330 -- 8 nos.
LEDs -- 4 nos
Single lead probes.
EQUIPMENT:
1. Power supply
2. Bread Board.
IC 7490/ 7493 PIN DIAGRAM:
Department of DECE
22
Department of DECE
Next State
Q3Q2Q1Q0
Decimal
Number
0 0 0 0
0 0 0 1
0 0 0 1
0 0 1 0
0 0 1 0
0 0 1 1
0 0 1 1
0 1 0 0
0 1 0 0
0 1 0 1
0 1 0 1
0 1 1
0 1 1
0 1 1 1
0 1 1 1
1 0 0 0
1 0 0 0
1 0 0 1
10 1 0 0 1
0 0 0 0
23
Department of DECE
24
Department of DECE
25
7490
Department of DECE
26
Department of DECE
27
RESULT:
Successfully constructed the decade counter and observed the waveform and checked its
counting sequences such as Even- Odd, Even and Odd.
Signature of Staff Member
Department of DECE
28
DATE:
SHIFT REGISTER(IC 7495,74194)
AIM:To study shift register using IC 7495 in all its modes i.e. SIPO/SISO, PISO/PIPO.
29
Department of DECE
30
Department of DECE
31
Department of DECE
32
Department of DECE
33
DATE:
DIGITAL COMPARATORS(IC 7485)
AIM:
i) To construct a Comparator using IC-7485 and to compare 2 BCD numbers in terms of
their Magnitude.
APPARATUS REQUIRED:
COMPONENTS:
1. IC-7485
EQUIPMENT:
1. IC Trainer Kit
2. IC7485
3. Connecting wires/Patch chords
.
THEORY:
The comparison of two numbers is an operator that determine one number is greater than,
less than (or) equal to the other number. A magnitude comparator is a combinational circuit that
compares two numbers A and B and determine their relative magnitude. The outcome of the
comparator is specified by three binary variables that indicate whether A>B, A=B (or) A<B.
A = A3 A2 A1 A0
and
B = B 3 B2 B1 B0
The equality of the two numbers and B is displayed in a combinational circuit designated by the
symbol (A=B).
This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits
starting from most significant position. A is 0 and that of B is 0.
We have A<B, the sequential comparison can be expanded as
A>B = A3B31 + X3A2B21 + X3X2A1B11 + X3X2X1A0B01
A<B = A31B3 + X3A21B2 + X3X2A11B1 + X3X2X1A01B0
Department of DECE
34
The same circuit can be used to compare the relative magnitude of two BCD digits.
Where, A = B is expanded as,
A = B = (A3 + B3) (A2 + B2) (A1 + B1) (A0 + B0)
x3 x2 x1 x0
Department of DECE
35
Department of DECE
36
PROCEDURE:
1. Connections are made as per the circuit diagram
2. Apply comparing inputs nad cascading inputs as per the truth table
3. Observe the corresponding inputs
4. Hence,verify the truth table.
RESULTS:
Department of DECE
37
EXP NO: 10
AIM: To Study a 4 bit R-2R ladder type Digital to Analog converter circuit.
APPARATUS REQUIRED:
Components:
1. 8-BIT DIGITAL TO ANALOG TRAINER KIT
Equipments:
1. C.R.O.
2. CRO PROBES.
3. Power supply.
PRINCIPLE:
The purpose of Digital to Analog Converter is to convert a binary number or word to
a proportional analog current or voltage. An 8-bit DAC takes 8-bit data as input and generates a
proportional voltage signal as the output. The output range can be 0 to 2.56V. There are two
methods of DAC
1. Binary Weighted Resistor method
2. R-2R Ladder Network method
R-2R LADDER METHOD
It uses only two types of resistors (R & 2R) only. It removes the disadvantages of binary
DAC method. The circuit is as shown in figure. The input to the circuit is applied through digital
switches (0 & 1). If switch is in zero position the input is zero otherwise one. This network is
linear its operation can be analyzed as the output voltage from each source is independent of
other sources. The sum of all sources gives the output voltage and current.
CIRCUIT DIAGRAM:
Department of DECE
38
3R
Vo
1
2R
2R
2R
2R
2R
LSB
M SB
Thus the input of DAC is proportional to the sum of the weights represented by the
switches that are connected to a reference voltage V. When three input bits are used, only 2 3(or 8)
different analogue voltages can be signaled by the circuit; if the number of bits is increased to 4,
this becomes 24 (or 16) different voltages and so on. The full scale FS is the full-scale output of
the DAC and it is the maximum output voltage it can deliver to a load. The FS is given for an nbit DAC
FS = 2n 1/(2n X FSR)
FSR - Full-scale range is the value, which is divided into 2 n parts to determine the least
significant bit. For example the FSR of a DAC is 10 V. If the DAC is a 3 bit circuit, then
Least significant bit LSB = 10/23 = 1.25 V
Most significant bit MSB = 10/2 = 5 V
FS = 10 1.25 = 8.75 V.
Department of DECE
39
PROCEDURE:
1. Switch on the experimental board.
2. Connect he clock generator to the clock input terminals.
3. Apply the digital inputs to the terminals as shown.
4. Apply LSB to MSB terminals for Binary weighted method.
5. Apply the LSB to LSB and MSB to MSB terminals on kit.
6. Apply the count enable switch by pushing the switch.
7. Connect the CRO probes to CRO terminal.
8. Observe the waveform on screen of CRO.
9. Note down the voltage level for every input digit position.
OBSEVATIONS
DIGITAL INPUTS
D0(MSB) D1 D2
Department of DECE
D3
D4
D5
40
D6
D7(LSB)
ANALOG OUTPUT
OBSERVED CALCULATED
Department of DECE
41
EXP NO: 11
IC 74153
Resistors - 330 -- 8 nos.
LEDs --8 nos
Single lead probes.
EQUIPMENT:
1. Power supply
2. Bread Board.
THEORY: Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there are 2 n
input line and n selection lines whose bit combination determine which input is selected.
BLOCK DIAGRAM
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects binary
information from one of many input lines and directs it to a single output line. The selection of a
particular input line is controlled by a set of selection lines. Normally there are 2n input line
andent any 2-variable ft is Y = A.B + A.B.ailable for multiplexers are 2:1, 4:1, 8:1 and 16:1. The
diff
Standard multiplexer ICs
Department of DECE
42
Department of DECE
43
Department of DECE
44
Department of DECE
45
DATE:
Department of DECE
46
Department of DECE
47
PRECAUTIONS:
1. Always use a straight lead probe to insert into the breadboard.
2. Apply proper grounding for ICs.
3. Check the starting pin number for each IC indicated with a dot as starting pin.
4. Use IC remover to remove IC from breadboard to avoid damage of pins of IC.
5. Dont touch the pins of ICs while power on.
6. Dont bend the pins of ICs.
7. Insert the components into the breadboard firmly.
8. Loose contact may result in error at output.
9. Give 1 level Voltage (+5V for TTL) or 0 level voltage to the inputs of the IC.
RESULT:
Successfully constructed the Demultiplexer Circuit and verified the Function Table.
Department of DECE
48
EXP NO: 13
DATE:
RANDOM ACESS MEMORY(RAM)(IC 7489)
AIM: To conduct an experiment to store a set of data in a RAM using IC 7489 starting from
location to location and retrieve the same data.
Apparatus Required: IC 7489, etc.
Procedure: 1.
2.
First you have to write the data and then read the data, for writing data make WE to low
and ME input to low
3.
For a 4-bit data select any address input from A0 to A9. for ex, select A3 to A0 and
connect the data inputs/ outputs i.e., I/O4 I/O1
4.
Write a 4-bit data of your choice in each of the required address inputs or memory
locations
5.
By doing the above steps 2, 3 and 4 the data will be stored in the memory location
6.
Department of DECE
49
Department of DECE
50
RESULT:
Department of DECE
51
EXP NO: 14
Department of DECE
52
FULL-ADDER:
Library IEEE;
Use IEEE.STD-LOGIC-1164.all;
Entity.
full-adder is
Port(a:in STD_LOGIC;
b:in STD-LOGIC;
c:in STD-LOGIC;
Sum:out STD-Logic;
Carry:out STD-Logic);
End Full-adder;
Architecture full-adder-arch of h-adder is
Begin
Sum <= a xor b xor c;
Carry<= (((a xor b) and c) or (a and b));
End full-adder-arch;
RESULTS:
Signature of Staff Member
Department of DECE
53
Department of DECE
54