SIMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) IN HSPICE

IKA DEWI BINTI SAIFUL BAHRI

This thesis is submitted in part of the requirement for the Degree of Bachelor
Engineering (Electrical-Microelectronics)

Electrical Engineering Faculty

University of Technology Malaysia

JULY, 2012

UNIVERSITI TEKNOLOGI MALAYSIA

DECLARATION OF THESIS / UNDERGRADUATE PROJECT PAPER AND
COPYRIGHT

Authors full name: IKA DEWI BINTI SAIFUL BAHRI

: 07 JULY 1988

Date of birth

: SIMULATION OF STATIC RANDOM ACCESS MEMORY

Title

(SRAM) IN HSPICE
.
Academic Session : 2011/2012
I declare that this thesis is classified as:

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(Contains confidential information under the Official Secret

Act 1972)*

RESTRICTED

(Contains restricted information as specified by the

organization where research was done)*

OPEN ACCESS

I agree that my thesis to be published as online open access

(full text)

I acknowledged that Universiti Teknologi Malaysia reserves the right as follows:

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Certified by:
SIGNATURE

SIGNATURE OF SUPERVISOR

880707-23-5064
(NEW IC NO. / PASSPORT NO.)

DR. MICHAEL TAN LOONG PENG

NAME OF SUPERVISOR

Date: 04 July 2012

Date: 04 July 2012

NOTES: * If the thesis is CONFIDENTAL or RESTRICTED, please attach with the letter from
the organization with period and reasons for confidentiality or restriction.

SIMULATION OF STATIC RANDOM ACCESS MEMORY (SRAM) IN HSPICE

IKA DEWI BINTI SAIFUL BAHRI

This thesis is submitted in part of the requirement for the Degree of Bachelor
Engineering (Electrical-Microelectronics)

Electrical Engineering Faculty

University of Technology Malaysia

JULY, 2012

ii

I declared that I have read through this thesis and my opinion this report is sufficient
enough for fulfilling the standard of the thesis for the Bachelor Degree in Electrical
Engineering (Electrical-Microelectronics)

Signature

..

Supervisors Name

DR. MICHAEL TAN LOONG PENG

Date

04 JULY 2012

iii

DECLARATION

I hereby declare that following project is the result of my own work expect for
commentaries and summaries that I had clearly stated the source.

Signature

Author

IKA DEWI BINTI SAIFUL BAHRI

I/C No

880707-23-5064

Date

04 JULY 2012

iv

DEDICATION

Special dedicated to
My lovely mother, Marlen Binti Agus
My dearest father, Saiful Bahri Bin Mohd
And all my family members and supportive friends
Thanks for your full support

ACKNOWLEDGEMENT

First of all, I would like to express my heartfelt thanks and highly appreciation
to my respected supervisor, Dr Michael Tan Loong Peng for his assistances, invaluable
advices, encouragement, guidance, motivation and comments throughout this thesis.

I also wish to convey my gratefulness to my beloved family for their love and
support to succeed this thesis. Special thanks to all my friends and all whom had helped
and support me in one way or other during my project.

vi

ABSTRACT

Nowadays, memory in one of the most important component in VLSI chip. It is

used wisely in most micro-processor not only to store the data, but also needed to read
and write the data. One type of the memories is called SRAM. In this thesis, a new
method is suggested for simulate of Static Random Access Memory by using the
Predictive Technology Model (PTM) card in HSPICE. This project is carried out to
investigate the performance and the characteristics of the SRAM. The six transistors
SRAM cell is one of the most prevalent circuits in microelectronic design. The 6T
SRAM cell is selected cell to be design in this project due to higher performance of the
cell compared with the other type of cell. The objectives of this study are to design the
SRAM cell by using the HSPICE software in three operations in the 6T SRAM cells
which are in the normal, write and read operation.

The operation time of each operation is observed and compared. The complete
time taken for the read operation is higher than write operation. Static noise margin
(SNM) in the write and read operation are calculated and discussed. SNM during read
simulation are greater than write operation. The smaller the static noise margins values
the better the design. The sizing of each MOSFET are really important in order to drive
the circuit achieved the maximum performance.

vii

ABSTRAK

Pada masa kini, memori di dalamsalah satukomponenyang palingpenting

dalamcipVLSI. Ia digunakansecarabijakdalamkebanyakanpemprosesmikrobukan
sahajauntuk menyimpan data, tetapi jugadiperlukanuntukmembaca dan menulisdata.
Satu jenismemori yangdipanggilSRAM. Dalam kajian ini,satu
kaedahramalanbarumencadangkanuntukmensimulasikanRandomAccessMemoryStatikd
enganmenggunakanModelTeknologiramalan(PTM) kaddalam perisianpekej HSPICE.
Model ramalanadalahproses di manamodeltelah ditubuhkan untukcubauntuk
meramalkebarangkalianmemilihkeputusan. Projek inidijalankan untuk
mengetahuiprestasidanciri-ciri jenis SRAM. EnamtransistorSRAMselmerupakan salah
satudaripadalitaryang paling lazimdalam reka bentukmikroelektronik.
SelSRAM6tdipilihselmenjadirekabentukdalam projek ini
keranaprestasiyanglebihtinggiselberbandingdenganjenislaincel. Objektif kajian
iniadalahuntuk mereka bentukselSRAMdengan menggunakanperisianpekej
HSPICEdalam tigaoperasi disel6TSRAMyangbiasa, menulisdan membacaoperasi.

Masaoperasisetiap operasidi kaji dan dibandingkan. Masayang lengkap

untukoperasimembacaadalahlebih tinggi daripadaoperasi tulis.
Marginbunyistatik(SNM) untuk operasi menulisdan membacadikiradan
dibincangkan.SNMsemasasimulasimembacaadalahlebih besar daripadaoperasi tulis.
Semakin kecilmarginbunyistatik semakin bagus reka bentuksesuatu litar.
SaizsetiapMOSFETbenar-benarpentinguntukmemaculitarmencapaiprestasimaksimum.

viii

TABLE OF CONTENTS

CHAPTER TITLE

PAGE

PAGE TITLE

DECLARATION

ii

DEDICATION

iii

ACKNOWLEDGEMENT

ABSTRACT

vi

ABSTRAK

vii

TABLE OF CONTENTS

viii

LIST OF FIGURES

xi

LIST TABLE

xiii

LIST OF ABBREVIATION

xiv

INTRODUCTION

1.1

Background

1.2

Problem Statement

1.3

Objective

1.4

Scope

ix

LITERATURE REVIEW
2.1

Introduction

2.2

HSPICE

2.3

CosmosScope

2.4

SRAM

2.4.1

Determine Cell (6T)

10

2.4.2

Static Noise Margin (SNM)

14

METHODOLOGY

3.1

Introduction

16

3.2

Flow Chart

17

3.3

Circuit Modelling

18

3.4

Design in HSPICE

19

3.5

Simulation Work in CosmosScope

19

RESULT AND DISCUSSION

4.1

Introduction

20

4.2

Inverter Simulation

21

4.2.2

Normal Operation Simulation

26

4.2.3

Read Operation Simulation

31

4.2.4

Write Operation Simulation

36

CONCLUSIONS AND FUTURE WORK

5.1

Conclusions

41

5.2

Future Work

43

REFERENCES

44

APPENDIX

46

xi

LIST OF FIGURES

FIGURES

TITLE

PAGE

1.1

Previous project of SRAM cell

2.1

HSPICE integrator program

2.2

6T SRAM cell

10

2.3

A six transistor CMOS SRAM cell

12

2.4

SNM for an SRAM cell

14

3.1

Methodology

17

3.2

Structure sizing of transistor

18

3.3

Step of HSPICE design

19

4.1

Description of CMOS inverter

21

4.2

The input waveform of the inverter

23

4.3

The output waveform of the inverter

24

4.4

The input and output waveform of the inverter

25

4.5

6T SRAM cell netlist

26

4.6

SRAM simulation

28

4.7

HSPICE simulation for normal operation

30

4.8

Read modeling structure

31

4.9

Read operation netlist

32

4.10

Simulation in read operation

34

4.11

HSPICE simulation for read operation

35

4.12

Write operation modeling

36

xii

4.13

Write operation netlist

37

4.14

Simulation in write operation

39

4.15

HSPICE simulation for write operation

40

xiii

LIST OF TABLES

TABLE

TITLE

PAGE

4.1

Graph description of normal operation

29

4.2

Transistor sizing

33

xiv

LIST OF ABBREVIATION

CMOS - Complementary Metal Oxide Semiconductor

EDA - Electronic Design Automation
FET Field-Effect Transistor
GUI - Graphical User Interface
IC - Integrated Circuit
MOS Metal-Oxide Semiconductor
MOSFET Metal-Oxide Semiconductor Field-Effect Transistor
NMOS - n-channel Metal-Oxide Semiconductor
PMOS - p-channel Metal-Oxide Semiconductor
VLSI - Very Large Scale Device
SNM Static Noise Margin

CHAPTER 1

INTRODUCTION

This thesis investigates the performance of Static Random Access Memory

(SRAM) in HISPICE simulation. 6T cell of SRAM is designed and the characteristic is
obtained from the CosmosScope. In this chapter, the background of the project, problem
statement, project objectives, scope of work and the organization of the thesis are
presented.

1.1

Background

Predictive Technology Model (PTM) provides accurate, customizable, and

predictive model files are compatible with the standard circuit simulators, such as
SPICE, and scalable with a wide range of process variations. With PTM, competitive
circuit design and research can start even before the advanced semiconductor
technology is fully developed.

SPICE is one of the types of Predictive Technology Model. There is a several

type of SPICE such as TSPICE, PSPICE and the latest type is HSPICE. HSPICE is
faster and has more capabilities than typical SPICE simulators. More time can be saved
and it easy to detect the error if there is the problem in simulation process.

The Static Random Access Memory (SRAM) was created by using the HSPICE
software. The circuits performance of SRAM will be obtained through HSPICE and the
performance of circuit will be analyzed based on the waveform in generate from
CosmosScope.

1.2

Problem Statement

According to this project, some major improvements are made from the previous
project methodology. Initially, the previous projects use the typical SPICE simulator
which is more complicated and need more step and process to finish the project. Start it
from design the schematic in S-Edit, proceed to draw the layout in L-Edit then
compared the net list in T-Spice. The problem will occur if both net lists are not same
and need to recheck the programmed from the start to solve the error.

a) Schematic design
Figure 1.1

b) Layout design
Previous project of SRAM cell

The major advantage by design the cell in HSPICE is faster and efficient
compared to other typical SPICE. The difference is HSPICE is that is no need to place
the schematic symbol onto the layout.

1.3

Objective

There are two objectives in this project. The main objective is to predict the
performance of 16 bit SRAM using Predictive Technology Models (PTM) card. These
predictable models files are compatible with the standard circuit simulators, such as
SPICE. The PTM model 32nm is one of PTM version for sub-45nm bulk CMOS. It is
providing new modeling features of metal gate/high-k, gate leakage, temperature
effect, and body bias.

Secondly, design circuit level modeling of SRAM in HSPICE.Generally the

fewer transistors used the better the design. Cell size accounts for most of array size.
Reduce cell size at expense of complexity. But the 1T and 3T cells are not types of
SRAM but DRAM. 6T cell SRAM had been choose as the cell SRAM in this project.

1.4

Scope of Project

This project consists of two phase; simulation and modeling. To study the
circuit-level modeling of SRAM which use HSPICE to design and simulate the netlist
of 6T cell SRAMand CosmosScope to produce the output waveform to investigate the
characteristic of 6T cell SRAM during the write and read operation. Secondly, study
on the characterization of the static random access memory and lastly, analyzing and
interpreting the data.

CHAPTER 2

LITERATURE REVIEW

This chapter provides the background and reading of the project. These include a
detail description of each device and operation that involved in this project.

2.1

Introduction

The software that will be used in order to simulate the Static Random Access Memory
(SRAM) cell is HSPICE and CosmosScope. The netlists is designed in HSPICE and the
output waveform will be generated by using CosmosScope. The simulation and
investigation focused on 6T SRAM cell. Each bit in an SRAM is stored on four
transistors that form two cross-coupled inverters. This storage cell has two stable states
which are used to denote 0 and 1. Two additional access transistors help controlling
the access to the cross coupled unit formed by the inverters during read and write
operations

7
2.2

HSPICE

Figure 2.1

HSPICE integrator program

HSPICE simulator is one of the products from the HSPICE Integrator Program.
It is able to generate the circuit in steady-state, frequency domains and also in the
transient state. Device reliability simulation and design yield process variability can be
done by using this program.

One of the advantages of the HSPICE is can produce the very useful graphs that
can design the project management and in engineering, which is graphical curves. This
software uses the synopsis which the accurate gold standard for simulate the circuit and
fully support the most accurate and expensive set of industry standard and propriety
simulation model. HSPICE precede the other program on both multicore and single
computers in term of the characterization application speed, extracted larger netlist,
designing 65nm and integrity of signal.

2.3

CosmosScope

CosmosScope program can help HSPICE simulator to generate the output

waveform. This is because CosmmosScope program can support the entire Synopsys
simulator. The data that are received from the other programme can be turn to the useful
information in CosmosScope. The advantages of the CosmosScope are:

a. Measurement capabilities and powerful of analysis.

b. Patented waveform-calculator technology.
c. Scripting language based on the industry standard Tcl/Tk
d. Can analyze the performance and quality of design; uparalleled capability
and flexibility

The result of the statistical circuit can be easy analysing by use CosmosScope
software. The different type of session of multiple output files generated can be simply
open with the help of signal manager.
Synopsys waveform calculator tool allows designers to further analyse
simulation results. With most waveform-analysis products, each session must be started
from scratch, requiring valuable time searching for data files, rearranging windows, and
so forth. CosmosScope, however, allows an entire session to be saved. Arrangements of
windows, complete graphs, calculator contents and macros can be restored from a
previous session to continue work without interruption.

After simulate, any number of graphs complete with annotations, text variables,
and measurements can be saved. Then, in a later session, the graphs can be quickly
restored for modification or for use as the basis for a new graph. CosmosScope also
incorporates graph outlines that let designers apply axis-range labels, annotations, text
variables and measurements to new sets of waveforms; this allows definition of a
standard template for subsequent sets of graphs and measurements.

2.4

SRAM

There is two type of RAM, first is SRAM and second is DRAM. Both of this
RAM is very important in computer system application. SRAM use a static method (as
long as the electric power is supplied to the memory chip, the data will remain constant
and static) in order to stores the data. On the others hand, DRAM use the dynamic
method, which is mean, it is always need to refresh the data stored in the memory.
SRAM is faster and can save the use of power supply compared with DRAM.

The structure of SRAM is more complex compared with DRAM. DRAM is less
expensive to manufacture than SRAM. This reason SRAM is normally used in smaller
application like CPU cache memory and user electronic and DRAM at all time used in
larger application like main memory for personal computers.

The fewer transistors used and the smaller the cell the better the design. Due to
increasing of price of silicon wafer, using the smaller cell can reduce the total cost per
bit of memory. The cell that used less that 3T is calling DRAM. The command cell
used in SRAM is 6T. The structure of 6T SRAM cell is performing by 2 connection
inverter. The four transistors in the center form two cross-coupled inverters. In actual
devices, these transistors are made as small as possible to save chip-area, and are very
weak. Due to the feedback structure, a low input value on the first inverter will generate
a high value on the second inverter, which amplifies (and stores) the low value on the
second inverter. Similarly, a high input value on the first inverter will generate a low
input value on the second inverter, which feeds back the low input value onto the first
inverter. Therefore, the two inverters will store their current logical value, whatever
value that is.

10

2.4.1 Determine Cell (6T)

Figure 2.2 below demonstrates the typical six-transistor cell used for CMOS
static random-access memories (SRAM). The cell consists of two cross-coupled CMOS
inverters that store one bit of information, and two N-type transistors that connect the
cell to the bit lines.

Figure 2.2

6T SRAM cell

The function of the logical gate inverter is to output the opposite of the input.
This can be chained with other logic gates to allow for very complicate logic circuits.
All logical circuits can be constructed out of OR and the invertors. A power inverter, on
the other hand, is a device that can be used to convert DC current to AC. This allows to
run normal appliances (that require AC) off a battery (which delivers DC) or the like
.An inverter is an electrical device that converts direct current (DC) to alternating

11

current (AC); the resulting AC can be at any required voltage and frequency with the
use of appropriate transformers, switching, and control circuits. Inverters are commonly
used to supply AC power from DC sources such as solar panels or batteries.

Static inverters have no moving parts and are used in a wide range of
applications, from small switching power supplies in computers, to large electric utility
high-voltage direct current applications that transport bulk power.

12

Figure 2.3

A six transistor CMOS SRAM cell

There are three operations in SRAM simulation which is standby mode, read
operation mode and write operation mode. If the word line is not asserted, the access
transistors M5 and M6 disconnect the cell from the bit lines. The two cross-coupled
inverters formed by M1 M4 will continue to reinforce each other as long as they are
connected to the supply. This operation is call standby operation.

In the read operation, word line is activated while the external word line driver
is disabled. The value can be determined by external logic if the inverter inside the
SRAM cell drives the bitlines.

In the write operation, in order to drive the bitlines, the big (external) tristate
drivers need to activate first. The previous state of the cross-couple can easily be
override. It is because the internal driver (small transistor used in the 6T SRAM cell) is
much smaller than the external drivers. Next, allowed the wordline transistors. Still,
when shafting the data, the short-circuit will happen for just a few nanoseconds.

13

So typically it takes six transistors to store one memory bit. The design of a
basic SRAM cell is shown in Figure 2.3. Access to the cell is enabled by the word line
(WL) which controls the two access transistors M5 and M6 which allow the access of
the memory cell to the bit lines: BL and BLbar. They are used to transfer data for
both read and write operations. The presence of dual bit lines i.e. BL and BLbar
improves noise margins over a single bit line. The operation of CNFETs based
memories is very similar to that of CMOS except for minor differences in device
orientation. One such difference being that the source and drain terminals of a CNFET
are not interchangeable as is the case with CMOS devices. Care must therefore be taken
to orient the transistors in a memory cell in a manner that will ensure correct
transmission of logic levels.

14

2.4.2 Static Noise Margin (SNM)

Static noise margin (SNM) is the maximum voltage amplitude of external signal
that can be algebraically added to the noise-free worst-case input level without causing
the output voltage to diverge from the allowable logic voltage level. SNM is the most
important parameters of SRAM cell because too compared which cell is better and as
DC disturbance present in logic gates. The concept of SNM for an SRAM cell is shown
the figure below.

Figure 2.4

SNM for an SRAM cell

15

The minimum noise voltage to flip the state of the cell at each of the cell storage
is called SNM. SNM can be obtained by drawing and mirroring the inverter
characteristics (left side and right side inverter of the 6T cell). Next, determine the
maximum square between both inverters.

CHAPTER 3

METHODOLOGY

3.1

Introduction

This chapter discusses the methodology and step that involved in this project.
This project implicates programming simulation and design only. This chapter also
explains the flow of the project step and the software involves in this project.

17

3.2

Flow Chart

Figure 3.1shows the flow chart of this project. The first stage is literature review
on HSPICE and CosmoScope software and SRAM chip in general and 6T cell SRAM
structure in particular. All of the information that collected from the web site, related
books and from my supervisor need to be understood thoroughly.

Literature review on Hspice, CosmosScope and

SRAM

Circuit modelling

Design in Hspice

Simulation in CosmosScope

Figure 3.1

Methodology

18

3.3

Circuit Modeling

There are 3 types of model that need to be design in this project which start from
the normal operation of SRAM cell then followed by the write operation and read
operation. The pull-up PMOS transistors is sized as twice or three-times the widths of
the pull-down NMOS transistors. It is because the mobility of PMOS is less than twice
or three time than the NMOS transistors. The size of both access transistor need to be
greater than the PMOS MOSFET and smaller than the NMOS MOSFET to achieve
higher design performance.

Figure 3.2

Structure sizing of transistor

19

3.4

HSPICE DESIGN

All 6 transistors and Word Line (WL), Bitline (BL) and BLB (BLB) are labeled
correctly. Node Q and QB are label in order to simply the process of design the netlist
in the HSPICE later. There are four processes in this step.

Inverter Netlist
SRAM cell netlist
Write and read operation netlist
Figure 3.3

3.5

Step of HSPICE design

Simulation Work in CosmosScope

Recalling that, HSPICE is used for circuit simulation and CosmosScope is used
to view output waveform. The simulation work of SRAM will be discussed more deeply
in the result and discussion part later. Time analysis and the characteristic of SRAM
will be diagnosed.

CHAPTER 4

RESULT AND DISCUSSION

4.1

Introduction

This chapter discusses the simulation of output waveform generated in

CosmosScope. It is divided into the four parts; inverter simulations, normal simulation,
write operation and read operation

21

4.2

Inverter Simulation

Since the 6T SRAM are formed by combination of two inverter, the

understanding of this project will start with the inverter net list first.

HSPICE is used for circuit simulation and CosmosScope is used to view

output waveform. 6T SRAM cell are form of two combination inverter. Figure
4.1 show the description of CMOS inverter.
.lib tsmc_018nm_model.txt cmos_model
M1 out in vdd vdd pmos L=0.18n W=1.8n
M2 out in 0 0 nmos L=0.18n W=0.9n
Vdd Vdd 0 2.5
Vin in 0 0 pulaw 0 2.5 200p 200p 200p 5n 10n
Cload out 0 20f
.options post
.tran 200p 20n
.print tran v(in) v (out)
.end

Figure 4.1

Description of CMOS inverter

The first line of the SPICE file is always a comment line. Therefore any
statements on this line will be ignored. The .lib line includes the model file
32n.txt, which is assumed to be in the current running directory. The next two
lines are a PMOS and an NMOS transistor, respectively. After the transistor
name (which must begin with m), the source, gate, drain, and bulk nodes are
given.

22

Next is the model. The length and width are specified. The process is a
0.18um process, so 0.18um is the minimum gate length. Source and drain
perimeters and areas can also be specified here. The two supply nets are defined
next.

A pulse voltage source is defined from 0 to 2.5 V with 100ps delay,

100ps rise time, 100ps fall time, 2n pulse width, and 4ns repetition period. A
capacitor of 20fF from node out to node 0 is given on the next line. .options post
instructs HSPICE to write an output file ending in .tr0 containing the simulation
waveforms. .tran indicates a transient analysis with a plot interval of 200ps and
simulation duration of 20ns. .print specifies the nodes to be printed to the .out
file. .end signifies the end of the SPICE stack. This command runs HSPICE on
this file: hspiceinv.cir>inv.out.

23

Several files are created by HSPICE: inv.ic: Text file containing the
circuit initial conditions inv.st0: Text files containing a summary of the
simulation inv.tr0: Binary files containing transient analysis waveforms.

Figure 4.2

Theinput waveform of the inverter

24

After the simulation, the waveforms can be viewed using CosmosScope.

A signal manager window and the Plot File window will open up. In the Plot
Filewindow, plot v(in) by double clicking v(in), or by selecting v(in) and
clicking Plot. Theinput waveform of the inverter will open up. Then, plot v(out),
the same way as plotted v(in). This will open another graph with v(out).

Figure 4.3

Theoutput waveform of the inverter

25

Then compare the input and ouput on the same graph, simply click and
drag the title v(out) from the top graph to the bottom graph where v(in) is
plotted.

Figure 4.4

The input and output waveform of the inverter

26

4.3

Normal Simulation

As mentioned before, by depending on the transistor label and node name in

Figure 3.2, the netlist of SRAM will be designed in HSPICE.
SRAM cell 6T
.lib "32n.txt" cmos_models
*source
**supply
vdd 4 0 dc 2
**access control
vwl wl 0 pulse(0 4 100u 100u 2m 8m)
**data
vbl bl1 0 dc 1
vblr blr1 0 pulse(0 1 5m 100u 100u 15m 1)
**control
vr_w r_w 0 pulse(0 1 0 1u 1u 10m 1)
*devices
**switches
GBL BL1 BL VCR PWL(1) r_w,0 0,1e20 1m,1e-20
GBLR BLR1 BLR VCR PWL(1) r_w,0 0,1e20 1m,1e-20
**mos transistors - latch
m1 Q QR 0 0 nmos W=88n L=22n
m2 Q QR 1 1 pmos W=33n L=33n
m3 QR Q 0 0 nmos W=88n L=22n
m4 QR Q 1 1 pmos W=33n L=33n
**mos transistors - data access
m5 BL wl Q 1 nmos W=44n L=22n
m6 BLR wl QR 1 nmos W=44n L=22n
*analysis
.tran 1u 45m 0
.option post
.end

Figure 4.5

6T SRAM cell netlist

27

As explained in the inverter simulation, the first line of the SPICE file is
always a comment line. Therefore any statements on this line will be ignored.
The .lib line includes the model file 32n.txt, which is assumed to be in the
current running directory. As a access controller, a pulse of wordline (WL)
source is defined from 0 to 4 V with 100 micro second rise time, 100 micro
second fall time, 2ms pulse width, and 8ms repetition period. As a data
controller, pulse voltage of bitline (BL) source is defined from 0 to 1 V with
5ms delay, 100 micro second rise time, 100 micro second fall time, 15m pulse
width, and 1 repetition period. . As a controller, a write pulse voltage source is
defined from 0 to 1 V with 0s delay, 100 micro second rise time, 1 micro second
fall time, 10ms pulse width, and 1 repetition period.

The command .options post instructs HSPICE to write an output file

ending in .tr0 containing the simulation waveforms. .tran indicates a transient
analysis with a plot interval of 1micro second and simulation duration of 45 ms.
.end signifies the end of the SPICE stack. This command runs HSPICE on this
file: hspiceinv.cir>inv.out

28

Figure 4.6

SRAM simulation

29

The Figure 4.1 shows the simulation of SRAM 6T cell. From the Figure 2.2 the
output voltage at node Q is depending on WL and BL input. Once the WL and BL are
supply with input and voltage at node Q will start to increase, otherwise it will remain
zero. On the other hand, the output voltage at node QB is depending on WL and BLB.
WL control both side of inverter.

Table 4.1

Graph description

V (WL)

Worldline voltage

V(r_w)

Write voltage

V(qr)

Voltage at node QR

V(q)

Voltage at node Q

V(bl)

Bitline voltage

V(blr)

Bitline Bar voltage

I(vr_w)

Write current

i(vdd)

Voltage supply current

i(vblr)

Bitline bar current

i(vbl)

Bitline current

30

Figure 4.7

HSPICE simulation

Figure 4.6 show the total MOSFET used is six; two PMOS MOSFET and four
NMOS MOSFET. The transient time is 0.10 second and the circuit took 0.20 seconds to
complete the simulation. This figure will only show when there is no error occur during
the simulation

31

4.4

Read Operation Simulation

The wordline (WL) and bitlines (BL) are held at VDDduring read operation.
Figure 4.8 shows how to extract the read static noise margin (SNM) of the cell.

Figure 4.8 Read modeling structure

First, the feedback from the cross coupled inverters is broken. Next, the voltage
of the inverter formed by half of the SRAM cell is found by sweeping Q (the inverters
input) from 0 to VDD and measuring QB (the inverters output). This plot is then used to
construct the butterfly plot that is representative of the two halves of the cell driving
each other. The read SNM is the side length of the maximum possible square that can fit
inside of the butterfly plot.

32

SRAM cell read 6T

*6Transistor SRAM
.TEMP 25.0000
.lib "32n.txt" cmos_models
.PARAM VDD= 0.95
.PARAM VNOISE = 0.66
.PARAM BITCAP = 1e-12
.OPTION POST
CBL BLB 0 BITCAP
CBLB BL 0 BITCAP
*one inverter
MPL Q QBN VDD! VDD! pmos L=33n W=33n
MNL Q QBN 0 0 nmos L=22n W=88n
*one inverter
MPR QB QN VDD! VDD! pmos L=33n W=33n
MNR QB QN 0 0 nmos L=22n W=88n
*access transistor
MNAL BLB WL QB 0 nmos L=22n W=44n
MNAR BL WL Q 0 nmos L=22n W=44n
VVDD! VDD!0 DC=VDD
VWL WL 0 DC=VDD
VNOISEL QBN QB DC=VNOISE
VNOISER Q QN DC=VNOISE
*logic 1 is stored in the cell initially
.IC V(Q)=VDD
.IC V(QB)=0
*writing logic 0 in cell
.IC V(BL)=VDD
.IC V(BLB)=VDD
.TRAN 0.1n 30n
.PRINT TRAN V(QB) V(Q) V(BLB) V(BL)
.END

Figure 4.9

Read operation netlist

The VDD supply was set to 0.95 V. The HSPICE simulator will give error if the
voltage is less than 0.25 V. It is happen because, the supply voltage need to be higher
than threshold voltage. Set the input for V(Q)= VDD and V(QB)=0 to store the logic 1
in the cell initially. Write the logic 0 in the cell by set the V(BL)= VDD and V(BLB)=
VDD .

33

Voltage VNOISE is used to control the cell flipping of the output. It can be set
into any required number and did some investigation, VNOISE= 0.66 volt is the value
for this simulation project. Broken up the cell inside the 6T SRAM into the two parts.
Each part acts as inverter. Length of transistor is set as Figure 3.2.

Table 4.2

Transistor sizing
Length(L)

Weight(W)

Pull-up

33n

33n

Pull-down

22n

88n

Pass gate

22n

44n

34

Figure 4.10
A. SNM in read operation

Simulation in read operation

B. Simulation in the right inverter.

C. Simulation in the left inverter

During the read operation, when QB reaches the threshold voltage of the
NMOS, M3, the voltage at node Q starts to fall and the regenerative action of the crosscoupled inverter will force the flipping on the bit in the cell. To prevent the read
operation failure the values of M5 should be strong enough to make sure the stability of
the operation can be achieved. The SNM value of the write operation is 0.1016V. The
total time to complete this operation is 0.22s

35

Figure 4.11

HSPICE simulation

Since, Figure 4.11shows the total MOSFET used in read simulation is six, it
means there is no missing transistor in this simulation. The HSPICE simulation
calculates it correct and no error occur. The transient time is 0.08 second and the circuit
took 0.22 seconds to complete the simulation.

36

4.5

Write Operation Simulation

During a write operation, VDD is applied to the wordline and the value to be
written into the memory cell is driven onto the bitlines. Thus, Figure 3.4 illustrates how
to extract the write static noise margin (SNM). Again, feedback from the cross-coupled
inverters is broken and the voltage of the inverter is measured. Note however that in this
case, the voltages of the two halves of the SRAM are no longer the same (since one the
bitlines is driven to 0V, and the other to VDD). These voltages are used to create a
butterfly plot, and write SNM is the side length of the largest that can fit inside of the
butterfly plot.

Figure 4.12Write operation modeling

37
*6Transistor SRAM
.TEMP 25.0000
.lib "32n.txt" cmos_models
.GLOBAL VDD!
.PARAM VDD = 0.95
.PARAM VNOISE = 0.66
.PARAM BITCAP = 1e-12
.OPTION POST
CBL BLB 0 BITCAP
CBLB BL 0 BITCAP
*one inverter
MPL Q QBN VDD! VDD! pmos L=32n W=32n
MNL Q QBN 0 0 nmos L=56n W=32n
*one inverter
MPR QB QN VDD! VDD! pmos L=32n W=32n
MNR QB QN 0 0 nmos L=56n W=32n
*access transistor
MNAL BLB WL QB 0 nmos L=38n W=37n
MNAR BL WL Q 0 nmos L=38n W=37n
VVDD! VDD!0 DC=VDD
VWL WL 0 DC=VDD
VNOISEL QBN QB DC=VNOISE
VNOISER Q QN DC=VNOISE
*logic 1 is stored in the cell initially
.IC V(Q)=VDD
.IC V(QB)=0
*writing logic 0 in cell
.IC V(BL)=0
.IC V(BLB)=VDD
.TRAN 0.1n 30n UIC
.PRINT TRAN V(QB) V(Q) V(BLB) V(BL)
.END

Figure 4.13

Write Operation netlist

38

Same as read operation, the VDD supply in write operation was set to 0.95 V.
The HSPICE simulator will give error if supply voltage is less than threshold voltage.
Set the input for V(Q)= VDD and V(QB)=0 to store the logic 1 in the cell initially.
Supply the logic 0 to the bitline voltage by set the V(BL)= 0. Then give the value 1
to the beltline bar, V(BLB)= VDD. The others values are same with the read operation.
Sizing of each transistor are set as table 4.1.

39

Figure 4.14

Simulation in write operation

A. SNM in the write operation

B. Simulation in the right inverter.

C. Simulation in the left inverter

During the write operation, write Q=0 while Q= VDD. When the voltage at node
Q reaches a voltage so that the PMOS, M2, gets on, the voltage at note QB starts to rise
and the regenerative action of the cross-coupled inverter will force the write Q=0. To
prevent the write operation failure the values of M6 should be strong enough to make
sure the stability of the operation can be achieved. The SNM value of the write
operation is 0.051792V. The total time to complete this operation is 0.09s

40

Figure 4.15 HSPICE simulation

Same as read operation, since, Figure 4.15shows the total MOSFET used in read
simulation is six; it means there is no missing transistor in this simulation. The HSPICE
simulation calculates it correct and no error occur. The transient time is 0.05 second and
the circuit took 0.09 seconds to complete the simulation.

CHAPTER 5

CONCLUSIONS AND FUTURE WORK

5.1

Conclusions

As a conclusion, this PTM model which is using HSPICE software and

produced the output in CosmosScope is more efficient compare to typical Spice. The
circuit performance of SRAM will be obtained through HSPICE software simulation
using PTM. The performance of each devices and circuit will be analysed based on the
waveform in generated from CosmosScope such as a Static Noise Margin (SNM). Static
noise margin is the DC disturbance present in logic gates. It is the most important
parameters of an SRAM cell. Can be determines by nesting the largest possible square
in the 2 voltage transfer curve of the CMOS inverters. The SNM defines as the sidelength of the square, given in volts. The SNM are determined to compared the which
operation is better. It is importance to use the exact transistor size in order to make sure
that the cell working and running with the maximum performance. The prediction
model is almost same, but not accurate due to the problem of finding the exact values of
transistor used.

42

The SNM values of the read operation were higher than write operation. The
read static-noise-margin (SNM) deteriorates with decrease in supply voltage (VDD) and
increases with the transistor mismatch. This mismatch happens due to variations in
physical quantities of identically designed devices i.e., their threshold voltages, body
factor and current factor. Though SNM decreases at low VDD the overall SRAM delay
increases and moreover the read operation at low VDD leads to storage data destruction
in SRAM cells. The main operations of the SRAM cell are the write, read and hold. The
static noise margin is certainly more important at hold and read operations. Specifically
in read operation when the wordline is 1 and the bitlines are precharged to 1. The
internal node of SRAM which stores 0 will be pulled up through the access transistor
across the access transistor and the driver transistor. This increase in voltage severely
degrades the SNM during read operation. The SNM deteriorates with the decrease in
supply voltage, at low VDD the read and write operations cannot perform properly. The
complete time for write operation is greater than the read operation because during read
operation, the cell need to wait the input from the outside to start operate, but in the
write operation the input is already store in the cell.

43

5.2

Future work

Regarding of the limited scope of this project, it is possible to chase all

requirement to a final better conclusion. To improve the project, the following
suggestion should be carried out.

a. The used of voltage VNOISE is to control and check the output cell flipping.
In order to get the exact values of VNOISE, graphical technique can be used.
The polarity of the noise voltage sources at the input of each inverter. It
depends on the logic values of the bit stored in the cell.

b. The cell ration (ratio of the widths of pull-down NMOS and access
transistor) for read and pull-up ratio (ratio of the width of pull-up PMOS and
access transistor) for write can be determine first in order the get the exact
value of transistors by using hand calculation.

44

REFERENCES

[1] http://www.ee.vt.edu/~ha/cadtools/hsp ice/hspice.html,HSPICE and

CosmosScope tutorial
[2] HSPICE RF Tutorial, Version X, 2005
[3] L. Chang et al, Stable SRAM Cell Design for the 32nm Node and Beyond,
Symp.VLSI Tech, Dig, pp. 292-293, Jun, 2005.
[4] Neil H. Weste, David Harris,"CMOS VLSI Design,"

3rd edition, Chapter 11,

Addison Wesley 2005

[5] K. Takeda et al, A Read-Static-Noise-Margin-Free SRAM Cell for Low-Vdd and
High-Speed Application, IEEE JSSC, pp, 113-121, Jan 2006.
[6]E. Seevinck et al Static-Noise Margin Analysis of MOS SRAM Cells, IEEE
JSSC, pp 748-754, Oct 1987.
[7]Mo Maggie Zhang, Performance Comparison of SRAM Cells Implemented in 6,7,
and 8-Transistor Cell Topologies, IEEE, 2000
[8] W.Zhao and Y.Cao, New Generation of Predictive Technology Model for Sub45nm Early Design Exploration (Journal), IEEE Transaction on Electron Devices,
Nov. 2006- 11: Vol.50
[9]http://en.wikipedia.org/wifi/SRAM
[10] Yasuhiro Marita, HidehiroFujiwira, Hiroki Noguchi, Yusuke Iguchi, Koji Nii,
Hirochi Kawaguchi, Masahiko Yoshimoto. Area comparison between 6T and 8T
SRAM Cells in Dual-Vdd Scheme and DVS Scheme, Trans. Fundamentaos,
Vol.E90-A, No12 December 2007
[11] S. R. Nassif, Modeling and analysis of manufacturing variations, in Proceedings
of the IEEEConference on Custom Integrated Circuits, pp. 223228, 2001.

45

[12] M. Orshansky, S. Nassif, and D. Boning, Design for manufacturability and

statistical design. Springer Publications, P.O.Box 17, 3300 AA Dordrecht, The
Netherlands, 2007.
[13]. S. Nassif, Delay variability: sources, impacts and trends, in Proceedings of the
IEEE International Solid-State Circuits Conference, pp. 368 369, 2000.
[14] E. Grossar, M. Stucchi and K. Maex, Read Stability and Write-Ability Analysis of
SRAM Cells for Nanometer Technologies, IEEE Journal of Solid-State Circuits,
41(11) (2006), pp. 2577-2588.
[15] S. Verhaegen, S. Cosemans, M. Dusa, P. Marchal, A. Nackaerts, G. Vandenberghe
andW. Dehaene, Litho Variations and Their Impact on the Electrical Yield of a
32nm Node 6T SRAM Cell, Proc. SPIE Design for Manufacturabilitythrough
Design-Process Integration II, 6925 (2008), pp. 69250R-169250R-12.
[16] J. Wang and A. K. Wong, Effects of Grid-Placed Contacts on Circuit
Performance, Proc. SPIE Cost and Performancein Integrated Circuit Creation,
5043 (2003), pp. 134-141.
[17]L. Chang et al., Stable SRAM Cell Design for the 32nm Node and Beyond,
Symp. VLSI Tech. Dig., pp. 292-293, Jun., 2005.
[18] K. Takeda et al., A Read-Static-Noise-Margin-Free SRAM Cell for Low-Vdd and
High-Speed Applications, IEEE JSSC, pp. 113-121, Jan., 2006.
[18] E. Seevinck et al., Static-Noise Margin Analysis of MOS SRAM Cells, IEEE
JSSC, pp.748-754, Oct.1987.
[19] J. Wang, A. K. Wong and E. Y. Lama, Standard Cell Design with RegularlyPlaced Contacts and Gates, Proc.SPIE Design and Process Integration for
Microelectronic Manufacturing, 5379 (2005), pp. 56-66.
[20] A. Bhavnagarwala, et al., A Transregional CMOS SRAM with Single, Logic
VDD and Dynamic Power Rails, Symp.on VLSI Circuits, 2004.
[21] H. Qin, et al., SRAM Leakage Supressiong by Minimizing Standby Supply
Voltage, ISQED, 2004.
[22] K. Takeuchi, R. Koh, and T. Mogami, "A Study of the Threshold Voltage
Variation for Ultra-Small Bulk andSOI CMOS," IEEE Transactions on Electron
Devices, Vol. 48, No. 9, September 2001

46

APPENDIX

32 PTM Model

* PTM 32nm Metal Gate / High-K

.lib cmos_models
.model nmos nmos level = 54
+version = 4.0
+capmod = 2
+diomod = 1
+permod = 1

binunit = 1
igcmod = 1
rdsmod = 0
acnqsmod= 0

paramchk= 1
igbmod = 1
rbodymod= 1
trnqsmod= 0

mobmod = 0
geomod = 1
rgatemod= 1

+tnom = 27
toxe = 7.5e-010
toxp = 5e-010
toxm = 7.5e-010
+dtox = 2.5e-010
epsrox = 3.9
wint = 5e-009
lint = 1.95e-009
+ll
=0
wl = 0
lln = 1
wln = 1
+lw
=0
ww
=0
lwn = 1
wwn = 1
+lwl = 0
wwl = 0
xpart = 0
toxref = 7.5e-010
xl
= -14e-9
+dlcig = 1.95e-009
+vth0 = 0.3558
k1
= 0.2
k2 = 0
k3 = 0
+k3b = 0
w0 = 2.5e-006
dvt0 = 1
dvt1 = 2
+dvt2 = 0
dvt0w = 0
dvt1w = 0
dvt2w = 0
+dsub = 0.078
minv = 0.05
voffl = 0
dvtp0 = 1e-011
+dvtp1 = 0.1
lpe0 = 0
lpeb = 0
xj = 1e-008
+ngate = 1e+023
ndep = 8.7e+018
nsd = 2e+020
phin = 0
+cdsc = 0
cdscb = 0
cdscd = 0
cit = 0
+voff = -0.13
nfactor = 2.1
eta0 = 0.005
etab = 0
+vfb = -1.058
u0 = 0.0238
ua = -5e-010
ub = 1.7e-018
+uc
=0
vsat = 182130
a0 = 1
ags = 0
+a1
=0
a2 = 1
b0
=0
b1
=0
+keta = 0.04
dwg = 0
dwb = 0
pclm = 0.06
+pdiblc1 = 0.001
pdiblc2 = 0.001
pdiblcb = -0.005
drout = 0.5
+pvag = 1e-020
delta = 0.01
pscbe1 = 2.0e+009
pscbe2 = 1e-007
+fprout = 0.2
pdits = 0.01
pditsd = 0.23
pditsl = 2300000
+rsh = 5
rdsw = 80
rsw = 40
rdw = 40
+rdswmin = 0
rdwmin = 0
rswmin = 0
prwg = 0
+prwb = 0
wr
=1
alpha0 = 0.074
alpha1 = 0.005
+beta0 = 30
agidl = 0.0002
bgidl = 2.1e+009
cgidl = 0.0002

47

+egidl = 0.8
+nigbacc = 1
+eigbinv = 1.1
+cigc = 0.002
+nigc = 1
+xrcrg1 = 12

aigbacc = 0.012
bigbacc = 0.0028
cigbacc = 0.002
aigbinv = 0.014
bigbinv = 0.004
cigbinv = 0.004
nigbinv = 3
aigc = 0.020014
bigc = 0.0027432
aigsd = 0.020014
bigsd = 0.0027432
cigsd = 0.002
poxedge = 1
pigcd = 1
ntox = 1
xrcrg2 = 5

+cgso = 9e-011
+cgsl = 7.5e-013
+ckappas = 0.6
+moin = 15

cgdo = 9e-011
cgbo = 0
clc = 1e-007
cle = 0.6
ckappad = 0.6
vfbcv = -1
noff = 1
voffcv = 0

cgdl = 7.5e-013
cf = 1.1e-010
acde = 1

+kt1 = -0.154
+ua1 = 1e-009
+at
= 33000

kt1l = 0
kt2 = 0.022
ute
ub1 = -1e-018
uc1 = -5.6e-011

= -1.1
prt = 0

+fnoimod = 1
tnoimod = 0
noia = 6.25e+041
noib =
3.125e+026
+noic = 8.75e+009
em
= 41000000
af
=1
ef
=1
+kf
=0
tnoia = 1.5
tnoib = 3.5
ntnoi = 1
+jss = 1.2e-006
jsws = 2.4e-013
jswgs = 2.4e-013
njs = 1
+ijthsfwd= 0.1
ijthsrev= 0.1
bvs = 10
xjbvs = 1
+jsd = 1.2e-006
jswd = 2.4e-013
jswgd = 2.4e-013
xjbvd = 1
+pbs = 1
cjs = 0.0018
mjs = 0.5
pbsws = 1
+cjsws = 1.2e-010
mjsws = 0.33
cjswgs = 2.1e-010
cjd = 0.0018
+cjswd = 1.2e-010
mjswd = 0.33
pbswgd = 1
cjswgd = 2.1e-010
+mjswgd = 0.33
tpb = 0
tcj = 0
tpbsw = 0
+tcjsw = 0
tpbswg = 0
tcjswg = 0
xtis = 3
+dmcg = 0
+dwj = 0

dmci = 0
xgw = 0

+rshg
+rbps

gbmin = 1e-010
rbdb = 15

= 0.4
= 15

dmdg = 0
xgl = 0
rbpb = 5
rbsb = 15

dmcgt = 0

rbpd = 15
ngcon = 1

.model pmos pmos level = 54

+version = 4.0
+capmod = 2
+diomod = 1
+permod = 1

binunit = 1
igcmod = 1
rdsmod = 0
acnqsmod= 0

+tnom = 27
toxe = 7.7e-010
+dtox = 2.7e-010
epsrox = 3.9
+ll
=0
wl = 0
lln

paramchk= 1
igbmod = 1
rbodymod= 1
trnqsmod= 0

mobmod = 0
geomod = 1
rgatemod= 1

toxp = 5e-010
toxm = 7.7e-010
wint = 5e-009
lint = 1.95e-009
=1
wln = 1

48

+lw
=0
ww
+lwl = 0
wwl
= -14e-9
+dlcig = 1.95e-009
+vth0 = -0.24123
+k3b = 0
+dvt2 = -0.032
+dsub = 0.1
+dvtp1 = 0.05
+ngate = 1e+023
+cdsc = 0
+voff = -0.13
+vfb = -1.058
+uc
=0
+a1
=0
+keta = -0.047
+pdiblc1 = 0.001
+pvag = 1e-020
007
+fprout = 0.2
+rsh = 5
+rdswmin = 0
+prwb = 0
+beta0 = 30
+egidl = 0.8
+nigbacc = 1
+eigbinv = 1.1
+cigc = 0.0008
+nigc = 1
+xrcrg1 = 12

=0
=0

lwn = 1
xpart = 0

wwn = 1
toxref = 7.7e-010

xl

k1 = 0.2
k2 = -0.01
k3 = 0
w0 = 2.5e-006
dvt0 = 1
dvt1 = 2
dvt0w = 0
dvt1w = 0
dvt2w = 0
minv = 0.05
voffl = 0
dvtp0 = 1e-011
lpe0 = 0
lpeb = 0
xj = 1.008e-008
ndep = 3.5e+018
nsd = 2e+020
phin = 0
cdscb = 0
cdscd = 0
cit = 0
nfactor = 2.1
eta0 = 0.0042
etab = 0
u0 = 0.00306
ua = -5e-010
ub = 1.6e-018
vsat = 78000
a0 = 1
ags = 1e-020
a2 = 1
b0
=0
b1
=0
dwg = 0
dwb = 0
pclm = 0.1
pdiblc2 = 0.001
pdiblcb = 3.4e-008
drout = 0.6
delta = 0.01
pscbe1 = 2e+009
pscbe2 = 9.58epdits = 0.08
pditsd = 0.23
pditsl = 2300000
rdsw = 80
rsw = 40
rdw = 40
rdwmin = 0
rswmin = 0
prwg = 0
wr
=1
alpha0 = 0.074
alpha1 = 0.005
agidl = 0.0002
bgidl = 2.1e+009
cgidl = 0.0002
aigbacc = 0.012
bigbacc = 0.0028
cigbacc = 0.002
aigbinv = 0.014
bigbinv = 0.004
cigbinv = 0.004
nigbinv = 3
aigc = 0.011942
bigc = 0.0012217
aigsd = 0.011942
bigsd = 0.0012217
cigsd = 0.0008
poxedge = 1
pigcd = 1
ntox = 1
xrcrg2 = 5

+cgso = 9e-011
+cgsl = 3e-011
+ckappas = 0.6
+moin = 15

cgdo = 9e-011
cgbo = 0
clc = 1e-007
cle = 0.6
ckappad = 0.6
vfbcv = -1
noff = 1
voffcv = 0

+kt1 = -0.14
+ua1 = 1e-009
+at
= 33000

kt1l = 0
kt2 = 0.022
ute
ub1 = -1e-018
uc1 = -5.6e-011

cf

cgdl = 3e-011
= 1.1e-010
acde = 1

= -1.1
prt = 0

+fnoimod = 1
tnoimod = 0
noia = 6.25e+041
noib =
3.125e+026
+noic = 8.75e+009
em = 41000000
af
=1
ef
=1
+kf
=0
tnoia = 1.5
tnoib = 3.5
ntnoi = 1

49

+jss = 2e-007
jsws = 4e-013
jswgs = 4e-013
njs = 1
+ijthsfwd= 0.1
ijthsrev= 0.1
bvs = 10
xjbvs = 1
+jsd = 2e-007
jswd = 4e-013
jswgd = 4e-013
xjbvd = 1
+pbs = 1
cjs = 0.0015
mjs = 0.5
pbsws = 1
+cjsws = 9.4e-011
mjsws = 0.33
cjswgs = 2e-010
cjd = 0.0015
+cjswd = 9.4e-011
mjswd = 0.33
pbswgd = 1
cjswgd = 2e-010
+mjswgd = 0.33
tpb = 0
tcj = 0
tpbsw = 0
+tcjsw = 0
tpbswg = 0
tcjswg = 0
xtis = 3
+dmcg = 0
+xgl = 0

dmdg

+rshg
+rbps

gbmin = 1e-012
rbdb = 50

= 0.1
= 50

=0

dmcgt = 0

rbpb = 50
rbsb = 50

xgw

=0

rbpd = 50
ngcon = 1