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( DOC No.

HX8352-C(T)-DS )

HX8352-C(T)
240RGB x 432 dot, 262K color,
with internal GRAM,
TFT Mobile Single Chip Driver
Temporary version 01 April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents

April, 2010

1.

General Description ................................................................................................................................ 10

2.

Features ...................................................................................................................................................11
2.1
2.2
2.3
2.4
2.5

3.

Device Overview ..................................................................................................................................... 13


3.1
3.2
3.3
3.4
3.5

4.

Display.............................................................................................................................................11
Display module................................................................................................................................11
Display / Control interface .............................................................................................................. 12
Input power..................................................................................................................................... 12
Miscellaneous................................................................................................................................. 12

Block diagram................................................................................................................................. 13
Pin description................................................................................................................................ 14
Pin assignment............................................................................................................................... 16
PAD coordinates............................................................................................................................. 17
Bump arrangement......................................................................................................................... 25

Interface .................................................................................................................................................. 26
4.1
System interface............................................................................................................................. 26
4.1.1 8080 System interface ............................................................................................................... 28
4.1.2 I80 8-bit Parallel Bus System Interface...................................................................................... 29
4.1.3 I80 9-bit Parallel Bus System Interface...................................................................................... 31
4.1.4 I80 16-bit Parallel Bus System Interface.................................................................................... 32
4.1.5 I80 18-bit Parallel Bus System Interface.................................................................................... 37
4.2
Serial Data Transfer Interface ........................................................................................................ 41
4.2.1 3-wire serial interface................................................................................................................. 41
4.2.2 4-wire serial interface................................................................................................................. 44
4.3
RGB interface................................................................................................................................. 45
4.3.1 RGB Interface Data Color Coding.............................................................................................. 47

5.

Function Description ............................................................................................................................... 50


5.1
Display data GRAM........................................................................................................................ 50
5.1.1 Address counter (AC) ................................................................................................................ 50
5.1.2 Source, gate and memory map.................................................................................................. 51
5.1.3 MCU to memory write / read direction ....................................................................................... 52
5.1.4 Fully display, partial display, vertical scrolling display................................................................ 54
5.2
Tearing Effect Output Line.............................................................................................................. 59
5.2.1 Tearing Effect Line Modes ......................................................................................................... 59
5.2.2 Tearing Effect Line Timing.......................................................................................................... 61
5.3
Oscillator......................................................................................................................................... 64
5.4
Source driver .................................................................................................................................. 65
5.5
Gate Driver ..................................................................................................................................... 66
5.6
Power generation ........................................................................................................................... 67
5.6.1 LCD power generation scheme ................................................................................................. 67
5.6.2 Power supply circuit ................................................................................................................... 68
5.7
Gamma characteristic correction function...................................................................................... 70
5.7.1 Gray Voltage Generator for Source Driver................................................................................. 71
5.7.2 Gray Voltage Generator for Digital Gamma Correction ............................................................. 82
5.8
Characteristics of I/O...................................................................................................................... 84
5.8.1 Output or bi-directional (I/O) pins............................................................................................... 84
5.8.2 Input pins.................................................................................................................................... 84
5.9
Power on/off sequence................................................................................................................... 85
5.9.1 Case 1: NRESET line is held high or unstable by host at power on.......................................... 86
5.9.2 Case 2: NRESET line is held low by host at power on .............................................................. 87
5.10
Uncontrolled power off ................................................................................................................... 88

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.2April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents

April, 2010

5.11
Power On/Off Sequence ................................................................................................................ 89
5.12
Content adaptive brightness control (CABC) function ................................................................... 92
5.12.1
Module architectures ............................................................................................................. 93
5.12.2
CABC block ........................................................................................................................... 94
5.12.3
Brightness control block ........................................................................................................ 95
5.12.4
Minimum brightness setting of CABC function ...................................................................... 96
5.13
OTP programing ............................................................................................................................. 97
5.13.1
OTP table............................................................................................................................... 97
5.13.2
OTP programming flow.......................................................................................................... 99
5.13.3
Programming sequence ...................................................................................................... 100
6.

Command.............................................................................................................................................. 101
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
6.16
6.17
6.18
6.19
6.20
6.21
6.22
6.23
6.24
6.25
6.26
6.27
6.28
6.29
6.30
6.31
6.32
6.33
6.34
6.35
6.36
6.37
6.38
6.39
6.40
6.41
6.42
6.43

Command list ............................................................................................................................... 101


Index register................................................................................................................................ 106
Himax ID register (PAGE0 -R00h)................................................................................................ 106
Display mode control register (PAGE0 -01h) ............................................................................... 106
Column address start register (PAGE0 -02~03h) ........................................................................ 107
Column address end register (PAGE0 -04~05h) ......................................................................... 107
Row address start register (PAGE0 -06~07h).............................................................................. 108
Row address end register (PAGE0 -08~09h)............................................................................... 108
Partial Area Start Row Register (PAGE0 -0A~0Bh) ..................................................................... 109
Partial Area End Row Register (PAGE0 -0C~0Dh)...................................................................... 109
Vertical scroll top fixed area register (PAGE0 -0E~0Fh) ............................................................... 111
Vertical scroll height area register (PAGE0 -10~11h).................................................................... 111
Vertical scroll button fixed area register (PAGE0 -12~13h)........................................................... 111
Vertical scroll start address register (PAGE0 -14~15h).................................................................112
Memory access control register (PAGE0 -16h).............................................................................114
COLMOD control register (PAGE0 -17h) ......................................................................................114
OSC control register (PAGE0 -18h & R19h) .................................................................................116
Power control 1 register (PAGE0 -1Ah) ........................................................................................117
Power control 2 register (PAGE0 -1Bh) ........................................................................................118
Power control 3 register (PAGE0 -1Ch) ........................................................................................119
Power control 5 register (PAGE0 -1Fh)........................................................................................ 120
Read data register (PAGE0 -22h) ................................................................................................ 121
VCOM control 1~3 register (PAGE0 -23~25h) ............................................................................. 122
Display control 1~7 register (PAGE0 -26h~2Ch) ......................................................................... 124
Cycle control 1~2 register (PAGE0 -2Dh~2Eh)............................................................................ 127
RGB interface control 1~4 register (PAGE0 -31h~34h) ............................................................... 128
Panel characteristic control register (PAGE0 -36h)...................................................................... 130
OTP control 1~5 register (PAGE0 -38h ~ 3Bh, 87h) .................................................................... 131
CABC control 1~4 register (PAGE0 -3Ch~3Fh) ........................................................................... 132
Gamma control 1~15 register (PAGE0 -40h~4Eh)....................................................................... 134
TE control register (PAGE0 -60h, 84h~85h) ................................................................................ 137
ID register (PAGE0 -61h~63h) ..................................................................................................... 138
Memory write control register (PAGE0 -68h) ............................................................................... 138
TE interval control register (PAGE0 -69h) .................................................................................... 139
RGB SRAM cycle control register (PAGE0 -6Ah) ........................................................................ 139
Data format control register (PAGE0 -6Bh) .................................................................................. 140
Frame rate control 1~8 register (PAGE0 -70h~77h) .................................................................... 141
Power control 6~11 register (PAGE0 -7Ah~7Fh) ......................................................................... 144
VPP voltage control register (PAGE0 -86h) ................................................................................. 146
Get scan line 1~2 register (PAGE0 -88h~89h)............................................................................. 146
Read VCOM OTP times register (PAGE0 -R8Ah) ....................................................................... 147
Read ID OTP times register (PAGE0 -R8Bh)............................................................................... 147
Command page select register (RFFh)........................................................................................ 148

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.3April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Contents
6.44
6.45
6.46
7.

April, 2010

DGC control register (PAGE1 -00h) ............................................................................................. 149


DGC LUT register (PAGE1 -01h~63h) ......................................................................................... 149
CABC control 5 & 7 register (PAGE1 C3h, C5h)........................................................................ 150

Layout Recommendation ...................................................................................................................... 151


7.1
7.2
7.3

8.

Layout Recommendation ............................................................................................................. 151


Maximum layout resistance.......................................................................................................... 152
External Components Connection ............................................................................................... 153

Electrical Characteristics....................................................................................................................... 154


8.1
Absolute maximum ratings ........................................................................................................... 154
8.2
ESD protection level..................................................................................................................... 154
8.3
DC characteristics ........................................................................................................................ 155
8.4
AC characteristics ........................................................................................................................ 156
8.4.1 8080 system interface characteristics...................................................................................... 156
8.4.2 Serial interface characteristics ................................................................................................. 157
8.4.3 RGB interface characteristics .................................................................................................. 158
8.4.4 Reset input timing .................................................................................................................... 160

9.
10.

Ordering Information ............................................................................................................................. 161


Revision History................................................................................................................................ 161

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.4April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2010

Figure 4.1: 8080 System interface protocol, write/read register .................................................... 28


Figure 4.2: 8080 System interface protocol, write/read GRAM...................................................... 28
Figure 4.3: Example of I80 8-bit bus interface ............................................................................... 29
Figure 4.4: Write data for RGB 5-6-5 bits input in I80 8-bit parallel bus interface.......................... 29
Figure 4.5: Write data for RGB 6-6-6 bits input in I80 8-bit parallel bus interface ......................... 30
Figure 4.6: Example of I80 9-bit bus interface ............................................................................... 31
Figure 4.7: Write data for RGB 6-6-6 bits input in I80 9-bit parallel bus interface ......................... 31
Figure 4.8: Example of I80 16-Bit parallel bus interface ................................................................ 32
Figure 4.9: Write data for RGB 5-6-5 bits input in I80 16-bit parallel bus interface ....................... 33
Figure 4.10: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (DFM=0) ...... 34
Figure 4.11: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=07h) . 35
Figure 4.12: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=04h) . 36
Figure 4.13: Example of I80 18-Bit parallel bus interface .............................................................. 37
Figure 4.14: Write data for RGB 6-6-6 bits input in I80 18-bit parallel bus interface ..................... 38
Figure 4.15: Index register read/write timing in 3-wire serial bus system interface ....................... 42
Figure 4.16: Data write timing in 3-wire serial bus system interface.............................................. 43
Figure 4.17: Index register write timing in 4-wire serial bus system interface ............................... 44
Figure 4.18: Data write timing in 4-wire serial bus system interface.............................................. 44
Figure 4.19: PCLK cycle................................................................................................................. 45
Figure 4.20: General Timing Diagram............................................................................................ 46
Figure 4.21: DPI timing diagram .................................................................................................... 46
Figure 4.22: 16 bit data bus color order on DPI interface .............................................................. 47
Figure 4.23: 18 bit data bus color order on DPI interface .............................................................. 48
Figure 5.1: MCU to Memory write / read direction ......................................................................... 52
Figure 5.2: MY, MX, MV setting ..................................................................................................... 52
Figure 5.3: Address direction settings............................................................................................ 53
Figure 5.4: 240RGB x 432 resolution............................................................................................. 54
Figure 5.5: Vertical scrolling ........................................................................................................... 56
Figure 5.6: Memory map of vertical scrolling 1 .............................................................................. 56
Figure 5.7: Memory map of vertical scrolling 2 .............................................................................. 57
Figure 5.8: Vertical scroll example 1 .............................................................................................. 58
Figure 5.9: Vertical scroll example 2 .............................................................................................. 58
Figure 5.10: Tearing Effect Output signal mode 1 ......................................................................... 59
Figure 5.11: TE Delay Output......................................................................................................... 59
Figure 5.12: Tearing Effect Output signal mode 2 ......................................................................... 60
Figure 5.13: TE Output for TELINE setting .................................................................................... 60
Figure 5.14: Tearing Effect Output signal ...................................................................................... 60
Figure 5.15: Tearing Effect Line Timing ......................................................................................... 61
Figure 5.16: Rise and Fall times of TE signal ................................................................................ 61
Figure 5.17: Tearing Effect - Example 1-1 ..................................................................................... 62
Figure 5.18: Tearing Effect - Example 1-2 ..................................................................................... 62
Figure 5.19: Tearing Effect - Example 2-1 ..................................................................................... 63
Figure 5.20: Tearing Effect - Example 2-2 ..................................................................................... 63
Figure 5.21: OSC aritecture ........................................................................................................... 64
Figure 5.22: Source channels of different inversion mode............................................................. 65
Figure 5.23: Scan direction of Gate Driver..................................................................................... 66
Figure 5.24: LCD power generation scheme ................................................................................. 67
Figure 5.25: Block diagram of HX8352-C power circuit with internal charge pump....................... 68
Figure 5.26: Gamma adjustments different of source driver with digital gamma correction .......... 70
Figure 5.27: Grayscale Control ...................................................................................................... 71
Figure 5.28: Structure of Grayscale Voltage Generator................................................................. 72
Figure 5.29: Gamma Resister Steam and Reference Voltage....................................................... 73
Figure 5.30: Relationship between source output and Vcom ........................................................ 81
Figure 5.31: Relationship between data and output level, REV =0, normal white......................... 81

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.5April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2010

Figure 5.32: Block Diagram of Digital Gamma Correction ............................................................. 82


Figure 5.33: Case 1: NRESET line is held high or unstable by host at power on.......................... 86
Figure 5.34: Case 2: NRESET line is held low by host at power on .............................................. 87
Figure 5.35: Display On/Off Set flow .............................................................................................. 89
Figure 5.36: Standby Mode Setting flow ........................................................................................ 89
Figure 5.37: Deep Standby Mode Setting flow............................................................................... 90
Figure 5.38: Power Supply Setting Flow ........................................................................................ 91
Figure 5.39: CABC block diagram.................................................................................................. 92
Figure 5.40: Module architecture ................................................................................................... 93
Figure 5.41: CABC gain / CABC duty generation .......................................................................... 94
Figure 5.42: CABC_PWM_OUT output duty.................................................................................. 95
Figure 5.43: OTP programming sequence..................................................................................... 99
Figure 6.1 Index register .............................................................................................................. 106
Figure 6.2 Himax ID register (PAGE0 -00h) ................................................................................. 106
Figure 6.3 Display mode control register (PAGE0 -01h) .............................................................. 106
Figure 6.4 Column address start register upper byte (PAGE0 -02h) ........................................... 107
Figure 6.5 Column address start register low byte (PAGE0 -03h)............................................... 107
Figure 6.6 Column address end register upper byte (PAGE0 -04h) ............................................ 107
Figure 6.7 Column address end register low byte (PAGE0 -05h)................................................ 107
Figure 6.8 Row address start register upper byte (PAGE0 -06h) ................................................ 108
Figure 6.9 Row address start register low byte (PAGE0 -07h) .................................................... 108
Figure 6.10 Row address end register upper byte (PAGE0 -08h) ............................................... 108
Figure 6.11 Row address end register low byte (PAGE0 -09h) ................................................... 108
Figure 6.12 Partial area start row register upper byte (PAGE0 -0Ah) ......................................... 109
Figure 6.13 Partial area start row register low byte (PAGE0 -0Bh) ............................................. 109
Figure 6.14 Partial area end row register upper byte (PAGE0 -0Ch) .......................................... 109
Figure 6.15 Partial area end row register low byte (PAGE0 -0Dh) .............................................. 109
Figure 6.16 Vertical scroll top fixed area register upper byte (PAGE0 -0Eh) ............................... 111
Figure 6.17 Vertical scroll top fixed area register low byte (PAGE0 -0Fh) ................................... 111
Figure 6.18 Vertical scroll height area register upper byte (PAGE0 -10h).................................... 111
Figure 6.19 Vertical scroll height area register low byte (PAGE0 -11h) ....................................... 111
Figure 6.20 Vertical scroll button fixed area register upper byte (PAGE0 -12h)........................... 111
Figure 6.21 Vertical scroll button fixed area register low byte (PAGE0 -13h)............................... 111
Figure 6.22 Vertical Scroll Start Address Register Upper Byte (PAGE0 -14h).............................112
Figure 6.23 Vertical Scroll Start Address Register Low Byte (PAGE0 -15h) ................................112
Figure 6.24 Memory access control register (PAGE0 -16h) .........................................................114
Figure 6.25 COLMOD control register (PAGE0 -17h)...................................................................114
Figure 6.26 OSC control 1 register (PAGE0 -18h) ........................................................................116
Figure 6.27 OSC control 2 register (PAGE0 -19h) ........................................................................116
Figure 6.28 Power control 1 register (PAGE0 -1Ah) .....................................................................117
Figure 6.29 Power control 2 register (PAGE0 -1Bh) .....................................................................118
Figure 6.30 Power control 3 register (PAGE0 -1Ch).....................................................................119
Figure 6.31 Power control 5 register (PAGE0 -1Fh) .................................................................... 120
Figure 6.32 Read data register (PAGE0 -22h) ............................................................................. 121
Figure 6.33 VCOM control 1 register (PAGE0 -23h).................................................................... 122
Figure 6.34 VCOM control 2 register (PAGE0 -24h).................................................................... 122
Figure 6.35 VCOM control 3 register (PAGE0 -25h) .................................................................... 122
Figure 6.36 Display control 1 register (PAGE0 -26h)................................................................... 124
Figure 6.37 Display control 2 register (PAGE0 -27h)................................................................... 124
Figure 6.38 Display control 3 register (PAGE0 -28h)................................................................... 124
Figure 6.39 Display control 4 register (PAGE0 -29h)................................................................... 124
Figure 6.40 Display control 5 register (PAGE0 -2Ah) .................................................................. 124
Figure 6.41 Display control 6 register (PAGE0 -2Bh) .................................................................. 124
Figure 6.42 Display control 7 register (PAGE0 -2Ch) .................................................................. 124
Figure 6.43 Cycle control 1 register (PAGE0 -2Dh) ..................................................................... 127

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.6April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2010

Figure 6.44 Cycle control 2 register (PAGE0 -2Eh) ..................................................................... 127


Figure 6.45 RGB interface control 1 register (PAGE0 -31h)........................................................ 128
Figure 6.46 RGB interface control 2 register (PAGE0 -32h)........................................................ 128
Figure 6.47 RGB interface control 3 register (PAGE0 -33h)........................................................ 128
Figure 6.48 RGB interface control 4 register (PAGE0 -34h)........................................................ 128
Figure 6.49 Panel characteristic control register (PAGE0 -36h) .................................................. 130
Figure 6.50 OTP control 1 (PAGE0 -38h) .................................................................................... 131
Figure 6.51 OTP control 2 (PAGE0 -39h) .................................................................................... 131
Figure 6.52 OTP control 3 (PAGE0 -3Ah).................................................................................... 131
Figure 6.53 OTP control 4 (PAGE0 -3Bh).................................................................................... 131
Figure 6.54 OTP control 5 (PAGE0 -87h) .................................................................................... 131
Figure 6.55 CABC control 1 register (PAGE0 -3Ch) .................................................................... 132
Figure 6.56 CABC control 2 register (PAGE0 -3Dh) .................................................................... 132
Figure 6.57 CABC control 3 register (PAGE0 -3Eh) .................................................................... 132
Figure 6.58 CABC control 4 register (PAGE0 -3Fh)..................................................................... 132
Figure 6.59 Gamma control 1 register (PAGE0 -40h) .................................................................. 134
Figure 6.60 Gamma control 2 register (PAGE0 -41h) .................................................................. 134
Figure 6.61 Gamma control 3 register (PAGE0 -42h) .................................................................. 134
Figure 6.62 Gamma control 4 register (PAGE0 -43h) .................................................................. 134
Figure 6.63 Gamma control 5 register (PAGE0 -44h) .................................................................. 134
Figure 6.64 Gamma control 6 register (PAGE0 -45h) .................................................................. 134
Figure 6.65 Gamma control 7 register (PAGE0 -46h) .................................................................. 135
Figure 6.66 Gamma control 8 register (PAGE0 -47h) .................................................................. 135
Figure 6.67 Gamma control 9 register (PAGE0 -48h) .................................................................. 135
Figure 6.68 Gamma control 10 register (PAGE0 -49h) ................................................................ 135
Figure 6.69 Gamma control 11 register (PAGE0 -4Ah)................................................................ 135
Figure 6.70 Gamma control 12 register (PAGE0 -4Bh) ............................................................... 135
Figure 6.71 Gamma control 13 register (PAGE0 -4Ch) ............................................................... 136
Figure 6.72 Gamma control 14 register (PAGE0 -4Dh) ............................................................... 136
Figure 6.73 Gamma control 15 register (PAGE0 -4Eh) ............................................................... 136
Figure 6.74 TE control register (PAGE0 -60h) ............................................................................. 137
Figure 6.75 TE output line2 register (PAGE0 -84h) ..................................................................... 137
Figure 6.76 TE output line1 register (PAGE0 -85h) ..................................................................... 137
Figure 6.77 ID1 register (PAGE0 -61h) ........................................................................................ 138
Figure 6.78 ID2 register (PAGE0 -62h) ........................................................................................ 138
Figure 6.79 ID3 register (PAGE0 -63h) ........................................................................................ 138
Figure 6.80 Memory write control register (PAGE0 -68h) ............................................................ 138
Figure 6.81 TE interval control register (PAGE0 -69h)................................................................. 139
Figure 6.82 RGB SRAM cycle control register (PAGE0 -6Ah)..................................................... 139
Figure 6.83 Data format control register (PAGE0 -6Bh)............................................................... 140
Figure 6.84 Frame rate control 1 register (PAGE0 -70h) ............................................................. 141
Figure 6.85 Frame rate control 2 register (PAGE0 -71h) ............................................................. 141
Figure 6.86 Frame rate control 3 register (PAGE0 -72h) ............................................................. 141
Figure 6.87 Frame rate control 4 register (PAGE0 -73h) ............................................................. 141
Figure 6.88 Frame rate control 5 register (PAGE0 -74h) ............................................................. 141
Figure 6.89 Frame rate control 6 register (PAGE0 -75h) ............................................................. 141
Figure 6.90 Frame rate control 7 register (PAGE0 -76h) ............................................................. 142
Figure 6.91 Frame rate control 8 register (PAGE0 -77h) ............................................................. 142
Figure 6.92 Power control 6 register (PAGE0 -7Ah) .................................................................... 144
Figure 6.93 Power control 7 register (PAGE0 -7Bh) .................................................................... 144
Figure 6.94 Power control 8 register (PAGE0 -7Ch) .................................................................... 144
Figure 6.95 Power control 9 register (PAGE0 -7Dh) .................................................................... 144
Figure 6.96 Power control 10 register (PAGE0 -7Eh) .................................................................. 144
Figure 6.97 Power control 11 register (PAGE0 -7Fh)................................................................... 144
Figure 6.98 VPP voltage control register (PAGE0 -86h) .............................................................. 146

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.7April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Figures

April, 2010

Figure 6.99 Get scan line 2 register (PAGE0 -88h)...................................................................... 146


Figure 6.100 Get scan line 1 register (PAGE0 -89h) ................................................................... 146
Figure 6.101 Read VCOM OTP times register (PAGE0 -R8Ah) .................................................. 147
Figure 6.102 Read ID OTP times register (PAGE0 -R8Bh) ......................................................... 147
Figure 6.103 Command page select register (RFFh) .................................................................. 148
Figure 6.104 DGC control register (PAGE1 -00h)........................................................................ 149
Figure 6.105 DGC LUT register (PAGE1 -01h~63h).................................................................... 149
Figure 6.106 CABC control 5 register (PAGE1 C3h) ................................................................. 150
Figure 6.107 CABC control 7 register (PAGE1 C5h) ................................................................. 150
Figure 7.1: Layout Recommendation ........................................................................................... 151
Figure 8.1: I80 interface characteristics ....................................................................................... 156
Figure 8.2: Serial interface characteristics ................................................................................... 157
Figure 8.3: General timings for RGB I/F-1 ................................................................................... 158
Figure 8.4: General timings for RGB I/F-2 ................................................................................... 159
Figure 8.5: Reset input timing ...................................................................................................... 160

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.8April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

List of Tables

April, 2010

Table 4.1: Interface selection .....................................................................................................26


Table 4.2: Pin connection based on different interface ..............................................................27
Table 4.3: I80 8-Bits Interface GRAM Write Table......................................................................39
Table 4.4: I80 9-Bits Interface GRAM Write Table......................................................................39
Table 4.5: I80 16-Bits Interface GRAM Write Table....................................................................39
Table 4.6: I80 18-Bits Interface GRAM Write Table....................................................................39
Table 4.7: I80 8-Bits Interface GRAM Read Table .....................................................................40
Table 4.8: I80 9-Bits Interface GRAM Read Table .....................................................................40
Table 4.9: I80 16-Bits Interface GRAM Read Table ...................................................................40
Table 4.10: I80 18-Bits Interface GRAM Read Table .................................................................40
Table 4.11: Data Mapping Extend to 18-bit Data........................................................................40
Table 4.12: Function of RS and R/W bit bus ..............................................................................41
Table 4.13: DPI Input Data Format.............................................................................................47
Table 4.14: DPI Data Mapping Extend to 18-bit Data ................................................................48
Table 5.1: Addresses counter range...........................................................................................50
Table 5.2: Memory map of 240RGB x432 resolution .................................................................51
Table 5.3: MY, MX, MV setting ...................................................................................................52
Table 5.4: 240RGB x 432 resolution (SRAM assignment) .........................................................54
Table 5.5: Memory map of partial display...................................................................................55
Table 5.6: AC characteristics of Tearing Effect Signal ...............................................................61
Table 5.7: Power supply voltage configuration...........................................................................67
Table 5.8: Adoptability of capacitor ............................................................................................69
Table 5.9: Gamma-Adjustment Registers ..................................................................................74
Table 5.10: Offset Adjustment ....................................................................................................75
Table 5.11: EEM Adjustment ......................................................................................................75
Table 5.12: Center Adjustment ...................................................................................................75
Table 5.13: Output Voltage of 8 to 1 Selector ............................................................................76
Table 5.14: Voltage Calculation Formula (Positive Polarity) ......................................................77
Table 5.15: Voltage Calculation Formula of Grayscale Voltage (Positive Polarity)....................78
Table 5.16: Voltage Calculation Formula (Negative Polarity).....................................................79
Table 5.17: Voltage Calculation Formula of Grayscale Voltage (Negative Polarity) ..................80
Table 5.18: DGC LUT .................................................................................................................83
Table 5.19: Characteristics of output or bi-directional (I/O) pins ................................................84
Table 5.20: Characteristics of input pins ....................................................................................84
Table 5.21: CABC timing table ...................................................................................................95
Table 5.22: OTP Programming sequence ................................................................................100
Table 6.1: List table of command set page 0............................................................................103
Table 6.2: List table of command set page 1............................................................................105
Table 7.1: Maximum Layout Resistance ..................................................................................152
Table 7.2: Adoptability of component .......................................................................................153
Table 8.1: Absolute maximum rating ........................................................................................154
Table 8.2: ESD protection level ................................................................................................154
Table 8.3: DC characteristic .....................................................................................................155
Table 8.4: I80 interface characteristics.....................................................................................156
Table 8.5: Serial interface characteristics.................................................................................157
Table 8.6: RGB interface characteristics-1...............................................................................158
Table 8.7: RGB interface characteristics-2...............................................................................159
Table 8.8: Reset timing.............................................................................................................160

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

- P.9April, 2010

HX8352-C(T)
240RGB x 432 dot, 262K color, with internal
GRAM, TFT Mobile Single Chip Driver

Temporary Version 01

April, 2010

1. General Description
This document describes Himaxs HX8352-C supports 240x432 resolution driving controller.
The HX8352-C is designed to provide a single-chip solution that combines a source driver,
power supply circuit to drive a TFT dot matrix LCD with 240RGBx432 dots at maximum.
The HX8352-C can be operated in low-voltage condition for the interface and integrated
internal boosters that produce the liquid crystal voltage, breeder resistance and the voltage
follower circuit for liquid crystal driver. In addition, The HX8352-C also supports various
functions to reduce the power consumption of a LCD system via software control.
The HX8352-C supports several interface modes, including System interface mode and RGB
interface mode. The interface mode is selected by the external hardware pins IM2~0.
The HX8352-C is suitable for any small portable battery-driven and long-term driving
products, such as small PDAs, digital cellular phones and bi-directional pagers.
This manual description focuses on Command-Parameter interface mode, about the
Command-Parameter interface mode, please refer to the HX8352-C(N) datasheet for detail.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.10April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

2. Features
2.1 Display




Single chip solution for a 240 x 432 type TFT LCD display
Resolution: 240RGB x 432
Display color modes
 262K colours (18-bit 6(R):6(G):6(B))
 65K colours (16-bit 5(R):6(G):5(B))
 8 colors (Idle mode on): 8 colors (3-bit binary mode)

2.2 Display module







Support 720 source channel outputs


Supports 1-line / n-line/ frame inversion
On module VCOM control (VCOMH= 3.0V to (DDVDH-0.5)V; VCOML=(VCL+0.5)V to 0V)
Charge bump circuit for source, glass gate level shifter
 DDVDH= 4.5V to 6.0V
 Source output voltage level: VREG1= 4.0V to 5.5V
 Positive gate driver output voltage level: VGH= 10V to 18V
 Negative gate driver output voltage level: VGL= -5V to -12.5V
Frame memory area 240 (H) x 432 (V) x 18-bit

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.11April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

2.3 Display / Control interface




Display interface types supported


 System Interface mode
 8080 MCU Type II interface (8-/ 9-/ 16-/ 18-bit bus)
 3 wrie Serial data transfer interface
 4 wrie Serial data transfer interface
 RGB Interface mode
 16 bit/pixel R(5), G(6), B(5)
 18 bit/pixel R(6), G(6), B(6)

2.4 Input power






I/O and Logic power power supply (IOVCC): 1.65V to 3.3V


Analog power supply (VCI): 2.5V to 3.3V
OTP programming voltage(internal generated or external supply on VGH): 7.5V 0.2V

2.5 Miscellaneous



















Partial display mode


Vertical scrolling display
Oscillator for display clock generation
Low power consumption, suitable for battery operated systems
CMOS compatible inputs
Proprietary multi phase driving for lower power consumption
GAS function for preventing image sticking when abnormal power off
Optimized layout for COG assembly
Temperature range: -40 to +85 C
Support inversion mode
DC/DC converter for source
Support AC COM driving
VCOM voltage generator
On-chip OTP program voltage generator
OTP memory to store initialization register settings
8 times MTP for VCOM setting and ID setting
Support CABC (Content Adaptive Brightness Control) function
Support DGC (Digital Gamma Correction) function

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.12April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

3. Device Overview
3.1 Block diagram

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.13April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

3.2 Pin description


Host interface pins
Signals

I/O

Pin no.

Connected
with

Description
Use with IFSEL=L Register-Content Interface mode
Select the interface mode as listed below:
IM2 IM1 IM0
Interface mode
DB pins
0
0
0 8080 MCU TYPE-II 18-bit DB17-DB0: Data

IM2 ~ IM0

IFSEL

NCS

NRESET

NRD

DNC

NWR_SCL

DB17~0

I/O

18

SDI_SDA

I/O

SDO

VSSD /
IOVCC

VSSD /
IOVCC

8080 MCU TYPE-II 9-bit

8080 MCU TYPE-II 16-bit

8080 MCU TYPE-II 8-bit

DB8-DB0: Unused,
DB17-DB9: Data
DB9, DB0:Unused,
DB17-DB10, DB8-DB1: Data
DB9-DB0: Unused,
DB17-DB10: Data
SDI_SDA, DB17-DB0
SDI_SDA, DB17-DB0

1
0
ID 3-wire SPI
1
1
X 4-wire SPI
Pixel format (RGB565 / RGB666) is selected by command (0x17h)
Must be connected to VSSD or IOVCC.
Interface format select pin
IFSEL0
Interface Format Selection
0
Register-content interface mode
1
Command-Parameter interface mode
In this document, the IFSEL has to be connected to IOVCC and Command-Parameter
interface mode is selected. This pin is internal weak pull high.

Chip select signal.


Low: chip can be accessed.
MPU
High: chip cannot be accessed.
If this pin is not used, please connect it to VSSD or IOVCC.
MPU or
Reset pin. Setting either pin low initializes the LSI. Must be reset after
reset circuit power is supplied (Must be connected to VSSD or IOVCC).
Serves as a read signal and read data at the low level.
MPU
If this pin is not used, please connect it to VSSD or IVCC.
Data / Command Selection pin
MPU
If this pin is not used, please connect it to VSSD or IOVCC.
DBI Type-B mode: Serves as a write signal and write data at the low level.
MPU
DBI Type-C mode: it servers as SCL (Serial Clock)
If this pin is not used, please connect it to VSSD or IOVCC.
Data bus.
Interface mode
Command
Data
8080 MCU TYPE-II 8-bit
DB17~10
DB17~10
8080 MCU TYPE-II 9-bit
DB17~10
DB17~9
MPU
8080 MCU TYPE-II 16-bit
DB8~1
DB17~10, DB8~1
8080 MCU TYPE-II 18-bit
DB8~1
DB17~0
RGB 16-bit
SDI_SDA
DB15~0
RGB 18-bit
SDI_SDA
DB17~0
Please connect to VSSD or IOVCC for not used pin.
Serves as serial data input/output when SDA_EN=1. Serves as serial data
MPU
input when SDA_EN=0.
If this pin is not used, please connect it to VSSD or IOVCC.
Serial data output.
MPU
If this pin is not used, let it open.

Clock input and DPI interface


HSYNC

MPU

DE

MPU

VSYNC

MPU

PCLK

MPU

Line synchronizing signal.


If this pin is not used, please connect it to VSSD or IOVCC.
A data enable signal in DPI I/F mode.
If this pin is not used, please connect it to VSSD or IOVCC.
Serves VS signal pin on DPI interface. (Input pad).
If this pin is not used, please connect it to VSSD or IOVCC.
Dot clock signal. If this pin is not used, please connect it to VSSD or
IOVCC.

Source driver output pins


S1~S720

720

LCD

TE

MPU

432

LCD

Output voltages applied to the liquid crystal.


Serves TE (Tearing Effect ) pin on MPU interface.
If not used, let it open.

Gate driver output pins


G1~G432

Output voltages applied to the liquid crystal.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.14April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Power supply pins
IOVCC

VCI

18

VSSA

18

VSSD

36

Power
supply
Power
supply
Power
supply
Power
supply

A power supply for the I/O circuit and logic power. IOVCC=1.65 to 3.3V
A power supply for the analog power, DC/DC converter VCI=2.5 to 3.3V.
Analoge ground. VSSA=0V. When using the COG method, connect to
VSSD on the FPC to prevent noise.
Ground for the internal logic. VSSD=0V. When using the COG method,
connect to VSSA on the FPC to prevent noise.

Output Pins of Power and reference voltage


DDVDH

VREG1

VCL

VDDD

VGH

VGL

13

VCOM

VGS

Stabilizing
capacitor
Open
Stabilizing
capacitor
Stabilizing
capacitor

Output voltage from the step-up circuit, it is generated from VCI. Connect to
a stabilizing capacitor between VSSA and DDVDH.
Internal generated stable power for source driver unit. Leave it open.
Output voltage from the step-up circuit, it is generated from VCI. Connect to
a stabilizing capacitor between VSSA and VCL.
Internal generated logic voltage(1.6V) output. Connect to a stabilizing
capacitor between VSSD and VDDD.
Output voltage from the step-up circuit, it is generated from DDVDH and
Stabilizing
VCI. Connect to a stabilizing capacitor between VSSA and VGH.
capacitor
If OTP program use external power mode, the VGH need connect to 7.5V.
Stabilizing Output voltage from the step-up circuit, it is generated from VCL and VCI.
capacitor Connect to a stabilizing capacitor between VSSA and VGL.
TFT
The power supply of common voltage in TFT driving. The voltage amplitude
common between VCOMH and VCOML is output. Connect this pin to the common
electrode electrode on TFT panel.
VSSD or
Connect to a variable resistor to adjusting internal gamma reference
external
voltage for matching the characteristic of different panel used.
resistor

DC/DC pumping
C11P, C11N
C12P, C12N
C21P, C21N
C22P, C22N
C31P, C31N

I/O
I/O

5, 5
5, 5
3, 3
3, 3

Step-up
Capacitor
Step-up
Capacitor
Step-up
Capacitor

Connect to the step-up capacitors according to the DC/DC pumping factor


by pumping the DDVDH voltage.
Connect to the step-up capacitors according to the DC/DC pumping factor
by pumping the VGH/VGL voltage.
Connect to the step-up capacitor according to the DC/DC pumping factor
by pumping the VCL voltage.

I/O

3, 3

CABC_PWM_OUT

LEDON

OSC

Open

TEST1~2

Open

TS0~7

Open

Open

Open

Dummy pads. Available for measuring the COG contact resistance. They
are short-circuited within the chip.

Open

Dummy pads. Available for measuring the COG contact resistance. They
are short-circuited within the chip.

6
6
50

Open
Open
Open

Dummy pads.
Dummy pads.
Dummy pads.

CABC & ABC


PWM output pin of Backlight control. If use CABC function, the pin can
connect to external LED driver IC. The output voltage range= VSSD to
IOVCC.
If not used, let it open.
Enable signal of Backlight LED driver( Active high). The output voltage
LED Driver range= VSSD to IOVCC.
If not used, let it open.
LED Driver

Test Pins

VTEST
DUMMYR1
DUMMYR4
DUMMYR2
DUMMYR3
VCOMH_DUMMY
VCOML_DUMMY
DUMMY

Oscillator input for test purpose.


If not used, please let it open or connected to VSSD.
A test pin. This pin is by internal logic function test.
If not used, let it open or connected to VSSD.(weak pull low)
A test pin. This pin is by internal logic function test.This pin can output on
FPC. If not used, let it open.
A test pin. Disconnect it. This pin will output Gamma voltage. This pin can
output on FPC.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.15April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

3.3 Pin assignment

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.16April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

3.4 PAD coordinates


No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60

Name
DUMMYR1
DUMMYR2
VSSD
DUMMY1
DUMMY2
DUMMY3
DUMMY4
VSSD
DUMMY5
DUMMY6
DUMMY7
DUMMY8
DUMMY9
DUMMY10
DUMMY11
DUMMY12
DUMMY13
VSSD
DUMMY14
DUMMY15
DUMMY16
DUMMY17
DUMMY18
DUMMY19
DUMMY20
DUMMY21
DUMMY22
DUMMY23
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VCI
VCI
VCI
VCI
VCI
VCI
VCI
DUMMY24
TS7
TS6
TS5
TS4
TS3
TS2
TS1
TS0
OSC
DUMMY25
DUMMY26
TEST2

Y
-9135
-9065
-8995
-8925
-8855
-8785
-8715
-8645
-8575
-8505
-8435
-8365
-8295
-8225
-8155
-8085
-8015
-7945
-7875
-7805
-7735
-7665
-7595
-7525
-7455
-7385
-7315
-7245
-7175
-7105
-7035
-6965
-6895
-6825
-6755
-6685
-6615
-6545
-6475
-6405
-6335
-6265
-6195
-6125
-6055
-5985
-5915
-5845
-5775
-5705
-5635
-5565
-5495
-5425
-5355
-5285
-5215
-5145
-5075
-5005

-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5

Bump size
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90

No.
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120

Name
TEST1
VSSD
DUMMY27
IM2
IM1
IM0
IOVCC
IFSEL
NRESET
VSSD
LEDON
CABC_PWM_OUT
VSYNC
HSYNC
IOVCC
DE
PCLK
DB17
DB16
VSSD
DB15
DB14
DB13
DB12
VSSD
DB11
DB10
DB9
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB8
VSSD
DB7
DB6
DB5
DB4
VSSD
DB3
DB2
DB1
DB0
VSSD
NCS
DNC
NWR_SCL
NRD
VSSD
TE
SDI_SDA
SDO
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD

X
-4935
-4865
-4795
-4725
-4655
-4585
-4515
-4445
-4375
-4305
-4235
-4165
-4095
-4025
-3955
-3885
-3815
-3745
-3675
-3605
-3535
-3465
-3395
-3325
-3255
-3185
-3115
-3045
-2975
-2905
-2835
-2765
-2695
-2625
-2555
-2485
-2415
-2345
-2275
-2205
-2135
-2065
-1995
-1925
-1855
-1785
-1715
-1645
-1575
-1505
-1435
-1365
-1295
-1225
-1155
-1085
-1015
-945
-875
-805

Y
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5

Bump size
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90

No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180

Name
VDDD
VDDD
VDDD
DUMMY28
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VGS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VTEST
DUMMY29
VREG1
DUMMY30
C11P
C11P
C11P
C11P
C11P
C11N
C11N
C11N
C11N
C11N
C12P
C12P
C12P

X
-735
-665
-595
-525
-455
-385
-315
-245
-175
-105
-35
35
105
175
245
315
385
455
525
595
665
735
805
875
945
1015
1085
1155
1225
1295
1365
1435
1505
1575
1645
1715
1785
1855
1925
1995
2065
2135
2205
2275
2345
2415
2485
2555
2625
2695
2765
2835
2905
2975
3045
3115
3185
3255
3325
3395

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Y
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5

Bump size
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90

-P.17April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240

Name

C12P
C12P
C12N
C12N
C12N
C12N
C12N

3465
3535
3605
3675
3745
3815
3885
3955
4025
4095
4165
4235
4305
4375
4445
4515
4585
4655
4725
4795
4865
4935
5005
5075
5145
5215
5285
5355
5425
5495
5565
5635
5705
5775
5845
5915
5985
6055
6125
6195
6265
6335
6405
6475
6545
6615
6685
6755
6825
6895
6965
7035
7105
7175
7245
7315
7385
7455
7525
7595

DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
DUMMY31
DUMMY32
DUMMY33
DUMMY34
DUMMY35
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VSSD
VSSD
VGH
VGH
VGH
VGH
VGH
VGH
VSSD

Y
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5

Bump size
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90

No.
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300

Name
VCL
VCL
VCL
C31P
C31P
C31P
C31N
C31N
C31N
C21P
C21P
C21P
C21N
C21N
C21N
C22P
C22P
C22P
C22N
C22N
C22N
DUMMY36
DUMMY37
DUMMY38
DUMMY39
VGL
G2
G4
G6
G8
G10
G12
G14
G16
G18
G20
G22
G24
G26
G28
G30
G32
G34
G36
G38
G40
G42
G44
G46
G48
G50
G52
G54
G56
G58
G60
G62
G64
G66
G68

X
7665
7735
7805
7875
7945
8015
8085
8155
8225
8295
8365
8435
8505
8575
8645
8715
8785
8855
8925
8995
9065
9135
9397.5
9382.5
9367.5
9352.5
9337.5
9322.5
9307.5
9292.5
9277.5
9262.5
9247.5
9232.5
9217.5
9202.5
9187.5
9172.5
9157.5
9142.5
9127.5
9112.5
9097.5
9082.5
9067.5
9052.5
9037.5
9022.5
9007.5
8992.5
8977.5
8962.5
8947.5
8932.5
8917.5
8902.5
8887.5
8872.5
8857.5
8842.5

Y
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
-297.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
50*90
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360

Name

G70
G72
G74
G76
G78
G80
G82
G84
G86
G88
G90
G92
G94
G96
G98
G100
G102
G104
G106
G108
G110
G112
G114
G116
G118
G120
G122
G124
G126
G128
G130
G132
G134
G136
G138
G140
G142
G144
G146
G148
G150
G152
G154
G156
G158
G160
G162
G164
G166
G168
G170
G172
G174
G176
G178
G180
G182
G184
G186
G188

8827.5
8812.5
8797.5
8782.5
8767.5
8752.5
8737.5
8722.5
8707.5
8692.5
8677.5
8662.5
8647.5
8632.5
8617.5
8602.5
8587.5
8572.5
8557.5
8542.5
8527.5
8512.5
8497.5
8482.5
8467.5
8452.5
8437.5
8422.5
8407.5
8392.5
8377.5
8362.5
8347.5
8332.5
8317.5
8302.5
8287.5
8272.5
8257.5
8242.5
8227.5
8212.5
8197.5
8182.5
8167.5
8152.5
8137.5
8122.5
8107.5
8092.5
8077.5
8062.5
8047.5
8032.5
8017.5
8002.5
7987.5
7972.5
7957.5
7942.5

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.18April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420

Name
G190
G192
G194
G196
G198
G200
G202
G204
G206
G208
G210
G212
G214
G216
G218
G220
G222
G224
G226
G228
G230
G232
G234
G236
G238
G240
G242
G244
G246
G248
G250
G252
G254
G256
G258
G260
G262
G264
G266
G268
G270
G272
G274
G276
G278
G280
G282
G284
G286
G288
G290
G292
G294
G296
G298
G300
G302
G304
G306
G308

X
7927.5
7912.5
7897.5
7882.5
7867.5
7852.5
7837.5
7822.5
7807.5
7792.5
7777.5
7762.5
7747.5
7732.5
7717.5
7702.5
7687.5
7672.5
7657.5
7642.5
7627.5
7612.5
7597.5
7582.5
7567.5
7552.5
7537.5
7522.5
7507.5
7492.5
7477.5
7462.5
7447.5
7432.5
7417.5
7402.5
7387.5
7372.5
7357.5
7342.5
7327.5
7312.5
7297.5
7282.5
7267.5
7252.5
7237.5
7222.5
7207.5
7192.5
7177.5
7162.5
7147.5
7132.5
7117.5
7102.5
7087.5
7072.5
7057.5
7042.5

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480

Name
G310
G312
G314
G316
G318
G320
G322
G324
G326
G328
G330
G332
G334
G336
G338
G340
G342
G344
G346
G348
G350
G352
G354
G356
G358
G360
G362
G364
G366
G368
G370
G372
G374
G376
G378
G380
G382
G384
G386
G388
G390
G392
G394
G396
G398
G400
G402
G404
G406
G408
G410
G412
G414
G416
G418
G420
G422
G424
G426
G428

X
7027.5
7012.5
6997.5
6982.5
6967.5
6952.5
6937.5
6922.5
6907.5
6892.5
6877.5
6862.5
6847.5
6832.5
6817.5
6802.5
6787.5
6772.5
6757.5
6742.5
6727.5
6712.5
6697.5
6682.5
6667.5
6652.5
6637.5
6622.5
6607.5
6592.5
6577.5
6562.5
6547.5
6532.5
6517.5
6502.5
6487.5
6472.5
6457.5
6442.5
6427.5
6412.5
6397.5
6382.5
6367.5
6352.5
6337.5
6322.5
6307.5
6292.5
6277.5
6262.5
6247.5
6232.5
6217.5
6202.5
6187.5
6172.5
6157.5
6142.5

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540

Name

G430
G432
VGL
DUMMY40
S720
S719
S718
S717
S716
S715
S714
S713
S712
S711
S710
S709
S708
S707
S706
S705
S704
S703
S702
S701
S700
S699
S698
S697
S696
S695
S694
S693
S692
S691
S690
S689
S688
S687
S686
S685
S684
S683
S682
S681
S680
S679
S678
S677
S676
S675
S674
S673
S672
S671
S670
S669
S668
S667
S666
S665

6127.5
6112.5
6097.5
5887.5
5872.5
5857.5
5842.5
5827.5
5812.5
5797.5
5782.5
5767.5
5752.5
5737.5
5722.5
5707.5
5692.5
5677.5
5662.5
5647.5
5632.5
5617.5
5602.5
5587.5
5572.5
5557.5
5542.5
5527.5
5512.5
5497.5
5482.5
5467.5
5452.5
5437.5
5422.5
5407.5
5392.5
5377.5
5362.5
5347.5
5332.5
5317.5
5302.5
5287.5
5272.5
5257.5
5242.5
5227.5
5212.5
5197.5
5182.5
5167.5
5152.5
5137.5
5122.5
5107.5
5092.5
5077.5
5062.5
5047.5

Y
173.5
292.5
173.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.19April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600

Name

S664
S663
S662
S661
S660
S659
S658
S657
S656
S655
S654
S653
S652
S651
S650
S649
S648
S647
S646
S645
S644
S643
S642
S641
S640
S639
S638
S637
S636
S635
S634
S633
S632
S631
S630
S629
S628
S627
S626
S625
S624
S623
S622
S621
S620
S619
S618
S617
S616
S615
S614
S613
S612
S611
S610
S609
S608
S607
S606
S605

5032.5
5017.5
5002.5
4987.5
4972.5
4957.5
4942.5
4927.5
4912.5
4897.5
4882.5
4867.5
4852.5
4837.5
4822.5
4807.5
4792.5
4777.5
4762.5
4747.5
4732.5
4717.5
4702.5
4687.5
4672.5
4657.5
4642.5
4627.5
4612.5
4597.5
4582.5
4567.5
4552.5
4537.5
4522.5
4507.5
4492.5
4477.5
4462.5
4447.5
4432.5
4417.5
4402.5
4387.5
4372.5
4357.5
4342.5
4327.5
4312.5
4297.5
4282.5
4267.5
4252.5
4237.5
4222.5
4207.5
4192.5
4177.5
4162.5
4147.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660

Name
S604
S603
S602
S601
S600
S599
S598
S597
S596
S595
S594
S593
S592
S591
S590
S589
S588
S587
S586
S585
S584
S583
S582
S581
S580
S579
S578
S577
S576
S575
S574
S573
S572
S571
S570
S569
S568
S567
S566
S565
S564
S563
S562
S561
S560
S559
S558
S557
S556
S555
S554
S553
S552
S551
S550
S549
S548
S547
S546
S545

X
4132.5
4117.5
4102.5
4087.5
4072.5
4057.5
4042.5
4027.5
4012.5
3997.5
3982.5
3967.5
3952.5
3937.5
3922.5
3907.5
3892.5
3877.5
3862.5
3847.5
3832.5
3817.5
3802.5
3787.5
3772.5
3757.5
3742.5
3727.5
3712.5
3697.5
3682.5
3667.5
3652.5
3637.5
3622.5
3607.5
3592.5
3577.5
3562.5
3547.5
3532.5
3517.5
3502.5
3487.5
3472.5
3457.5
3442.5
3427.5
3412.5
3397.5
3382.5
3367.5
3352.5
3337.5
3322.5
3307.5
3292.5
3277.5
3262.5
3247.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720

Name

S544
S543
S542
S541
S540
S539
S538
S537
S536
S535
S534
S533
S532
S531
S530
S529
S528
S527
S526
S525
S524
S523
S522
S521
S520
S519
S518
S517
S516
S515
S514
S513
S512
S511
S510
S509
S508
S507
S506
S505
S504
S503
S502
S501
S500
S499
S498
S497
S496
S495
S494
S493
S492
S491
S490
S489
S488
S487
S486
S485

3232.5
3217.5
3202.5
3187.5
3172.5
3157.5
3142.5
3127.5
3112.5
3097.5
3082.5
3067.5
3052.5
3037.5
3022.5
3007.5
2992.5
2977.5
2962.5
2947.5
2932.5
2917.5
2902.5
2887.5
2872.5
2857.5
2842.5
2827.5
2812.5
2797.5
2782.5
2767.5
2752.5
2737.5
2722.5
2707.5
2692.5
2677.5
2662.5
2647.5
2632.5
2617.5
2602.5
2587.5
2572.5
2557.5
2542.5
2527.5
2512.5
2497.5
2482.5
2467.5
2452.5
2437.5
2422.5
2407.5
2392.5
2377.5
2362.5
2347.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.20April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780

Name
S484
S483
S482
S481
S480
S479
S478
S477
S476
S475
S474
S473
S472
S471
S470
S469
S468
S467
S466
S465
S464
S463
S462
S461
S460
S459
S458
S457
S456
S455
S454
S453
S452
S451
S450
S449
S448
S447
S446
S445
S444
S443
S442
S441
S440
S439
S438
S437
S436
S435
S434
S433
S432
S431
S430
S429
S428
S427
S426
S425

X
2332.5
2317.5
2302.5
2287.5
2272.5
2257.5
2242.5
2227.5
2212.5
2197.5
2182.5
2167.5
2152.5
2137.5
2122.5
2107.5
2092.5
2077.5
2062.5
2047.5
2032.5
2017.5
2002.5
1987.5
1972.5
1957.5
1942.5
1927.5
1912.5
1897.5
1882.5
1867.5
1852.5
1837.5
1822.5
1807.5
1792.5
1777.5
1762.5
1747.5
1732.5
1717.5
1702.5
1687.5
1672.5
1657.5
1642.5
1627.5
1612.5
1597.5
1582.5
1567.5
1552.5
1537.5
1522.5
1507.5
1492.5
1477.5
1462.5
1447.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840

Name
S424
S423
S422
S421
S420
S419
S418
S417
S416
S415
S414
S413
S412
S411
S410
S409
S408
S407
S406
S405
S404
S403
S402
S401
S400
S399
S398
S397
S396
S395
S394
S393
S392
S391
S390
S389
S388
S387
S386
S385
S384
S383
S382
S381
S380
S379
S378
S377
S376
S375
S374
S373
S372
S371
S370
S369
S368
S367
S366
S365

X
1432.5
1417.5
1402.5
1387.5
1372.5
1357.5
1342.5
1327.5
1312.5
1297.5
1282.5
1267.5
1252.5
1237.5
1222.5
1207.5
1192.5
1177.5
1162.5
1147.5
1132.5
1117.5
1102.5
1087.5
1072.5
1057.5
1042.5
1027.5
1012.5
997.5
982.5
967.5
952.5
937.5
922.5
907.5
892.5
877.5
862.5
847.5
832.5
817.5
802.5
787.5
772.5
757.5
742.5
727.5
712.5
697.5
682.5
667.5
652.5
637.5
622.5
607.5
592.5
577.5
562.5
547.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900

Name

S364
S363
S362
S361
DUMMY41
DUMMY42
DUMMY43
DUMMY44
DUMMY45
DUMMY46
DUMMY47
DUMMY48
S360
S359
S358
S357
S356
S355
S354
S353
S352
S351
S350
S349
S348
S347
S346
S345
S344
S343
S342
S341
S340
S339
S338
S337
S336
S335
S334
S333
S332
S331
S330
S329
S328
S327
S326
S325
S324
S323
S322
S321
S320
S319
S318
S317
S316
S315
S314
S313

532.5
517.5
502.5
487.5
472.5
457.5
442.5
427.5
-427.5
-442.5
-457.5
-472.5
-487.5
-502.5
-517.5
-532.5
-547.5
-562.5
-577.5
-592.5
-607.5
-622.5
-637.5
-652.5
-667.5
-682.5
-697.5
-712.5
-727.5
-742.5
-757.5
-772.5
-787.5
-802.5
-817.5
-832.5
-847.5
-862.5
-877.5
-892.5
-907.5
-922.5
-937.5
-952.5
-967.5
-982.5
-997.5
-1012.5
-1027.5
-1042.5
-1057.5
-1072.5
-1087.5
-1102.5
-1117.5
-1132.5
-1147.5
-1162.5
-1177.5
-1192.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.21April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960

Name

S312
S311
S310
S309
S308
S307
S306
S305
S304
S303
S302
S301
S300
S299
S298
S297
S296
S295
S294
S293
S292
S291
S290
S289
S288
S287
S286
S285
S284
S283
S282
S281
S280
S279
S278
S277
S276
S275
S274
S273
S272
S271
S270
S269
S268
S267
S266
S265
S264
S263
S262
S261
S260
S259
S258
S257
S256
S255
S254
S253

-1207.5
-1222.5
-1237.5
-1252.5
-1267.5
-1282.5
-1297.5
-1312.5
-1327.5
-1342.5
-1357.5
-1372.5
-1387.5
-1402.5
-1417.5
-1432.5
-1447.5
-1462.5
-1477.5
-1492.5
-1507.5
-1522.5
-1537.5
-1552.5
-1567.5
-1582.5
-1597.5
-1612.5
-1627.5
-1642.5
-1657.5
-1672.5
-1687.5
-1702.5
-1717.5
-1732.5
-1747.5
-1762.5
-1777.5
-1792.5
-1807.5
-1822.5
-1837.5
-1852.5
-1867.5
-1882.5
-1897.5
-1912.5
-1927.5
-1942.5
-1957.5
-1972.5
-1987.5
-2002.5
-2017.5
-2032.5
-2047.5
-2062.5
-2077.5
-2092.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020

Name

S252
S251
S250
S249
S248
S247
S246
S245
S244
S243
S242
S241
S240
S239
S238
S237
S236
S235
S234
S233
S232
S231
S230
S229
S228
S227
S226
S225
S224
S223
S222
S221
S220
S219
S218
S217
S216
S215
S214
S213
S212
S211
S210
S209
S208
S207
S206
S205
S204
S203
S202
S201
S200
S199
S198
S197
S196
S195
S194
S193

-2107.5
-2122.5
-2137.5
-2152.5
-2167.5
-2182.5
-2197.5
-2212.5
-2227.5
-2242.5
-2257.5
-2272.5
-2287.5
-2302.5
-2317.5
-2332.5
-2347.5
-2362.5
-2377.5
-2392.5
-2407.5
-2422.5
-2437.5
-2452.5
-2467.5
-2482.5
-2497.5
-2512.5
-2527.5
-2542.5
-2557.5
-2572.5
-2587.5
-2602.5
-2617.5
-2632.5
-2647.5
-2662.5
-2677.5
-2692.5
-2707.5
-2722.5
-2737.5
-2752.5
-2767.5
-2782.5
-2797.5
-2812.5
-2827.5
-2842.5
-2857.5
-2872.5
-2887.5
-2902.5
-2917.5
-2932.5
-2947.5
-2962.5
-2977.5
-2992.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080

Name

S192
S191
S190
S189
S188
S187
S186
S185
S184
S183
S182
S181
S180
S179
S178
S177
S176
S175
S174
S173
S172
S171
S170
S169
S168
S167
S166
S165
S164
S163
S162
S161
S160
S159
S158
S157
S156
S155
S154
S153
S152
S151
S150
S149
S148
S147
S146
S145
S144
S143
S142
S141
S140
S139
S138
S137
S136
S135
S134
S133

-3007.5
-3022.5
-3037.5
-3052.5
-3067.5
-3082.5
-3097.5
-3112.5
-3127.5
-3142.5
-3157.5
-3172.5
-3187.5
-3202.5
-3217.5
-3232.5
-3247.5
-3262.5
-3277.5
-3292.5
-3307.5
-3322.5
-3337.5
-3352.5
-3367.5
-3382.5
-3397.5
-3412.5
-3427.5
-3442.5
-3457.5
-3472.5
-3487.5
-3502.5
-3517.5
-3532.5
-3547.5
-3562.5
-3577.5
-3592.5
-3607.5
-3622.5
-3637.5
-3652.5
-3667.5
-3682.5
-3697.5
-3712.5
-3727.5
-3742.5
-3757.5
-3772.5
-3787.5
-3802.5
-3817.5
-3832.5
-3847.5
-3862.5
-3877.5
-3892.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.22April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

No.
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140

Name

S132
S131
S130
S129
S128
S127
S126
S125
S124
S123
S122
S121
S120
S119
S118
S117
S116
S115
S114
S113
S112
S111
S110
S109
S108
S107
S106
S105
S104
S103
S102
S101
S100
S99
S98
S97
S96
S95
S94
S93
S92
S91
S90
S89
S88
S87
S86
S85
S84
S83
S82
S81
S80
S79
S78
S77
S76
S75
S74
S73

-3907.5
-3922.5
-3937.5
-3952.5
-3967.5
-3982.5
-3997.5
-4012.5
-4027.5
-4042.5
-4057.5
-4072.5
-4087.5
-4102.5
-4117.5
-4132.5
-4147.5
-4162.5
-4177.5
-4192.5
-4207.5
-4222.5
-4237.5
-4252.5
-4267.5
-4282.5
-4297.5
-4312.5
-4327.5
-4342.5
-4357.5
-4372.5
-4387.5
-4402.5
-4417.5
-4432.5
-4447.5
-4462.5
-4477.5
-4492.5
-4507.5
-4522.5
-4537.5
-4552.5
-4567.5
-4582.5
-4597.5
-4612.5
-4627.5
-4642.5
-4657.5
-4672.5
-4687.5
-4702.5
-4717.5
-4732.5
-4747.5
-4762.5
-4777.5
-4792.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200

Name

S72
S71
S70
S69
S68
S67
S66
S65
S64
S63
S62
S61
S60
S59
S58
S57
S56
S55
S54
S53
S52
S51
S50
S49
S48
S47
S46
S45
S44
S43
S42
S41
S40
S39
S38
S37
S36
S35
S34
S33
S32
S31
S30
S29
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
S16
S15
S14
S13

-4807.5
-4822.5
-4837.5
-4852.5
-4867.5
-4882.5
-4897.5
-4912.5
-4927.5
-4942.5
-4957.5
-4972.5
-4987.5
-5002.5
-5017.5
-5032.5
-5047.5
-5062.5
-5077.5
-5092.5
-5107.5
-5122.5
-5137.5
-5152.5
-5167.5
-5182.5
-5197.5
-5212.5
-5227.5
-5242.5
-5257.5
-5272.5
-5287.5
-5302.5
-5317.5
-5332.5
-5347.5
-5362.5
-5377.5
-5392.5
-5407.5
-5422.5
-5437.5
-5452.5
-5467.5
-5482.5
-5497.5
-5512.5
-5527.5
-5542.5
-5557.5
-5572.5
-5587.5
-5602.5
-5617.5
-5632.5
-5647.5
-5662.5
-5677.5
-5692.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
Name
X
1201
S12
-5707.5
1202
S11
-5722.5
1203
S10
-5737.5
1204
S9
-5752.5
1205
S8
-5767.5
1206
S7
-5782.5
1207
S6
-5797.5
1208
S5
-5812.5
1209
S4
-5827.5
1210
S3
-5842.5
1211
S2
-5857.5
1212
S1
-5872.5
1213 DUMMY49 -5887.5
1214
VGL
-6097.5
1215
G431
-6112.5
1216
G429
-6127.5
1217
G427
-6142.5
1218
G425
-6157.5
1219
G423
-6172.5
1220
G421
-6187.5
1221
G419
-6202.5
1222
G417
-6217.5
1223
G415
-6232.5
1224
G413
-6247.5
1225
G411
-6262.5
1226
G409
-6277.5
1227
G407
-6292.5
1228
G405
-6307.5
1229
G403
-6322.5
1230
G401
-6337.5
1231
G399
-6352.5
1232
G397
-6367.5
1233
G395
-6382.5
1234
G393
-6397.5
1235
G391
-6412.5
1236
G389
-6427.5
1237
G387
-6442.5
1238
G385
-6457.5
1239
G383
-6472.5
1240
G381
-6487.5
1241
G379
-6502.5
1242
G377
-6517.5
1243
G375
-6532.5
1244
G373
-6547.5
1245
G371
-6562.5
1246
G369
-6577.5
1247
G367
-6592.5
1248
G365
-6607.5
1249
G363
-6622.5
1250
G361
-6637.5
1251
G359
-6652.5
1252
G357
-6667.5
1253
G355
-6682.5
1254
G353
-6697.5
1255
G351
-6712.5
1256
G349
-6727.5
1257
G347
-6742.5
1258
G345
-6757.5
1259
G343
-6772.5
1260
G341
-6787.5

Y
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-P.23April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
No.
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319
1320

Name
G339
G337
G335
G333
G331
G329
G327
G325
G323
G321
G319
G317
G315
G313
G311
G309
G307
G305
G303
G301
G299
G297
G295
G293
G291
G289
G287
G285
G283
G281
G279
G277
G275
G273
G271
G269
G267
G265
G263
G261
G259
G257
G255
G253
G251
G249
G247
G245
G243
G241
G239
G237
G235
G233
G231
G229
G227
G225
G223
G221

X
-6802.5
-6817.5
-6832.5
-6847.5
-6862.5
-6877.5
-6892.5
-6907.5
-6922.5
-6937.5
-6952.5
-6967.5
-6982.5
-6997.5
-7012.5
-7027.5
-7042.5
-7057.5
-7072.5
-7087.5
-7102.5
-7117.5
-7132.5
-7147.5
-7162.5
-7177.5
-7192.5
-7207.5
-7222.5
-7237.5
-7252.5
-7267.5
-7282.5
-7297.5
-7312.5
-7327.5
-7342.5
-7357.5
-7372.5
-7387.5
-7402.5
-7417.5
-7432.5
-7447.5
-7462.5
-7477.5
-7492.5
-7507.5
-7522.5
-7537.5
-7552.5
-7567.5
-7582.5
-7597.5
-7612.5
-7627.5
-7642.5
-7657.5
-7672.5
-7687.5

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
1321
1322
1323
1324
1325
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380

Name

G219
G217
G215
G213
G211
G209
G207
G205
G203
G201
G199
G197
G195
G193
G191
G189
G187
G185
G183
G181
G179
G177
G175
G173
G171
G169
G167
G165
G163
G161
G159
G157
G155
G153
G151
G149
G147
G145
G143
G141
G139
G137
G135
G133
G131
G129
G127
G125
G123
G121
G119
G117
G115
G113
G111
G109
G107
G105
G103
G101

-7702.5
-7717.5
-7732.5
-7747.5
-7762.5
-7777.5
-7792.5
-7807.5
-7822.5
-7837.5
-7852.5
-7867.5
-7882.5
-7897.5
-7912.5
-7927.5
-7942.5
-7957.5
-7972.5
-7987.5
-8002.5
-8017.5
-8032.5
-8047.5
-8062.5
-8077.5
-8092.5
-8107.5
-8122.5
-8137.5
-8152.5
-8167.5
-8182.5
-8197.5
-8212.5
-8227.5
-8242.5
-8257.5
-8272.5
-8287.5
-8302.5
-8317.5
-8332.5
-8347.5
-8362.5
-8377.5
-8392.5
-8407.5
-8422.5
-8437.5
-8452.5
-8467.5
-8482.5
-8497.5
-8512.5
-8527.5
-8542.5
-8557.5
-8572.5
-8587.5

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

No.
Name
X
1381
G99
-8602.5
1382
G97
-8617.5
1383
G95
-8632.5
1384
G93
-8647.5
1385
G91
-8662.5
1386
G89
-8677.5
1387
G87
-8692.5
1388
G85
-8707.5
1389
G83
-8722.5
1390
G81
-8737.5
1391
G79
-8752.5
1392
G77
-8767.5
1393
G75
-8782.5
1394
G73
-8797.5
1395
G71
-8812.5
1396
G69
-8827.5
1397
G67
-8842.5
1398
G65
-8857.5
1399
G63
-8872.5
1400
G61
-8887.5
1401
G59
-8902.5
1402
G57
-8917.5
1403
G55
-8932.5
1404
G53
-8947.5
1405
G51
-8962.5
1406
G49
-8977.5
1407
G47
-8992.5
1408
G45
-9007.5
1409
G43
-9022.5
1410
G41
-9037.5
1411
G39
-9052.5
1412
G37
-9067.5
1413
G35
-9082.5
1414
G33
-9097.5
1415
G31
-9112.5
1416
G29
-9127.5
1417
G27
-9142.5
1418
G25
-9157.5
1419
G23
-9172.5
1420
G21
-9187.5
1421
G19
-9202.5
1422
G17
-9217.5
1423
G15
-9232.5
1424
G13
-9247.5
1425
G11
-9262.5
1426
G9
-9277.5
1427
G7
-9292.5
1428
G5
-9307.5
1429
G3
-9322.5
1430
G1
-9337.5
1431
VGL
-9352.5
1432 DUMMY50 -9367.5
1433 DUMMYR3 -9382.5
1434 DUMMYR4 -9397.5

Alignment Mark
A1
A2

Y
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5
173.5
292.5

Bump size
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100
15*100

-9381 -234.5
9381 -234.5

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.24April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

3.5 Bump arrangement

50

70

Input Pad
(No.1~262)

90

unit: um
15 15 15

15 15

Output Pad
(No.263~1434)

unit: um
Alignment Mark

10

10

30

20

30

20

30

110

30

110

30

30

10

10

unit: um

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.25April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4. Interface
4.1 System interface
The HX8352-C supports System Interface and RGB Interface. Where System Interface
supports 8080 MCU (18-/16-/9-/8-bit) Parallel Interface (Type II) and Serial interface (3-wire/
4-wire). The interface mode can be selected by IM2-0 pins setting as show in Table 4.1.
IM2
0
0
0
0
1
1

IM1
0
0
1
1
0
1

IM0
0
1
0
1
ID
X

Interface
8080 System TYPE-II 18-bit
8080 System TYPE-II 9-bit
8080 System TYPE-II 16-bit
8080 System TYPE-II 8-bit
3-wire SPI
4-wire SPI
Table 4.1: Interface selection

Display data
GRAM
GRAM
GRAM
GRAM
RGB / GRAM
RGB / GRAM

The HX8352-C includes an index register (IR), which is stored the index data of internal
control register and GRAM. When DNC=L, the command via 8080 system interface write
into register. When DNC=H, GRAM data via R22h register can be written through data
bus. When the data is written into the GRAM from the MPU, it is first written into the
write-data latch and then automatically written into the GRAM by internal operation. Data is
read through the read-data latch when reading from the GRAM.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.26April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

When data is read from the GRAM to the MPU, it is first read from GRAM to the read-data
latch and then data is read to MPU through the read-data latch in next read operation.
Therefore, the first read operation data in data bus is invalid, and the second and the
following read operation data in data bus is valid.

Interface

NRD

NWR_SCL

DNC

D17D0 or other input pin

DB17DB0: 18-bit data bus


SDI_SDA, SDO
DB17DB0: 18-bit data bus
4-wire serial interface
Unused
SCL
DNC
SDI_SDA, SDO
DB9DB0: Unused,
8080 System Type II 8-bit
NRD
NWR
DNC
D17D10: 8-bit data bus
DB8DB0: Unused,
8080 System Type II 9-bit
NRD
NWR
DNC
DB17DB9: 9-bit data bus
DB9,DB0: Unused,
8080 System Type II 16-bit
NRD
NWR
DNC
DB17DB10,DB8DB1: 16-bit data bus
8080 System Type II 18-bit
NRD
NWR
DNC DB17DB0: 18-bit data bus
Table 4.2: Pin connection based on different interface
3-wire serial interface

Unused

SCL

Unused

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.27April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.1.1 8080 System interface


The selection of 8080 System interface is by IM2~IM0 pins. The parallel interface timing
diagram is described in Figure 4.1~4.2.
Write to the register
NCS
DNC
NRD
NWR_SCL
DB7-0

"index" write to index register

Command write to the register

"index" write to index register

Command read from the register

Read the register


NCS
DNC
NRD

NWR_SCL
DB7-0

Figure 4.1: 8080 System interface protocol, write/read register


Write to the graphic RAM
NCS
DNC

NRD
NWR_SCL

DB[B:0]

"22 " h

1st write data 2nd write data

3rd write data

4th write data

5th write data

Read the graphic RAM


NCS
DNC

NRD
NWR_SCL
1st read data

DB[B:0]

2nd read read

3rd read data

"22" h
Dummy Read Data

Figure 4.2: 8080 System interface protocol, write/read GRAM

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
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DATA SHEET Temporary V01

4.1.2 I80 8-bit Parallel Bus System Interface


The I80 8-bit parallel bus interface mode can be used by setting external pins IM2-0 pins to
011. Figure 4.3 is the example of I80 8-bit interface

Figure 4.3: Example of I80 8-bit bus interface

8-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 17H=05h. There is
1-pixel (3 sub-pixels) per 2-bytes.
NRESET 1
NCS
DNC
NWR_SCL
NRD

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

Pixel n+1

Pixel n

16-bits

16-bits

Color Mapping for 65K-colors (16-Bits to 18-Bits)


18-bits

Frame
Memory

18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.4: Write data for RGB 5-6-5 bits input in I80 8-bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
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DATA SHEET Temporary V01

8-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=06h. There is
1-pixel (3 sub-pixels) per 3-bytes.
NRESET 1
NCS
DNC
NWR_SCL
NRD

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

Pixel n

Pixel n+1
18-bits
-

Frame
Memory

18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.5: Write data for RGB 6-6-6 bits input in I80 8-bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

-P.30April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.1.3 I80 9-bit Parallel Bus System Interface


The I80 9-bit parallel bus interface mode can be used by setting external pins IM2-0 pins to
001. Figure 4.6 is the example of I80 9-bit interface.

Figure 4.6: Example of I80 9-bit bus interface

9-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=06h. There is
1-pixel (3 sub-pixels) per 2-bytes.
NRESET 1
NCS
DNC
NWR_SCL
NRD

DB17
DB16
DB15
DB14
DB13
DB12
DB11
DB10
DB9
Pixel n
18-bits

Frame
Memory

Pixel n+1
18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.7: Write data for RGB 6-6-6 bits input in I80 9-bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

-P.31April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.1.4 I80 16-bit Parallel Bus System Interface


The I80 16-bit parallel bus interface mode can be used by setting external pins IM2-0pins to
010. Figure 4.8 is the example of I80 16-bit interface.

Figure 4.8: Example of I80 16-Bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
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DATA SHEET Temporary V01

16-bits data bus for 16-bits/pixel (RGB 5-6-5-bits input), 65K-colors, 17H=05h. There is
1-pixel (3 sub-pixels) per 1-byte

NRESET 1
NCS
DNC
NWR_SCL
NRD

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

Pixel n

Pixel n+1

16-bits

Pixel n+2

Pixel n+3

16-bits

Color Mapping for 65K-colors (16-Bits to 18-Bits)


18-bits

Frame
Memory

18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.9: Write data for RGB 5-6-5 bits input in I80 16-bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
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DATA SHEET Temporary V01

16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=06h. There are
2-pixels (6 sub-pixels) per 3-bytes

Figure 4.10: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (DFM=0)

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=07h. There are
1-pixels (3 sub-pixels) per 2-bytes

Figure 4.11: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=07h)

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

16-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=04h. There are
1-pixels (3 sub-pixels) per 2-bytes

Figure 4.12: Write data for RGB 6-6-6 bits input in I80 16-bit parallel bus interface (R17h=04h)

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.1.5 I80 18-bit Parallel Bus System Interface


The I80 18-bit parallel bus interface mode can be used by setting external pinsIM2-0 pins to
000. Figure 4.13 is the example of interface with I8018-bit interface.

Figure 4.13: Example of I80 18-Bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

18-bits data bus for 18-bits/pixel (RGB 6-6-6-bits input), 262K-colors, 17H=06h, There is
1-pixel (3 sub-pixels) per 1-byte
NRESET 1
NCS
DNC
NWR_SCL
NRD

DB17

DB16

DB15

DB14

DB13

DB12

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Pixel n

Pixel n+1

18-bits

Frame
Memory

Pixel n+2

Pixel n+3

18-bits

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.14: Write data for RGB 6-6-6 bits input in I80 18-bit parallel bus interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

I80 Interface Data Color Coding


I80 Interface Data Color Coding for GRAM data Write
- I80 8-Bits Bus Interface (IM2-0=011)
Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

17h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

05h

06h

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Command
22h
Color
65K-Color
(1-pixels/ 2-bytes)
262K-Color
(1-pixels/ 3bytes)

Table 4.3: I80 8-Bits Interface GRAM Write Table

- I80 9-Bits Bus Interface (IM2-0=001)


Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

17h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

06h

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Register
22h
Color
262K-Color
(1-pixels/ 2bytes)

Table 4.4: I80 9-Bits Interface GRAM Write Table

- I80 16-Bits Bus Interface (IM2-0=010)


Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

17h
05h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

06h
07h
04h

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

R15

R14

R13

R12

R11

R10

G15

G14

G13

G12

G11

G10

B15

B14

B13

B12

B11

B10

R25

R24

R23

R22

R21

R20

G25

G24

G23

G22

G21

G20

B25

B24

B23

B22

B21

B20

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Command
22h
Color
65K-Color
262K-Color
(2-pixels/ 3bytes)
262K-Color
(1-pixels/ 2bytes)
262K-Color
(1-pixels/ 2bytes)

Table 4.5: I80 16-Bits Interface GRAM Write Table

- I80 18-Bits Bus Interface (IM2-0=000)


Register DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Command
x
x
x
x
x
x
x
x
x
0
0
1
0
0
0
1
0
x

17h
06h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9


R5

R4

R3

R2

R1

R0

G5

G4

G3

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

G2

G1

G0

B5

B4

B3

B2

B1

B0

Register
22h
Color
262K-Color

Table 4.6: I80 18-Bits Interface GRAM Write Table

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

I80 Interface Data Color Coding for GRAM data Read


- I80 8-Bits Bus Interface (IM2-0=011)
Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9


0

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

Read Data
foramt

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Command
22h
Color
Dummy Read
262K-Color
(1-pixels/ 3-bytes)

Table 4.7: I80 8-Bits Interface GRAM Read Table

- I80 9-Bits Bus Interface (IM2-0=001)


Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9


0

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

Read Data
foramt

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Register
22h
Color
Dummy Read
262K-Color
(1-pixels/ 2bytes)

Table 4.8: I80 9-Bits Interface GRAM Read Table

- I80 16-Bits Bus Interface (IM2-0=010)


Register
Command

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9


x

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

Read Data
foramt

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

R15

R14

R13

R12

R11

R10

G15

G14

G13

G12

G11

G10

B15

B14

B13

B12

B11

B10

R25

R24

R23

R22

R21

R20

G25

G24

G23

G22

G21

G20

B25

B24

B23

B22

B21

B20

Command
22h
Color
Dummy Read
262K-Color
(2-pixels/ 3bytes)

Table 4.9: I80 16-Bits Interface GRAM Read Table

- I80 18-Bits Bus Interface (IM2-0=000)


Register DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
Command
x
x
x
x
x
x
x
x
x
0
0
1
0
0
0
1
0
x

Read Data
foramt

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0
x

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

Register
22h
Color
Dummy Read
262K-Color

Table 4.10: I80 18-Bits Interface GRAM Read Table

- Data Mapping Extend to 18-bit Data


GRAM Data
Input Data
18-bit
16-bit

EPF[1:0]
X
00
01
10
11

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

R5
R4
R4
R4

R4
R3
R3
R3

R3
R2
R2
R2

R2
R1
R1
R1

DB5

DB4

DB3

DB2

DB1

DB0

R1 R0 G5 G4 G3 G2 G1 G0 B5
R0 0 G5 G4 G3 G2 G1 G0 B4
R0 1 G5 G4 G3 G2 G1 G0 B4
R0 R4 G5 G4 G3 G2 G1 G0 B4
Reference EPF[1:0] setting in R6Bh

DB8

DB7

DB6

B4
B3
B3
B3

B3
B2
B2
B2

B2
B1
B1
B1

B1
B0
B0
B0

B0
0
1
B4

Table 4.11: Data Mapping Extend to 18-bit Data

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.2 Serial Data Transfer Interface


The HX8352-C supports 3-wire and 4-wire serial data transfer interface, the interface
selection by setting IM2-0 pins, The IM2-0 set 10x is select option1 3 wire serial bus. The
IM2-0 set 11x is select option3 4 wire serial bus.
The 3 wire serial bus is use: chip select line (NCS), the serial transfer clock line (NWR_SCL).
When SDA_EN=0, SDI_SDA pin is for serial interface input data and SDO pin is for serial
interface output data. When SDA_EN=1, SDI_SDA pin is for serial interface input/output data
and SDO pin is unused.
The 4 wire serial bus is use: chip select line (NCS), data/command select (DNC), the serial
transfer clock line (NWR_SCL). When SDA_EN=0, SDI_SDA pin is for serial interface input
data and SDO pin is for serial interface output data. When SDA_EN=1, SDI_SDA pin is for
serial interface input/output data and SDO pin is unused.

4.2.1 3-wire serial interface


As the chip select signal (NCS) goes low, the start byte needs to be transferred first. The start
byte is made up of 6-bit bus device identification code; register select (RS) bit and read/write
operation (RW) bit. The five upper bits of 6-bit bus device identification code must be set to
01110, and the least significant bit of the identification code must be set as the external pin
IM0 input as ID.
The seventh bit (RS) of the start byte determines internal index register or register, GRAM
accessing. RS must be set to 0 when writing data to the index register or reading the status
and it must be set to 1 when writing or reading a command or GRAM data. The read or write
operation is selected by the eighth bit (RW) of the start byte. The data is written to the chip
when R/W = 0, and read from chip when RW = 1.
RS
0
1
1

R/W
Function
0
Set index register
0
Writes Instruction or GRAM data
1
Reads command (Not support GRAM read)
Table 4.12: Function of RS and R/W bit bus

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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
A) TransferTiming Format in Serial Bus Interface for Index Register or Register Wirte
1

10

11

12

13

14

15

16

NWR_SCL

Start

End

NCS

SDI_SDA

" 01110" ID
Device ID code
Start byte

RS

RW

S7

S6

S5

S4

S3

S2

S1

S0

Index register set ,


register set ,

Figure 4.15: Index register read/write timing in 3-wire serial bus system interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
A )1616-bit Data Transfer Timing Format in Serial Bus Interface for GRAM write ( Index 17h
17h= 05)
05)
1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

NWR_SCL

Start

End

NCS

"01110" ID

SDA

RS RW R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

Device ID code

B1

B0

Start byte

65k colors mapping (16 Bits to 18Bits)


18- bits
Frame
Memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

B )1818-bit Data Transfer Timing Format in Serial Bus Interface for GRAM write ( Index 17H
17H=06)
06)
1

10

11

12

13

14

15 16

17

18

19

20 21

22

23

24

25

26

NWR_SCL

End

Start
NCS

R
" 01110" ID

SDA

RS RW R5

R4

R3

R2

R1

R0

G5

G4

G3

B
G2

G1

G0

B5

B4

B3

B2

B1

B0

Device ID code
Start byte

18- bits
Frame
Memory

R1 G1 B1 R2 G2 B2 R3 G3 B3

Figure 4.16: Data write timing in 3-wire serial bus system interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.2.2 4-wire serial interface


4-pin serial case, data packet contains just transmission byte and control bit DNC is
transferred by DNC pin. If DNC is low, the transmission byte is command byte. If DNC is high,
the transmission byte is stored to index register or GRAM. The MSB is transmitted first. The
serial interface is initialized when NCS is high. In this state, NWR_SCL clock pulse or SDA
data have no effect. A falling edge on NCS enables the serial interface and indicates the start
of data transmission.
4-Wire Serial Interface Protocol
DNC
NCS
NWR_SCL
D7

SDA

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Parameter

Command
NCS can be "H" between
Command and parameter

Figure 4.17: Index register write timing in 4-wire serial bus system interface
1616-bit Data Transfer Timing Format in 4-wire Serial Bus Interface for GRAM write ( Index 17h
17h= 05)
05)

NWR_SCL
SDA

R1 4 R13 R1 2 R1 1 R10 G1 5 G14 G13 G12 G11 G10 B1 4

B1 3

B1 2

B1 1

B1 0

16-bit

65K colors mapping (16-bit to 18 bit)


18-bit
GRAM

R1

G1

B1

R2

G2

B2

1818-bit Data Transfer Timing Format in 4-wire Serial Bus Interface for GRAM write ( Index 17h
17h= 06)
06)

NWR_SCL
SDA

R15

R14 R13

R12

R11 R10

G15 G14 G13 G12 G11 G10

B15

B14

B13

B12

B11

B10

18-bit

GRAM

R1

G1

B1

R2

G2

B2

R3

G3

B3

Figure 4.18: Data write timing in 4-wire serial bus system interface

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

-P.44April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.3

RGB interface
The HX8352-C uses 16, 18-bit parallel RGB interface which includes: HSYNC, VSYNC, DE,
PCLK, DB17~DB0. The interface is active after Power On sequence. Pixel clock (PCLK) is
running all the time without stopping and it is used to entering HSYNC, VSYNC, DE and
DB17~DB0 lines states when there is a rising edge of the PCLK. The PCLK cannot be used
as continue internal clock for other functions of the display module e.g. Standby mode etc.
Vertical synchronization (VSYNC) is used to tell when there is received a new frame of the
display. This is negative (-, 0, low) active and its state is read to the display module by a
rising edge of the PCLK-line. Horizontal synchronization (HSYNC) is used to tell when there
is received a new line of the frame. This is negative (-, 0, low) active and its state is read to
the display module by a rising edge of the PCLK-line. Data enable (DE) is used to tell when
there is received RGB information that should be transferred on the display. This is positive
(+, 1, high) active and its state is read to the display module by a rising edge of the
PCLK-line. 18 bit: DB17-DB12(R5-R0), DB11-DB6(G5-G0) and DB5-DB0(B5-B0); 16 bit:
DB15-DB11(R4- R0), DB10-DB5(G5-G0) and DB4-DB0(B4-B0) are used to tell what is the
information of the image that is transferred on the display (when DE =1 and there is a rising
edge of PCLK). DB17~DB0 lines can be set to 0 (low) or 1 (high). These lines are read
by a rising edge of the PCLK-line.
The pixel clock cycle is described in the following figure.

Figure 4.19: PCLK cycle


Note: PCLK is an unsynchronized signal (It can be stopped).

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

General Timing Diagram

Figure 4.20: General Timing Diagram


1 Frame

VBP

432

Panel
Display
VSYNC

Display

Area

HSYNC
DE
Start to latch data

PCLK
HBP
HSYNC
PCLK
DE
Data Bus

D1

D2

D238

D239

D240

Figure 4.21: DPI timing diagram

The image information must be correct on the display, when the timings are in range on the
interface. However, the image information can be incorrect on the display, when timings are
out of the range on the interface (Out of the range timings cannot cause any damage on the
display module or it cannot cause any damage on the host side). The correct image
information must be displayed automatically (by the display module) on the next frame
(vertical sync.), when there is returned from out of the range to in range interface timings.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

4.3.1 RGB Interface Data Color Coding


The RGB interface includes two types which are 16-/ 18-bit data format by register R17h to
select.
R17h

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DPI Interface
mode

50h

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B4

B3

B2

B1

B0

16-bit 65K-Color

60h

R5

R4

R3

R2

R1

R0

G5

G4

G3

G2

G1

G0

B5

B4

B3

B2

B1

B0

18-bit 262K-Color

Table 4.13: DPI Input Data Format


PCLK
DB17,R4

R 1, BIT4
BIT4

R 2, BIT4
BIT4

R 3, BIT4
BIT4

R 4 , BIT4
BIT4

R 5 , BIT4
BIT4

DB16,R3

R 1, BIT3
BIT3

R 2, BIT3
BIT3

R 3, BIT3
BIT3

R 4 , BIT3
BIT3

R 5 , BIT3
BIT3

DB15,R2

R 1, BIT2
BIT2

R 2, BIT2
BIT2

R 3, BIT2
BIT2

R 4 , BIT2
BIT2

R 5 , BIT2
BIT2

DB14,R1

R 1, BIT1
BIT1

R 2, BIT1
BIT1

R 3, BIT1
BIT1

R 4 , BIT1
BIT1

R 5 , BIT1
BIT1

DB13,R0

R 1, BIT0
BIT0

R 2, BIT0
BIT0

R 3, BIT0
BIT0

R 4 , BIT0
BIT0

R 5 , BIT0
BIT0

DB11,G5

G 1 , BIT5
BIT 5

G 2, BIT5
BIT 5

G 3, BIT5
BIT 5

G 4, BIT5
BIT 5

G 5, BIT5
BIT 5

DB10,G4

G 1 , BIT4
BIT 4

G 2, BIT4
BIT 4

G 3, BIT4
BIT 4

G 4, BIT4
BIT 4

G 5, BIT4
BIT 4

DB9,G3

G 1 , BIT3
BIT 3

G 2, BIT3
BIT 3

G 3, BIT3
BIT 3

G 4, BIT3
BIT 3

G 5, BIT3
BIT 3

DB8,G2

G 1 , BIT2
BIT2

G 2, BIT2
BIT2

G 3, BIT2
BIT2

G 4, BIT2
BIT2

G 5, BIT2
BIT2

DB7,G1

G 1 , BIT1
BIT 1

G 2, BIT1
BIT 1

G 3, BIT1
BIT 1

G 4, BIT1
BIT 1

G 5, BIT1
BIT 1

DB6,G0

G 1 , BIT0
BIT 0

G 2, BIT0
BIT 0

G 3, BIT0
BIT 0

G 4, BIT0
BIT 0

G 5, BIT0
BIT 0

DB5,B4

B 1, BIT4
BIT4

B 2, BIT4
BIT4

B 3 , BIT4
BIT4

B 4 , BIT4
BIT4

B 5 , BIT4
BIT 4

DB4,B3

B 1, BIT3
BIT3

B 2, BIT3
BIT3

B 3 , BIT3
BIT3

B 4 , BIT3
BIT3

B 5 , BIT3
BIT 3

DB3,B2

B 1, BIT2
BIT2

B 2, BIT2
BIT2

B 3 , BIT2
BIT2

B 4 , BIT2
BIT2

B 5 , BIT2
BIT 2

DB2,B1

B 1, BIT1
BIT1

B 2, BIT1
BIT1

B 3 , BIT1
BIT1

B 4 , BIT1
BIT1

B 5 , BIT1
BIT 1

DB1,B0

B 1, BIT0
BIT0

B 2, BIT0
BIT0

B 3 , BIT0
BIT0

B 4 , BIT0
BIT0

B 5 , BIT0
BIT0

DB12

DB0
16Bits

16Bits

16Bits

Color Mapping for 65K data (16-bit to 18-bit)


18Bits

Pixels on
the display

R
1

18Bits
G
1

B
1

R
2

18Bits
G
2

B
2

R
3

G
3

B
3

Figure 4.22: 16 bit data bus color order on DPI interface

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
PCLK
DB17,R5
DB16,R4
DB15,R3
DB14,R2
DB13,R1
DB12,R0
DB11,G5
DB10,G4
DB9,G3
DB8,G2
DB7,G1
DB6,G0
DB5,B5
DB4,B4
DB3,B3
DB2,B2
DB1,B1
DB0,B0
18Bits

Pixels on
the display

18Bits

R
1

G B
1 1

18Bits

R G
2 2

B
2

R G
3 3

B
3

Figure 4.23: 18 bit data bus color order on DPI interface

- Data Mapping Extend to 18-bit Data


GRAM Data
Input Data
18-bit
16-bit

EPF[1:0]
X
00
01
10
11

DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

R5
R4
R4
R4

R4
R3
R3
R3

R3
R2
R2
R2

R2
R1
R1
R1

DB5

DB4

DB3

DB2

DB1

DB0

R1 R0 G5 G4 G3 G2 G1 G0 B5
R0 0 G5 G4 G3 G2 G1 G0 B4
R0 1 G5 G4 G3 G2 G1 G0 B4
R0 R4 G5 G4 G3 G2 G1 G0 B4
Reference EPF[1:0] setting in R6Bh

DB8

DB7

DB6

B4
B3
B3
B3

B3
B2
B2
B2

B2
B1
B1
B1

B1
B0
B0
B0

B0
0
1
B4

Table 4.14: DPI Data Mapping Extend to 18-bit Data

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

DPI interface displaying moving pictures can be selected to rewrite into the GRAM or not
through GRAM. The selection is set by register DM[1:0] and RM.
RM The bit is used to select an interface for the Frame Memory access operation. The Frame
Memory is accessed only via the interface defined by RM bit. Because the interface can be
selected separately from display operation mode, writing data to the Frame Memory is
possible via system interface when RM = 0, even in the DPI display operation.
RM setting is enabled from the next frame. Wait 1 frame to transfer data after setting.
RM
0
1

Interface for RAM access


DBI Interface (CPU)
DPI Interface (RGB)

DM[1:0] The bit is used to select display operation mode. The setting allows switching
between display operation in synchronization with internal oscillation clock, VSYNC, or DPI
signal.
Note that switching between DPI operation is prohibited.

DM 1
0
0
1
1

DM 0
0
1
0
1

Operation Mode
Internal clock operation
(displaying still pictures)
DPI interface : capture mode (1)
(displaying moving pictures)
DPI interface : capture mode (2)
(rewriting still pictures while
displaying moving pictures)
DPI interface : through mode (1)
(displaying moving pictures)
DPI interface : through mode (2)
(displaying moving pictures)
Internal clock operation
DPI data format

Display Mode
Internal oscillation clock
DPI interface(GRAM)
RGB data bypass GRAM mode 1
RGB data bypass GRAM mode 2
Frame Memory Access
Setting (RM)
MPU interface
(RM=0)
DPI interface
(RM=1)

Display Operation Mode


(DM[1:0])
Internal clock operation
(DM[1:0]=00)
DPI interface : VS & HS
(DM[1:0]=01)

MPU interface
(RM=0)

DPI interface : VS
(DM[1:0]=01)

Bypass frame memory


Bypass frame memory
DPI interface
(RM=1)

DPI interface : VS & HS & DE


(DM[1:0]=10)
DPI interface : VS & HS
(DM[1:0]=11)
Internal clock operation
(DM[1:0]=00)

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5. Function Description
5.1 Display data GRAM
HX8352-C support the display data RAM that stores display dots and consists of 1,866,240
bits (240x432x18 bits). There is no restriction on access to the RAM even when the display
data on the same address is loaded to DAC There will be no abnormal visible effect on the
display when there is a simultaneous Panel Read and Interface Read or Write to the same
location of the Frame Memory.

5.1.1

Address counter (AC)

The HX8352-C contains an address counter (AC) which assigns address for writing/reading
pixel data to/from GRAM. The address pointers set the position of GRAM whose addresses
range:
MV
0
1

X range
Y range
Panel resolution
0~239d.
0~431d.
240 RGBX432 dot
0~431d.
0~239d.
Table 5.1: Addresses counter range

Every time when a pixel data is written into the GRAM, the X address or Y address of AC will
be automatically increased by 1 (or decreased by 1), which is decided by the register (MV,
MX and MY bit) setting.
To simplify the address control of GRAM access, the window address function allows for
writing data only to a window area of GRAM specified by registers. After data is written to the
GRAM, the AC will be increased or decreased within setting window address-range which is
specified by the Column address register (start: SC, end: EC) or the Row address register
(start: SP, end: EP). Therefore, the data can be written consecutively without thinking a data
wrap by those bit function.

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.1.2 Source, gate and memory map

S715

S716

S717

S718

S719

S720

BGR=1

---

B GR=0

S6

BGR=1

S5

B GR=0

S4
B GR=0

RA

S3

BGR=1

S2
BGR=1

S1
BGR=0

Source Out

SA

MY=0 MY=1
0
1

431

429

428

427

426

425

424

8
9

423

--------------------:

:
7

425
426

6
5

427

428

429

2
1

CA

R1 5-0

G1 5-0 B1 5-0

422

431

G0 5-0 B0 5-0

430

424

430

R0 5-0

0
MX=0

MX=1

239

1
238

R238 5-0 G238 5-0 B238 5-0 R239 5-0 G239 5-0 B239 5-0

ML=0

ML=1

0
1

431

429

428

427

426

425

424

8
9

423

430

422

:
---------------------

238

239

424

425
426

6
5

427

428

429
430

2
1

431

Note:RA=Row Address
CA=Colum Address
SA=Scan Address
MX=Colum address direction parameter
MY=Row address direction parameter
ML=Scan direction parameter
RGB=Red,Green and Blue pixel position change
Table 5.2: Memory map of 240RGB x432 resolution

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.1.3 MCU to memory write / read direction


Data stream from MCU is like
this figure

E
Figure 5.1: MCU to Memory write / read direction

The data is written in the order as illustrated above. The counter that dictates which physical
memory the data is to be written is controlled by Memory Access Control Command, Bits
MY, MX, MV as described below.

Physical Row Pointer

MV

MX

MY

Figure 5.2: MY, MX, MV setting


MV
0

MX
0

MY
0

0
0
1
1
1
1

1
1
0
0
1
1

0
1
0
1
0
1

CASET
Direct to Physical Column Pointer

PASET
Direct to Physical Row Pointer
Direct to (431-Physical Row Pointer)
Direct to Physical Column Pointer
with SC
Direct to (239-Physical Column Pointer) Direct to Physical Row Pointer
Direct to (239-Physical Column Pointer) Direct to (431-Physical Row Pointer)
Direct to Physical Row Pointer
Direct to Physical Column Pointer
Direct to (431-Physical Row Pointer)
Direct to Physical Column Pointer
Direct to Physical Row Pointer
Direct to (239-Physical Column Pointer)
Direct to (431-Physical Row Pointer)
Direct to (239-Physical Column Pointer)
Table 5.3: MY, MX, MV setting

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

The following figure depicts the update method set by MV, MX and MY bit.
Display Data
Direction

Memory Access
Control
MV MX MY

Image in the Host

H/W Position (0,0)

Normal

Image in the Driver (GRAM)


B

X,Y address (0,0)


X: CASET
Y: RASET

E
B

Y-Mirror

H/W Position (0,0)

1
E

X,Y address (0,0)


X: CASET
Y: RASET

X-Mirror

0
E
B

X-Mirror
Y-Mirror

1
E
B

X-Y
Exchange

H/W Position (0,0)

X,Y address (0,0)


X: CASET
Y: RASET

E
B

X-Y
Exchange
Y-Mirror

H/W Position (0,0)

1
X,Y address (0,0)
X: CASET
Y: RASET

E
B

X-Y
Exchange
X-Mirror

H/W Position (0,0)

B
B

X,Y address (0,0)


X: CASET
Y: RASET

0
E

X-Y
Exchange
X-Mirror
Y-Mirror

H/W Position (0,0)

1
E

X,Y address (0,0)


X: CASET
Y: RASET

Figure 5.3: Address direction settings

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.1.4 Fully display, partial display, vertical scrolling display


5.1.4.1 Fully display
Example: (1) 240RGBx432 dot display mode.
(2) Normal Display Mode.
(3) SC=0x000h, EC=0x0EFh and SP=0x000h, EP=0x1AFh, ML=0.

------1AA000H
1AB000H
1AC000H
1AD000H
1AE000H
1AF000H

---------------------------------------------------------

0EEh
DB---DB
17 ---0
0000EEH
0010EEH
0020EEH
0030EEH
0040EEH
0050EEH

0EFh
DB---DB
17 ---0
0000EFH
0010EFH
0020EFH
0030EFH
0040EFH
0050EFH

---------

-------

------1AAh
1ABh
1ACh
1ADh
1AEh
1AFh

---------

-------

001h
DB---DB
17 ---0
000001H
001001H
002001H
003001H
004001H
005001H
-------

000h
001h
002h
003h
004h
005h

000h
DB---DB
17 ---0
000000H
001000H
002000H
003000H
004000H
005000H

GRAM

1AA001H
1AB001H
1AC001H
1AD001H
1AE001H
1AF001H

-------------------------------------------------

1AA0EEH
1AB0EEH
1AC0EEH
1AD0EEH
1AE0EEH
1AF0EEH

1AA0EFH
1AB0EFH
1AC0EFH
1AD0EFH
1AE0EFH
1AF0EFH

Table 5.4: 240RGB x 432 resolution (SRAM assignment)

Figure 5.4: 240RGB x 432 resolution

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.1.4.2 Partial Display


Example: (1) 240RGBx432 dot display mode.
(2) PLTON=1.
(3) SR[15:0]=0002h, ER[15:0]=01ABh, ML=0.

000h
001h
002h
003h
004h
005h

00h
DB---DB
17 --- 0
000000H
001000H
002000H
003000H
004000H
005000H

01h
DB---DB
17 --- 0
000001H
001001H
002001H
003001H
004001H
005001H

GRAM

EFh
DB---DB
17 --- 0
0000EFH
0010EFH
0020EFH
0030EFH
0040EFH
0050EFH

-------

-------

---------

-------

-------

1AAh
1ABh
1ACh
1ADh
1AEh
1AFh

1AA000H
1AB000H
1AC000H
1AD000H
1AE000H
1AF000H

1AA001H
1AB001H
1AC001H
1AD001H
1AE001H
1AF001H

-------------------------------------------------

1AA0EEH
1AB0EEH
1AC0EEH
1AD0EEH
1AE0EEH
1AF0EEH

1AA0EFH
1AB0EFH
1AC0EFH
1AD0EFH
1AE0EFH
1AF0EFH

LCD panel
S/G pins

Pixel 1

Pixel 2

---------

Pixel239

Pixel240

G1
G2
G3
G4
G5
G6

000000H
001000H
002000H
003000H
004000H
005000H

000001H
001001H
002001H
003001H
004001H
005001H

-------------------------------------------------

0000EEH
0010EEH
0020EEH
0030EEH
0040EEH
0050EEH

0000EFH
0010EFH
0020EFH
0030EFH
0040EFH
0050EFH

-------

-------

---------

-------

-------

Non-display area
-> 4 lines

-------------------------------------------------

EEh
DB---DB
17 --- 0
0000EEH
0010EEH
0020EEH
0030EEH
0040EEH
0050EEH

-------

Display area
-> 426 lines

---------

-------

Non-display area
-> 2 lines

---------

G427
G428
G429
G430
G431
G432

1AA000H
1AB000H
1AC000H
1AD000H
1AE000H
1AF000H

1AA001H
1AB001H
1AC001H
1AD001H
1AE001H
1AF001H

-------------------------------------------------

1AA0EEH
1AB0EEH
1AC0EEH
1AD0EEH
1AE0EEH
1AF0EEH

1AA0EFH
1AB0EFH
1AC0EFH
1AD0EFH
1AE0EFH
1AF0EFH

Table 5.5: Memory map of partial display

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.1.4.3 Vertical scrolling display


When SCROL bit is set to 1, the scrolling display mode is active and the vertical scrolling
display is specified by TFA, VSA, BFA bits (R0Eh~R13h) and VSP bits (R14h~R15h).

Original

Scrolling
TFA

VSA

BFA

Figure 5.5: Vertical scrolling

When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=Panel total scan lines. In


this case, scrolling is applied as shown below.

Example:
When Vertical Scrolling Definition Parameters (TFA+VSA+BFA)=432. In this case, scrolling is
applied as shown below.
Example (1) TFA=2, VSA=430, BFA=0 when ML=0

Figure 5.6: Memory map of vertical scrolling 1

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

Example (2) TFA=2, VSA=428, BFA=2 when ML=0

Figure 5.7: Memory map of vertical scrolling 2

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

Vertical scroll example


There are 2 types of vertical scrolling, which are determined by the TFA, VSA, BFA bits
(R0Eh~R13h) and VSP bits (R14h~R15h).
Case 1: TFA + VSA + BFA432
Do not set TFA + VSA + BFA432. In that case, unexpected picture will be shown.
Case 2: TFA + VSA + BFA=432 (Scrolling)
Example (1) When TFA=0, VSA=432, BFA=0 and VSP=40. ML=0
P h y s ic a l L in e
P o in t e r

M e m o r y P h ysica l A x is
(0 ,0 )

D isp la y
A xis ( 0 , 0 )

2
1

VS CRS A DD
1

F ra m e
M e m o ry

D is p la y
In cr e m e n t
V S CRS A DD

P h y s ic a l L in e
P o in t e r

D isp la y
A xis ( 0 ,0 )

V S CRS A DD

D is p la y

F ra m e
M e m o ry

Figure 5.8: Vertical scroll example 1

Example (2) TFA=30, VSA=402, BFA=0 and VSP =80. ML=1


Physical Line
Pointer

Memory Physical Axis


(0,0)

Display
Axis (0,0)

VSCRSADD

Frame
Memory

Display
Increment
VSCRSADD

Physical Line
Pointer

Memory Physical Axis


(0,0)

TFA

TFA

Display
Axis (0,0)

2
3

VSCRSADD
3

2 1

TFA

Frame
Memory

TFA

Display

Figure 5.9: Vertical scroll example 2

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240RGBx432dots, TFT Mobile Single Chip Driver
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5.2 Tearing Effect Output Line


The Tearing Effect output line supplies to the MPU a Panel synchronization signal. This
signal can be enabled or disabled by the Tearing Effect Line Off & On commands. The mode
of the Tearing Effect signal is defined by the parameter of the Tearing Effect Line On
command. The signal can be used by the MPU to synchronize Frame Memory Writing when
displaying video images.

5.2.1 Tearing Effect Line Modes


Mode 1, the Tearing Effect Output signal consists of V-Blanking Information only:

Figure 5.10: Tearing Effect Output signal mode 1


tvdh= The LCD display is not updated from the Frame Memory
tvdl= The LCD display is updated from the Frame Memory (except Invisible Line see below)

Under Mode1, the TE output timing will be defined by TSEL[15:0] setting.


Ex: 1. TSEL[15:0]=0, then TE signal will output after last Line finished.
TSEL[15:0]=2, then TE signal will output at second Line start.

Figure 5.11: TE Delay Output

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Mode 2, the Tearing Effect Output signal consists of V-Blanking and H-Blanking Information,
there is one V-sync and 432 H-sync pulses per field.

Figure 5.12: Tearing Effect Output signal mode 2


thdh= The LCD display is not updated from the Frame Memory
thdl= The LCD display is updated from the Frame Memory (except Invisible Line see above)

Under Mode2, the H-sync pulese output amount will be defined by TSEL[15:0] setting.
Ex: 1. TSEL[15:0]=0, then TE signal will output 432 H-sync.
TSEL[15:0]=1, then TE signal will output 431 H-sync.

Figure 5.13: TE Output for TELINE setting

Figure 5.14: Tearing Effect Output signal


Note: During Sleep In Mode, the Tearing Output Pin is active Low

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5.2.2 Tearing Effect Line Timing


The Tearing Effect signal is described below:

Figure 5.15: Tearing Effect Line Timing

Idle Mode Off (Frame Rate = 60Hz)


Symbol
tvdl
tvdh
thdl
thdh

Parameter
Vertical Timing Low Duration
Vertical Timing High Duration
Horizontal Timing Low Duration
Horizontal Timing High Duration

Min.
1000
-

Max.
500

Unit
ms
us
us
us

description
-

NOTE: The timings in Table 5.6 apply when MADCTL ML=0 and ML=1

Table 5.6: AC characteristics of Tearing Effect Signal

The signals rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.

tr

tf

Figure 5.16: Rise and Fall times of TE signal

The Tearing Effect Output Line is fed back to the MPU and should be used as shown below to
avoid Tearing Effect:

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Example 1: MPUs Write is Faster than Panels Read.

MCU to Memory
1st

Time

432th

TE output signal
Time

Memory to LCD
Time
1st

Image on LCD

432th

Figure 5.17: Tearing Effect - Example 1-1

Data write to Frame Memory is now synchronized to the Panel Scan. It should be written
during the vertical sync pulse of the Tearing Effect Output Line. This ensures that data is
always written ahead of the panel scan and each Panel Frame refresh has a complete new
image:

Figure 5.18: Tearing Effect - Example 1-2

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Example 2: MPUs Write is Slower than Panels Read.

MCU to Memory
1st

Time

432th

TE output signal
Time

Memory to LCD
Time
1st

Image on LCD

432th

Figure 5.19: Tearing Effect - Example 2-1

The MPU to Frame Memory write begins just after Panel Read has commenced i.e. after one
horizontal sync pulse of the Tearing Effect Output Line. This allows time for the image to
download behind the Panel Read pointer and finishing download during the subsequent
Frame before the Read Pointer catches the MPU to Frame memory write position.

Figure 5.20: Tearing Effect - Example 2-2

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5.3 Oscillator
The HX8352-C can oscillate an internal R-C oscillator with an internal oscillation resistor (Rf).
The oscillation frequency is changed according to the RADJ[3:0] internal register. The default
frequency is 3.69MHz.
RGB Display Mode

PCLK

Display
Controller
DIV[
DIV[1:0]

Internal Display Mode

Oscillator
Clock

3.69MHz
69MHz

fosc
RADJ[
RADJ[3:0]

Frequency
Divider 1
DC0
DC0[1:0]

Step up Circuit 1
( for DDVDH)
DDVDH)

Frequency
Divider 2
DC1
DC1[1:0]

Step up Circuit 2
( for VCL,
VCL,VGH,
VGH,VGL)
VGL)

PCLK
RGB Display Mode

PWM_
PWM_CLK
(for Backlight CABC)
CABC)

Figure 5.21: OSC aritecture

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5.4 Source driver


The HX8352-C contains a 720 channels of source driver which is used for driving the source
line of TFT LCD panel. The source driver converts the digital data from GRAM into the analog
voltage for 720 channels and generates corresponding gray scale voltage output, which can
realize a 262K colors display simultaneously. Since the output circuit of this source driver
incorporates an operational amplifier, a positive and a negative voltage can be alternately
outputted from each channel.

Inversion mode

1 line type
Date
Line
#1

Date
Line
#2

Date
Line
#3

Date
Line
#718

Date
Line
#719
718

...

Date
Line
#1

Date
Line
#720
719

Frame type

720

Gate#1

Date
Line
#2

Date
Line
#3

Date
Line
#718

...

Date
Line
#719

Date
Line
#720

718

719

720

718

719

720

718

719

720

718

719

720

Gate#1

718

...

720

719

...

Gate#2

...

718

719

720

718

719

720

Gate#3

Gate#2

...

Gate#3

...

...

Gate#4

Date
Line
#1

Date
Line
#2

Date
Line
#3
+

Date
Line
#718

...

Date
Line
#719
+

Gate#4

Date
Line
#1

Date
Line
#720
+

Gate#1

Date
Line
#2

Date
Line
#3

Date
Line
#718

...

Date
Line
#719

Date
Line
#720

+-

Gate#1

...

...

Gate#2

...

Gate#2

Gate#3

...

Gate#3

...

...

Gate#4

Gate#4

Figure 5.22: Source channels of different inversion mode

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240RGBx432dots, TFT Mobile Single Chip Driver
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5.5 Gate Driver


The HX8352-C contains a 432 gate channels of gate driver (G1~G432) which is used for
driving the gate. The gate driver level is VGH when scan some line, VGL the other lines.
HX8352-C can set internal register SM and GS bit to determine the pin assignment of gate.
The SM and GS setting allows changing the shift direction of gate outputs by connecting LCD
panel with the HX8352-C.
SM

GS

Scan direction
G1
G3

EvenG2
number line G4

Oddnumber line

TFT panel
0

G429
G431

G430
G432

HX8352-C
G1, G2, G3, G4,......,G429, G430, G431, G432
G1
G3

EvenG2
number line G4

Oddnumber line

TFT panel
0

G429
G431

G430
G432

HX8352-C
G432, G431, G430, G429,......,G4, G3, G2, G1
G1
TFT panel
G431

Evennumber line G2
1

Oddnumber line

0
G432

HX8352-C
G1, G3,....,G429, G431, G2, G4,...., G430, G432
G1
TFT panel
G431

Evennumber line G2
1

Oddnumber line

1
G432

HX8352-C
G432, G430,....,G4, G2, G431, G429,...., G3, G1

Figure 5.23: Scan direction of Gate Driver

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240RGBx432dots, TFT Mobile Single Chip Driver
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5.6 Power generation


5.6.1 LCD power generation scheme
VGH

DDVDH

DC/DC
converter

VREG1
VREG1
VCOMH

VCI (2.5V ~ 3.3V)


IOVCC (1.65V
65V ~ 3.3V)
VDDD

VSSD,
VSSD,VSSA
DC/DC
converter
VCOML

VCL (-VCI)
VCI)

VGL

Figure 5.24: LCD power generation scheme

Voltage configuration
HX8352-C has an internal power supply circuit to drive a-Si LCD panel. Please set up each
voltage output according to the LCD panel.
Name
DDVDH
VCL
VREG1
VGH
VGL
VCOMH
VCOML

Function
Set up Value
DC/DC converter circuit output
4.5 V or 6.0V
DC/DC converter circuit output
-VCI
Reference voltage for gamma circuit
4.0 ~ 5.5V
TFT gate on voltage output
10 ~ 18V
TFT gate off voltage output
-5 ~ -12.5V
TFT common electrode voltage
3 ~ (DDVDH-0.5)V
TFT common electrode voltage
(VCL+0.5) ~ 0V
Table 5.7: Power supply voltage configuration

Note
Reference register
Reference register
Reference register
Reference register
Reference register

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5.6.2 Power supply circuit


The power circuit of HX8352-C is used to generate supply voltages for LCD panel driving and
backlight control.

C31P

C11P

C31

C11

C31N
Cvcl

Step up
Circuit 3

C11N

VCL

Step up
Circuit 1

Reference
Voltage
Generation
Circuit

C12P
C12

C12N
DDVDH

Cddvdh

VREG1
Reference
Voltage
Generation
Circuit

VCI
VSSA
VSSD
IOVCC

DDVDH
Cvddd

VDDD

Reference
Voltage
Generation
Circuit

C21N
C21

C21P
Step up
Circuit 2

VPP

VPP
Generation
Circuit

VGH

C22P
C22

C22N
VGH
VGL

Cgh
Cgl

Figure 5.25: Block diagram of HX8352-C power circuit with internal charge pump

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240RGBx432dots, TFT Mobile Single Chip Driver
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Specification of connected passive component


Capacitor
Cvddd (VDDD)
Cddvdh (DDVDH)
Cvcl (VCL)
C11 (C11P/N)
C12 (C12P/N)
C31 (C31P/N)
C21 (C21P/N)
C22 (C22P/N)
Cgh (VGH)
Cgl (VGL)

Recommended voltage
Capacity
6V
1 F (B characteristics)
10V
1 F (B characteristics)
6V
1 F (B characteristics)
6V
1 F (B characteristics)
6V
1 F (B characteristics)
6V
1 F (B characteristics)
10V
1 F (B characteristics)
10V
1 F (B characteristics)
25V
1 F (B characteristics)
16V
1 F (B characteristics)
Table 5.8: Adoptability of capacitor

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5.7

Gamma characteristic correction function


The HX8352-C offers two kinds of Gamma adjustment ways to come to accord with LC
characteristic, one kind is through Source Driver directly, another one is adjusted by the
digital gamma correction. The Gamma adjustment way is select by internal register DGC_EN
bit.

Figure 5.26: Gamma adjustments different of source driver with digital gamma correction

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5.7.1 Gray Voltage Generator for Source Driver


The HX8352-C incorporates gamma adjustment function for the 262,144-color display.
Gamma adjustment operation is implemented by deciding the 8 grayscale levels firstly in
gamma adjustment control registers to match the LCD panel. Then total 128 grayscale levels
are generated in grayscale voltage generator. These registers are available for both
polarities.

Graphics
RAM
(GRAM)
Positive Polarity Register
R R R R R R GG G G GG B B B B B B
543210 543210 543210
VRP03 VRP02 VRP01 VRP00
VRP14 VRP13 VRP12 VRP11 VRP10

V0
6-bit Grayscale

6-bit Grayscale

6-bit Grayscale

D/A Converter

D/A Converter

D/A Converter

Output Driver

RP00

RP 12

RP 11

RP 0

KP 02

KP 01

KP00

KP 12

KP 11

KP10

KP 22

KP 21

KP20

KP 32

KP 31

KP30

KP 42

KP 41

KP40

KP 52

KP 51

KP50

Negative Polarity Register


Grayscale
Voltage

Output Driver

RP 01

V1

Generator
Output Driver

RP 02

V63

LCD

VRN03 VRN02 VRN01 VRN00


VRN14 VRN13 VRN12 VRN11 VRN10
RN 02

RN01

RN00

RN 12

RN11

RN 0

KN 02

KN01

KN00

KN 12

KN11

KN10

KN 22

KN21

KN20

KN 32

KN31

KN30

KN 42

KN41

KN40

KN 52

KN51

KN50

Figure 5.27: Grayscale Control

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5.7.1.1 Structure of Grayscale Voltage Generator


Eight reference gamma voltages VgP/N(4, 9, 16, 28, 51, 63, 70, 75) for positive and negative
polarity are specified by the center adjustment, the micro adjustment and the offset
adjustment registers firstly. With those eight voltages injected into specified node of
grayscale voltage generator, total 64 grayscale voltages (V0-V63) can be generated from
grayscale amplifier for LCD panel used.
Micro Adjust Register (6* 3 bits)

VREG1

KP/N5

KP/N4 KP/N3

KP/N2

EEM Adjust Register

KP/N1 KP/N0

VREP/N0

VREP/N1 VREP/N2

VgP0/VgN0

VgP4/VgN4
V0

8 to 1
select

8 to 1
select

VRP/N0

Register
VRP/N1

8 to 1
select

RP/N0
Center Adjust

VgP16/VgN16

V8

VgP28/VgN28

V20

Register
RP/N1

8 to 1
select

V1

4
Offset Adjust

VgP9/VgN9

VgP51/VgN51

Gray scale
voltage
generator

V43

3
8 to 1
select

8 to 1
select

VgP63/VgN63

VgP70/VgN70

VgP75/VgN75

V55

V62

V63

VgP79/VgN79

VGS

Figure 5.28: Structure of Grayscale Voltage Generator

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Figure 5.29: Gamma Resister Steam and Reference Voltage

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5.7.1.2 Gamma Characteristics Adjustment Register


This HX8352-C has register groups for specifying a series grayscale voltage that meets the
Gamma-characteristics for the LCD panel used. These registers are divided into two groups,
which correspond to the gradient, amplitude, and macro adjustment of the voltage for the
grayscale characteristics. The polarity of each register can be specified independently.
(1) Offset adjustment registers
The offset adjustment variable registers are used to adjust the amplitude of the grayscale
voltage. This function is implemented by controlling these variable resisters in the top and
bottom of the gamma resister stream for reference gamma voltage generation. These
registers are available for both positive and negative polarities.
(2) Gamma center adjustment registers
The gamma center adjustment registers are used to adjust the reference gamma voltage in
the middle level of grayscale without changing the dynamic range. This function is
implemented by choosing one input of 8 to 1 selector in the gamma resister stream for
reference gamma voltage generation. These registers are available for both positive and
negative polarities.
(3) Gamma macro adjustment registers
The gamma macro adjustment registers can be used for fine adjustment of the reference
gamma voltage. This function is implemented by controlling the 8-to-1 selectors (KP/N0~5),
each of which has 8 inputs and generate one reference voltage output (VgP/N) 9, 16, 28, 51,
63, 70). These registers are available for both positive and negative polarities.
Register
Groups
Center
Adjustment

Macro
Adjustment

Offset
Adjustment

Positive
Polarity
RP0 2-0
RP1 2-0
KP0 2-0
KP1 2-0
KP2 2-0
KP3 2-0
KP4 2-0
KP5 2-0
VRP0 3-0
VRP1 4-0

Negative
Description
Polarity
RN0 2-0
Variable resistor (RCP/N0) for center adjustment
RN1 2-0
Variable resistor (RCP/N1) for center adjustment
KN0 2-0
8-to-1 selector (voltage level of grayscale 70)
KN1 2-0
8-to-1 selector (voltage level of grayscale 63)
KN2 2-0
8-to-1 selector (voltage level of grayscale 51)
KN3 2-0
8-to-1 selector (voltage level of grayscale 28)
KN4 2-0
8-to-1 selector (voltage level of grayscale 16)
KN5 2-0
8-to-1 selector (voltage level of grayscale 9)
VRN0 3-0
Variable resistor (ROP/N0) for offset adjustment
VRN1 4-0
Variable resistor (ROP/N1) for offset adjustment
Table 5.9: Gamma-Adjustment Registers

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DATA SHEET Temporary V01

Variable Resister
There are three types of variable resistors, one is for center adjustment, one is for offset
adjustment and the other one is for EEM adjustment. The resistances are decided by setting
values in the center adjustment, offset adjustment and EEM adjustment registers. Their
relationships are shown below.

Value in Register
VR(P/N)0 3-0
0000
0001
0010

1101
1110
1111

Resistance
RO(P/N)0
0R
2R
4R

26R
28R
30R

Value in Register
VR(P/N)1 4-0
00000
00001
00010

11101
11110
11111

Resistance
RO(P/N)1
0R
1R
2R

29R
30R
31R

Table 5.10: Offset Adjustment


Value in Register
VRE(P/N)0 3-0
0000
0001
0010

1101
1110
1111

Resistance
RE(P/N)0
0R
1R
2R

13R
14R
15R

Value in Register
VRE(P/N)1 3-0
0000
0001
0010

1101
1110
1111

Resistance
RE(P/N)1
0R
1R
2R

13R
14R
15R

Value in Register
VRE(P/N)2 3-0
0000
0001
0010

1101
1110
1111

Resistance
RE(P/N)2
0R
1R
2R

13R
14R
15R

Table 5.11: EEM Adjustment


Value in Register
R(P/N)0 2-0
000
001
010

101
110
111

Resistance
RC(P/N)0
0R
4R
8R

20R
24R
28R

Value in Register
R(P/N)1 2-0
000
001
010

101
110
111

Resistance
RC(P/N)1
0R
4R
8R

20R
24R
28R

Table 5.12: Center Adjustment

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8 to 1 Selector
The 8 to 1 selector has eight input voltages generated by gamma resister stream. It outputs one
reference voltages selected from inputs for gamma reference voltage generation by setting value in
macro adjustment register. These six 8 to 1 selectors and the relationship are shown below.

Value in Register
K(P/N) 2-0
000
001
010
011
100
101
110
111

Voltage level
Vg(P/N) 9 Vg(P/N) 16 Vg(P/N) 28 Vg(P/N) 51
VP(N)1
VP(N)9
VP(N)17
VP(N)25
VP(N)2
VP(N)10
VP(N)18
VP(N)26
VP(N)3
VP(N)11
VP(N)19
VP(N)27
VP(N)4
VP(N)12
VP(N)20
VP(N)28
VP(N)5
VP(N)13
VP(N)21
VP(N)29
VP(N)6
VP(N)14
VP(N)22
VP(N)30
VP(N)7
VP(N)15
VP(N)23
VP(N)31
VP(N)8
VP(N)16
VP(N)24
VP(N)32
Table 5.13: Output Voltage of 8 to 1 Selector

V(P/N) 63
VP(N)33
VP(N)34
VP(N)35
VP(N)36
VP(N)37
VP(N)38
VP(N)39
VP(N)40

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V(P/N) 70
VP(N)41
VP(N)42
VP(N)43
VP(N)44
VP(N)45
VP(N)46
VP(N)47
VP(N)48

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
The grayscale levels are determined by the following formulas
Reference
Voltage
VgP79
VgP75

Macro Adjustment Value

Formula

Pin

VgP4

KP5 2-0=111
KP5 2-0=110
KP5 2-0=101
KP5 2-0=100
KP5 2-0=011
KP5 2-0=010
KP5 2-0=001
KP5 2-0=000
KP4 2-0=111
KP4 2-0=110
KP4 2-0=101
KP4 2-0=100
KP4 2-0=011
KP4 2-0=010
KP4 2-0=001
KP4 2-0=000
KP3 2-0=111
KP3 2-0=110
KP3 2-0=101
KP3 2-0=100
KP3 2-0=011
KP3 2-0=010
KP3 2-0=001
KP3 2-0=000
KP2 2-0=111
KP2 2-0=110
KP2 2-0=101
KP2 2-0=100
KP2 2-0=011
KP2 2-0=010
KP2 2-0=001
KP2 2-0=000
KP1 2-0=111
KP1 2-0=110
KP1 2-0=101
KP1 2-0=100
KP1 2-0=011
KP1 2-0=010
KP1 2-0=001
KP1 2-0=000
KP0 2-0=111
KP0 2-0=110
KP0 2-0=101
KP0 2-0=100
KP0 2-0=011
KP0 2-0=010
KP0 2-0=001
KP0 2-0=000
-

VP48
VP47
VP46
VP45
VP44
VP43
VP42
VP41
VP40
VP39
VP38
VP37
VP36
VP35
VP34
VP33
VP32
VP31
VP30
VP29
VP28
VP27
VP26
VP25
VP24
VP23
VP22
VP21
VP20
VP19
VP18
VP17
VP16
VP15
VP14
VP13
VP12
VP11
VP10
VP9
VP8
VP7
VP6
VP5
VP4
VP3
VP2
VP1
-

VgP0

VD*(8R /sumRP) + VGS


VD*(8R+REP2+ROP1)/sumRP + VGS
VD*(13R+REP2+ROP1)/sumRP + VGS
VD*(17R+REP2+ROP1)/sumRP + VGS
VD*(21R+REP2+ROP1)/sumRP + VGS
VD*(25R+REP2+ROP1)/sumRP + VGS
VD*(29R+REP2+ROP1)/sumRP + VGS
VD*(33R+REP2+ROP1)/sumRP + VGS
VD*(37R+REP2+ROP1)/sumRP + VGS
VD*(41R+REP2+ROP1)/sumRP + VGS
VD*(41R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(42R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(43R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(44R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(45R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(46R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(47R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(48R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(53R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(54R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(55R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(56R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(57R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(58R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(59R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(60R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(76R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(77R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(78R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(79R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(80R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(81R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(82R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(83R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(88R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(89R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(90R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(91R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(92R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(93R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(94R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(95R+REP2+ROP1+RCP1)/sumRP + VGS
VD*(95R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(99R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(103R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(107R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(111R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(115R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(119R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(123R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(128R+REP2+ROP1+RCP1+RCP0)/sumRP + VGS
VD*(128R+
REP2+ROP1+RCP1+RCP0+ROP0+REP1)/sumRP + VGS

VgP70

VgP63

VgP51

VgP28

VgP16

VgP9

sumRP = 128R + REP0 + REP1 + ROP0 + RCP0 + RCP1 + ROP1 + REP2


sumRN = 128R + REN0 + REN1 + RON0 + RCN0 + RCN1 + RON1 + REN2
VD=( VREG1 -VGS)

Table 5.14: Voltage Calculation Formula (Positive Polarity)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.77April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Grayscale
Voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31

Formula
VgP4
VgP9
(30/48)*(VgP9-VgP16) + VgP16
(23/48)*(VgP9-VgP16) + VgP16
(16/48)*(VgP9-VgP16) + VgP16
(12/48)*(VgP9-VgP16) + VgP16
(8/48)*(VgP9-VgP16) + VgP16
(4/48)*(VgP9-VgP16) + VgP16
VgP16
(22/24)*(VgP16-VgP28) + VgP28
(20/24)*(VgP16-VgP28) + VgP28
(18/24)*(VgP16-VgP28) + VgP28
(16/24)*(VgP16-VgP28) + VgP28
(14/24)*(VgP16-VgP28) + VgP28
(12/24)*(VgP16-VgP28) + VgP28
(10/24)*(VgP16-VgP28) + VgP28
(8/24)*(VgP16-VgP28) + VgP28
(6/24)*(VgP16-VgP28) + VgP28
(4/24)*(VgP16-VgP28) + VgP28
(2/24)*(VgP16-VgP28) + VgP28
VgP28
(22/23)*(VgP28-VgP51) + VgP51
(21/23)*(VgP28-VgP51) + VgP51
(20/23)*(VgP28-VgP51) + VgP51
(19/23)*(VgP28-VgP51) + VgP51
(18/23)*(VgP28-VgP51) + VgP51
(17/23)*(VgP28-VgP51) + VgP51
(16/23)*(VgP28-VgP51) + VgP51
(15/23)*(VgP28-VgP51) + VgP51
(14/23)*(VgP28-VgP51) + VgP51
(13/23)*(VgP28-VgP51) + VgP51
(12/23)*(VgP28-VgP51) + VgP51

Grayscale
Voltage
V32
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
V43
V44
V45
V46
V47
V48
V49
V50
V51
V52
V53
V54
V55
V56
V57
V58
V59
V60
V61
V62
V63

Formula
(11/23)*(VgP28-VgP51) + VgP51
(10/23)*(VgP28-VgP51) + VgP51
(9/23)*(VgP28-VgP51) + VgP51
(8/23)*(VgP28-VgP51) + VgP51
(7/23)*(VgP28-VgP51) + VgP51
(6/23)*(VgP28-VgP51) + VgP51
(5/23)*(VgP28-VgP51) + VgP51
(4/23)*(VgP28-VgP51) + VgP51
(3/23)*(VgP28-VgP51) + VgP51
(2/23)*(VgP28-VgP51) + VgP51
(1/23)*(VgP28-VgP51) + VgP51
VgP51
(22/24)*(VgP51-VgP63) + VgP63
(20/24)*(VgP51-VgP63) + VgP63
(18/24)*(VgP51-VgP63) + VgP63
(16/24)*(VgP51-VgP63) + VgP63
(14/24)*(VgP51-VgP63) + VgP63
(12/24)*(VgP51-VgP63) + VgP63
(10/24)*(VgP51-VgP63) + VgP63
(8/24)*(VgP51-VgP63) + VgP63
(6/24)*(VgP51-VgP63) + VgP63
(4/24)*(VgP51-VgP63) + VgP63
(2/24)*(VgP51-VgP63) + VgP63
VgP63
(44/48)*(VgP63-VgP70) + VgP70
(40/48)*(VgP63-VgP70) + VgP70
(36/48)*(VgP63-VgP70) + VgP70
(32/48)*(VgP63-VgP70) + VgP70
(25/48)*(VgP63-VgP70) + VgP70
(18/48)*(VgP63-VgP70) + VgP70
VgP70
VgP75

Table 5.15: Voltage Calculation Formula of Grayscale Voltage (Positive Polarity)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.78April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Reference
Voltage
VgN79
VgN75

Macro Adjustment Value

Formula

Pin

VgN4

KN5 2-0=111
KN5 2-0=110
KN5 2-0=101
KN5 2-0=100
KN5 2-0=011
KN5 2-0=010
KN5 2-0=001
KN5 2-0=000
KN4 2-0=111
KN4 2-0=110
KN4 2-0=101
KN4 2-0=100
KN4 2-0=011
KN4 2-0=010
KN4 2-0=001
KN4 2-0=000
KN3 2-0=111
KN3 2-0=110
KN3 2-0=101
KN3 2-0=100
KN3 2-0=011
KN3 2-0=010
KN3 2-0=001
KN3 2-0=000
KN2 2-0=111
KN2 2-0=110
KN2 2-0=101
KN2 2-0=100
KN2 2-0=011
KN2 2-0=010
KN2 2-0=001
KN2 2-0=000
KN1 2-0=111
KN1 2-0=110
KN1 2-0=101
KN1 2-0=100
KN1 2-0=011
KN1 2-0=010
KN1 2-0=001
KN1 2-0=000
KN0 2-0=111
KN0 2-0=110
KN0 2-0=101
KN0 2-0=100
KN0 2-0=011
KN0 2-0=010
KN0 2-0=001
KN0 2-0=000
-

VN48
VN47
VN46
VN45
VN44
VN43
VN42
VN41
VN40
VN39
VN38
VN37
VN36
VN35
VN34
VN33
VN32
VN31
VN30
VN29
VN28
VN27
VN26
VN25
VN24
VN23
VN22
VN21
VN20
VN19
VN18
VN17
VN16
VN15
VN14
VN13
VN12
VN11
VN10
VN9
VN8
VN7
VN6
VN5
VN4
VN3
VN2
VN1
-

VgN0

VD*(8R /sumRN) + VGS


VD*(8R+REN2+RON1)/sumRN + VGS
VD*(13R+REN2+RON1)/sumRN + VGS
VD*(17R+REN2+RON1)/sumRN + VGS
VD*(21R+REN2+RON1)/sumRN + VGS
VD*(25R+REN2+RON1)/sumRN + VGS
VD*(29R+REN2+RON1)/sumRN + VGS
VD*(33R+REN2+RON1)/sumRN + VGS
VD*(37R+REN2+RON1)/sumRN + VGS
VD*(41R+REN2+RON1)/sumRN + VGS
VD*(41R+REN2+RON1+RCN1)/sumRN + VGS
VD*(42R+REN2+RON1+RCN1)/sumRN + VGS
VD*(43R+REN2+RON1+RCN1)/sumRN + VGS
VD*(44R+REN2+RON1+RCN1)/sumRN + VGS
VD*(45R+REN2+RON1+RCN1)/sumRN + VGS
VD*(46R+REN2+RON1+RCN1)/sumRN + VGS
VD*(47R+REN2+RON1+RCN1)/sumRN + VGS
VD*(48R+REN2+RON1+RCN1)/sumRN + VGS
VD*(53R+REN2+RON1+RCN1)/sumRN + VGS
VD*(54R+REN2+RON1+RCN1)/sumRN + VGS
VD*(55R+REN2+RON1+RCN1)/sumRN + VGS
VD*(56R+REN2+RON1+RCN1)/sumRN + VGS
VD*(57R+REN2+RON1+RCN1)/sumRN + VGS
VD*(58R+REN2+RON1+RCN1)/sumRN + VGS
VD*(59R+REN2+RON1+RCN1)/sumRN + VGS
VD*(60R+REN2+RON1+RCN1)/sumRN + VGS
VD*(76R+REN2+RON1+RCN1)/sumRN + VGS
VD*(77R+REN2+RON1+RCN1)/sumRN + VGS
VD*(78R+REN2+RON1+RCN1)/sumRN + VGS
VD*(79R+REN2+RON1+RCN1)/sumRN + VGS
VD*(80R+REN2+RON1+RCN1)/sumRN + VGS
VD*(81R+REN2+RON1+RCN1)/sumRN + VGS
VD*(82R+REN2+RON1+RCN1)/sumRN + VGS
VD*(83R+REN2+RON1+RCN1)/sumRN + VGS
VD*(88R+REN2+RON1+RCN1)/sumRN + VGS
VD*(89R+REN2+RON1+RCN1)/sumRN + VGS
VD*(90R+REN2+RON1+RCN1)/sumRN + VGS
VD*(91R+REN2+RON1+RCN1)/sumRN + VGS
VD*(92R+REN2+RON1+RCN1)/sumRN + VGS
VD*(93R+REN2+RON1+RCN1)/sumRN + VGS
VD*(94R+REN2+RON1+RCN1)/sumRN + VGS
VD*(95R+REN2+RON1+RCN1)/sumRN + VGS
VD*(95R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(99R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(103R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(107R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(111R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(115R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(119R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(123R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(128R+REN2+RON1+RCN1+RCN0)/sumRN + VGS
VD*(128R+
REN2+RON1+RCN1+RCN0+RON0+REN1)/sumRN + VGS

VgN70

VgN63

VgN51

VgN28

VgN16

VgN9

sumRP = 128R + REP0 + REP1 + ROP0 + RCP0 + RCP1 + ROP1 + REP2


sumRN = 128R + REN0 + REN1 + RON0 + RCN0 + RCN1 + RON1 + REN2
VD=( VREG1 -VGS)

Table 5.16: Voltage Calculation Formula (Negative Polarity)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.79April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Grayscale
Voltage
V0
V1
V2
V3
V4
V5
V6
V7
V8
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
V21
V22
V23
V24
V25
V26
V27
V28
V29
V30
V31

Formula
VgN4
VgN9
(30/48)*(VgN9-VgN16) + VgN16
(23/48)*(VgN9-VgN16) + VgN16
(16/48)*(VgN9-VgN16) + VgN16
(12/48)*(VgN9-VgN16) + VgN16
(8/48)*(VgN9-VgN16) + VgN16
(4/48)*(VgN9-VgN16) + VgN16
VgN16
(22/24)*(VgN16-VgN28) + VgN28
(20/24)*(VgN16-VgN28) + VgN28
(18/24)*(VgN16-VgN28) + VgN28
(16/24)*(VgN16-VgN28) + VgN28
(14/24)*(VgN16-VgN28) + VgN28
(12/24)*(VgN16-VgN28) + VgN28
(10/24)*(VgN16-VgN28) + VgN28
(8/24)*(VgN16-VgN28) + VgN28
(6/24)*(VgN16-VgN28) + VgN28
(4/24)*(VgN16-VgN28) + VgN28
(2/24)*(VgN16-VgN28) + VgN28
VgN28
(22/23)*(VgN28-VgN51) + VgN51
(21/23)*(VgN28-VgN51) + VgN51
(20/23)*(VgN28-VgN51) + VgN51
(19/23)*(VgN28-VgN51) + VgN51
(18/23)*(VgN28-VgN51) + VgN51
(17/23)*(VgN28-VgN51) + VgN51
(16/23)*(VgN28-VgN51) + VgN51
(15/23)*(VgN28-VgN51) + VgN51
(14/23)*(VgN28-VgN51) + VgN51
(13/23)*(VgN28-VgN51) + VgN51
(12/23)*(VgN28-VgN51) + VgN51

Grayscale
Voltage
V32
V33
V34
V35
V36
V37
V38
V39
V40
V41
V42
V43
V44
V45
V46
V47
V48
V49
V50
V51
V52
V53
V54
V55
V56
V57
V58
V59
V60
V61
V62
V63

Formula
(11/23)*(VgN28-VgN51) + VgN51
(10/23)*(VgN28-VgN51) + VgN51
(9/23)*(VgN28-VgN51) + VgN51
(8/23)*(VgN28-VgN51) + VgN51
(7/23)*(VgN28-VgN51) + VgN51
(6/23)*(VgN28-VgN51) + VgN51
(5/23)*(VgN28-VgN51) + VgN51
(4/23)*(VgN28-VgN51) + VgN51
(3/23)*(VgN28-VgN51) + VgN51
(2/23)*(VgN28-VgN51) + VgN51
(1/23)*(VgN28-VgN51) + VgN51
VgN51
(22/24)*(VgN51-VgN63) + VgN63
(20/24)*(VgN51-VgN63) + VgN63
(18/24)*(VgN51-VgN63) + VgN63
(16/24)*(VgN51-VgN63) + VgN63
(14/24)*(VgN51-VgN63) + VgN63
(12/24)*(VgN51-VgN63) + VgN63
(10/24)*(VgN51-VgN63) + VgN63
(8/24)*(VgN51-VgN63) + VgN63
(6/24)*(VgN51-VgN63) + VgN63
(4/24)*(VgN51-VgN63) + VgN63
(2/24)*(VgN51-VgN63) + VgN63
VgN63
(44/48)*(VgN63-VgN70) + VgN70
(40/48)* (VgN63-VgN70) + VgN70
(36/48)* (VgN63-VgN70) + VgN70
(32/48)* (VgN63-VgN70) + VgN70
(25/48)* (VgN63-VgN70) + VgN70
(18/48)* (VgN63-VgN70) + VgN70
VgN70
VgN75

Table 5.17: Voltage Calculation Formula of Grayscale Voltage (Negative Polarity)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.80April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.7.1.3 Relationship between data and output voltages

Figure 5.30: Relationship between source output and Vcom

V0

Output Level

Positive polarity

Negative polarity

V63

RAM Data

000000

111111

(Same characteristic for each RGB)


Figure 5.31: Relationship between data and output level, REV =0, normal white

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.81April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

5.7.2

Gray Voltage Generator for Digital Gamma Correction

Gary-scale

luminance of B

Gary-scale

luminance of G

Gary-scale

luminance of R

The HX8352-C digital gamma correction can reach the independent GAMMA curve of RGB.
HX8352-C utilizes DGC_LUT (Digital Gamma Correction Look Up Table) to change input
data from 6-bit into 8-bit and sends 8-bit data to Dithering circuit, and then drive Source
Driver via Dithering circuit. The following of the block diagram of the function.

Figure 5.32: Block Diagram of Digital Gamma Correction

The HX8352-C builds one 99-bytes DGC_LUT (Digital Gamma Correction Look Up Table) to
transfer every display data of Dithering circuit input and setting by DGC_LUT register.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.82April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
LUT
st
1
nd
2
rd
3
:
:
nd
32
rd
33
th
34
th
35
th
36
:
:
th
65
th
66
th
67
th
68
th
69
:
:
th
98
th
99

D7
R007
R017
R027
:
:
R317
R327
G007
G017
G027
:
:
G317
G327
B007
B017
B027
:
:
B317
B327

D6
R006
R016
R026
:
:
R316
R326
G006
G016
G026
:
:
G316
G326
B006
B016
B026
:
:
B316
B326

D5
R005
R015
R025
:
:
R315
R325
G005
G015
G025
:
:
G315
G325
B005
B015
B025
:
:
B315
B325

D4
R004
R014
R024
:
:
R314
R324
G004
G014
G024
:
:
G314
G324
B004
B014
B024
:
:
B314
B324

D3
D2
D1
R003 R002 R001
R013 R012 R011
R023 R022 R021
:
:
:
:
:
:
R313 R312 R311
R323 R322 R321
G003 G002 G001
G013 G012 G011
G023 G022 G021
:
:
:
:
:
:
G313 G312 G311
G323 G322 G321
B003 B002 B001
B013 B012 B011
B023 B022 B021
:
:
:
:
:
:
B313 B312 B311
B323 B322 B321
Table 5.18: DGC LUT

D0 Default
R000
00h
R010
08h
R020
10h
:
:
:
:
R310
F8h
R320
FCh
G000
00h
G010
08h
G020
10h
:
:
:
:
G310
F8h
G320
FCh
B000
00h
B010
08h
B020
10h
:
:
:
:
B310
F8h
B320
FCh

Gray Mapping
R_V0
R_V2
R_V4
:
:
R_V62
R_V63
G_V0
G_V2
G_V4
:
:
G_V62
G_V63
B_V0
B_V2
B_V4
:
:
B_V62
B_V63

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5.8 Characteristics of I/O


5.8.1 Output or bi-directional (I/O) pins
Output or
bi-directional pins
TE
CABC_PWM_OUT
LEDON
DB17 to DB0
(Output driver)
SDI_SDA
SDO

After power on

After hardware reset

After software reset

Low
Low
Low

Low
Low
Low

Low
Low
Low

High-Z (Inactive)

High-Z (Inactive)

High-Z (Inactive)

High-Z (Inactive)
High-Z (Inactive)

High-Z (Inactive)
High-Z (Inactive)

High-Z (Inactive)
High-Z (Inactive)

Table 5.19: Characteristics of output or bi-directional (I/O) pins

5.8.2 Input pins


Input pins
NRESET
NCS
DNC
NWR_SCL
NRD
DB17 to DB0
SDI_SDA
HSYNC
VSYNC
PCLK
DE
OSC, IFSEL, IM2,
IM1, IM0,
TEST2-1

Input valid
Input valid
Input valid
Input valid
Input valid

After
hardware
reset
Input valid
Input valid
Input valid
Input valid
Input valid

After
software
reset
Input valid
Input valid
Input valid
Input valid
Input valid

Input valid

Input valid

Input valid

Input valid

Input valid

Input valid
Input valid
Input valid
Input valid

Input valid
Input valid
Input valid
Input valid

Input valid
Input valid
Input valid
Input valid

Input valid
Input valid
Input valid
Input valid

Input valid
Input valid
Input valid
Input valid

Input valid

Input valid

Input valid

Input valid

Input valid

Low

Low

During power
on process

After power
on

Setion.5.10
Input valid
Input valid
Input valid
Input valid

Low
Low
Low
Table 5.20: Characteristics of input pins

During power
off process
Setion.5.10
Input valid
Input valid
Input valid
Input valid

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5.9

Power on/off sequence


IOVCC and VCI can be applied in any order. IOVCC and VCI can be powered down in any
order. During power off, if LCD is in the Sleep Out mode, IOVCC must be powered down
minimum 120msec after NRESET has been released. During power off, if LCD is in the
Standby mode, IOVCC and VCI can be powered down minimum 0msec after NRESET has
been released. NCS can be applied at any timing or can be permanently grounded. NRESET
has priority over NCS. There will be no damage to the display module if the power sequences
are not met. There will be no abnormal visible effects on the display panel during the Power
On/Off Sequences. There will be no abnormal visible effects on the display between end of
Power On Sequence and before receiving STB Out command. Also between receiving STB
In command and Power Off Sequence. If NRESET line is not held stable by host during
Power On Sequence as defined in Sections 5.9.1 and 5.9.2, then it will be necessary to apply
a Hardware Reset (NRESET) after Host Power On Sequence is complete to ensure correct
operation. Otherwise function is not guaranteed. The power on/off sequence is illustrated
below.

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5.9.1 Case 1: NRESET line is held high or unstable by host at power on


If NRESET line is held high or unstable by the host during power on, then a Hardware Reset
must be applied after both IOVCC and VCI have been applied- otherwise correct functionality
is not guaranteed. There is no timing restriction upon this hardware reset.

tRPW= +/- no limit

tFPW= +/- no limit

IOVCC

VCI
Time when the latter signal rises up to 90% of its typical value. Ex. When VCI comes latter.
This time is defined at the cross point of 90% of 2.5V/2.75V.

Time when the former signal falls down to 90% of its typical value. Ex. When VCI falls
earilier. This time is defined at the cross point of 90% of 2.5V/2.75V.

tRPWICS= +/- no limit

NCS

tFPWICS= +/- no limit

H or L

tRPWIRES= + no limit
tFPWIRES1= min 120ms

NRESET
(Power down in standby out mode)

tRPWIRES= + no limit

NRESET
(Power down in standby in mode)

tFPWIRES2= min 0ns

tFPWIRES1 is applied to NRESET falling in the Standby Out Mode


tFPWIRES2 is applied to NRESET falling in the Standby In Mode

Figure 5.33: Case 1: NRESET line is held high or unstable by host at power on

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5.9.2

Case 2: NRESET line is held low by host at power on

If NRESET line is held low (and stable) by the host during power on, then the NRESET must
be held low for minimum 10sec after both IOVCC and VCI have been applied.

tRPW= +/- no limit

tFPW= +/- no limit

IOVCC

VCI

Time when the latter signal rises up to 90% of its typical value.
Ex. When VCI comes latter. This time is defined at the cross
point of 90% of 2.5V/2.75V.
Time when the former signal falls down to 90% of its typical
.
value. Ex. When VCI falls earlier. This time is defined at the cross
point of 90% of 2.5V/2.75V.
tRPWNCS= +/- no limit

tRPWNCS= +/- no limit

NCS

H or L

tFPWNRES1= min120ms
tRPWNRES = min10us

NRESET
( Power down in
Standby Out mode
)
tRPWNRES= min10us

NRESET
tFPWNRES 2 = min0ns
( Power down in
Standby In mode)
tFPWNRES1 is applied to NREST falling in the Standby Out Mode
tFPWNRES2 is applied to NREST falling in the Standby In Mode

Figure 5.34: Case 2: NRESET line is held low by host at power on

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5.10 Uncontrolled power off


The uncontrolled power off means a situation when e.g. there is removed a battery without
the controlled power off sequence. There will not be any damages for the display module or
the display module will not cause any damages for the host or lines of the interface. At an
uncontrolled power off the display will go blank and there will not be any visible effects within
1 second on the display (blank display) and remains blank until Power On Sequence
powers it up.

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5.11 Power On/Off Sequence


The following are the sequences of register setting flow that applied to this driver driving the
TFT display, when operate in Register-Content interface mode.
Display On/Off Set flow

Figure 5.35: Display On/Off Set flow

Standby Mode Set up Flow

Figure 5.36: Standby Mode Setting flow

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Deep Standby Mode Set up Flow


Deep
Standby
Display off flow

Set standby (STB = "1")


Set deep standby
(DP_STB_S = "1")

Set deep
standby

Set deep standby


(DP_STB = "1")
Stop oscillation (OSC_EN = "0")
Start oscillation (OSC_EN = "1")
Set deep standby
(DP_STB = "0")
Wait >20ms
Set deep standby
(DP_STB_S = "0")

Release
deep
standby

Release from deep


standby (STB = "0")

Power supply setting

Display on flow

Figure 5.37: Deep Standby Mode Setting flow

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Power On/Off Setting up Flow

Figure 5.38: Power Supply Setting Flow

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5.12 Content adaptive brightness control (CABC) function


The general block diagram of the CABC and the brightness control is illustrated below:

External VSYNC, HSYNC, DE,


PCLK
(RGB interface)

Display Control
Signal Generator

Display Data
Generator

Image data

Display Data
Contents Analysis

C[1:0]= 00 off
C[1:0]= 01, 10,
11 on

CABC Gain / Duty


CABC Block
DBV[7:0]
(BL=0)
PWM_CLK
(FoscD)

PWM Clock Devider

Brightness Control
Block

BC (BL=1)

CABC[1:0]
SAVEPOWER[6:0]
DBG0~8[6:0]
PWMDIV[2:0]

DBV[7:0]
BCTRL, BL,
CMB[7:0])
INVPLUS
SEL_BLDUTY
PWM_PERIOD

Figure 5.39: CABC block diagram

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5.12.1 Module architectures


HX8352-C can support two module architectures for CABC operation. The BL bit setting of
R53h can be used to select used display module architecture. White LED driver circuit for
display backlight is located on the main PWB, not in the display module both in architecture I
and II.

Architecture I

Architecture II

Figure 5.40: Module architecture

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5.12.2 CABC block


There are DBG0~8[6:0] register bits in CABC block to define the CABC gain/ CABC duty
table. Every DBGx[6:0] has 33 gain/duty value setting.
After one-frame display data content analysis, LSI will generate one CABC gain / CABC duty
value calculated from DBG0~8[6:0] register bits setting (by using interpolated method) for
display data generating and for backlight PWM pulse generating.
Please note that the CABC gain / CABC duty value calculated by the LSI is one of the 33
gain/duty value setting in DBGxx[6:0].
Please note that : Duty ( valid level period (LED on) / one complete period)=1/ gain.

DBG0

Gain curve
DBG1
DBG2

DBG3
DBG4

Gain

DBG5
SAVEPOWER

DBG6
DBG7
DBG8

32

64

96

128

160

192

224

256

One frame display data


content analysis

Figure 5.41: CABC gain / CABC duty generation

For power saving of backlight module, there are SAVEPOWER[6:0] bits to define the
minimum gain/ maximum duty of CABC block output. If the CABC gain / duty after
one-frame display data contents analysis is smaller(gain) / larger(duty) than
SAVEPOWER[6:0] bits setting, the CABC block will output CABC gain / duty equal to
SAVEPOWER[6:0] and ignore the result of display data contents analysis.

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DATA SHEET Temporary V01

5.12.3 Brightness control block


There is an external output signal(CABC_PWM_OUT) from brightness block to control the
LED driver IC in order to control display brightness.
There are resister bits DBV[7:0] for display brightness of manual brightness setting. The
CABC_PWM_OUT output duty is calculated as (DBV[7:0])/255 x CABC duty (generated after
one-frame display data content analysis).
For ex: CABC_PWM_OUT output period=2.95 ms, and DBV[7:0](R51h)=228DEC and
CABC duty is 74.42%. Then CABC_PWM_OUT output duty=(228) / 255 x 74.42%66.54%.
Correspond to the CABC_PWM_OUT output period=2.95 ms, the high-level of
CABC_PWM_OUT output (high effective) = 1.96ms, and the low-level of BC output =0.99ms.

One Period

ON

CABC_
PWM_OUT
(INVPLUS=`1`)

Display
Brightness
OFF
Duty = 100%
OFF

Duty = 100%
Maximum

Duty = 33%

Duty = 66.54%

Figure 5.42: CABC_PWM_OUT output duty


Symbol
tpw

Parameter
Min.
Max.
Pulse width
0.0333
8.33
Table 5.21: CABC timing table

Unit
ms

Description
-

Note1: The signal rise and fall times (tf, tr) are stipulated to be equal to or less than 15ns.
Note2: The pulse width range by setting CABC related registers is locate between 0.0333ms to 8.33ms.

When Architecture II module is used (BL=0) with the example below, the CABC_PWM_OUT
is always output low and the DBV[7:0] will be read a value as 169DEC ((169)/255 66.27%).

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5.12.4 Minimum brightness setting of CABC function


CABC function is automatically reduced backlight brightness based on image contents. In the
case of the combination with the CABC or manual brightness setting, display brightness is
too dark. It must affect to image quality degradation. CABC minimum brightness setting
(CMB[7:0] bits) is to avoid too much brightness reduction.
When CABC is active, CABC can not reduce the display brightness to less than CABC
minimum brightness setting. Image processing function is worked as normal, even if the
brightness can not be changed.
This function does not affect to the other function, manual brightness setting. Manual
brightness can be set the display brightness to less than CABC minimum brightness. Smooth
transition and dimming function can be worked as normal.
When display brightness is turned off (BCTRL=0), CABC minimum brightness setting is
ignored. CMB[7:0], Read CABC minimum brightness always read the setting value of
CMB[7:0], Write CABC minimum brightness

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5.13 OTP programing


5.13.1 OTP table
PA
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38

D7

nValid_ID8
nValid_VCM1

D6

nValid_ID7

D5

nValid_ID6

D4

D3

ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
ID1[7:0]
ID2[7:0]
ID3[7:0]
nValid_ID5
nValid_ID4
VCM[6:0]

No used

D0

nValid_ID3

nValid_ID2

nValid_ID1

VCM[6:0]
No used

VDV[4:0]

nValid_VCM3

VCM[6:0]
No used

VDV[4:0]

nValid_VCM4

VCM[6:0]
No used

VDV[4:0]

nValid_VCM5

VCM[6:0]
No used

VDV[4:0]

nValid_VCM6

VCM[6:0]
No used

VDV[4:0]

nValid_VCM7

VCM[6:0]
No used

VDV[4:0]

nValid_VCM8

No used
No used
No used
No used

D1

VDV[4:0]

nValid_VCM2

nValid_PANEL
nValid_GAM
No used
No used
No used

D2

VCM[6:0]
No used
No used
KP1[2:0]
KP3[2:0]
KP5[2:0]
RP1[2:0]
No used
No used
KN1[2:0]
KN3[2:0]
KN5[2:0]
RN1[2:0]
No used
No used
VREP1[3:0]
VREN0[3:0]
VREN2[3:0]

REV

SM
No used
No used
No used
No used

No used
No used
No used
No used

VDV[4:0]
GS

BGR
KP0[2:0]
KP2[2:0]
KP4[2:0]
RP0[2:0]
VRP0[3:0]
VRP1[4:0]
KN0[2:0]
KN2[2:0]
KN4[2:0]
RN0[2:0]
VRN0[3:0]
VRN1[4:0]
VREP0[3:0]
VREP2[3:0]
VREN1[3:0]

SS

Command
Set
-

Note: (1) The same color means the same nVALID bit controlled. When OTP Index programmed, the related nVALID bit
will be programmed to 0 automatically. If the nVALID bit programmed to 0, the OTP value will be reload to
related register after HW reset or SLPOUT command.
(2) If want to program ID1~ID3, it just need to program Index 00h (ID2 and ID3 will be programmed automatically).
If ID had be programmed, it also need to program Index 00h when second to eighth times programming(it will

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be programmed to corresponding Index automatically).
(3) If want to program VCOM, it just need to program Index 19h (VDV will be programmed automatically). If VCOM
had be programmed, it also need to program Index 19h when second to eighth times programming(it will be
programmed to corresponding Index automatically).

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5.13.2 OTP programming flow


Sleep Out
Set SLPOUT

Write OTP data to the


related register

OTP program enable


Set OTP_KEY[7:0]=8'hAA

OTP
Programming
Set OTP Address
Set OTP_ MASK [7:0]
Set OTP_ INDEX [7:0]

Set VPP_SEL=1
Wait 1us

Set VPP_EN=1
Wait 1us

OTP program start


Set OTP_ PROG = 1

Wait for programming


Wait 10ms

OTP_PROG=0, VPP_EN=0, VPP_SEL=0


( Automatically set by LSI)

OTP program disable


Set OTP_KEY[7:0]=8'h55

Figure 5.43: OTP programming sequence

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5.13.3 Programming sequence


Step
1
2
3
4
5
6
7
8
9
10
11
12
13
14

Operation
Power on and reset the module.
SLPOUT
Set VPP power to 7.5V for OTP programming state.
Write optimized values to related registers.
Set OTP_KEY[7:0] (REBh)=0xAAh to enter OTP program mode.
Specify OTP_INDEX, please refer to the OTP table.
Set OTP_MASK[7:0]=0x00h, programming the entire bit of one parameter.
Set VPP_SEL=1
Wait 1 us
Set VPP_EN=1
Wait 1 us
Set OTP_PROG=1, Internal register begin write to OTP according to OTP_INDEX.
Wait 10 ms
Complete programming one parameter to OTP. If continue to programming other parameter, return to
step (6). Otherwise, set OTP_KEY[7:0] (RBBh)=0x55h to leave OTP program mode and power off the
module.
Table 5.22: OTP Programming sequence

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6. Command
6.1 Command list
Register
No.
R00h

Register

Upper
W/R Code
D[17:8]

Lower Code
D7

D6

D5

D4

D3

D2

D1

D0

0
DSTB(
0)

0
SCROLL
(0)

0
IDMON
(0)

1
INVON
(0)

0
PTLON
(0)

R17h
R18h

Himax ID
Display Mode
control
Column address
start 2
Column address
start 1
Column address
end 2
Column address
end 1
Row address start
2
Row address start
1
Row address end
2
Row address end
1
Partial area start
row 2
Partial area start
row 1
Partial area end
row 2
Partial area end
row 1
Vertical Scroll Top
fixed area 2
Vertical Scroll Top
fixed area 1
Vertical Scroll
height area 2
Vertical Scroll
height area 1
Vertical Scroll
Button area 2
Vertical Scroll
Button area 1
Vertical Scroll Start
address 2
Vertical Scroll Start
address 1
Memory Access
control
COLMOD
OSC Control 2

R19h

OSC Control 1

W/R

R1Ah

Power Control 1

W/R

R1Bh

Power Control 2

W/R

R1Ch

Power Control 3

W/R

Power Control 5

W/R

VCOMG
(0)

R1Fh

VCIRE(
1)
GASEN
(1)

PON(0)

DK(1)

R22h

SRAM Write
Control

W/R

R01h
R02h
R03h
R04h
R05h
R06h
R07h
R08h
R09h
R0Ah
R0Bh
R0Ch
R0Dh
R0Eh
R0Fh
R10h
R11h
R12h
R13h
R14h
R15h
R16h

Default
Value

W/R

W/R

SC[15:8] (8'b0000_0000)

0x00

W/R

SC[7:0] (8'b0000_0000)

0x00

W/R

EC[15:8] (8'b0000_0000)

0x00

W/R

EC[7:0] (8'b1110_1111)

0xEF

W/R

SP[15:8] (8'b0000_0000)

0x00

W/R

SP[7:0] (8'b0000_00000)

0x00

W/R

EP[15:8] (8'b0000_0001)

0x01

W/R

EP[7:0] (8'b1010_1111)

0xAF

W/R

PSL[15:8] (8'b0000_0000)

0x00

W/R

PSL[7:0] (8'b0000_00000)

0x00

W/R

PEL[15:8] (8'b0000_0001)

0x01

W/R

PEL[7:0] (8'b1010_1111)

0xAF

W/R

TFA[15:8] (8'b0000_0000)

0x00

W/R

TFA[7:0] (8'b0000_0000)

0x00

W/R

VSA[15:8] (8'b0000_0001)

0x01

W/R

VSA[7:0] (8'b1011_0000)

0xB0

W/R

BFA[15:8] (8'b0000_0000)

0x00

W/R

BFA [7:0] (8'b0000_0000)

0x00

W/R

VSP [15:8] (8'b0000_0000)

0x00

W/R

VSP [7:0] (8'b0000_0000)

0X00

W/R

MY(0)

MX(0)

W/R
W/R

MV(0)

ML(0)

BGR(0)

CSEL[2:0] (3b110)
-

IFPF[2:0] (3b110)
RADJ[2:0](4b0100)
OSC_E
N(0)
BT[2:0] (100)
VRH[4:0] (0_1100)

VCOM Control 1

W/R

R24h
R25h
R26h

VCOM Control 2
VCOM Control 3
Display Control 1

W/R
W/R
W/R

0x00

0x00
0x66
0x04
0x00
0x04
0x8C

AP[2:0] (011)
DDVDH_
XDK(0)
STB(1)
TRI(0)

SRAM Write

R23h

0x72

0x03
0x89
-

VCM[6:0](100_0000)
VDV[4:0](0_1111)
PTG(0)
ISC[3:0](0001)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

SELVC
M(0)

0x00
0x40
0x0F
0x01

-P.101April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Register
No.

Register

Upper
W/R Code
D[17:8]

Lower Code
D7

D6

D5

D4

D3

R27h
R28h
R29h
R2Ah

Display Control 2
Display Control 3
Display Control 4
Display Control 5

W/R
W/R
W/R
W/R

GON(1)

DTE(0)

R2Bh

Display Control 6

W/R

R2Ch
R2Dh
R2Eh

Display Control 7
Cycle Control 1
Cycle Control 2
RGB interface
control 1
RGB interface
control 2
RGB interface
control 3
RGB interface
control 4

W/R
W/R
W/R

SDT[2:0](000)

W/R

RM(0)

W/R

SDA_
EN(0)

VSPL
(0)

HSPL
(0)

W/R

W/R

R31h
R32h
R33h
R34h

D2

D1

D0

REF(1)
-

D[1:0] (00)
NL[5:0](6b11_0101)
SCN[6:0](000_0000)
-

0x01
0x20
0x35
0x00

PTS[1:0](00)

0x00

DIVE[1:0](10)
NOW[2:0](110)
NW[5:0](00_0000)

0x02
0x06
0x00

DM[1:0](00)
EPL(1)

DPL(0)

HBP[7:0](8b0000_1000)
HBP[9:8](2b00)

Default
Value

0x00
0x02
0x08

VBP[5:0](6b00_0100)

0x04

REV_P
SM_P
GS_PAN BGR_PA
SS_PA
ANEL
ANEL
EL(0)l
NEL(0)
NEL (0)
(0)
(0)
OTP_MASK[7:0] (8h00)
OTP_INDEX[7:0] (8h00)
VPP_EN OTP_POR( OTP_PW
OTP_PTM[1:0]
VPP_SEL OTP_PR
(0)
0)
E(0)
(00)
(0)
OG(0)
OTP_DATA[7:0]
DBV[7:0] (8h00)
BCTRL
DD(0)
BL(0)
(0)
CACB[1:0] (00)
CMB[7:0] (8h00)
KP1[2:0](100)
KP0[2:0](100)
KP3[2:0](100)
KP2[2:0](100)
KP5[2:0](100)
KP4[2:0](100)
RP1[2:0](100)
RP0[2:0](100)
VRP0[3:0]
VRP1[4:0]
KN1[2:0](100)
KN0[2:0](100)
KN3[2:0](100)
KN2[2:0](100)
KN5[2:0](100)
KN4[2:0](100)
RN1[2:0](100)
RN0[2:0](100)
0x08
VRN1[3:0]
VREP1[3:0]
VREP0[3:0]
VREN0[3:0]
VREP2[3:0]
VREN2[3:0]
VREN1[3:0]
TE_MO
TEON
DE(0)
(0)
ID1[7:0](8h00)
ID2[7:0](8h00)
ID3[7:0](8h00)
WEMODE
(1)
TEI[2:0](000)
DENC[2:0](000)

R36h

Panel
Characteristic

W/R

R38h
R39h

OTP Control 1
OTP Control 2

W/R
W/R

R3Ah

OTP Control 3

W/R

R3Bh
R3Ch

OTP Control 4
CABC Control 1

R
W/R

R3Dh

CABC Control 2

W/R

R3Eh
R3Fh
R40h
R41h
R42h
R43h
R44h
R45h
R46h
R47h
R48h
R49h
R4Ah
R4Bh
R4Ch
R4Dh
R4Eh

CABC Control 3
CABC Control 4
Gamma Control 1
Gamma Control 2
Gamma Control 3
Gamma Control 4
Gamma Control 5
Gamma Control 6
Gamma Control 7
Gamma Control 8
Gamma Control 9
Gamma Control 10
Gamma Control 11
Gamma Control 12
Gamma Control 13
Gamma Control 14
Gamma Control 15

W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R

R60h

TE Control

W/R

R61h
R62h
R63h

ID1
ID2
ID3
Memory Write
Control
TE Interval Control
RGB SRAM Cycle
Data Format
Control
Frame Rate
Control 1
Frame Rate
Control 2
Frame Rate
Control 3
Frame Rate
Control 4
Frame Rate
Control 5
Frame Rate
Control 6

W/R
W/R
W/R

W/R

W/R
W/R

W/R

EPF[1:0](10)

W/R

W/R

W/R

BP0[7:0](8h02)

0x02

W/R

FP0[7:0](8h02)

0x02

W/R

W/R

R68h
R69h
R6Ah
R6Bh
R70h
R71h
R72h
R73h
R74h
R75h

BC0(1)

DFM(0)

DIV0[1:0](00)

RTN0[4:0](1_0000)

BC2(0)

0x00
0x00
0x00
0x00
0xFF
0x00
0x00
0x00
0x00
0x44
0x44
0x44
0x44
0x08
0x10
0x44
0x44
0x44
0x44
0x08
0x10
0x88
0x88
0x88
0x00
0x00
0x00
0x00
0x02
0x00
0x00
0x20
0x10
0x10

DIV2[1:0](00)

RTN2[4:0](1_0000)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

0x00
0x10

-P.102April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Register
No.
R76h
R77h
R7Ah
R7Bh
R7Ch
R7Dh
R7Eh
R7Fh
R84h
R85h
R86h
R87h
R88h
R89h
R8Ah
R8Bh
RFFh

Register
Frame Rate
Control 7
Frame Rate
Control 8
Power Control 6
Power Control 7
Power Control 8
Power Control 9
Power Control 10
Power Control 11
TE Output Line 2
TE Output Line 1
VPP Control
OTP Control 5
Get Scan Line 2
Get Scan Line 1
Read VCOM OTP
Times
Read ID OTP
Times
Page select

Upper
W/R Code
D[17:8]

Lower Code
D7

D6

D5

D4

D3

D2

D1

D0

BP2[7:0](8h02)

Default
Value

W/R

0x02

W/R

W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
W/R
R
R

VCOM_OTP_TIMES[3:0]

0x00

ID_OTP_TIMES[3:0]

0x00

W/R

FP2[7:0](8h02)
-

DC10[2:0](100)
DC11[2:0](100)
DC12[2:0](100)

0x02

TSEL[15:8](8h00)
TSEL[7:0](8h00)
OTP_KEY[7:0](8h55)
SL[15:8](8hFF)
SL[7:0](8hFF)

SAP0[2:0](001)
DC00[2:0](100)
SAP1[2:0](001)
DC01[2:0](100)
SAP2[2:0](001)
DC02[2:0](100)

VPP[2:0](011)

PAGE_SEL[1:0] (00)

0x01
0x44
0x01
0x44
0x01
0x44
0x00
0x00
0x03
0x55
0xFF
0xFF

0x00

Table 6.1: List table of command set page 0

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.103April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
Register
No.

Register

Upper
W/R Code
D[17:8]

R00h

DGC Control

W/R

R01h
R02h
R03h
R04h
R05h
R06h
R07h
R08h
R09h
R0Ah
R0Bh
R0Ch
R0Dh
R0Eh
R0Fh
R10h
R11h
R12h
R13h
R14h
R15h
R16h
R17h
R18h
R19h
R1Ah
R1Bh
R1Ch
R1Dh
R1Eh
R1Fh
R20h
R21h
R22h
R23h
R24h
R25h
R26h
R27h
R28h
R29h
R2Ah
R2Bh
R2Ch
R2Dh
R2Eh
R2Fh
R30h
R31h
R32h
R33h
R34h
R35h
R36h
R37h
R38h
R39h
R3Ah
R3Bh
R3Ch
R3Dh
R3Eh
R3Fh
R40h
R41h
R42h

DGC LUT1
DGC LUT2
DGC LUT3
DGC LUT4
DGC LUT5
DGC LUT6
DGC LUT7
DGC LUT8
DGC LUT9
DGC LUT10
DGC LUT11
DGC LUT12
DGC LUT13
DGC LUT14
DGC LUT15
DGC LUT16
DGC LUT17
DGC LUT18
DGC LUT19
DGC LUT20
DGC LUT21
DGC LUT22
DGC LUT23
DGC LUT24
DGC LUT25
DGC LUT26
DGC LUT27
DGC LUT28
DGC LUT29
DGC LUT30
DGC LUT31
DGC LUT32
DGC LUT33
DGC LUT34
DGC LUT35
DGC LUT36
DGC LUT37
DGC LUT38
DGC LUT39
DGC LUT40
DGC LUT41
DGC LUT42
DGC LUT43
DGC LUT44
DGC LUT45
DGC LUT46
DGC LUT47
DGC LUT48
DGC LUT49
DGC LUT50
DGC LUT51
DGC LUT52
DGC LUT53
DGC LUT54
DGC LUT55
DGC LUT56
DGC LUT57
DGC LUT58
DGC LUT59
DGC LUT60
DGC LUT61
DGC LUT62
DGC LUT63
DGC LUT64
DGC LUT65
DGC LUT66

W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W

Lower Code
D7

D6

D5

D4

D3

D2

D1

DGC_LUT_R00(8h00)
DGC_LUT_R01(8h08)
DGC_LUT_R02(8h10)
DGC_LUT_R03(8h18)
DGC_LUT_R04(8h20)
DGC_LUT_R05(8h28)
DGC_LUT_R06(8h30)
DGC_LUT_R07(8h38)
DGC_LUT_R08(8h40)
DGC_LUT_R09(8h48)
DGC_LUT_R10(8h50)
DGC_LUT_R11(8h58)
DGC_LUT_R12(8h60)
DGC_LUT_R13(8h68)
DGC_LUT_R14(8h70)
DGC_LUT_R15(8h78)
DGC_LUT_R16(8h80)
DGC_LUT_R17(8h88)
DGC_LUT_R18(8h90)
DGC_LUT_R19(8h98)
DGC_LUT_R20(8hA0)
DGC_LUT_R21(8hA8)
DGC_LUT_R22(8hB0)
DGC_LUT_R23(8hB8)
DGC_LUT_R24(8hC0)
DGC_LUT_R25(8hC8)
DGC_LUT_R26(8hD0)
DGC_LUT_R27(8hD8)
DGC_LUT_R28(8hE0)
DGC_LUT_R29(8hE8)
DGC_LUT_R30(8hF0)
DGC_LUT_R31(8hF8)
DGC_LUT_R32(8hFC)
DGC_LUT_G00(8h00)
DGC_LUT_G01(8h08)
DGC_LUT_G02(8h10)
DGC_LUT_G03(8h18)
DGC_LUT_G04(8h20)
DGC_LUT_G05(8h28)
DGC_LUT_G06(8h30)
DGC_LUT_G07(8h38)
DGC_LUT_G08(8h40)
DGC_LUT_G09(8h48)
DGC_LUT_G10(8h50)
DGC_LUT_G11(8h58)
DGC_LUT_G12(8h60)
DGC_LUT_G13(8h68)
DGC_LUT_G14(8h70)
DGC_LUT_G15(8h78)
DGC_LUT_G16(8h80)
DGC_LUT_G17(8h88)
DGC_LUT_G18(8h90)
DGC_LUT_G19(8h98)
DGC_LUT_G20(8hA0)
DGC_LUT_G21(8hA8)
DGC_LUT_G22(8hB0)
DGC_LUT_G23(8hB8)
DGC_LUT_G24(8hC0)
DGC_LUT_G25(8hC8)
DGC_LUT_G26(8hD0)
DGC_LUT_G27(8hD8)
DGC_LUT_G28(8hE0)
DGC_LUT_G29(8hE8)
DGC_LUT_G30(8hF0)
DGC_LUT_G31(8hF8)
DGC_LUT_G32(8hFC)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

D0
DGC_E
N(0)

Default
Value
0x00
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80
0x88
0x90
0x98
0xA0
0xA8
0xB0
0xB8
0xC0
0xC8
0xD0
0xD8
0xE0
0xE8
0xF0
0xF8
0xFC
0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80
0x88
0x90
0x98
0xA0
0xA8
0xB0
0xB8
0xC0
0xC8
0xD0
0xD8
0xE0
0xE8
0xF0
0xF8
0xFC

-P.104April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

R43h
R44h
R45h
R46h
R47h
R48h
R49h
R4Ah
R4Bh
R4Ch
R4Dh
R4Eh
R4Fh
R50h
R51h
R52h
R53h
R54h
R55h
R56h
R57h
R58h
R59h
R5Ah
R5Bh
R5Ch
R5Dh
R5Eh
R5Fh
R60h
R61h
R62h
R63h

DGC LUT67
DGC LUT68
DGC LUT69
DGC LUT70
DGC LUT71
DGC LUT72
DGC LUT73
DGC LUT74
DGC LUT75
DGC LUT76
DGC LUT77
DGC LUT78
DGC LUT79
DGC LUT80
DGC LUT81
DGC LUT82
DGC LUT83
DGC LUT84
DGC LUT85
DGC LUT86
DGC LUT87
DGC LUT88
DGC LUT89
DGC LUT90
DGC LUT91
DGC LUT92
DGC LUT93
DGC LUT94
DGC LUT95
DGC LUT96
DGC LUT97
DGC LUT98
DGC LUT99

Upper
W/R Code
D[17:8]
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
-

RC3h

CABC Control 5

W/R

RC5h
RFFh

CABC Control 7
Page select

W/R
W/R

Register
No.

Register

Lower Code
D7

D6

LEDO
NPOL
(0)
-

D5

D4
D3
D2
DGC_LUT_B00(8h00)
DGC_LUT_B01(8h08)
DGC_LUT_B02(8h10)
DGC_LUT_B03(8h18)
DGC_LUT_B04(8h20)
DGC_LUT_B05(8h28)
DGC_LUT_B06(8h30)
DGC_LUT_B07(8h38)
DGC_LUT_B08(8h40)
DGC_LUT_B09(8h48)
DGC_LUT_B10(8h50)
DGC_LUT_B11(8h58)
DGC_LUT_B12(8h60)
DGC_LUT_B13(8h68)
DGC_LUT_B14(8h70)
DGC_LUT_B15(8h78)
DGC_LUT_B16(8h80)
DGC_LUT_B17(8h88)
DGC_LUT_B18(8h90)
DGC_LUT_B19(8h98)
DGC_LUT_B20(8hA0)
DGC_LUT_B21(8hA8)
DGC_LUT_B22(8hB0)
DGC_LUT_B23(8hB8)
DGC_LUT_B24(8hC0)
DGC_LUT_B25(8hC8)
DGC_LUT_B26(8hD0)
DGC_LUT_B27(8hD8)
DGC_LUT_B28(8hE0)
DGC_LUT_B29(8hE8)
DGC_LUT_B30(8hF0)
DGC_LUT_B31(8hF8)
DGC_LUT_B32(8hFC)

PWMDIV[2:0](000)

SEL_GAIN[1:0]
(11)

PWM_PERIOD[7:0](8h23)
-

D1

Default
Value

D0

0x00
0x08
0x10
0x18
0x20
0x28
0x30
0x38
0x40
0x48
0x50
0x58
0x60
0x68
0x70
0x78
0x80
0x88
0x90
0x98
0xA0
0xA8
0xB0
0xB8
0xC0
0xC8
0xD0
0xD8
0xE0
0xE8
0xF0
0xF8
0xFC
INVPLU
S(1)

SEL_B
LDUTY
(1)

PAGE_SEL[1:0](00)

0x0F
0x23
0x00

Table 6.2: List table of command set page 1

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.105April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.2 Index register


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

ID7

ID6

ID5

ID4

ID3

ID2

ID1

ID0

Figure 6.1 Index register

Index register (IR) specifies the Index of register from R00h to RFFh. It sets the register
number (ID7-0) in the range from 00000000b to 11111111b in binary form.

6.3 Himax ID register (PAGE0 -R00h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

Figure 6.2 Himax ID register (PAGE0 -00h)

This command is used to read this ICs ID code. The ID code of this IC is 72h.

6.4 Display mode control register (PAGE0 -01h)


R/W

DNC

RB7

DST
B

RB6

RB5

DST
B

RB4

RB1

RB0

SCR IDMO INVO


N
N
OLL

RB3

RB2

PLT
ON

SCR IDMO INVO


N
N
OLL

PLT
ON

Figure 6.3 Display mode control register (PAGE0 -01h)

DSTB: This bits can let the driver into the deep standby mode. And when into deep
standby(DSTB=1), all display operation stops, including the internal R-C oscillator.
In the deep standby mode, the GRAM data and register content are not retained.
IDMON: This bit is Idle mode (8-color display mode) enable bit. IDMON = 1, chip will be into
idle mode, and color expression is reduced. The primary and the secondary colors
using MSB of each R, G and B in the Frame Memory, 8 color depth data is
displayed.

(Idel Mode On Example)


Display
Memory

SCROLL : This bit turns on scroll mode by setting SCROLL = 1. The scroll mode window is
described by the Vertical Scroll Area command TFA[15:0], VSA[15:0], BFA[15:0]
and the Vertical start address VSP[15:0] (R0Eh~R15h). To leave scroll mode to
normal mode, the SCROLL bit should be set to 0.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.106April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

INVON: This bit is display inversion mode enable bit. INVON = 1, chip will be into display
inversion mode, and makes no change of contents of frame memory. Every bit is
inverted from the frame memory to the display.

(Example)
memory

display

PTLON: This command is used for turning on/off Partial mode by setting PTLON=1/0. The
partial mode window is described by the Partial Area command PSL[15:0], PEL[15:0]
bits(R0Ah~R0Dh). To leave Partial mode to normal mode, the PLTON bit should be set
to 0.

6.5 Column address start register (PAGE0 -02~03h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SC
15

SC
14

SC
13

SC
12

SC
11

SC
10

SC9

SC8

SC
15

SC
14

SC
13

SC
12

SC
11

SC
10

SC9

SC8

Figure 6.4 Column address start register upper byte (PAGE0 -02h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SC7

SC6

SC5

SC4

SC3

SC2

SC1

SC0

SC7

SC6

SC5

SC4

SC3

SC2

SC1

SC0

Figure 6.5 Column address start register low byte (PAGE0 -03h)

6.6 Column address end register (PAGE0 -04~05h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

EC
15

EC
14

EC
13

EC
12

EC
11

EC
10

EC9

EC8

EC
15

EC
14

EC
13

EC
12

EC
11

EC
10

EC9

EC8

Figure 6.6 Column address end register upper byte (PAGE0 -04h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

EC7

EC6

EC5

EC4

EC3

EC2

EC1

EC0

EC7

EC6

EC5

EC4

EC3

EC2

EC1

EC0

Figure 6.7 Column address end register low byte (PAGE0 -05h)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.107April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.7 Row address start register (PAGE0 -06~07h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SP
15

SP
14

SP
13

SP
12

SP
11

SP
10

SP9

SP8

SP
15

SP
14

SP
13

SP
12

SP
11

SP
10

SP9

SP8

Figure 6.8 Row address start register upper byte (PAGE0 -06h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

Figure 6.9 Row address start register low byte (PAGE0 -07h)

6.8 Row address end register (PAGE0 -08~09h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

EP
15

EP
14

EP
13

EP
12

EP
11

EP
10

EP9

EP8

EP
15

EP
14

EP
13

EP
12

EP
11

EP
10

EP9

EP8

Figure 6.10 Row address end register upper byte (PAGE0 -08h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

EP7

EP6

EP5

EP4

EP3

EP2

EP1

EP0

Figure 6.11 Row address end register low byte (PAGE0 -09h)

These commands (R02h~R09h) are used to define area of frame memory where MCU can
access. The values of SC[15:0], EC[15:0], SP[15:0] and EP[15:0] are referred when RAMWR
command comes. Each value of SC[15:0], EC[15:0] represents one column line in the Frame
Memory. Each value of SP[15:0], EP[15:0] represents one page line in the Frame Memory.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.108April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.9 Partial Area Start Row Register (PAGE0 -0A~0Bh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PSL
15

PSL
14

PSL
13

PSL
12

PSL
11

PSL
10

PSL
9

PSL
8

PSL
15

PSL
14

PSL
13

PSL
12

PSL
11

PSL
10

PSL
9

PSL
8

Figure 6.12 Partial area start row register upper byte (PAGE0 -0Ah)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PSL
7

PSL
6

PSL
5

PSL
4

PSL
3

PSL
2

PSL
1

PSL
0

PSL
7

PSL
6

PSL
5

PSL
4

PSL
3

PSL
2

PSL
1

PSL
0

Figure 6.13 Partial area start row register low byte (PAGE0 -0Bh)

6.10 Partial Area End Row Register (PAGE0 -0C~0Dh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PEL
15

PEL
14

PEL
13

PEL
12

PEL
11

PEL
10

PEL
9

PEL
8

PEL
15

PEL
14

PEL
13

PEL
12

PEL
11

PEL
10

PEL
9

PEL
8

Figure 6.14 Partial area end row register upper byte (PAGE0 -0Ch)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PEL
7

PEL
6

PEL
5

PEL
4

PEL
3

PEL
2

PEL
1

PEL
0

PEL
7

PEL
6

PEL
5

PEL
4

PEL
3

PEL
2

PEL
1

PEL
0

Figure 6.15 Partial area end row register low byte (PAGE0 -0Dh)

These commands (PAGE0 -0Ah~~0Dh) define the partial modes display area. The Start
Row (PSL) and the second the End Row (PEL) are illustrated in the figures below. PSL and
PEL refer to the Frame Memory Line Pointer.
If End Row > Start Row
Start Row
PSL [15:0]

Partial Display Area


PEL[15:0]
End Row

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.109April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

If End Row < Start Row

If End Row = Start Row then the Partial Area will be one row deep.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.110April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.11 Vertical scroll top fixed area register (PAGE0 -0E~0Fh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TFA
15

TFA
14

TFA
13

TFA
12

TFA
11

TFA
10

TFA
9

TFA
8

TFA
15

TFA
14

TFA
13

TFA
12

TFA
11

TFA
10

TFA
9

TFA
8

Figure 6.16 Vertical scroll top fixed area register upper byte (PAGE0 -0Eh)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TFA
7

TFA
6

TFA
5

TFA
4

TFA
3

TFA
2

TFA
1

TFA
0

TFA
7

TFA
6

TFA
5

TFA
4

TFA
3

TFA
2

TFA
1

TFA
0

Figure 6.17 Vertical scroll top fixed area register low byte (PAGE0 -0Fh)

6.12 Vertical scroll height area register (PAGE0 -10~11h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSA
15

VSA
14

VSA
13

VSA
12

VSA
11

VSA
10

VSA
9

VSA
8

VSA
15

VSA
14

VSA
13

VSA
12

VSA
11

VSA
10

VSA
9

VSA
8

Figure 6.18 Vertical scroll height area register upper byte (PAGE0 -10h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSA
7

VSA
6

VSA
5

VSA
4

VSA
3

VSA
2

VSA
1

VSA
0

VSA
7

VSA
6

VSA
5

VSA
4

VSA
3

VSA
2

VSA
1

VSA
0

Figure 6.19 Vertical scroll height area register low byte (PAGE0 -11h)

6.13 Vertical scroll button fixed area register (PAGE0 -12~13h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BFA
15

BFA
14

BFA
13

BFA
12

BFA
11

BFA
10

BFA
9

BFA
8

BFA
15

BFA
14

BFA
13

BFA
12

BFA
11

BFA
10

BFA
9

BFA
8

Figure 6.20 Vertical scroll button fixed area register upper byte (PAGE0 -12h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BFA
7

BFA
6

BFA
5

BFA
4

BFA
3

BFA
2

BFA
1

BFA
0

BFA
7

BFA
6

BFA
5

BFA
4

BFA
3

BFA
2

BFA
1

BFA
0

Figure 6.21 Vertical scroll button fixed area register low byte (PAGE0 -13h)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.111April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

These commands (PAGE0 -0E~0Fh, R10~11h, R12~13h) define the Vertical Scrolling Area
of the display.
TFA[15:0] describes the Top Fixed Area (in No. of lines from Top of the Frame Memory and
Display).
VSA[15:0] describes the height of the Vertical Scrolling Area (in No. of lines of the Frame
Memory [not the display] from the Vertical Scrolling Start Address). The first line read from
Frame Memory appears immediately after the bottom most line of the Top Fixed Area.
BFA[15:0] describes the Bottom Fixed Area (in No. of lines from Bottom of the Frame
Memory and Display).
TFA, VSA and BFA refer to the Frame Memory Line Pointer.

Please note that (TFA+VSA+BFA) must be set to 432d, otherwise Scrolling mode is
undefined. In Vertical Scroll Mode, MV bit should be set to 0 this only affects the Frame
Memory Write.

6.14 Vertical scroll start address register (PAGE0 -14~15h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSP
15

VSP
14

VSP
13

VSP
12

VSP
11

VSP
10

VSP
9

VSP
8

VSP
15

VSP
14

VSP
13

VSP
12

VSP
11

VSP
10

VSP
9

VSP
8

Figure 6.22 Vertical Scroll Start Address Register Upper Byte (PAGE0 -14h)
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VSP
7

VSP
6

VSP
5

VSP
4

VSP
3

VSP
2

VSP
1

VSP
0

VSP
7

VSP
6

VSP
5

VSP
4

VSP
3

VSP
2

VSP
1

VSP
0

Figure 6.23 Vertical Scroll Start Address Register Low Byte (PAGE0 -15h)

VSP[15:0] is used together with Vertical Scrolling Definition register (PAGE0 -0Eh~R13h),
which describe the scrolling area and the scrolling mode.
VSP[15:0] refers to the Frame Memory line Pointer, and describes the address of the line in
the Frame Memory that will be written as the first line after the last line of the Top Fixed Area
on the display as illustrated below:

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.112April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

Example:
When Top Fixed Area TFA = 00d, Bottom Fixed Area BFA = 02d, Vertical Scrolling Area
VSA = 430'd and VSP = 3d (SS=0, GS=0)
(Example)
(0,0)
Line Pointer
VSP[15:0]

Memory

Display
Pointer
0
1
2
3
:
:
:
:
430
431

(0,431)

When new Pointer position and Picture Data are sent, the result on the display will happen at
the next Panel Scan to avoid tearing effect.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.113April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.15 Memory access control register (PAGE0 -16h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

MY

MX

MV

ML

BGR

MY

MX

MV

ML

BGR

Figure 6.24 Memory access control register (PAGE0 -16h)

This command defines read/write scanning direction of frame memory. MX, MY bits also define
the display direction in the RGB interface. This command makes no change on the other driver
status.
Bit
MY
MX
MV
ML
BGR

Name
PAGE ADDRESS ORDER
COLUMN ADDRESS ORDER
PAGE/COLUMN SELECTION
Vertical ORDER
RGB-BGR ORDER

Description
These 3 bits controls MCU to
memory write direction.
LCD vertical refresh direction control
Color selector switch control
(0=RGB color filter panel, 1=BGR
color filter panel)

6.16 COLMOD control register (PAGE0 -17h)


R/W

DNC

RB7

RB6

RB5

CSEL2

CSEL1

CSEL2

CSEL1

RB4

RB3

RB2

RB1

RB0

CSEL0

IFPF2

IFPF1

IFPF0

CSEL0

IFPF2

IFPF1

IFPF0

Figure 6.25 COLMOD control register (PAGE0 -17h)

This command is used to define the format of RGB picture data, which is to be transfer via the
system and RGB interface. The formats are shown in the table:

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.114April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

System interface
Interface Format
Not Defined
Not Defined
Not Defined
Not Defined
Not Defined
16 Bit/Pixel
18 Bit/Pixel
Not Defined

IFPF2
0
0
0
0
1
1
1
1

IFPF1
0
0
1
1
0
0
1
1

IFPF0
0
1
0
1
0
1
0
1

RGB interface
Interface Format
16 Bit/Pixel
18 Bit/Pixel
Not Defined

CSEL2
CSEL1
CSEL0
1
0
1
1
1
0
The Other Setting

Himax Confidential Temporary Version


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in whole or in part without prior written permission of Himax.

-P.115April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.17 OSC control register (PAGE0 -18h & R19h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RADJ
3

RADJ
2

RADJ
1

RADJ
0

RADJ
3

RADJ
2

RADJ
1

RADJ
0

Figure 6.26 OSC control 1 register (PAGE0 -18h)

R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

OSC_
EN

OSC_
EN

Figure 6.27 OSC control 2 register (PAGE0 -19h)

These commands are used to set internal oscillator related setting


OSC_EN: Enable internal oscillator, OSC_EN = 1, internal oscillator start to oscillate.
OSC_EN = 0, internal oscillator stop. In RGB interface mode (DM[1:0] = 01 or 1x), internal
oscillator will be stop to oscillate and OSC_EN bit control is invalid.
RADJ[3:0]: Internal oscillator frequency adjusts.
RADJ3 RADJ2 RADJ1 RADJ0
0
0
0
0
0
0
0
0
1
1
1
1
1

0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
Other setting

0
1
0
1
0
1
0
1
0
1
0
1
0

Internal Oscillator
Display Frame rate
Frequency
160% x 3.69MHz
96Hz
147% x 3.69MHz
88Hz
137% x 3.69MHz
82Hz
127% x 3.69MHz
76Hz
120% x 3.69MHz
72Hz
113% x 3.69MHz
68Hz
107% x 3.69MHz
64Hz
100% x 3.69MHz
60Hz
167% x 3.69MHz
100Hz
175% x 3.69MHz
105Hz
183% x 3.69MHz
110Hz
192% x 3.69MHz
115Hz
200% x 3.69MHz
120Hz
Setting Inhibited

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.116April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.18 Power control 1 register (PAGE0 -1Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BT2

BT1

BT0

BT2

BT0

BT0

Figure 6.28 Power control 1 register (PAGE0 -1Ah)

BT[2:0]: Switch the output factor of step-up circuit 2 for VGH and VGL voltage generation.
The LCD drive voltage level can be selected according to the characteristic of liquid crystal
which panel used. Lower amplification of the step-up circuit consumes less current and then
the power consumption can be reduced.
BT2 BT1 BT0 DDVDH
0
0
0
5.0V
0
0
1
5.0V
0
1
0
5.0V
0
1
1
5.0V
1
0
0
5.0V
1
0
1
5.0V
1
1
0
5.0V
1
1
1
5.0V

VCL
-VCI
-VCI
-VCI
-VCI
-VCI
-VCI
-VCI
-VCI

VGH
3DDVDH
3DDVDH
3DDVDH
VCI + 2DDVDH
VCI + 2DDVDH
VCI + 2DDVDH
2DDVDH
2DDVDH

VGL
-VCI-2DDVDH
-2DDVDH
VCI-2DDVDH
-VCI-2DDVDH
-2DDVDH
VCI-2DDVDH
-2DDVDH
-VCI-DDVDH

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.117April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.19 Power control 2 register (PAGE0 -1Bh)


DNC

RB7

RB6

RB5

VCIR
E

VRH4 VRH3 VRH2 VRH1 VRH0

VCIR
E

VRH4 VRH3 VRH2 VRH1 VRH0

R/W

RB4

RB3

RB2

RB1

RB0

Figure 6.29 Power control 2 register (PAGE0 -1Bh)

VCIRE: Select VREG1 reference voltage come from external voltage or internal generated voltage.
0: External reference voltage VCI.
1: Internal reference voltage 2.5V
VRH[4:0]: Specify the VREG1 voltage adjusting. (VREG1 must lower than DDVDH - 0.3V).
VRH[4:0]

VREG1 Voltage (VCIRE=0)

VRH[4:0]

VREG1 Voltage (VCIRE=1)

5h00
5h01
5h02
5h03
:
5h0E
5h0F
5h10
5h11
5h12
5h13
5h14
5h15
5h16
5h17
5h18
Others

VCI x 1.600
VCI x 1.625
VCI x 1.650
VCI x 1.675
:
VCI x 1.950
VCI x 1.975
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited
Setting inhabited

5h00
5h01
5h02
5h03
:
5h0E
5h0F
5h10
5h11
5h12
5h13
5h14
5h15
5h16
5h17
5h18
Others

2.5 x 1.600
2.5 x 1.625
2.5 x 1.650
2.5 x 1.675
:
2.5 x 1.950
2.5 x 1.975
2.5 x 2.000
2.5 x 2.025
2.5 x 2.050
2.5 x 2.075
2.5 x 2.100
2.5 x 2.125
2.5 x 2.150
2.5 x 2.175
2.5 x 2.200
Setting inhabited

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.118April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.20 Power control 3 register (PAGE0 -1Ch)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

AP2

AP1

AP0

AP2

AP1

AP0

Figure 6.30 Power control 3 register (PAGE0 -1Ch)

AP[2:0]: Adjust the amount of current driving for the operational amplifier in the power supply
circuit. When the amount of fixed current is increased, the LCD driving capacity and
the display quality are high, but the current consumption is increased. Adjust the
fixed current by considering both the display quality and the current consumption.
AP2
0
0
0
0
1
1
1
1

AP1
0
0
1
1
0
0
1
1

AP0
0
1
0
1
0
1
0
1

Constant Current of Operational Amplifier


Operation of the operational amplifier stops
Small
Small
Small
Medium
Medium High
Large
Small

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.119April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.21 Power control 5 register (PAGE0 -1Fh)


R/W

DNC

RB7

RB6

GAS
EN

VCO
MG

RB5

RB4

RB3

RB2

PON

DK

XDK

GAS
EN

VCO
MG

PON

DK

XDK

RB1
DDV
DH_T
RI
DDV
DH_T
RI

RB0
STB
STB

Figure 6.31 Power control 5 register (PAGE0 -1Fh)

PON: Specify on/off control of step-up circuit 2 for VGH, VGL voltage generation.
For detail, see the Power On/Off Setting Flow.
PON
0
1

Operation of step-up circuit 2


OFF
ON

DK: Specify on/off control of step-up circuit 1 for DDVDH voltage generation. For detail, see
the Power Supply Setting Sequence.
DK
0
1

Operation of step-up circuit 1


ON
OFF

STB: When STB = 1, the HX8352-C into the standby mode, where all display operation
stops, suspend all the internal operations including the internal R-C oscillator. During the
standby mode, only the following process can be executed. For details, please refer to STB
mode flow.
a. Start the oscillation
b. Exit the Standby mode (STB = 0) ,
In the standby mode, the GRAM data and register content are retained.
XDK, DDVDH_TRI: Specify the ratio of step-up circuit for DDVDH voltage generation.
DDVDH_TRI
0
0
1
1

XDK
0
1
0
1

Step up circuit 1
2 x VCI
2 x VCI
3 x VCI
Setting inhabited

Capacitor connection pins used


C11P, C11N
C11P, C11N, C12P, C12N
C11P, C11N, C12P, C12N
Setting inhabited

VCOMG: Specify on/off control of step-up circuit 3 for VCL voltage generation. For detail, see
the Power Supply Setting Sequence. When VCOMG = 0, VCOML = GND.
VCOMG

Operation of step-up circuit 3

0
1

OFF
ON

GASEN: This stands for abnormal power-off monitor function when the power is off.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.120April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.22 Read data register (PAGE0 -22h)

Figure 6.32 Read data register (PAGE0 -22h)

WD[17:0] : Transforms the data into 18-bit bus before written to GRAM through the write
data register (WDR). After a write operation is issued, the address is automatically updated
according to the AM and I/D bits.
RD[17:0]: Read 18-bit data from GRAM through the read data register (RDR). When the data
is read by microcomputer, the first-word read immediately after the GRAM address setting is
latched from the GRAM to the internal read-data latch. The data on the data bus (D170)
becomes invalid and the second-word read is normal.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.121April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.23 VCOM control 1~3 register (PAGE0 -23~25h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SEL
VCM

SEL
VCM

Figure 6.33 VCOM control 1 register (PAGE0 -23h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VCM VCM VCM VCM VCM VCM VCM


6
5
4
3
2
1
0

VCM VCM VCM VCM VCM VCM VCM


6
5
4
3
2
1
0

Figure 6.34 VCOM control 2 register (PAGE0 -24h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VDV
4

VDV
3

VDV
2

VDV
1

VDV
0

VDV
4

VDV
3

VDV
2

VDV
1

VDV
0

Figure 6.35 VCOM control 3 register (PAGE0 -25h)

This command is used to set VCOM Voltage include VCOM Low and VCOM High Voltage
SELVCM: Select the VCM setting. When OTP is programmed, the SELVCM will be set as 1
automatically.
0: Register R24h&R25h setting selected for VCOM voltage.
1: OTP value selected for VCOM voltage.
VCM[6:0]: Set VCOMH voltage.
VCM[6:0]
7h00
7h01
7h02
7h02
:
7h7C
7h7D
7h7E
7h7F

VCOMH Voltage
VREG1 x 0.492
VREG1 x 0.496
VREG1 x 0.500
VREG1 x 0.504

:
VREG1 x 0.988
VREG1 x 0.992
VREG1 x 0.996
VREG1 x 1.00

VDV[4:0]: Set VCOM amplitude.


VDV[4:0]
5h00
5h01
5h02
5h02
:

VCOM Amplitude
VREG1 x 070
VREG1 x 0.72
VREG1 x 0.74
VREG1 x 0.76

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.122April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
5h1C
5h1D
5h1E
5h1F

VREG1 x 1.26
VREG1 x 1.28
VREG1 x 1.30
VREG1 x 1.32

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.123April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.24 Display control 1~7 register (PAGE0 -26h~2Ch)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PTG

ISC3 ISC2 ISC1 ISC0

PTG

ISC3 ISC2 ISC1 ISC0

Figure 6.36 Display control 1 register (PAGE0 -26h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PTV
1

PTV
0

REF

PTV
1

PTV
0

REF

Figure 6.37 Display control 2 register (PAGE0 -27h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

GON

DTE

D1

D0

GON

DTE

D1

D0

Figure 6.38 Display control 3 register (PAGE0 -28h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

NL5

NL4

NL3

NL2

NL1

NL0

NL5

NL4

NL3

NL2

NL1

NL0

Figure 6.39 Display control 4 register (PAGE0 -29h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SCN
5

SCN
4

SCN
3

SCN
2

SCN
1

SCN
0

SCN
5

SCN
4

SCN
3

SCN
2

SCN
1

SCN
0

SCN
6

SCN
6

Figure 6.40 Display control 5 register (PAGE0 -2Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0
PTS
0
PTS
0

PTS
1

PTS
1

Figure 6.41 Display control 6 register (PAGE0 -2Bh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

DIVE DIVE
1
0

DIVE DIVE
1
0

Figure 6.42 Display control 7 register (PAGE0 -2Ch)

PTG: Set the scan mode in non-display area. Select frame inversion when interval scan
selected.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.124April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
PTG

Scan Mode in Non-display Area

0
1

Normal Scan
Interval Scan

ISC[3:0]: Specify the scan cycle of gate driver when REF = 1 in non-display area. Then scan
cycle is odd number from 3 to 31 frame.The polarity is inverted every scan cycle.
ISC3

ISC2

ISC1

ISC0

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

Scan Cycle

fFLM = 60Hz

Setting inhibited
3 frames
50ms
5 frames
83ms
7 frames
117ms
9 frames
150ms
11 frames
183ms
13 frames
217ms
15 frames
250ms
17 frames
19 frames
21 frames
23 frames
25 frames
27 frames
29 frames
31 frames

283ms
317ms
350ms
383ms
417ms
450ms
483ms
517ms

REF: Refresh display in non-display area in Partial mode enable bit.


REF = 0: Refresh display operation is disabling.
REF = 1: Refresh display operation is enable.

GON, DTE: Control gate output level.


GON
0
0
1
1

DTE
0
1
0
1

Gate Output
Fixed to VGH
Fixed to VGH
Fixed to VGL
Normal Operation (VGH/VGL)

D[1:0]: When D1 = 1, display is on; when D1 = 0, display is off. When display is off, the
display data is retained in the GRAM and the entire source outputs are set to the VSSD level.
When D[1:0]= 01, the internal display of the HX8352-C is performed although the actual
display is off. When D[1:0]= 00, the internal display operation halts and the display is off.
D1
0
0
1
1

D0
0
1
0
1

Source Output Internal Display Operations Gate-Driver Control Signals


VSSD
Halt
Halt
VSSD
Operate
Operate
=PTS(0,0)
Operate
Operate
Display
Operate
Operate

NL[5:0]: Set the number of lines to drive the LCD at an interval of 8 lines. The GRAM
address mapping is not affected by the number of lines set by NL[5:0]. The number of lines
must be the same or more than the number of lines necessary for the size of the liquid crystal

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.125April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

panel.
NL5

NL4

NL3

NL2

NL1

NL0

LCD Drive Lines

0
0
0
:

0
0
0
:

0
0
0
:

0
0
0
:

0
0
1
:

0
1
0
:

8 lines
16 lines
24 lines

1
1

1
1

0
0

0
1

0
1
0
1
Other Setting

:
424 lines
432 lines
432 lines

SCN[6:0]: Specifies the gate line where the gate driver starts scan.
Scanning Start Position
SCN[6:0]

SM=0

SM=1

GS=0

GS=1

GS=0

00h~35h

G(1+SCN[6:0]*4)

G(432-SCN[6:0]*4)

36h~6Bh

G(1+SCN[6:0]*4)

Others

Setting inhibited

GS=1

G(1+SCN[6:0]*8) G(432-SCN[6:0]*8)
G(2+(SCN[6:0]-36h) G(431-(SCN[6:0]-36
G(432-SCN[6:0]*4)
*8)
h)*8)
Setting inhibited
Setting inhibited
Setting inhibited

PTS[1:0]: Specify the Non-display area source output in partial display mode.
PTS[1:0]
Refresh cycle
00

Non-refresh cycle
Refresh cycle

01

Non-refresh cycle
Refresh cycle

10

Non-refresh cycle
Refresh cycle

11

Non-refresh cycle

Source/VCOM Outputs in Non-display Area


(REV=0)
(REV=1)
White
Black
Source=GND
Source=GND
VCOM=GND
VCOM=GND
Black
White
Source=V0
Source=V0
VCOM=VCOML
VCOM=VCOML
White
Black
Source=V63
Source=V63
VCOM=VCOML
VCOM=VCOML
White
Black
Source=Hi-Z
Source=Hi-Z
VCOM=Hi-Z
VCOM=Hi-Z

DIVE[1:0]: Used to set division ratio of PCLK clock frequency when the DPI interface
selected. The divided PCLK will be used as internal clock for the source pre-charge, VCOM
equalizing, etc.
DIVE[1:0]

Division Ratio

2b00
2b01
2b10
2b11

1/8
1/1
1/2
1/4

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.126April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.25 Cycle control 1~2 register (PAGE0 -2Dh~2Eh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SDT
2

SDT
1

SDT
0

NO
W2

NO
W1

NO
W0

SDT
2

SDT
1

SDT
0

NO
W2

NO
W1

NO
W0

Figure 6.43 Cycle control 1 register (PAGE0 -2Dh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

NW5 NW4 NW3 NW2 NW1 NW0

NW5 NW4 NW3 NW2 NW1 NW0

Figure 6.44 Cycle control 2 register (PAGE0 -2Eh)

SDT[2:0]: No function.
NOW[2:0]: Used to set the gate output non-overlap.
1 clock cycle=4 oscillator clock cycle.
NOW[2:0]
Gate Output Non-overlap Period
3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

Setting Inhibited
1 clock
2 clocks
3 clocks
4 clocks
5 clocks
6 clocks
7 clocks

NW[5:0]: Set number of lines for VCOM inverting.


NW[5:0]
6h00
6h01
6h02
:
6h3E
6h3F

Inversion Lines
1 line
2 lines
3 lines
:
63 lines
64 lines

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.127April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.26 RGB interface control 1~4 register (PAGE0 -31h~34h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RM

DM1

DM0

RM

DM1

DM0

Figure 6.45 RGB interface control 1 register (PAGE0 -31h)


R/W

DNC

RB7

RB6

RB5

SDA
_EN

SDA
_EN

RB4

RB3

RB2

RB1

RB0

VSPL HSPL

EPL

DPL

VSPL HSPL

EPL

DPL

Figure 6.46 RGB interface control 2 register (PAGE0 -32h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

HBP7 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0

HBP7 HBP6 HBP5 HBP4 HBP3 HBP2 HBP1 HBP0

Figure 6.47 RGB interface control 3 register (PAGE0 -33h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

HBP9 HBP8 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0

HBP9 HBP8 VBP5 VBP4 VBP3 VBP2 VBP1 VBP0

Figure 6.48 RGB interface control 4 register (PAGE0 -34h)

This command is used to set RGB interface related register.


RM: Interface slecetion for GRAM access.
RM
0
1

Interface for RAM access


DBI Interface (CPU)
DPI Interface (RGB)

DM[1:0]: Display mode selection for DPI interface.


DM 1
0
0
1
1

DM 0
0
1
1
1

Display Mode
Internal oscillation clock
DPI interface(GRAM)
RGB data bypass GRAM mode 1
RGB data bypass GRAM mode 2

EPL: Specify the polarity of Enable pin in RGB interface mode.


EPL
0
0
1
1

DE pin
Low
High
Low
High

GRAM address
Update
Keep
Keep
Update

Write to GRAM
Enable
Disable
Disable
Enable

Operation
Write data to DB17-0
Disable
Disable
Write data to DB17-0

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.128April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

VSPL: The polarity of VSYNC pin. When VSPL=0, the VSYNC signal is Low active. When
VSPL=1, the VSYNC signal is High active.
HSPL: The polarity of HSYNC pin. When HSPL=0, the HSYNC signal is Low active. When
HSPL=1, the HSYNC signal is High active.
DPL: The polarity of DOTCLK pin. When DPL=0, the data is latched by the chip on the rising
edge of DOTCLK signal. When DPL=1, the data is latched by the chip on the falling edge of
DOTCLK signal.
HBP and VBP are used to set vertical and horizontal back porch control in RGB I/F bypass
GRAM mode 2 (DM[1:0]= 11)
HBP[9:0]: Set the delay period from falling edge of HSYNC signal to first valid data in RGB
I/F bypass GRAM mode 2.
HBP[9:0]
00d
01d
02d
03d
04d
:
1021d
1022d
1023d

No. of Clock Cycle of DOTCLK


Setting Inhibited
Setting Inhibited
2
3
4
:
1021
1022
Setting Inhibited

VBP[5:0]: Set the delay period from falling edge of VSYNC signal to first valid line in RGB I/F
bypass GRAM mode 2.
VBP[5:0]
00d
01d
02d
03d
04d
:
61d
62d
63d

No. of Clock Cycle of HSYNC


Setting Inhibited
Setting Inhibited
2
3
4
:
61
62
63

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.129April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.27 Panel characteristic control register (PAGE0 -36h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

REV_P
ANEL

SM_PA
NEL

GS_PA
NEL

BGR_P
ANEL

SS_PA
NEL

REV_P
ANEL

SM_PA
NEL

GS_PA
NEL

BGR_P
ANEL

SS_PA
NEL

Figure 6.49 Panel characteristic control register (PAGE0 -36h)

This command is internal use for display panel setting.


REV_PANEL: The source output data polarity selected. When REV_PANEL=0, normally white
panel is selected. When REV_PANEL = 1, normally black panel is selected.
SM_PANEL: Set the gate driver pin arrangement in combination with the GS bit to slecet the
optimal scan mode for the module. Please reference Scan direction of Gate Driver.
GS_PANEL: The gate driver output shift direction selected. When GS_PANEL=0, the shift
direction dont reverse. When GS_PANEL = 1, the shift direction will be reversed.
BGR_PANEL: The color filter order direction selected. When BGR_PANEL=0, RGB-BGR
order dont reverse. When BGR_PANEL = 1, the color filter order will be reversed.
SS_PANEL: The source driver output shift direction selected. When SS_PANEL=0, the shift
direction dont reverse. When SS_PANEL = 1, the shift direction will be reversed.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.130April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.28 OTP control 1~5 register (PAGE0 -38h ~ 3Bh, 87h)


R/W

DNC

D7

D6

D5

D4

D3

D2

D1

D0

OTP_

OTP_

OTP_

MASK6

MASK5

OTP_
MASK4

OTP_
MASK3

OTP_
MASK2

OTP_
MASK1

OTP_
MASK0

OTP_
MASK4

OTP_
MASK3

OTP_
MASK2

OTP_
MASK1

OTP_
MASK0

MASK7

OTP_

OTP_

OTP_

MASK7

MASK6

MASK5

Figure 6.50 OTP control 1 (PAGE0 -38h)


R/W

DNC

D7

D6

D5

D4

D3

D2

D1

D0

OTP_
INDEX4

OTP_
INDEX3

OTP_
INDEX2

OTP_
INDEX1

OTP_
INDEX0

OTP_
INDEX4

OTP_
INDEX3

OTP_
INDEX2

OTP_
INDEX1

OTP_
INDEX0

OTP_

OTP_

OTP_

INDEX7

INDEX6

INDEX5

OTP_

OTP_

OTP_

INDEX7

INDEX6

INDEX5

Figure 6.51 OTP control 2 (PAGE0 -39h)


R/W

DNC

D7

D6

D5

D4

D3

D2

D1

D0

VPP_ OTP_ OTP_ OTP_ OTP_ VPP_ OTP_


EN
POR PWE PTM1 PTM0 SEL PROG

VPP_ OTP_ OTP_ OTP_ OTP_ VPP_ OTP_


EN
POR PWE PTM1 PTM0 SEL PROG

Figure 6.52 OTP control 3 (PAGE0 -3Ah)


R/W

DNC

D7

D6

D5

D4

D3

D2

D1

D0

OTP_
DOUT4

OTP_
DOUT3

OTP_
DOUT2

OTP_
DOUT1

OTP_
DOUT0

OTP_

OTP_

OTP_

DOUT7

DOUT6

DOUT5

Figure 6.53 OTP control 4 (PAGE0 -3Bh)


R/W

DNC

D7

D6

D5

D4

D3

D2

D1

D0

OTP_ OTP_ OTP_ OTP_ OTP_ OTP_ OTP_


KEY7 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1

OTP_
KEY0

OTP_ OTP_ OTP_ OTP_ OTP_ OTP_ OTP_


KEY7 KEY6 KEY5 KEY4 KEY3 KEY2 KEY1

OTP_
KEY0

Figure 6.54 OTP control 5 (PAGE0 -87h)

This command is used to set the OTP related setting. Please see OTP flow for detail use.
OTP_MASK[7:0]: OTP bit programming mask, if set to 1, it means the related bit in OTP
can not be programmed.
OTP_INDEX[7:0]: Set index location in OTP to be programmed.
OTP_PROG: When this bit set to 1, it will programmed to the setting OTP index from
related register value..
VPP_SEL: When set to 1, VPP input voltage is fed to OTP.
VPP_EN: When written to 1, OTP power OP is enable.
OTP_PTM[1:0]: Internal use, not open.
OTP_PWE: Internal use, not open.
OTP_POR: When set to 1, OTP data can be read the related OTP Index data at
OTP_DOUT[7:0]
OTP_DOUT[7:0]: Read OTP data.
OTP_KEY[7:0]: Set to AAh to enable OTP control register access.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.131April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.29 CABC control 1~4 register (PAGE0 -3Ch~3Fh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0

DBV7 DBV6 DBV5 DBV4 DBV3 DBV2 DBV1 DBV0

Figure 6.55 CABC control 1 register (PAGE0 -3Ch)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BCT
RL

DD

BL

BCT
RL

DD

BL

Figure 6.56 CABC control 2 register (PAGE0 -3Dh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

CAB
C1

CAB
C0

CAB
C1

CAB
C0

Figure 6.57 CABC control 3 register (PAGE0 -3Eh)


R/ W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

CMB
7

CMB
6

CMB
5

CMB
4

CMB
3

CMB
2

CMB
1

CMB
0

CMB
7

CMB
6

CMB
5

CMB
4

CMB
3

CMB
2

CMB
1

CMB
0

Figure 6.58 CABC control 4 register (PAGE0 -3Fh)

These commands are used to set CABC parameter


DBV[7:0]: The backlight PWM pulse output duty is equal to DBV[7:0]/255 x CABC_duty.
BCTRL: Backlight Control Block On/Off, This bit is always used to switch brightness for
display.
0 = Off (Equal to DBV[7:0] = 00h)
1 = On (Brightness registers are active.)
DD: Display Dimming (Only for manual brightness setting)
0: Display Dimming is off.
1: Display Dimming is on.
BL: Backlight Control On/Off
0 = Off (Completely turn off backlight circuit. Control lines must be low. )
1 = On

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.132April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

Dimming function is adapted to the brightness registers for display when bit BCTRL is
changed at DD=1, e.g. BCTRL: 0 -> 1 or 1-> 0.
When BL bit change from On to Off, backlight is turned off without gradual dimming, even
if dimming-on (DD=1) are selected.
C[1:0]: This command is used to set parameters for image content based adaptive
brightness control functionality.
There is possible to use 4 different modes for content adaptive image functionality, which are
defined on a table below.
C1
0
0
1
1

C0
0
1
0
1

Function
Off
User Interface Image
Still Picture
Moving Image

Note
-

CMB[7:0]: This command is used to set the minimum brightness value of the display for
CABC function.
In principle relationship is that 00h value means the lowest brightness for CABC and FFh
value means the highest brightness for CABC.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.133April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.30 Gamma control 1~15 register (PAGE0 -40h~4Eh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

KP12

KP11

KP10

KP02

KP01

KP00

KP12

KP11

KP10

KP02

KP01

KP00

Figure 6.59 Gamma control 1 register (PAGE0 -40h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

KP32

KP31

KP30

KP22

KP21

KP20

KP32

KP31

KP30

KP22

KP21

KP20

Figure 6.60 Gamma control 2 register (PAGE0 -41h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

KP52

KP51

KP50

KP42

KP41

KP40

KP52

KP51

KP50

KP42

KP41

KP40

Figure 6.61 Gamma control 3 register (PAGE0 -42h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RP12

RP11

RP10

RP02

RP01

RP00

RP12

RP11

RP10

RP02

RP01

RP00

Figure 6.62 Gamma control 4 register (PAGE0 -43h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRP0 VRP0 VRP0 VRP0


3
2
1
0

VRP0 VRP0 VRP0 VRP0


3
2
1
0

Figure 6.63 Gamma control 5 register (PAGE0 -44h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRP1 VRP1 VRP1 VRP1 VRP1


4
3
2
1
0

VRP1 VRP1 VRP1 VRP1 VRP1


4
3
2
1
0

Figure 6.64 Gamma control 6 register (PAGE0 -45h)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.134April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

DATA SHEET Temporary V01


RB1 RB0

KN12

KN11

KN10

KN02

KN01

KN00

KN12

KN11

KN10

KN02

KN01

KN00

Figure 6.65 Gamma control 7 register (PAGE0 -46h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

KN32

KN31

KN30

KN22

KN21

KN20

KN32

KN31

KN30

KN22

KN21

KN20

Figure 6.66 Gamma control 8 register (PAGE0 -47h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

KN52

KN51

KN50

KN42

KN41

KN40

KN52

KN51

KN50

KN42

KN41

KN40

Figure 6.67 Gamma control 9 register (PAGE0 -48h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RN12 RN11 RN10

RN02 RN01 RN00

RN12 RN11 RN10

RN02 RN01 RN00

Figure 6.68 Gamma control 10 register (PAGE0 -49h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRN0 VRN0 VRN0 VRN0


3
2
1
0

VRN0 VRN0 VRN0 VRN0


3
2
1
0

Figure 6.69 Gamma control 11 register (PAGE0 -4Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRN1 VRN1 VRN1 VRN1 VRN1


4
3
2
1
0

VRN1 VRN1 VRN1 VRN1 VRN1


4
3
2
1
0

Figure 6.70 Gamma control 12 register (PAGE0 -4Bh)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.135April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

DATA SHEET Temporary V01


RB1 RB0

VRE
P13

VRE
P12

VRE
P11

VRE
P10

VRE
P03

VRE
P02

VRE
P01

VRE
P00

VRE
P13

VRE
P12

VRE
P11

VRE
P10

VRE
P03

VRE
P02

VRE
P01

VRE
P00

Figure 6.71 Gamma control 13 register (PAGE0 -4Ch)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRE
N03

VRE
N02

VRE
N01

VRE
N00

VRE
P23

VRE
P22

VRE
P21

VRE
P20

VRE
N03

VRE
N02

VRE
N01

VRE
N00

VRE
P23

VRE
P22

VRE
P21

VRE
P20

Figure 6.72 Gamma control 14 register (PAGE0 -4Dh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VRE
N23

VRE
N22

VRE
N21

VRE
N20

VRE
N13

VRE
N12

VRE
N11

VRE
N10

VRE
N23

VRE
N22

VRE
N21

VRE
N20

VRE
N13

VRE
N12

VRE
N11

VRE
N10

Figure 6.73 Gamma control 15 register (PAGE0 -4Eh)

VRP0[3:0], VRP1[4:0]: Gamma Offset adjustment registers for positive polarity output
VRN0[3:0], VRN1[4:0]: Gamma Offset adjustment registers for negative polarity output
RP1-0[2:0]: Gamma Center adjustment registers for positive polarity output
RN1-0[2:0]: Gamma Center adjustment registers for negative polarity output
KP5-0[2:0]: Gamma Macro adjustment registers for positive polarity output
KN5-0[2:0]: Gamma Macro adjustment registers for negative polarity output
VREP2-0[3:0]: Gamma EEM adjustment registers for positive polarity output
VREN2-0[3:0]: Gamma EEM adjustment registers for negative polarity output
For details, please refer to 5.7.1.2 Gamma Characteristics Adjustment Register.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.136April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.31 TE control register (PAGE0 -60h, 84h~85h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TEO
N

TEO
N

TEM
ODE

TEM
ODE

Figure 6.74 TE control register (PAGE0 -60h)


R /W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TSE
L15

TSE
L14

TSE
L13

TSE
L12

TSE
L11

TSE
L10

TSE
L9

TSE
L8

TSE
L15

TSE
L14

TSE
L13

TSE
L12

TSE
L11

TSE
L10

TSE
L9

TSE
L8

Figure 6.75 TE output line2 register (PAGE0 -84h)


DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TSE
L7

TSE
L6

TSE
L5

TSE
L4

TSE
L3

TSE
L2

TSE
L1

TSE
L0

TSE
L7

TSE
L6

TSE
L5

TSE
L4

TSE
L3

TSE
L2

TSE
L1

TSE
L0

R /W

Figure 6.76 TE output line1 register (PAGE0 -85h)

TEMODE: Specify the Tearing-Effect mode.


When TEMODE = 0: The Tearing Effect Output line (TE) consists of V-Blanking information
only.

When TEMODE =1: The Tearing Effect Output Line (TE) consists of both V-Blanking and
H-Blanking information

Note: During Standby Mode with Tearing Effect Line On, Tearing Effect Output pin active low

TEON: This command is used to turn ON the Tearing Effect output signal from the TE signal
line.
TSEL[15:0]: This command is used to setting TE delay line at TEMODE=0. When
TSEL[15:0]=16h0000,
TE
output
is
the
same
as
TEMODE=0.
When
Decimal(TSEL[15:0])=n, TE output at n-th line starting.
TSEL=0
n-th line

n-th line

TSEL=n

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.137April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.32 ID register (PAGE0 -61h~63h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

ID17

ID16

ID15

ID14

ID13

ID12

ID11

ID10

ID17

ID16

ID15

ID14

ID13

ID12

ID11

ID10

Figure 6.77 ID1 register (PAGE0 -61h)


R /W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

ID27

ID26

ID25

ID24

ID23

ID22

ID21

ID20

ID27

ID26

ID25

ID24

ID23

ID22

ID21

ID20

Figure 6.78 ID2 register (PAGE0 -62h)


R /W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

ID37

ID36

ID35

ID34

ID33

ID32

ID31

ID30

ID37

ID36

ID35

ID34

ID33

ID32

ID31

ID30

Figure 6.79 ID3 register (PAGE0 -63h)

ID1~ID3: ID setting related register.

6.33 Memory write control register (PAGE0 -68h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

WEM
ODE

WEM
ODE

Figure 6.80 Memory write control register (PAGE0 -68h)

WEMODE: Memory write control register.


WEMODE = 0: When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the
exceeding data will be ignored.
WEMODE = 1: When the transfer number of data exceeds (EC-SC+1)*(EP-SP+1), the
column and page number will be reset, and the exceeding data will be written into the
following column and page.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.138April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.34 TE interval control register (PAGE0 -69h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

TEI2

TEI1

TEI0

TEI2

TEI1

TEI0

Figure 6.81 TE interval control register (PAGE0 -69h)

TEI[2:0]: TE output interval control.


TEI[2:0]
3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

TE Output Interval
1 frame
2 frame
3 frame
4 frame
5 frame
6 frame
7 frame
8 frame

6.35 RGB SRAM cycle control register (PAGE0 -6Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

DEN
C2

DEN
C1

DEN
C0

DEN
C2

DEN
C1

DEN
C0

Figure 6.82 RGB SRAM cycle control register (PAGE0 -6Ah)

DENC[2:0]: Set the GRAM write cycle through the RGB interface.
DENC[2:0]
3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

GRAM Write Cycle


1 frame
2 frame
3 frame
4 frame
5 frame
6 frame
7 frame
8 frame

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.139April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.36 Data format control register (PAGE0 -6Bh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

EPF1

EFP0

DFM

EPF1

EPF0

DFM

Figure 6.83 Data format control register (PAGE0 -6Bh)

EPF[1:0]: Set the data mapping 16-bit/pixel data to 18-bit internal GRAM.
EPF[1:0]

Gate Outputs in Non-display Area

2b00

r[5:0] = {R[4:0],0}
g[5:0] = G[5:0]
b[5:0] = {B[4:0],0}
Exception: R[4:0], B[4:0]=5h1F => r[5:0], b[5:0]=6h3E

2b01

r[5:0] = {R[4:0],1}
g[5:0] = G[5:0]
b[5:0] = {B[4:0],1}
Exception: R[4:0], B[4:0]=5h00 => r[5:0], b[5:0]=6h01

2b10

r[5:0] = {R[4:0],R[4]}
g[5:0] = G[5:0]
b[5:0] = {B[4:0],B[4]}

2b11

Compare R[4:0], G[5:1] and B[4:0] :


Case 1: R=G=B => r[5:0] = {R[4:0], G[0]}, g[5:0] = G[5:0],
b[5:0] = {B[4:0], G[0]}
Case 2: R=BG => r[5:0] = {R[4:0], R[4]}, g[5:0] = G[5:0],
b[5:0] = {B[4:0], B[4]}
Case 3: R=GB => r[5:0] = {R[4:0], G[0]}, g[5:0] = G[5:0],
b[5:0] = {B[4:0], B[4]}
Case 4: B=GR => r[5:0] = {R[4:0], R[4]}, g[5:0] = G[5:0],
b[5:0] = {B[4:0], G[0]}

DFM: No function.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.140April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.37 Frame rate control 1~8 register (PAGE0 -70h~77h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BC0

DIV0
1

DIV0
0

BC0

DIV0
1

DIV0
0

Figure 6.84 Frame rate control 1 register (PAGE0 -70h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RTN0 RTN0 RTN0 RTN0 RTN0


4
3
2
1
0

RTN0 RTN0 RTN0 RTN0 RTN0


4
3
2
1
0

Figure 6.85 Frame rate control 2 register (PAGE0 -71h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BP07

BP06

BP05

BP04

BP03

BP02

BP01

BP00

BP07

BP06

BP05

BP04

BP03

BP02

BP01

BP00

Figure 6.86 Frame rate control 3 register (PAGE0 -72h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

FP07

FP06

FP05

FP04

FP03

FP02

FP01

FP00

FP07

FP06

FP05

FP04

FP03

FP02

FP01

FP00

Figure 6.87 Frame rate control 4 register (PAGE0 -73h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BC2

DIV2
1

DIV2
0

BC2

DIV2
1

DIV2
0

Figure 6.88 Frame rate control 5 register (PAGE0 -74h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

RTN2 RTN2 RTN2 RTN2 RTN2


4
3
2
1
0

RTN2 RTN2 RTN2 RTN2 RTN2


4
3
2
1
0

Figure 6.89 Frame rate control 6 register (PAGE0 -75h)

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.141April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

BP27

BP26

BP25

BP24

BP23

BP22

BP21

BP20

BP27

BP26

BP25

BP24

BP23

BP22

BP21

BP20

Figure 6.90 Frame rate control 7 register (PAGE0 -76h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

FP27

FP26

FP25

FP24

FP23

FP22

FP21

FP20

FP27

FP26

FP25

FP24

FP23

FP22

FP21

FP20

Figure 6.91 Frame rate control 8 register (PAGE0 -77h)

BC0: Used to select Normal/Partial mode VCOM drive waveform.


BC2: Used to select Idle mode VCOM drive waveform.
0: Frame inversion waveform is selected
1: Line inversion waveform is selected.
DIV0[1:0]: Used to set Normal/Partial mode division ratio of internal clock frequency. The
internal operation is synchronized with the frequency divided internal clock. When DIV0
setting is changed, the width od the reference clock for LC control signals is changed. The
frame frequency can be adjusted by register setting (RTN and DIV bits)
DIV2[1:0]: Used to set Idle mode division ratio of internal clock frequency. The internal
operation is synchronized with the frequency divided internal clock. When DIV2 setting is
changed, the width od the reference clock for LC control signals is changed. The frame
frequency can be adjusted by register setting (RTN and DIV bits)
DIV0/2[1:0]

Division Ratio

2b00
2b01
2b10
2b11

fosc/1
fosc/2
fosc/4
fosc/8

RTN0[4:0]: Specify Normal/Partial mode clock number of one line period for internal
operation.
RTN2[4:0]: Specify Idle mode clock number of one line period for internal operation.
RTN0/2[4:0]
5b00000
5b00001
5b00010
5b00011
5b00100
5b00101
5b00110
5b00111
5b01000
5b01001
5b01010
5b01011

Clock cycles=1/internal operation clock frequency(fosc)


Clock number per Line
RTN0/2[4:0]
Clock number per Line
Setting Inhibited
5b10000
132
Setting Inhibited
5b10001
133
Setting Inhibited
5b10010
134
Setting Inhibited
5b10011
135
Setting Inhibited
5b10100
136
Setting Inhibited
5b10101
137
Setting Inhibited
5b10110
138
Setting Inhibited
5b10111
139
Setting Inhibited
5b11000
140
Setting Inhibited
5b11001
141
Setting Inhibited
5b11010
142
127
5b11011
143

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.142April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
5b01100
5b01101
5b01110
5b01111

128
129
130
131

5b11100
5b11101
5b11110
5b11111

DATA SHEET Temporary V01


144
145
146
147

BP0[7:0]: Specify Normal/Partial mode back porch lines.


BP2[7:0]: Specify Idle mode back porch lines.
FP0[7:0]: Specify Normal/Partial mode front porch lines.
FP2[7:0]: Specify Idle mode front porch lines.
BP0/2[7:0], FP0/2[7:0]

Line number of back/front porch

000d
001d
002d
003d
004d
:
127d
128d
129d
130d
131d
132d
:
142d
others

15
16
17
18
19
:
142
Setting Inhibited
Setting Inhibited
2
3
4
:
14
Setting Inhibited

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.143April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.38 Power control 6~11 register (PAGE0 -7Ah~7Fh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SAP0 SAP0 SAP0


2
1
0

SAP0 SAP0 SAP0


2
1
0

Figure 6.92 Power control 6 register (PAGE0 -7Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

DC10 DC10 DC10


2
1
0

DC00 DC00 DC00


2
1
0

DC10 DC10 DC10


2
1
0

DC00 DC00 DC00


2
1
0

Figure 6.93 Power control 7 register (PAGE0 -7Bh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SAP1 SAP1 SAP1


2
1
0

SAP1 SAP1 SAP1


2
1
0

Figure 6.94 Power control 8 register (PAGE0 -7Ch)


R/W

DNC

RB7

RB6

RB5

RB4

DC11 DC11 DC11


2
1
0

DC11 DC11 DC11


2
1
0

RB3

RB2

RB1

RB0

DC01 DC01 DC01


2
1
0

DC01 DC01 DC01


2
1
0

Figure 6.95 Power control 9 register (PAGE0 -7Dh)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

SAP2 SAP2 SAP2


2
1
0

SAP2 SAP2 SAP2


2
1
0

RB2

RB1

RB0

Figure 6.96 Power control 10 register (PAGE0 -7Eh)


R/W

DNC

RB7

RB6

RB5

RB4

DC12 DC12 DC12


2
1
0

DC12 DC12 DC12


2
1
0

RB3

RB2

RB1

RB0

DC02 DC02 DC02


2
1
0

DC02 DC02 DC02


2
1
0

Figure 6.97 Power control 11 register (PAGE0 -7Fh)

SAP0[2:0]: Used to adjust the Normal mode constant current in the operational amplifier
circuit in the LCD power supply circuit. Larger constant current enhances the driving ability of
the LCD, but it also increases the current consumption. In no-display period, set
SAP0[2:0]=3b000 to halt the operational amplifier circuit and the step-up circuits to reduce
current consumption.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.144April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

SAP1[2:0]: Used to adjust the Partial mode constant current in the operational amplifier
circuit in the LCD power supply circuit. Larger constant current enhances the driving ability of
the LCD, but it also increases the current consumption. In no-display period, set
SAP1[2:0]=3b000 to halt the operational amplifier circuit and the step-up circuits to reduce
current consumption.
SAP2[2:0]: Used to adjust the Idle mode constant current in the operational amplifier circuit
in the LCD power supply circuit. Larger constant current enhances the driving ability of the
LCD, but it also increases the current consumption. In no-display period, set
SAP2[2:0]=3b000 to halt the operational amplifier circuit and the step-up circuits to reduce
current consumption.
SAP0/1/2[2:0]
3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

Gamma Driver Amplifier


Halt operation
1.00
1.00
1.00
0.75
0.75
0.75
0.50

Source Driver Amplifier


Halt operation
1.00
0.75
0.50
1.00
0.75
0.50
0.50

DC00[2:0]: Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1 for
DDVDH voltage generation in Normal mode.
DC01[2:0]: Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1 for
DDVDH voltage generation in Partial mode.
DC02[2:0]: Set the operating frequency of the step-up circuit 1 and extra step-up circuit 1 for
DDVDH voltage generation in Idle mode.
DC00/1/2[2:0]

Operation Frequency of Step-up Circuit 1


and Extra Step-up circuit 1

3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

x H Line Frequency
x H Line Frequency
1 x H Line Frequency
1.5 x H Line Frequency
2 x H Line Frequency
3 x H Line Frequency
4 x H Line Frequency
8 x H Line Frequency

DC10[2:0]: Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and VCL
voltage generation in Normal mode.
DC11[2:0]: Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and VCL
voltage generation in Partial mode.
DC12[2:0]: Set the operating frequency of the step-up circuit 2 and 3 for VGH, VGL and VCL
voltage generation in Idle mode.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.145April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01
DC10/1/2[2:0]

Operation Frequency of Step-up Circuit 2,


Step-up Circuit 3

3b000
3b001
3b010
3b011
3b100
3b101
3b110
3b111

x H Line Frequency
x H Line Frequency
1 x H Line Frequency
1.5 x H Line Frequency
2 x H Line Frequency
3 x H Line Frequency
4 x H Line Frequency
8 x H Line Frequency

6.39 VPP voltage control register (PAGE0 -86h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VPP2 VPP1 VPP0

VPP2 VPP1 VPP0

Figure 6.98 VPP voltage control register (PAGE0 -86h)

VPP[2:0]: Internal generated OTP VPP voltage setting.


VPP2
0
0
0
0
1
1
1
1

VPP1
0
0
1
1
0
0
1
1

VPP0
0
1
0
1
0
1
0
1

VPP Voltage
7.2V
7.3V
7.4V
7.5V
7.6V
7.7V
7.8V
Exrenal VPP Supplied

6.40 Get scan line 1~2 register (PAGE0 -88h~89h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SL15

SL14

SL13

SL12

SL11

SL10

SL9

SL8

Figure 6.99 Get scan line 2 register (PAGE0 -88h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

SL7

SL6

SL5

SL4

SL3

SL2

SL1

SL0

Figure 6.100 Get scan line 1 register (PAGE0 -89h)

SL[15:0]: The display module returns the current scanline, N, used to update the display device.
The total number of scanlines on a display device is defined as VSYNC + VBP + VACT + VFP. The
first scanline is defined as the first line of V Sync and is denoted as Line 0.

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.146April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.41 Read VCOM OTP times register (PAGE0 -R8Ah)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

VCOM_
OTP_TI
MES3

VCOM_
OTP_TI
MES2

VCOM_
OTP_TI
MES1

VCOM_
OTP_TI
MES0

Figure 6.101 Read VCOM OTP times register (PAGE0 -R8Ah)

VCOM_OTP_TIMES[3:0]: Read VCOM OTP programmed times.


VCOM_OTP_TIMES[3:0] VCOM OTP programmed times
4b0000
Not programmed
1 time
4b0001
2 times
4b0010
3 times
4b0011
4 times
4b0100
5 times
4b0101
6 times
4b0110
7 times
4b0111
8 times
4b1000

6.42 Read ID OTP times register (PAGE0 -R8Bh)


R/W
R

DNC
1

RB7
0

RB6
0

RB5
0

RB4

RB3

RB2

RB1

RB0

ID_OT
P_TIM
ES3

ID_OT
P_TIM
ES2

ID_OT
P_TIM
ES1

ID_OT
P_TIM
ES0

Figure 6.102 Read ID OTP times register (PAGE0 -R8Bh)

ID_OTP_TIMES[3:0]: Read ID OTP programmed times.


ID_OTP_TIMES[3:0]
4b0000
4b0001
4b0010
4b0011
4b0100
4b0101
4b0110
4b0111
4b1000

ID OTP programmed times


Not programmed
1 time
2 times
3 times
4 times
5 times
6 times
7 times
8 times

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.147April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.43 Command page select register (RFFh)


R/ W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0
PAGE
_SEL
0
PAGE
_SEL
0

PAGE
_SEL
1

PAGE
_SEL
1

Figure 6.103 Command page select register (RFFh)

PAGE_SEL[1:0]: Command set page select.


PAGE_SEL1
0
0

PAGE_SEL0
0
1

Command Page
Page 0
Page 1

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.148April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.44 DGC control register (PAGE1 -00h)


R /W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

DGC
_EN

DGC
_EN

Figure 6.104 DGC control register (PAGE1 -00h)

DGC_EN: Digital gamma correction enable.


0: Disable
1: Enable

6.45 DGC LUT register (PAGE1 -01h~63h)


R /W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

D7

D6

D5

D4

D3

D2

D1

D0

D7

D6

D5

D4

D3

D2

D1

D0

Figure 6.105 DGC LUT register (PAGE1 -01h~63h)

There are 99 bytes DGC LUT to set R, G, B gamma independently. When DGC_EN=1, R, G, B
gamma will mapping V0, V2, V4, ...., V60, V62, V63 voltage to the LUT register setting gray
level voltage of real gamma. V(2N+1) = (V(2N) + V(2N+2))/2 (N=0~30).
LUT
R01h
R02h
R03h
:
:
R20h
R21h
R22h
R23h
R24h
:
:
R41h
R42h
R43h
R44h
R45h
:
:
R62h
R63h

D7
R007
R017
R027
:
:
R317
R327
G007
G017
G027
:
:
G317
G327
B007
B017
B027
:
:
B317
B327

D6
R006
R016
R026
:
:
R316
R326
G006
G016
G026
:
:
G316
R326
B006
B016
B026
:
:
B316
B326

D5
R005
R015
R025
:
:
R315
R325
G005
G015
G025
:
:
G315
G325
B005
B015
B025
:
:
B315
B325

D4
R004
R014
R024
:
:
R314
R324
G004
G014
G024
:
:
G314
G324
B004
B014
B024
:
:
B314
B324

D3
R003
R013
R023
:
:
R313
R323
G003
G013
G023
:
:
G313
G323
B003
B013
B023
:
:
B313
B323

D2
R002
R012
R022
:
:
R312
R322
G002
G012
G022
:
:
G312
G322
B002
B012
B022
:
:
B312
B322

D1
R001
R011
R021
:
:
R311
R321
G001
G011
G021
:
:
G311
G321
B001
B011
B021
:
:
B311
B321

D0
R000
R010
R020
:
:
R310
R320
G000
G010
G020
:
:
G310
G320
B000
B010
B020
:
:
B310
B320

Default Gray Mapping


00h
R_V0
08h
R_V2
10h
R_V4
:
:
:
:
F8h
R_V62
FCh
R_V63
00h
G_V0
08h
G_V2
10h
G_V4
:
:
:
:
F8h
G_V62
FCh
G_V63
00h
B_V0
08h
B_V2
10h
B_V4
:
:
:
:
F8h
B_V62
FCh
B_V63

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.149April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

6.46 CABC control 5 & 7 register (PAGE1 C3h, C5h)


R/W

DNC

RB7
LED
ONP
OL
LED
ONP
OL

RB6

RB5

RB4

PWM
DIV2

PWM
DIV1

PWM
DIV0

PWM
DIV2

PWM
DIV1

PWM
DIV0

RB3

RB2

SEL_
GAIN
1
SEL_
GAIN
1

SEL_
GAIN
0
SEL_
GAIN
0

RB1
INVP
LUS
INVP
LUS

RB0
SEL_
BLDU
TY
SEL_
BLDU
TY

Figure 6.106 CABC control 5 register (PAGE1 C3h)


R/W

DNC

RB7

RB6

RB5

RB4

RB3

RB2

RB1

RB0

PWM PWM PWM PWM PWM PWM PWM PWM


_PER _PER _PER _PER _PER _PER _PER _PER
IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0
PWM PWM PWM PWM PWM PWM PWM PWM
_PER _PER _PER _PER _PER _PER _PER _PER
IOD7 IOD6 IOD5 IOD4 IOD3 IOD2 IOD1 IOD0

Figure 6.107 CABC control 7 register (PAGE1 C5h)

LEDONPOL: The control reigister for LED driver when IC needs enable signal.
0: LEDONPOL pin=L.
1: LEDONPOL pin=H.
PWMDIV[2:0]: Internal PWM_CLK divider for CABC clock.
PWMDIV[2:0]
0
1
2
3
4
5
6
7

Divider
PWM_CLK/1
PWM_CLK/2
PWM_CLK/4
PWM_CLK/8
PWM_CLK/16
PWM_CLK/32
PWM_CLK/64
PWM_CLK/128

SEL_GAIN[1:0]: CABC gain select. (Not Open)


SEL_BLDUTY: The backlight PWM output duty on/off control when CABC operated.
0: The backlight PWM output duty is 100%.
1: The backlight PWM output duty is calculated from CABC operation.
INVPULS: The backlight PWM output polarity select.
0, The backlight PWM output is low level active.
1, The backlight PWM output is high level active.
PWM_PERIOD[7:0] : The backlight PWM output period setting.
Backlight PWM output period = 1 / (PWM_CLK / clock divider (PWMDIV)) x
(255x(PWM_PERIOD[7:0]+1))

Himax Confidential Temporary Version


This information contained herein is the exclusive property of Himax and shall not be distributed, reproduced, or disclosed
in whole or in part without prior written permission of Himax.

-P.150April, 2010

HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

7. Layout Recommendation
7.1 Layout Recommendation
Panel_VCOM
A2

10

C22
10

10

C21
10

10

C31
10

C5

10
10

C1
10

10

C2
10

10

VCI (2.5V~3.3V)

10

C4
10

10

C12
10

10

C11
10

VREG1

50

VTEST

100

TE

10

VGS

10
100

10

10

C3
10

SDO
SDI_SDA
TE

100
100
100

NRD

10
100

DNC

100
100

NWR_SCL
NCS

100
10

DB0

100

DB2

100
100

DB1

100

DB3

10

DB4
DB5

100
100

DB6
DB7

100
100

DB8

IOVCC (1.65V~3.3V)

10
100

10

DB9

100

DB10
DB11

100
100
10

DB12
DB13
DB14

100
100
100
100

DB15

10

DB16
DB17
PCLK
DE

100
100
100
100

HSYNC
VSYNC
CABC_PWM_OUT
LEDON

10
100
100
100
100
10

NRESET
IFSEL

100
100
10

IM0

100
100

IM2

100

IM1

10

100

VCI (2.5V~3.3V)

10

10

10

10

10

DUMMY36
C22N
C22N
C22N
C22P
C22P
C22P
C21N
C21N
C21N
C21P
C21P
C21P
C13N
C13N
C13N
C13P
C13P
C13P
VCL
VCL
VCL
VSSD
VGH
VGH
VGH
VGH
VGH
VGH
VSSD
VSSD
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VGL
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
DUMMY35
DUMMY34
DUMMY33
DUMMY32
DUMMY31
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VCI
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
DDVDH
C12N
C12N
C12N
C12N
C12N
C12P
C12P
C12P
C12P
C12P
C11N
C11N
C11N
C11N
C11N
C11P
C11P
C11P
C11P
C11P
DUMMY30
VREG1
DUMMY29
VTEST
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VGS
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VSSA
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOML_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOMH_DUMMY
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
VCOM
DUMMY28
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
VDDD
SDO
SDI_SDA
TE
VSSD
NRD
NWR_SCL
DNC
NCS
VSSD
DB0
DB1
DB2
DB3
VSSD
DB4
DB5
DB6
DB7
VSSD
DB8
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
IOVCC
DB9
DB10
DB11
VSSD
DB12
DB13
DB14
DB15
VSSD
DB16
DB17
PCLK
DE
IOVCC
HSYNC
VSYNC
CABC_PWM_OUT
LEDON
VSSD
NRESET
IFSEL
IOVCC
IM0
IM1
IM2
DUMMY27
VSSD
TEST1
TEST2
DUMMY26
DUMMY25
OSC
TS0
TS1
TS2
TS3
TS4
TS5
TS6
TS7
DUMMY24
VCI
VCI
VCI
VCI
VCI
VCI
VCI
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
VSSD
DUMMY23
DUMMY22
DUMMY21
DUMMY20
DUMMY19
DUMMY18
DUMMY17
DUMMY16
DUMMY15
DUMMY14
VSSD
DUMMY13
DUMMY12
DUMMY11
DUMMY10
DUMMY9
DUMMY8
DUMMY7
DUMMY6
DUMMY5
VSSD
DUMMY4
DUMMY3
DUMMY2
DUMMY1
VSSD
DUMMYR2
DUMMYR1

DUMMY37 DUMMY38
DUMMY39 VGL
G2
G4
G6

G8

G10

G12
G16

G14
G18

G20

G410
G414

G412

G418

G420

G422

G424

G426

G428
G432

G430
VGL

G416

DUMMY40 S720
S719
S718
S717

S716

S715

S714

S713

S712

S711

S710

S709

S375

S374

S373

S372

S371
S369
S367

X
(0,0)

S708

S370
S368
S366

S365

S364

S363

S362

S361

DUMMY41
DUMMY42 DUMMY43
DUMMY44

Pin Assignment
HX8352-C
Face Down

DUMMY45
DUMMY46 DUMMY47
DUMMY48
S360
S359
S358
S357
S356
S355
S354
S353
S351

S352

S349

S348

S347

S346

S350

S12
S11

S10

S9

S8

S7

S6

S5
S3

S4
S2

S1

DUMMY49

VGL
G431
G427
G423
G419

G429
G425
G421
G417

G415

G413

G411

G409

G19

G17

G15
G11

G13

G7

G5

G3

G1

G9

VGL

DUMMY50
DUMMYR3 DUMMYR4
A1

Panel_VCOM

Figure 7.1: Layout Recommendation

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

7.2 Maximum layout resistance


Name

Type

Maximum series
resistance
10
10
10
10
100
100
100
100
100
100
10
10
10
50
10
10
10
10
100

IOVCC
Power supply
VCI
Power supply
VSSD
Power supply
VSSA
Power supply
IFSEL, IM[2:0]
Input
NRD, NWR_SCL, DNC, NCS, NRESET
Input
HSYNC, VSYNC, DE, PCLK
Input
SDI_SDA
Input + Output
DB[17:0]
Output
SDO, CABC_PWM_OUT, LEDON, TE
Output
VCOM
Output
VDDD
Capacitor Connection
DDVDH
Capacitor Connection
VREG1
Output
VGS
Power supply
VCL
Capacitor Connection
VGL
Capacitor Connection
VGH
Capacitor Connection
OSC
Input
C11P,C11N,C12P,C12N,,
C21P,C21N,C22P,C22N,
Capacitor Connection
C31P,C31N
TEST[2:1]
Input
VTEST, TS[7:0]
Output
Table 7.1: Maximum Layout Resistance

Unit

10

100
100

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

7.3 External Components Connection


Internal charge pumping mode:
Symbol

Pad Name

Connection

C1
C2
C11
C12
C21
C22
C31
C3
C4
C5

VGH
VGL
C11P C11N
C12P C12N
C21P C21N
C22P C22N
C31P C31N
VDDD
DDVDH
VCL

Connect to Capacitor (Min. 25V): VGH ---(+)----| |--- (-)----- VSSA


Connect to Capacitor (Min. 16V): VGL ---(+)----| |--- (-)----- VSSA
Connect to Capacitor (Min. 6V): C11P ---(+)----| |--- (-)-----C11N
Connect to Capacitor (Min. 6V): C12P ---(+)----| |--- (-)-----C12N
Connect to Capacitor (Min. 10V): C21P ---(+)----| |--- (-)-----C21N
Connect to Capacitor (Min. 10V): C22P ---(+)----| |--- (-)-----C22N
Connect to Capacitor (Min. 6V): C31P ---(+)----| |--- (-)-----C31N
Connect to Capacitor (Min. 6V): VDDD ---(+)----| |--- (-)-----VSSD
Connect to Capacitor (Min. 10V):DDVDH ---(+)----| |--- (-)-----VSSA
Connect to Capacitor (Min. 6V):VCL ---(+)----| |--- (-)-----VSSA

Typical
Component
Value
1 F
1 F
1 F
1 F
1 F
1 F
1 F
1 F
1 F
1 F

Table 7.2: Adoptability of component

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8. Electrical Characteristics
8.1 Absolute maximum ratings
The absolute maximum ratings are list on Table 8.1. When used out of the absolute maximum
ratings, the LSI may be permanently damaged. Using the LSI within the following electrical
characteristics limit is strongly recommended for normal operation. If these electrical
characteristic conditions are exceeded during normal operation, the LSI will malfunction and
cause poor reliability.
Item
Power Supply Voltage 1
Power Supply Voltage 2
Power Supply Voltage 3
Power Supply Voltage 4
Power Supply Voltage 5
Power Supply Voltage 6
Power Supply Voltage 6
Operating Temperature
Storage Temperature

Symbol

Unit

Value

Note

IOVCC~ VSSD
VCI ~ VSSA
DDVDH ~ VSSA
VSSA ~ VCL
DDVDH ~ VCL
VGH ~ VSSA
VSSA ~ VGL
Topr
Tstg

V
V
V
V
V
V
V
C
C

-0.3 to +4.6
-0.3 to +4.6
-0.3 to +6.6
-0.3 to +4.6
-0.3 to +9
-0.3 to 18.5
-16.5 to 0
-40 to +85
-55 to +110

Note
(1),(3)
Note
(4)
Note
(5)
Note
(6)
Note
(7)
Note
(8)
Note
(9)
Note
(10)
Note

(1),(2)

Note: (1) IOVCC, VCI, VSSD, VSSSA must be maintained.


(2) To make sure IOVCC VSSD.
(3) To make sure VCI VSSA.
(4) To make sure DDVDH VSSA.
(5) To make sure VSSA VCL.
(6) To make sure DDVDH VCL
(7) To make sure VGH VSSA.
(8) To make sure VSSA VGL
VGH +|VGL| < 32V
(9) For die and wafer products, specified up to +85.
(10) This temperature specifications apply to the TCP package.

Table 8.1: Absolute maximum rating

8.2 ESD protection level


Mode

Test condition

Criteria

Human Body Model

C=100 pF, R=1.5 k

2.0KV

Machine Model

C=200 pF, R=0.0

200V

Standard
MIL-STD-883F
Method 3015.7
EIA/JEDEC
JESD22-A115-A

Table 8.2: ESD protection level

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HX8352-C(T)
240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8.3 DC characteristics
(VCI=2.5 ~ 3.3V, IOVCC=1.65~3.3V, T A=-40 ~ 85 C)
Item

Symbol

Unit

Test condition

Max.

VIH
VIL

V
V

IOVCC=1.65 ~ 3.3V
IOVCC=1.65 ~ 3.3V

Min.
0.7xIOVCC
-0.3V

Typ.

Input high voltage


Input low voltage
Output high voltage
( DB0-17 Pins,
SDA/SDO)
Output low voltage
( DB0-17 Pins,
SDA/SDO)
I/O leakage current
Current consumption
during normal operation
( IOVCC-VSSD )

IOVCC
0.3xIOVCC

VOH1

IOH= -1mA

0.8xIOVCC

VOL1

IOVCC=1.65 ~ 2.4V
IOL=1mA

0.2xIOVCC

ILi

Vin=0 ~ IOVCC

TBD.

IOP(IOVCC)

TBD.

TBD.

TBD.

TBD.

Current consumption
during normal operation
( VCI VSSA )

IOP(VCI)

Current consumption
during standby mode
IST(IOVCC)
( IOVCC-VSSD )
Current consumption
during standby mode
IST(VCI)
(VCI-VSSA)
Output voltage deviation
Dispersion of the
V
Average Output Voltage

mA

IOVCC=VCI=2.8V ,
Ta=25C ,
GRAM data=0000h,
Frame rate=60Hz,
REV=0
No panel load

A
IOVCC=2.8V, VCI=2.8V ,
Ta=25C
A
mV

TBD.

mV

TBD.

Table 8.3: DC characteristic

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8.4

AC characteristics

8.4.1 8080 system interface characteristics

Figure 8.1: I80 interface characteristics


(VSSA=0V, IOVCC=1.8V, VCI=2.8V, T A=25C)
Signal

Symbol
Parameter
Min.
Max.
tAST
Address setup time
0
DNC
tAHT
Address hold time (Write/Read)
10
tCS
Chip select setup time (Write)
15
tRCS
Chip select setup time (Read register)
45
NCS
Chip select setup time (GRAM)
355
tRCS
tCSF
Chip select wait time (Write/Read)
10
tWC
Write cycle
66
NWR_SCL
tWRH
Control pulse H duration
15
tWRL
Control pulse L duration
15
tRC
Read cycle (read register)
160
tRC
Read cycle (GRAM)
450
NRD
tRDH
Control pulse H duration
90
tRDL
Control pulse L duration(read register)
45
tRDL
Control pulse L duration(GRAM)
355
tWDT
Data setup time
10
tWHT
Data hold time
10
DB[17:0]
tRACC
Read access time(read register)
40
tRACC
Read access time(GRAM)
340
tROH
Output disable time
20
80
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.

Unit

Description

ns

ns

ns

ns

ns

For maximum CL=30pF


For minimum CL=8pF

Table 8.4: I80 interface characteristics

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8.4.2 Serial interface characteristics

Figure 8.2: Serial interface characteristics


(VSSA=0V, IOVCC=1.8V, VCI=2.8V, T A = 25C)
Signal

Symbol
Parameter
Min.
Max.
Unit
tCSS
Chip select setup time (Write)
15
Chip select setup time (Read)
60
tCSS
NCS
ns
tCSH
Chip select hold time (Write)
15
tCSH
Chip select hold time (Read)
65
tAST
Address setup time
0
DNC
ns
tAHT
Address hold time (Write/Read)
10
tWC
Write cycle
66
NWR_SCL
Control pulse H duration
15
ns
tWRH
(Write)
Control pulse L duration
15
tWRL
tRC
Read cycle
150
NWR_SCL
tRDH
Control pulse H duration
60
ns
(Read)
tRDL
Control pulse L duration
60
SDI_SDA
tDS
Data setup time
10
ns
(Input)
tDT
Data hold time
10
SDA, SDO
tRACC
Read access time
10
50
ns
(Output)
tOD
Output disable time
15
50
Note: The input signal rise time and fall time (tr, tf) is specified at 15 ns or less.
Logic high and low levels are specified as 30% and 70% of IOVCC for Input signals.

Description
-

For maximum CL=30pF


For minimum CL=8pF

Table 8.5: Serial interface characteristics

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8.4.3 RGB interface characteristics

Figure 8.3: General timings for RGB I/F-1

(TA=25C, IOVCC=1.65~3.3V, VCI=2.5~3.3V, VSSA=0V)


Item
Vertical sync. Setup Time
Vertical sync. Hold Time
Horizontal sync. Setup Time
Horizontal sync. Hold Time
Pixel Clock Cycle
Pixel Clock Setup Time
Pixel Clock High Time
Data Setup Time DB[17:0], Enable
Data Hold Time DB[17:0], Enable

Symbol

Condition

VSST
VSHT
HSST
HSHT
PCLKCYC
PLCKLT
PCLKHT
DST
DHT

18-/ 16-bit
-

Min.
10
10
10
10
100
10
10
10
10

Spec.
Typ.
-

Max.
-

Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns

Note: (1) Signal rise and fall times are equal or less than 20ns.
(2) Measure of input signals are using 0.3xIOVCC for low state and 0.7xIOVCC for high state.

Table 8.6: RGB interface characteristics-1

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

Figure 8.4: General timings for RGB I/F-2

Item
Vertical Timing
Vertical cycle period
Vertical low pulse width
Vertical front porch
Vertical back porch
Vertical blanking period
Vertical active area

Symbol

Condition

TVP
TVS
TVFP
TVBP
TVBL

TVS + TVBP + TVFP

TVDISP

Min
438
2
2
2
6
-

Specification
Type.
2
2
6
10
432

Max
503
6
63
71
80

Vertical refresh rate


TVRR
Frame rate
50
60
Horizontal Timing
Horizontal cycle period
THP
246
1008
Horizontal low pulse width
THS
2
2
256
Horizontal front porch
THFP
2
2
256
Horizontal back porch
THBP
2
6
256
Horizontal blanking period
THBL
THS + THBP + THFP
6
10
768
Horizontal active area
THDISP
240
Pixel clock cycle
fCLKCYC
5.39
16.6
Note: (1) IOVCC=1.65 to 3.3V, VCI=2.5 to 3.3V, VSSA=VSSD=0V, Ta=-30 to 70 (to +85 no damage)
(2) Data lines can be set to High or Low during blanking time Dont care.
(3) HP is multiples of PCLK.

Unit
HS
HS
HS
HS
HS
HS
HS
HS
Hz
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
MHz

Table 8.7: RGB interface characteristics-2

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

8.4.4 Reset input timing

Figure 8.5: Reset input timing


Symbol
tRESW
tREST

Parameter
(1)
Reset low pulse width
Reset complete time

Related pins
NRESET

Min.
10

Typ.
-

Max.
-

120

(2)

Note
When reset is applied
during Standby mode
When reset is applied
during STB Out mode

Unit
s
ms
ms

Note: (1) Spike due to an electrostatic discharge on NRESET line does not cause irregular system reset according to the
table below.
NRESET Pulse
Action
Reset Rejected
Shorter than 5s
Reset
Longer than 10 s
Between 5 s and 10 s Reset Start
(2) During the resetting period, the display will be blanked (The display is entering blanking sequence, which
maximum time is 120 ms, when Reset Starts in Standby Out mode. The display remains the blank state in
Standby mode) and then returns to Default condition for H/W reset.
(3) During Reset Complete Time, ID2 value in OTP will be latched to internal register during this period. This loading
is done every time when there is H/W reset complete time (tREST) within 5ms after a rising edge of NRESET.
(4) Spike Rejection also applies during a valid reset pulse as shown below:

(5) When Reset is applied during Standby Mode.


(6) When Reset is applied during Standby Out Mode.
(7) It is necessary to wait 5msec after releasing NRESET before sending commands. Also Standby Out command
cannot be sent for 120msec.

Table 8.8: Reset timing

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240RGBx432dots, TFT Mobile Single Chip Driver
DATA SHEET Temporary V01

9. Ordering Information
Part No.
HX8352-C000 PDxxx

Package
PD: mean COG
xxx: mean chip thickness (m), (default: 250 m)

10. Revision History


01

Date
2010/03/31
2010/04/15

2010/04/28

Description of Changes
New setup
1. Modify Pin 63 and Pin 68 in P.17.
2. Modify TEI[2:0] setting in P.139.
3. Modify NL[5:0] setting in P.126.
4. Modify DIVE[1:0] setting in P.126.
1. Modify OTP flow in P.99~P100.

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