Chapter 1

Introduction
Silicon-Germanium Heterojunction Bipolar Transistors (SiGe HBTs) are superior in
performance to Si BJTs and are comparable to the GaAs transistors since they are suitable for
low power wireless applications. SiGe HBTs utilize the advantage of relatively simple
integration with conventional CMOS and BiCMOS technologies. Although GaAs, InP exhibit
better high frequency performance than SiGe HBTs for a specific geometry they lack the
advantages of a highly developed processing technology.
The principle of operation of HBTs is the same as that of BJTs with the exception that the
bandgap of the base region is smaller than that of the emitter region. This resultant
increase in current gain gives the scope to reduce the base width and increase the base doping
thereby improving the high frequency circuit performance.
1.1 Objective
In this work we systematically design an HBT with the objective of optimizing the device
structure for better high frequency performance. Some of the measures of circuit performance
improvement include higher values of current gain , unity gain cutoff frequency fT,
maximum oscillation frequency, fmax. In the process we need to make some fundamental
tradeoffs according as the demands of the device application. As the device is getting scaled
continuously the effect of noise is becoming increasingly important. In this work we study
the different noise behavior in HBT and supplement it with a suitable model and try to
optimize the device structure for minimum noise without affecting the circuit performance or
film stability. For our experiments we use SILVACO TCAD tools ATHENA (Process
simulator) and ATLAS (Device simulator) and the various simulations packages BLAZE,
SPISCES and NOISE that are used in conjunction with ATLAS.

1.2 Overview
As mentioned earlier in HBT introduction of Ge in the base results in bandgap reduction of
the base that allows for higher doping and also narrowing of the base width to obtain a higher
current gain and a smaller base transit time. In addition to this Ge grading in the base results
in grading of the potential barrier for the carriers in the base. This gives rise to a band-grading
field that accelerates the carriers and reduces the transit time even more. While designing the
collector we go for a profile that results in reduced field in the collector-base junction, low
values of collector-base capacitance and less charge storage.
With scaling down of devices study of noise has become a very important topic. Particularly
frequency dependence of noise adversely affects the device performance at higher
frequencies. In our design process we thus need to consider noise as one of our optimization
criteria. Noise in low frequency originates from various complex trapping-detrapping
mechanisms in the device. This low frequency noise gets coupled and upconverted in RF
oscillators and contributes to the phase noise thus degrading the performance.
1.3 Organization of the thesis
In chapter 2 we talk about the silicon-germanium heterojunction bipolar transistor, the
various models and parameters for the device necessary for simulation purpose. In chapter 3
we take up collector optimization; we introduce different (graded, retrograded and flat)
collector profiles and optimize for reduced collector-base capacitance, higher breakdown
voltage, delayed onset of Kirk effect and at the same time lesser transit time. Chapter 4 talks
about base design where we introduce graded Ge profiles in the base and show the variation
of the different figures of merit such as f T and fmax; the high injection effcts are discussed and
an attempt made to reduce Ge enhanced hih injection effects. Chapter 6 gives the different
noise models based on Y-parameters and an optimization technique to obtain a device
structure with minimum Noise Figure. Chapter 7 identifies the various types of noise in HBT
and in chapter 8 we take up a study of low frequency noise with the case of a SiGe:C HBT.

Chapter 2
Simulation of Silicon Germanium Heterojunction Bipolar Transistor

In order to understand how the heterojunction device operates we need to look into the energy
band diagram.

Fig 2.1 Energy band diagram for SiGe HBT (Reference: [1])
The key idea of an HBT is to lower the potential barrier seen by the carriers responsible for
output current compared with the ones responsible for input current, thereby increasing the
current gain. This is achieved as shown in the above figure where the potential barrier for the
holes constituting the base current increases and the potential barrier for electrons
constituting the collector current decreases due to incorporation of Ge in the base, leading to
enhancement of by a factor

. As will be discussed in chapter 4, grading of Ge

concentration further reduces the bandwidth.

2.1 Device Modeling and material parameters

The addition of Ge changes the properties of the base region and the emitter-base and
collector base junctions [1] and hence suitable models and material parameters need to be
chosen for simulation purpose. The lattice constant of strained Si 1-xGex varies from that of Si;
Ge modifies the dielectric constant, bandgap, and the density of states; in addition parameters
like mobility, diffusivity change owing to effects like alloy scattering. The material
parameters depend on the concentration of Ge (i.e. x)
In our experiments we use a physically based device simulator ATLAS to characterize the
device. The device structure is generated by process simulator ATHENA. The structure is
mapped into a 2-D mesh and the simulators apply a set of partial differential equations
(Maxwells equations, Boltzmans transport equation, Poissons equation etc) along with the
supplied bias conditions to solve for the carrier transport characteristics.
2.1.1 Mobility
ATLAS assumes the drift diffusion model, the energy balance and the hydrodynamic models
[1] for transport equations. In ATLAS a wide range of mobility models are available for SiGe
HBT. In low field region mobility is primarily degraded by phonon scattering and impurity
scattering, whereas in high field regions the limiting parameters are velocity saturation and
hot carrier effects. In addition to these alloy scattering and strain also affect the mobility
according to Mathiessens rule. The 1-D device simulator SCORPIO describes mobility
enhancement of holes as well as electrons in SiGe as

= (1+K.x)

2.1

where k is a fitting constant ~10.

2.1.2 Bandgap

One of the most significant parameters depending on the Ge composition x is bandgap.

Bandgap is dependent on temperature; there are several polynomial models for temperature
dependence of bandgap. For dependence on Ge compostion we have several empirical
models derived from fitting observed data. ATLAS uses complex piecewise linear functions
over different ranges of x; these can be found in details in ATLAS users manual [2].

2.1.3 Electron affinity

Electron affinity is independent of Ge and is same as that of Si [2].
2.1.4 Effective density of states
Effective density of states decreases with Ge concentration because the amount of degeneracy
in the valence and conduction band decreases. ATLAS users empirical relations for modeling
purpose.
2.1.5 Bandgap Narrowing
ATLAS assumes the same model for Si as well as SiGe for high doping induced bandgap
narrowing. This assumption is found to hold good for doping levels as high as 1e19 cm -2 but
seem to face problems beyond that [1].
2.1.6 Recombination models
ATLAS has several recombination models like SRH, Auger, radiative recombination models.
2.1.7 Lattice constant and Germanium film stability
Si (5.43A) and Ge (5.65A) have a lattice mismatch of 4.2% thus when Si 1-xGex is grown on Si
substrate (as is the case with our HBT) it is subject to compressive strain. The lattice constant
of Si1-xGex is given by
a (Si1-xGex) = a (Si) + x. a(Ge)

. 2.2

As the thickness of the SiGe layer increases so does the strain energy and at some point misfit
dislocations are obtained. Thus there is a critical thickness which again depends on the
composition of Ge, x. This is shown in figure 2.2

Fig 2.2 Figure showing variation of critical thickness of Si1-xGex alloy with Ge composition x
(source: [1])
2.2 High Frequency figures of merit
2.2.1 Unity gain cutoff frequency fT
fT is the frequency at which common emitter short circuit ac current gain is unity. It is the
inverse of the transit time from emitter to collector. The emitter-base transit time takes into
consideration the delay due to the neutral emitter, due to the emitter base space charge,
neutral base transit time, collector-base space charge time and finally the collector transit
time. Decreasing any of these time periods increases fT.

. 2.3

Reducing the capacitive effects at the junctions also improves fT .

2.2.2 Maximum oscillation frequency, fmax
fT does not take into consideration the effects of the base resistance and the collector base
capacitance which however affect the circuit performance at high frequencies. The maximum

oscillation frequency or fmax denotes the frequency at which the unilateral power gain is unity,
and it given by

It takes into account the charging time due to internal capacitance and hence is a more
representative figure of merit than fT.
2.3 Breakdown Voltage BVCE0 and BVCB0
Collector breakdown is limited by Zener and Avalanche breakdowns. Zener breakdown
occurs when both the n and p sides are highly doped and tunneling occurs. Avalanche
breakdown occurs at very high voltage when the carriers gain in sufficient kinetic energy to
collide with and impact ionize other carriers. The collector emitter breakdown voltage at
common emitter configuration BVCE0 is essential as it gives an upper limit for the supply
voltage. It is related to the common base breakdown voltage BVCB0 as

As we shall see in the subsequent chapters a fundamental tradeoff exists between fT and BVCE0
given by Johnsons Limit.

Chapter 3
Collector Design

3.1 Introduction
The main considerations during collector design are based on conflicting requirements to
achieve a low base-collector capacitance, low base-collector signal delay, a high breakdown
voltage and also maintain a high value of fT simultaneously.
The collector doping profile decides the base-collector transit time which plays a major
component in the forward transit time and also the base-collector intrinsic capacitance which
along with the bas resistance plays an important role in the circuit performance.
Another factor to be taken care of during base design is the base widening and Kirk Effect in
high injections.
In this section we discuss several collector doping profiles and their pros and cons and try to
arrive at an optimum one by trading off some requirements for others. The collector emitter
breakdown voltage BVCE0 is related to the fT value according to Johnsons Limit and falls
monotonically as the design is modified to increase fT .
To discuss collector design, some phenomena need to be discussed first, they are Kirk Effect
and base pushing effect, and Johnson limit.

3.2 Kirk Effect

The observed fall-off of unity gain cutoff frequency f T at high current densities is attributed to
the phenomenon of base widening i.e. spreading of the neutral base into the collector region
in high current densities. At sufficiently high collector current levels the mobile space-charge
density in the collector transition region cannot be considered negligible in comparison to the
fixed charge density in that region. [3]. The effect of taking the mobile space charge into
account is that at high current densities (high field) the transition region boundary adjacent to
the neutral base is displaced towards the collector thereby increasing the base transit time,
which forms a major part of the forward transit time for a bipolar transistor.
We derive [4] the expression for the critical current density JK for a collector doping of NC(x).
and as a function of the depletion width, W. Now our derivations are based on the assumption
that at the onset of kirk effect n(x) is not negligible compared to N C(x). Thus applying Gauss
Law to the Poissons equation =q.[N(c)-n(x)] over the depletion layer thickness W , we
have (Electric field being zero at both base-collector junction and the end of the depletion
layer).

dx = 0 =

dx

3.1

From where we have

Jk = -q.

= -q.<N><v>

3.2

Where <N> is the average doping concentration in the collector and <v> is the harmonic
mean velocity.

3.3 Johnsons limit

It is fundamental tradeoff between the cutoff frequency f T and the breakdown voltage of the
reverse biased collector-base junction, BVCE0. In a bipolar transistor the unity gain cutoff f T is
given as
fT= 1/(2)

3.3

where represents the average transit time from emitter to collector. Now, for a given value
of the emitter-collector distance, L, the transit time is minimized when the average drift
velocity is maximized. With very high field, velocity saturation is attained. The transit time
can be reduced by reducing the emitter-collector distance L. However, there is a limit on the
value of L, set up by the breakdown field (E=V/L , where V is the collector emitter voltage).
This in simple words is Johnsons Limit [5]. In our case to increase f T by reducing the basecollector transit time, we can increase collector doping, however that would undermine the
base-collector breakdown properties. This is reflected in Fig 1.

10

Fig. 3.1 Showing Johnsons Limit, BVCE0 vs fT plot. [6]

3.4 Graded and Retrograded Collectors and Selectively Implanted Collectors (SIC)
A conventional way to suppress base widening at high injections is to have a thin, highly
doped epitaxial collector layer; however this undermines the BV CE0 characteristics. One of the
methods to suppress base widening and at the same time have an appreciable breakdown
voltage is to have retrograde doping of the collector. We use lowly doped collector epi-layers
formed with selective implantations (SIC). The figures 3.2a through 3.2d describe the graded
and retrograded collector profiles.

11

Fig 3.2(a)

Fig 3.2(b)
12

Fig 3.2(c)

Fig 3.2(d)
13

Fig. 3.2 a-d. (a) Dopant distribution for graded collector. (b) Device structure for graded
collector. (c) Doping distribution for retrograde collector. (d) Device structure for retrograde
collector.
3.4.1 Graded Collector Profiles: Results
Let us now see how BVCE0 changes with the position of the peak in a graded collector profile.
The closer the peak is to the collector-base junction the higher is the doping in the depletion
region and lesser is the breakdown voltage.
BVCE0 = BVCB0 / 1/n

Fig 3.3(a)

14

.3.4

Fig 3.3(b)

Fig 3.3(c)

15

Fig 3.3(d)

Fig 3.3(e)

16

Fig 3.3(f)
Fig 3.3 a-f. (a-b) BVCB0 = 10V (BVCE0 = 3.98V) (c-d) BVCB0 = 9V (BVCE0 = 3.58V)
(e-f) BVCB0 = 8V (BVCE0 = 3.18 V); different collector profiles, the closer the peak is to the
base-collector junction the lesser is the breakdown voltage.
However owing to the high doping concentration in the base-collector region, the basecollector depletion layer width is reduced resulting in a reduction in base collector transit
time. Also as the collector doping exceeds that of the tail of the base doping, the basecollector junction is formed inside the base thus reducing the base width and reducing the
base transit time. This leads to enhancement of the high frequency performance as the overall
forward transit time is reduced.

17

Fig 3.4 IC vs fT curves for the three different profiles shown above in figures 3.3 a-c

From Fig 3.4 it is evident that the profile (c) with the highest doping closest to the basecollector junction has the maximum value of unity gain cutoff frequency, f T but the lowest
value of BVCE0.This is because with high collector doping the base-collector transit time is
reduced while the breakdown voltage also falls. This reflects Johnsons limit.
Thus for device applications which could allow a relatively low value of BV CE0 we can have
graded collector profiles and take advantage of the enhanced cutoff frequency and gain.
3.4.2 Retrograde Collector Profiles: Results
18

To suppress base widening and at the same time maintain a high value of junction
breakdown, we can retrograde the doping profile in the collector. High energy implants are
used for this purpose; the profile and the device structure have been shown in Fig 3.2c and
3.2d respectively.
The following table gives the fT, BVCB0 and BVCE0 values corresponding to different implant
energies.
Implant Energy

fT max (Ghz)

BVCB0 (V)

BVCE0 (V)

(KeV)
160
200
240
280
320

36.4
34
30
27.5
26

16.6
20
28
32
37

5.93
7.23
10.31
11.91
13.87

172
162
148
140
135

Table 3.1 Device parameters for the various retrograde collector profiles.

Fig 3.5 Maximum fT vs implant energy for the different retrograde profiles.

19

Fig 3.6 BVCE0 vs implant energy for the retrograde profiles.

Fig 3.7 vs implant energy for the different retrograde profiles

20

Fig 3.8 BVCE0 vs maximum fT for the different retrograde profiles.

As the SIC implant energy is increased, the peak of the collector doping shifts towards the
bulk and the concentration at the collector base junction decreases. Thus the depletion layer
width increases and base push-out effects become more prominent at high currents. This
results in decrease in fT value with increasing implant energy.
As the base collector depletion width increases and doping density decreases the capacitance
decreases. Thus we have a reduced field profile which leads to higher breakdown voltages
and hence higher values of BVCE0.

21

Fig 3.9 Figure shows reduction of electric field in the junction region due to the retrograde
profile.

Thus with a suitable retrograde profile we can have a fT - BVCE0 tradeoff following Johnsons
Limit. For device applications requiring high value of BV CE0 such as in high power devices,
the retrograde collector profile has to be assumed.

3.5 Selectively Implanted Collector profiles and effect on circuit performance

One of the major disadvantages of having a high doping concentration at the collector-base
junction is a high value of the C CB which affects the circuit performance of the device. One of
the ways to reduce the collector base capacitance is to have an SIC profile where
implantations for the collector are done only in the active emitter window. This way the
external base-collector capacitance gets reduced. Using medium to high energy implants we
22

can have various collector profiles from graded to retrograded. In current high speed low
voltage devices a retrograde profile with concentration increasing towards the buried
collector is desired. That way the maximum electric field in the base collector junction is
decreased compared to uniformly doped collector [7] .
Figures 3.10 and 3.11 show the structures corresponding to SIC profile for graded collector
(30KeV) profile and retrograde collector (240KeV) profiles respectively.

Fig 3.10 Showing structure for graded SIC profile

23

Fig 3.11 Showing structure for retrograded SIC profile

Fig 3.12 Figure showing enhancement of with selective implantation in the collector

24

Fig 3.13 Figure showing enhancement of fT with SIC energy variation

As it can be seen from figures 3.12 and 3.13 there is considerable performance improvement
when the collector is selectively doped; for such high implant energies the profile assumes a
retrograde shape. For the graded profiles the improvement in fT and is more pronounced.
Implant Energy
30KeV

for non-SIC profile

233

for SIC
257

fT for non-SIC
35.7GHz

fT for SIC
41GHz

Table 3.2 Showing device parameters for graded collector SIC and non-SIC devices
Although the gain () and fT values are higher for the graded collector device than that of the
retrograde devices, the increased collector base doping in graded devices highly undermines
the circuit performance by reducing the value of fmax i.e. the frequency where unilateral power
gain is 0dB. For the graded collector device discussed above with f T as 41GHz the fmax =
24GHz. Figure 3.14 and 3.15 show fmax (for vBE=0.75V) values for the different devices
(different implantation energies.)

25

Fig 3.14 fmax vs SIC Implant energy

Fig 3.15 Bar diagram comparing fT and fmax in retrograde SIC

As can be seen from figure 3.14 in retrograde collectors the maximum oscillation frequency
is improved mainly due to less collector base capacitance.

26

3.6 Antimony (Sb) Launcher profile

Narrow doping peaks called launchers have been demonstrated in [7]. The material used as a
launcher is Antimony (Sb) because of its low diffusivity; therefore the launcher profile
remains unchanged due to temperature effects and further processing steps. The highly doped
Sb implant close to the base-collector junction suppresses the base widening and compensates
for the boron out-diffusion. Thus onset of Kirk effect is delayed to a higher current density
and eventually the device can attain higher and f T values. For correct evaluation of the
event, it needs to be modeled using non-local impact ionization. Figures 3.16 and 3.17
describe the fT and characteristics of a device with retrograde collector and another with a
retrograde doping as well as an Sb launcher implant.
Thickness of the Sb launcher layer was around 20nm.
From the figures it is observed that the and f T roll off occurs at higher current density thus
implicating suppression of Kirk effect by the Sb launcher. However this design poses some
problems also. Due to high doping at the base-collector junction the capacitance is increased
which is undesired for the circuit performance of the device. At high I C the launcher device

27

enters into quasi-saturation due to the high voltage drop across the lowly doped part of the
collector and hence and fT rolls of very rapidly.
Gunnar Malm et. al observed similar variations in and f T in [7] which support our
simulation results and serve as a validation. The exact magnitudes are different because of
different doping concentrations and other design parameters. The results in [7] are shown in
Fig 3.18 and 3.19 for quick reference.

Fig 3.16 vs IC curves for two devices with and without a launcher.

28

Fig 3.17 fT vs IC curves for two devices with and without launcher.

Fig 3.18 vs IC curves Source: [7]

29

Fig 3.19 fT vs IC curves Source: [7]

3.7 Summary
In this chapter we study different collector profiles and their pros and cons and try to arrive at
a suitable tradeoff situation. Graded collectors have high values of fT due to reduced base
transit time and base-collector depletion layer transit time; however they have lower values of
BVCE0 compared to retrograde collectors. Retrograde collectors also have a low collector base
capacitance which improves the circuit performance of the device and also a lower electric
field in the junction regions. In order to suppress Kirk Effect and delay it to higher currents
we use narrow highly doped antimony launcher profiles; the collector base capacitance is
increased due to higher doping and also the device moves into quasi saturation and and f T
roll off is much rapid.
The external collector base capacitances can be reduced by selectively implanted collector
design by implanting through the active window for emitter implantation.

30

Chapter 4
Base Design
4.1 Introduction
The introduction of Ge into the base of a bipolar transistor reduces the bandgap in the base
(SiGe alloy) relative to the Si in the emitter and collector regions. This reduction in bandgap
is utilized to enhance the performance of SiGe HBTs. The concentration of charge carriers
(electrons) injected into the base is higher in HBTs compared to the conventional BJT due to
a lower conduction band barrier. As an effect, the current gain in an HBT can be related [1] to
that of a conventional BJT as
SiGe = Si exp( Eg(x)/ KT )

4.1

Where Eg(x) = EgSi - EgSiGe(x)

31

This implies that compared to a similarly doped BJT, the collector current will be much
higher; however the base current remains unaffected. In a conventional BJT a high emitter
injection efficiency demands that the emitter be more doped than the base.
The main incentive of HBT however, is not the high current gain, but the high frequency
performance. The high current gain is traded off with a high base doping. Increased base
doping concentrations reduces the base resistance, which improves the fmax for the device.
The key idea of bandgap engineering exploited in an HBT is to lower the potential barrier
seen by the carriers responsible for output current, while keeping that seen by the carriers of
input current unaffected. The following figure (Fig 4.1) shows the band diagram of a typical
n-p-n SiGe HBT and explains this.

Fig4.1 Shows lowering of conduction band in the base region due to incorporation of Ge. [1]
For the purpose of comparison it is considered that both the transistors are similar other than
the base of one of them is SiGe.
It is observed that grading the concentration of Ge in the base region results in bandgap
grading with depth in the base; this results in a bandgap grading field in the base. This field
accelerates the carriers and thus reduces the base transit time. This is illustrated in the
following figure. (Fig 4.2). Reduction in base transit time improves the fT value of the device.

32

Fig4.2 Band Energy diagram across a SiGe HBT in forward active mode. [1]

4.2 The SiGe:C HBT

A key problem in n-p-n SiGe HBT is the out-diffusion of boron in the epitaxy-subsequent
phases. Since the diffusivity of boron is quite high, heat treatments and transient enhanced
diffusion (TED) caused by annealing implantation defects lead to the broadening of the thin
base doping layer of boron [8]. A high base doping concentration of boron is required to
improve high frequency performance as discussed before.
This is highly undesirable as it leads to formation of parasitic potential barrier in the
conduction band, thereby compromising the current gain. This poses as a serious issue in
modern BiCMOS process integration where SiGe HBTs are used as it reduces the thermal
budget and also necessitates absence of As implant. [8]
To accommodate this effect undoped spacer layers of SiGe are grown on either side of the
doped base. However, here also a technological problem is faced as the thickness is limited
with strain induced dislocation constraints. [9]
It has been observed that incorporation of carbon into the base of SiGe HBT substitutionally
suppresses the TED of boron. [8].

33

Fig. 4.3 SIMS of SiGe, SiGeC and SiGe/SiGeC/SiGe devices implanted with As and
annealed at 755C. [8]
The suppression of TED is governed by the competition between boron and carbon in the
substitutional sites of the lattice to occupy the silicon self-interstitials. [10]

4.3 Base design through process simulations

4.3.1 Triangular, Box and Trapezoidal profiles: Results
The main considerations related to base design are those of a high cutoff frequency and high
current gain. At the same time, base doping needs to be kept high so that we have the minimal
base resistance. In this section of the work we design different base profiles and discuss the
pros and cons using the SILVACO TCAD tool for process simulation ATHENA and
characterize the devices using the 2-D device simulator ATLAS.
In this work we consider three types of Ge profiles, a box profile, a triangular profile and a
trapezoidal profile. Figures 4.4, 4.5 and 4.6 show different representative profiles.

34

Fig 4.4 Box profile of Ge; x=0.15

Fig 4.5 Triangular Ge profile x=0.02 to x=0.22

35

Fig 4.6 Trapezoidal Ge profile x=0.05 to x=0.22 with xT/wB=0.6

Figure 4.7 Shows the energy band diagram across three structures (box with x=0.15; and
triangular and trapezoidal with x=0.02 to 0.22).
36

One thing to be noted in the figure is the grading of the band edges as in the case of the
triangular profile. This gives rise to a band grading field which accelerates the mobile charges
and thus helps to reduce the forward transit time and enhances high frequency operation of
the device. Thus the triangular profile is expected to have highest value of fT. Whereas since
depends directly on the percentage of Ge in the base-emitter junction the flat (box) profile
can be utilized to have the maximum gain value, all other parameters kept unchanged. These
are shown in figures 4.8 and 4.9

Fig 4.8 Showing gain vs IC for the three profiles (with same average Ge content in the base)

37

Fig 4.9 Showing fT vs IC for the three profiles.

Currently we shall discuss trapezoidal Ge profiles in the base as it is found to be an optimum

profile to support high current gain as well as cutoff frequency.
4.3.2 Optimal trapezoidal profile: Results
We shall now try to further optimize this base profile in terms of germanium content and
position of the ramp (XT). The criteria for optimization would be base transit time
minimization at the same time have a high gain. In a later chapter we shall further try some
optimization method for noise reduction.

38

Fig 4.10 Showing the grading in trapezoidal base.

We know that for a BJT with base width WB the base transit time is given as WB2/ 2Dn
For a SiGe HBT with trapezoidal Ge profile in the base as schematically in figure 4.10, the
base transit time could be expresses as [11]

+ kTX2T

4.2

We normalize this transit time B with respect to the base transit time of BJT (W B2/ 2Dn) and
obtain
= B / (WB2/ 2Dn )

4.3

To find an optimum trapezium profile we have to find an optimum value for (X T/WB ). Thus
differentiating with respect to X T/WB we get a relationship in X T/WB from where an
optimum value can be obtained.

| XTopt = 0
39

4.4

In our simulations we derive different structures with different Ge profiles having (X T / WB)
value ranging from 0.3 to 0.8 and observed parameters like , f T , fmax and hence tried to
arrive at some optimum profile. The table below summarizes the observations.
XT / WB
0.3
0.4
0.5
0.6
0.7
0.8

155
135
117.7
98
85.4
74.6

Max fT GHz
36.8
38.5
39.1
38.7
37.4
35.7

fmax GHz
38
36.7
34
32.7
33
30

Table 4.1 Showing performance of different devices with different SiGe trapezoidal profiles
in their base
From the data it can be seen that increases monotonically as we move from triangular to
box profile through trapezoidal profiles. This is expected as depends directly on the slope of
the Ge profile at the emitter edge.
The reason of fT variation with wT is the band grading field distribution. The graded electric
field reduces the amount of base charge stored per unit collector current.
As we approach a triangular profile the fmax values decrease monotonically, this reflects the
variation of the base resistance which increases monotonically too.

40

Fig 4.11 vs IC variation for the different profiles

Fig 4.12 fT vs IC variation for the different profiles

Thus from the above figures it is evident that X T = 0.5 corresponds to an optimum Ge
trapezoidal profile optimized for minimum base transit time.
4.3.3 Position of the Ge peak and onset of Kirk effect (Ge induced high injection effects)
The abrupt fall in Ge concentration in the collector side gives rise to a barrier at the base
collector junction which opposes carrier transport [12]. The barrier is located in the basecollector depletion region close to the neutral base and during high current densities due to
base pushout effect it affects the net electric field. The accumulating carriers in the space
charge region reduces the total electric field and hence reduces carrier velocity, thus
degrading fT . When the local electric field reduces to the same order as that of the retarding
field, carrier accumulation starts thus hastening high injection effects. Thus we observe high
injection before Kirk Effect predicts it. This phenomena is termed Ge induced high injection
effect. In order to reduce this effect we can retrograde the Ge towards the collector so that the
slope is less and hence the retarding field is less.

41

Fig 4.13 Showing onset of fT roll off in box, trapezoidal and triangular profiles
Let us consider figure 4.13 showing fT vs IC for the different profiles, box, triangular and
trapezoidal. The onset of fT roll off is the earliest in the box profile as evident from the figures
whereas the knee current density has its maximum value for the triangular profile. During
high injection the band grading field plays an important role in determining onset of f T rolloff. Since in the box profile there is no band grading field, the f T values start degrading as
predicted by Kirk effect. In triangular profile the band grading field is maximum (recall
figure 4.7) and uniform throughout the base, whereas in the trapezoidal devices the field
distribution is complex. During base widening the band grading field accelerates the carriers
and compensates somewhat for the increased base width and hence f T roll off is delayed than
what is predicted in Kirk effect.
4.4 Base Resistance
For better circuit performance in high frequency it is desired to have a low base resistance. In
HBTs taking advantage of enhancement through band gap reduction the base is heavily
doped and the base resistance is lowered. The base resistance R bb is divided into two parts
namely the intrinsic base resistance or R bi describing the resistance of the neutral base part
under the active emitter window, and Rbx or extrinsic base resistance corresponding to the link
region and the semiconductor region underneath the base contact [13].
42

Extraction of external base resistance is essential in order to know the maximum oscillation
frequency, fmax given as

...4.5

fmax =

Where = CbciRbi + CbcxRbx

4.6

Conventional approach of extracting Rbx can be found in [14] based on Z parameters. The
technique involves plotting of Re (Z11 Z12) vs 1/Ib and linearly extrapolating the plot;
however at very high base currents most of the base is short circuited due to current crowding
effects and results are erroneous. In [13] the authors have expressed Re (Z 11 - Z12) as an
effective base resistance comprising of the external base resistance and a scaled factor of the
intrinsic resistance and the extrinsic resistance. At high frequencies the intrinsic part becomes
negligible and we can approximate Rbx to be Re (Z11 Z12).

Fig 4.14 Showing Extraction of Rbx. Re (Z11 Z12) vs frequency. Rbx= 12.

43

Figure 4.14 gives the Rbx extraction for the optimized trapezoidal Ge / retrograde collector
SIC profile at 1mA current. As it can be seen R bx remains constant at 12. As a verification
of the order of the resistance, in [13] Rbx for the InP/InGaAs device was extracted to be 8.
The overall effect of base resistance (intrinsic and extrinsic) can be exactly calculated from
the fT and fmax values. For the optimized profile at hand
fT is 41.2GHz
fmax is 32 GHz and
CCB at 10GHz and 1mA current is around 10fF.
With these data at hand the equivalent base resistance can be calculated as 75.

4.5 Summary
While designing the base we exploit the phenomena of bandgap reduction due to Ge in the
base of HBT and hence make high doping in the base in order to reduce the base resistance.
In case of graded Ge profiles due to grading of the bandwidth there exists a band-grading
field along the base which accelerates charges and reduces base transit time. Hence for the
same average Ge concentration a triangular or trapezoidal profile has smaller base transit
time than a box profile. On the other hand since current gain depends directly on the extent of
bandgap reduction at the emitter-base junction which in turn depends on the amount of Ge
and the gradient of the Ge profile in the emitter-base junction, hence the box profile has the
maximum value of . So a tradeoff exists and the trapezoidal profile stands out to be an
optimal one. The band grading field is non-uniform in the trapezoidal profile and hence the
base transit time depends on the position of the peak concentration. It is found that the
highest fT values are obtained for XT/XB = 0.5 which is thus considered as the optimal profile.

44

Due to abrupt fall of Ge concentration at the base-collector junction a retarding field is

developed which becomes important in high injection hastening base widening and Kirk
effect. This phenomenon is often referred to as high injection effects due to Ge. This effect
can be reduced by retrograding the tail of the Ge profile into the collector.
The base resistance is a critical parameter for the HBT as it directly affects circuit behavior.
The base resistance is extracted from the high frequency characteristics; also the external
base resistance is estimated from the simulated Z-parameters.
The device thus optimized has a retrograde collector SIC doping, an optimized trapezoidal Ge
profile and high base doping. The different figures of merit can be listed as
max = 119.2
fT = 41.2 GHz
and fmax = 32GHz .

Chapter 5
Emitter Design

While designing the emitter the desired parameters are low emitter saturation current density,
low emitter resistance, low charge storage and a low emitter-base capacitance [1]. To meet
these requirements we use polysilicon emitter contact.
An alternate structure can be a high-low emitter profile consisting of a thin epitaxial emitter
cap layer and a heavily doped polysilicon layer above it. Such a structure allows a further
reduction in the emitter-base capacitance thereby increasing the fT at lower collector currents,
and also decouples the base from the emitter and hence allows for arbitrary high base doping.
The emitter cap thickness need to be controlled (around 200-300A) so as to minimize the
charge storage effects. The highly doped polysilicon ensures low emitter resistance [1].
45

The polysilicon emitter transistor has a more complex oxide structure near the base-emitter
junction compared to its monocrystalline counterpart. The key difference lies in the process
steps [15]. In crystalline emitter transistors, the emitter is either implanted or diffused into the
monocrystalline silicon and metal is used as a contact. Whereas, in poly-emitter transistors
the process is self-aligned. The ploy is either doped in situ or deposited and then doped
through ion implantation.
To improve the current gain, normally a thin layer (10 to 30 Angstroms) of oxide (interfacial
oxide or IFO) is grown between the polycrystalline and monocrystalline emitters. This oxide
acts as a barrier to minority carriers being injected into the emitter. However, the IFO is
found to be acting as a site for source of low frequency noise.

Chapter 6
Noise in semiconductors

Noise is unwanted fluctuations in the signal. In semiconductors noise originate from random
behaviors of the charge carriers and depends on frequency, defect density, material purity and
many other factors. In this chapter we would briefly introduce the different types of noise
namely thermal noise, shot noise, generation-recombination noise and flicker noise and
describe their origin.
6.1 Thermal Noise
Thermal noise or Johnsons noise or white noise originates from thermally activated random
fluctuations in current or voltage [16]. It depends directly on the absolute temperature, but is

46

independent of frequency and can be attributed to the Brownian motion of the carriers.
Thermal noise forms the noise floor and is always there at the background.
The noise power spectral density for a resistance of R at absolute temperature T is given
by
< Vn2 > = 4kTRf

6.1

Where k is Boltzmanns constant and f denotes the bandwidth of observation

6.2 Shot Noise

Shot noise originates from fluctuations associated with charges flowing across a potential
barrier and hence can be observed in transistors where electrons and holes which constitute
the DC current transcend the p-n junction barriers.
The noise power spectral density is given by
< in2 > = 2qIDC f

6.2

In bipolar transistors the base current and the collector current shot noises plays an important
role as we shall be seeing in the next chapter. The emitter current shot noise forms a part of
both the base and collector current shot noise with some phase difference and thus are
correlated. While modeling noise in bipolar devices, considering this correlation is essential.
6.3 Generation-recombination noise (GR noise)
GR noise originates mostly due to random trapping and de-trapping of carriers by trap centers
and variation of number of carriers in the process. The number fluctuations can be given by

and the noise PSD can be given by

6.4

47

This gives a Lorentzian spectrum in the frequency domain.

6.4 Flicker Noise (1/f noise)

Flicker noise affects in the low frequency spectrum as it is of 1/f type but becomes
increasingly important for high frequency applications as it gets up converted by super
heterodynes in mixers and other applications. The origin of flicker noise is yet to be known
for sure, there are two schools of thought one due to McWhorter another due to Hooge.
McWhorter gives a number fluctuation theory based on trapping and detrapping of carriers by
interface traps. Hooges mobility fluctuation theory assigns the origin of 1/f noise to bulk
mobility fluctuations. The combined McWhorter-Hooge model suggests that 1/f noises
originate due to mobility fluctuations arising out of trapping and de-trapping of carriers at the
interface traps.
We shall discuss Flicker noise in detail in a subsequent chapter.

Chapter 7
Modeling of noise in HBT

RF transceiver blocks like LNA, mixer often require very low broad-band noise, high gain,
excellent linearity, thus complicating the design. In this chapter we discuss an intuitive noise
model and identify the noise sources for the control of profile design for the HBT.
SiGe profiles are designed to explicitly improve the noise performance without sacrificing the
film stability and other key performance metrics.

48

We examine the key issues using the 2-D process and device simulators ATHENA and
ATLAS respectively.
7.1 The y-parameter based noise model
The input of the noise model is the device y-parameters which can be simulated or calculated
from the s-parameters. At high frequencies the major noise sources in the transistor include
the base current shot noise, the collector current shot noise and the base resistance induced
thermal noise. These sources are shown in Fig.7.1.

Fig 7.1 Schematic of noise sources in bipolar transistor.

According to circuit theory any linear noisy two-port network can be represented as a
noiseless 2-port, an input current noise source, i n and an input voltage noise source, vn. This
representation is shown in Fig.7.2.

49

Fig.7.2 2-port network representation of the device.

Traditional way of noise modeling is to compute noise figure from an equivalent circuit. In
this case the minimum noise figure (NFmin), optimum source admittance , Yopt, and the noise
resistance Rn can be expressed explicitly as functions of < vn >, < in > and < vn > < in* > .
Noise figure gives the estimate of the extent to which the device under consideration
degrades the input SNR or in other words how much noise gets added into the circuit because
of the device itself.

SNRinput =

7.1

SNRoutput =

7.2

Noise Factor, F =

.7.3

Noise figure, NF = 10 log (Noise Factor, F)

50

.7.4

For the given models of the transistor, vn and in can be derived [17] as
< in2 > = 2qIB + 2qIC / |h21|2

7.5

< vn2 > = 4KTRB + 2qIC / |y21|2

7.6

< vn in* > = 2qIC y*11 / |y21|2

7.7

Where y21 and h21 are the AC transconductance and AC current gain at the frequency of
interest respectively and y11 is the input admittance.
Physically thinking, the current noise source is contributed by the base current shot noise and
the collector current shot noise and the voltage noise source is contributed by the base
resistance induced thermal noise and the collector current shot noise. Noise figure can be
decreased by reducing either <v2n> or <i2n>.
7.1.1 Input noise current limiting factors
Let us consider the bias current dependence of the collector current shot noise. Firstly, at a
particular frequency of operation the term |h21|2 increases with IC and saturates when fT
becomes much larger than the frequency of operation, eventually decreases at higher currents
when high injection effects set in. However, for RF applications such as LNA we do not need
such high values of IC. Again the term 2qIC increases monotonically with IC.
Thus the term 2qIC / |h21|2 first decreases with IC and then increases.
The contribution from the base current shot noise, 2qIB dominates <in2>, implying that a high
value of is required to reduce <in2>.
7.1.2 Input noise voltage limiting factors
As we had mentioned before the RF applications like LNA do not operate at very high
currents where high injection effects creep in and f T roll-off starts. At such current densities, |
y21| can be expressed as
|y21| = q IC / kT

.7.8

Thus the contribution from the collector current shot noise is independent of any transistor
parameters and solely depends on 1/IC terms (prior to high injection).

51

For the devices under consideration the contribution of the base resistance thermal noise is
dominant over the bias current range. Thus to improve the noise performance one needs to
reduce the base resistance and hence increase the base doping.
7.1.3 Scope of improvement of Noise performance
As mentioned earlier, to improve noise performance we need to reduce <v 2n> and <i2n>. Now,
to reduce RB for the abovementioned purpose we can increase the base doping or increase the
emitter length. The latter however will increase the parasitic capacitances and degrade noise
performance and the former is limited by thermal cycle. Thus <v n2> can be reduced only by
lateral and vertical scaling or by carbon doping. Thus in a given technology generation <v 2n>
and RB is fixed.
We can however lower the <in2> by increasing the value for the transistor: that way we
reduce the contribution from the base current shot noise; and by increasing f T : that way we
increase the denominator part |h21|2.
7.2 Noise optimized HBT structure
Thus the optimization strategy for better noise performance stands as follows: optimization of
the SiGe profile in the base to obtain a high value of and f T at the operating current
densities, under the constraints of film stability. High values of in turn will reduce noise in
the circuit. We simulate several profiles based on this optimization approach and try to attain
better noise performance without affecting circuit performance. The 2-D device simulator
ATLAS is used in conjunction with the process simulator ATHENA.
As a figure of merit, minimum Noise Figure (NF min) is calculated for different profiles. As
discussed above in order to reduce noise figure we have to maximize the current gain. In
chapter 4 we have discussed optimization techniques based on current gain for base profile
design. Here we compare those profiles for NFmin characteristics and verify our postulate.

52

Fig 7.3 NFmin vs frequency for box Ge profile in the base

Fig 7.4 NFmin vs frequency for trapezoidal Ge profile in the base

53

Fig 7.5 NFmin vs frequency for box Ge profile in the base

As can be seen from figures 7.3, 7.4 and 7.5 the box profile with the highest value of has
the lowest value of noise figure of 6dB at 10GHz; whereas the optimum profile i.e. the
trapezoidal profile has NFmin of 6.3dB and the triangular profile which had the lowest value of
has NFmin of 9.5dB. Hence the design we chose for noise optimized HBT structure has
trapezoidal Ge profile in the base.
Now we verify our conjecture that noise is reduced by increasing current gain by studying
different trapezoidal profiles by varying the edge of the triangular part (i.e. X T / WB ). The
results are shown in figure 7.6

54

Fig 7.6 Figure showing how and NFmin varies with XT/WB for a trapezoidal profile
From the above figure, minimum noise will be observed in the device with box Ge profile i.e.
XT/WB = 0; however the device performance (i.e. , f T, fmax) is compromised in that case. Thus
we go for the profile with XT/WB = 0.5 trading off the increase in Noise Figure with improved
device performance.
In the next chapter we would take up a case study of a device. We measure and characterize
the low frequency noise in a SiGe:C base HBT.

55

Chapter 8
Characterization and modeling of low frequency noise in SiGe:C HBT

A Case Study

Low frequency noise is dominated by Flicker Noise (1/f type) and Random Telegraph Noise
(1/f2 type). Low frequency noise behavior of the device is critical as it is upconverted to
phase noise in oscillators through nonlinearities in the I-V C-V characteristics inherent to the
transistor [18]. Thus low frequency noise adds noise sidebands on the carrier frequency and
thus limits the signal purity.
We have introduced flicker noise or 1/f noise in chapter 5. There are two accepted models for
flicker noise namely Hooges model and McWhorters model. Here we describe in brief the
two theories. Flicker noise in SiGe HBTs mostly originates in the pseudomorphic emitterbase and collector-base junction space charge regions.
8.1 Hooges mobility fluctuation model
Hooges model of flicker noise attributes the origin to mobility fluctuations arising out of
lattice scattering in the bulk. The model known as the 1/f model rests on the following
relationship [16]

Where,

8.1

is the Hooges parameter, N the total number of free carriers in the device and I

the short circuit current.

The mobility 1/f noise is suggested to be primarily generated in the phonon scattering. In the
general case, each scattering process j generates mobility fluctuation noise with a magnitude
given by the Hooge parameter of the process

. If the scattering processes are independent

of one another Matthiessens rule can be applied.

56

=
Where

and

varies due to bias.

The Hooges parameter,

can be considered constant, however bias dependence of

scattering phenomena affect the mobility fluctuation noise.

8.2 McWhorters number fluctuation model
The physical mechanism behind the number fluctuation model is trapping and de-trapping of
carriers during their active interaction with trap centres. The fluctuations can be observed in
the base and collector current and voltage power spectrum. The power spectral density for
such noise can be given by

(f) =

8.3

Where denotes the time constant for the carrier-trap system and g() denotes the degeneracy
level of the traps. The McWhorter model assumes no interactions between the trap levels at
different energies; if interactions were present a Lorentzian spectrum instead of 1/f spectrum
would have been observed [18].

Fig. 8.1 Showing superposition of Lorentzian spectra to obtain 1/f noise. [Reference: 18]
57

8.3 Combined Hooge-McWhorter model for low frequency noise

In modern applications a combination of Hooge-McWhorter theory is utilized for low
frequency noise modeling. In this model it is assumed that low frequency noise originates
from trapping and de-trapping of carriers and hence cause a fluctuation in number as well as
mobility which contributes to the fluctuations in conductivity through the relation
= q(n

8.4

8.4 Random Telegraph Noise (RTN)

Random telegraph noise becomes more important when the number of traps is less i.e. when
emitter area is much less i.e. on downscaling of the device. RTN originates from individual
trapping detrapping from the trap centres. Random Telegraph Signal (RTS) shows a
Lorentzian spectrum and is typically 1/f2 type.
Two kinds of traps have been identified; accepter and donor traps and correspondingly the
trap-carrier system can have two characteristic time constants, the capture time and the
emission time. Capture time denotes the average time taken by the trap to capture the carrier
and depends directly on the activation energy of the traps and also on the location of the
traps. Once captured, the carriers are emitted due to thermal emissions; this time to emission
is called emission time. Sometimes they are referred to as high time

and low time

respectively.
The RTS exhibits a Lorentzian spectrum with a corner frequency given by
fC = 1/

+ 1/

8.5

As mentioned earlier RTN depends on the position of the traps and the activation energy; if
the trap level is much higher than the Fermmi level then it is always empty whereas it is
always occupied if it is much below the Fermi level. So ideally the traps have to be within a
few kTs of the Fermi level.
The polysilicon emitter transistor has a more complex oxide structure near the base-emitter
junction compared to its monocrystalline counterpart. The key difference lies in the process
steps [15]. In crystalline emitter transistors, the emitter is either implanted or diffused into the
58

monocrystalline silicon and metal is used as a contact. Whereas, in poly-emitter transistors

the process is self-aligned. The poly is either doped in situ or deposited and then doped
through ion implantation.
A thin crystalline emitter surface is formed by the high temperature drives. The oxide used to
isolate the base and emitter contacts serve as a potential site for trapping detrapping of
carriers and result in Lorentzian type RTS.
Again to improve the current gain, normally a thin layer (10 to 30 Angstroms) of oxide
(interfacial oxide or IFO) is grown between the polycrystalline and monocrystalline emitters.
This oxide acts as a barrier to minority carriers being injected into the emitter. However, the
IFO is found to be acting as an active source for low frequency noise.
Traps in the emitter-base space charge region cause fluctuations in the barrier height across
the junction, which can give rise to RTS pulses. Several physical mechanisms have also been
proposed [19], such as fluctuating barrier height for trap assisted tunneling current,
fluctuating recombination rates at the space charge region due to fluctuation of number of
carriers and so on. Trapping and detrapping will have more pronounced effects if the traps are
located in a bottleneck as happens in this case (base emitter p-n junction and the thin IFO).
8.5 Device details
The details of the process flow for the device used can be obtained in reference 20.
The device used is a poly emitter SiGe:C base (around 30nm basewidth) HBT with maximum
Ge concentration x = 0.2.
The carbon content in the base layer is about 1 X 1020 cm-3.
The emitter area for the device = 0.42 X 0.84 m2.
The value measured was 120 to 150.
fT and fmax values observed were 120GHz and 140GHz respectively. [20]

59

Fig. 8.2 fT and fmax versus collector current at VCE = 2V. [20]

8.6 Measurement setup

The characterization of the device was done with the help of HP 4145B semiconductor
parameter analyzer.
The noise measurement setup included an Agilent E5263A 2-channel high speed source
monitor unit, an SR 570 low noise amplifier (LNA) and Agilent 35670A dynamic signal
analyzer. The SMU provided the necessary base emitter and collector emitter bias.
The minute fluctuations in the base voltage and base current were amplified to the
measureable range using the low noise amplifier .The output of the amplifier is fed to the
dynamic signal analyzer.
A computer interface is connected with the measuring system through GPIB connection to
control the dynamic signal analyzer and for noise data collection.

60

Fig 8.3 A schematic diagram of the experimental setup.

8.7 Results: observations

The following figure shows the IC-VCE plot obtained for the device. The collector bias is
swept from 0V to 1.0V in steps of 0.01V. Different sets of reading are taken for V BE value
from 0.70V to 0.90V.

61

Fig 8.4 Ic versus VCE for the device

Fig. 8.5 Gummel plot to calculate avg. = 120

The low frequency noise in base voltage and collector voltage was observed. The following
figures show the Flicker noise and Random Telegraph noise as observed in the base voltage
and current signals.

62

Fig 8.6 Base voltage Flicker noise.

Fig. 8.7 Random Telegraph noise in base current.

8.8 Results: Analysis

63

The Fourier Transform of the RTS signal was taken to obtain the nature of the noise in the
frequency domain. It was observed that the RTS appeared as Lorentzian 1/f 2 type. The
following figure illustrates.

Fig.8.8 1/f2 type Random Telegraph Noise.

The 1/f2 type noise observed can be attributed to the trapping-detrapping mechanisms in the
IFO and the spacer oxides. In RTS process the current switches between two (or more) states
when a carrier is trapped or detrapped. The characteristic time for an electron trapping is
given by the Shockley Read Hall statistics as :

8.6

where n is the density of electrons in the vicinity of the trap, v th is the thermal velocity of
electrons and e is the electron capture cross section. The emission time of an electron
depends upon the activation energy of the trap with respect to the conduction band.

8.7

64

The base emitter junction is abrupt and the doping concentrations are high on either sides,
therefore tunneling transitions can occur creating traps in the space charge region or in the
IFO.
Trap energy should be within a few kT of the Fermi level; a trap much below the Fermi level
is expected to be always occupied and a trap much above the Fermi level will always be
empty.
It can be shown [19] that when a carrier is trapped in the base-emitter junction region the
base current switches as
IB/IB0 = LS2 / AE.exp(qVBE/nkT)
= LS2 / AE.qVBE/nkT
= -1

if VBE >> nkT/q

if

nkT/q < VBE < nkT/q

if VBE <<- nkT

. 8.8

where AE is the emitter area, IB the amplitude of the RTS, V BE a small fluctuation in the
energy barrier influenced by the trapped carrier and LS a small length over which a charged
carrier can influence its neighbors and n is the ideality factor.
The device under study shows current dependence weaker than I B IB . It is observed to
vary approximately as .exp(qVBE/2kT), the ideality factor n = 2. This implies that
recombination is limited by both carriers. RTS scaling with non-ideal base currents often
originate from oxide traps in the spacer oxide (along the periphery) [19]. Thus, the
microscopic noise sources contributing to the RTS in base current can be assumed to be
originating from the spacer oxide traps.

65

Fig.8.9 IB versus IB
The 1/f noise observed is proportional to the square of IB . This is typically observed when the
microscopic noise sources reside in the base-emitter space charge region. Thus we can
conclude that the microscopic noise sources contributing to the observed Flicker are not
present in the oxide, rather in the space charge region.

Fig. 8.10 SIB versus IB

The characteristic times l , h are plotted with VBE in figure 8.11. Thermal emission of carriers
is independent of bias, whereas capture of carriers depends on the density of electrons in the
66

vicinity of the trap, which changes with bias. The capture cross section depends on bias
which affects both the characteristic times. A small decrease in the electric field due to VBE in
the space charge region however is not expected to cause much variation in the characteristic
times. This is reflected in the results. The emission and capture times decrease but not very
rapidly with the ideality factor as 3.45.

Fig 8.11 Characterisitc low and high times versus VBE.

8.9 Summary
In our work so far we have characterized the low frequency noise behavior of a SiGe:C HBT.
Since the theory of low frequency noises in HBTs is not yet completely developed, we have
tried to draw inferences from various measurements and speculate about the nature of
trapping detrapping mechanisms. The 1/f type Flicker seems to originate from defects in the
base emitter space charge region, whereas the RTS observed can be attributed to noise
sources in the spacer oxide and to some extent the IFO.

67

Chapter 9
Conclusions

In this work we design an optimum SiGe HBT for high frequency applications. The criteria
of optimization were set by high current gain, high cut-off frequency, low base resistance,
low base-collector capacitance and low Noise Figure. The reduction in bandgap

inclusion of Ge in the base results in an enhancement of by a factor of

due to

. We trade of this

gain enhancement to increase the base doping and reduce the base width. Increased base
doping reduces the base resistance and reduced base width reduces the base transit time. In
designing the collector profile our objective is to have a device with high cutoff frequency as
well as a relatively high BVCE0 value. This is made possible by an optimized retrograde
profile which results in reduced field in the base-collector space charge, reduced basecollector capacitance and increased breakdown voltage. In the design of the base region we
grade the Ge composition of the base which gives rise to a bandgrading field that accelerates
the carriers and further reduce the transit time. Different profiles are studied for Ge in the
base and an optimized trapezoidal profile is obtained by calculations and simulations. We
have used polysilicon emitter contact with a thin emitter cap which reduces the emitter-base
capacitance further reducing the transit time.
With downscaling of devices study of noise has become extremely important. In this work we
take up an optimization technique in designing the transistor for minimal noise without
degrading circuit performance. We discuss a noise model given by the Y-parameters of the
device and accordingly decide an optimum structure with low Noise Figure, high current
gain, high cutoff frequencies.
The device parameters for the optimum structure thus obtained are listed in Table 9.1
max
119.2

fT (GHz) fmax GHz) BVCE0(V) NFmin dB

CCB (F)
RB,eff ()
41.2
32
10.31
6.3
10fF
75
Table 9.1 Showing the device parameters for the optimized structure

68

RBx()
12

Bibliography
[1] C.K. Maiti and G.A. Armstrong. Application of Silicon Germanium Heterostructure
Devices. Institute of Physics Publishing, Bristol and Philadelphia.
[2] Silvaco International 1997, SILVACO-ATLAS Manual, Version4.0.
[3] C.T.Kirk, A theory of transistor cutoff frequency falloff at high current densities IEEE,
Transactions on Electron devices, vol. ED-9, no2, pp164-174, Feb 1962.
[4] R.J Hueting, Analysis of the Kirk Effect in silicon based bipolar transistors with a
nonuniform collector profile, IEEE Trans. on Electron Devices Vol 52, No 11, November
2005.
[5] E.O.Johnson, Physical Limitations on frequency and power parameters of transistors
RCA Review, vol. 26, pp163-177, 1965.
[6] S.H.Voldman et al,"Silicon Germanium heterojunction bipolar transistor ESD power
clamps and the Johnson Limit," Electrical Overstress / Electrostatic Discharge Symposium,
2001. EOS/ESD '01. , vol., no., pp.324-334, 11-13 Sept. 2001.
[7] Gunnar Malm et al. Implanted collector profile optimization in a SiGe HBT process,
Solid State Electronics Vol 45 pp 399-404, 2001.
[8] L.Lanzerotti et al.

Suppression of Boron outdiffusion in SiGe HBT by Carbon

incorporation IEEE IEDM 96, pp 249-252.

[9] E. Prinz. The Effects of Base Dopant outdiffusion and undoped SiGe junction spacer
layers in Si/SiGe/Si Heterojunction Bipolar Transistor IEEE Electron Device Letters,
Voulme 12 No 2 pp 42-44 Feb 1991.
[10] J Raolt, Impact of Carbon concentration on 1/f noise and random telegraph noise in
SiGe:C heterojunction bipolar transistors,Journal of Applied Physics. 103, 114508 (2008).
[11] J.Song et al. Optimum Ge profile for base transit time minimization of SiGe HBT,
Solid State Electronics Vol-41, No 12, pp 1957-1959. 1997.
69

[12] D.L.Harame et al. 30Ghz polysilicon emitter and single crystal emitter graded SiGe
base PNP Transistor, IEDM Tech.Dig., pp 33-36, 1990.
[13] T.K.Johansen et al. Improved external base resistance extraction for submicrometer
InP/InGaAs DHBT Models,IEEE Transactions on Electron Devices, Vol. 58, No.9, pp-30043011, September 2011.
[14] C.J.Wei et al. Direct extraction of equivalent circuit parameters for heterojunction
bipolar transistors IEEE Trans. Microw. Theory Tech.,Vol. 43, no. 9, pp-2035-2040, Sept
1995.
[15] E. Enlow, Response of advanced bipolar process to ionizing radiation, IEEE
Transactions on Nuclear Science, Volume. 38 No. 6 pp 1342-1351, Dec 1991.
[16] W.M.C.Sansen et al. Low-Noise Wide-Band Amplifiers in Bipolar and CMOS
Technologies Kluwer Academic Publishers, 1991.
[17] G.F.Niu et al. Noise parameter optimization of UHV/CVD SiGE HBTs for RF and
microwave applications IEEE Trans. Electron Devices, vol 46, pp 1347-1354, Aug 1999.
[18] G.Niu Low Frequency Noise, Silicon Heterostructure Handbook. Nov 2005, 4.4-427
-4.4-438.
[19] M.Haartman, Random Telegraph Signal Noise in SiGe heterojunction bipolar
transistors, Journal of Applied Physics, Vol 92, No 8, pp 4414-4421.Oct 2002.
[20] D. Knoll, BiCMOS integration of SiGe:C Heterojunction bipolar transistors, IEEE
BCTM 9.2 , pp 162-166. 2002.

70