MINISTY OF HIGHER EDUCATION

AINSHAMS UNIVERSITY
FACULTY OF ENGINEERING

Assignment 1
Flash Memory Wear
Supervised By: Prof. Dr. Ayman Wahba
By:Ahmed Abd-Elshakour Allam

1 Contents
2

Introduction .......................................................................................................................................... 2

Overview of the flash technology ......................................................................................................... 3

Wearing Mechanism ............................................................................................................................. 5

Wear Mitigation .................................................................................................................................... 6

5.1

Wear leveling ................................................................................................................................ 6

5.2

Anealing ........................................................................................................................................ 6

Conclusion ............................................................................................................................................. 7

References ............................................................................................................................................ 7

List of Figures:
Figure 1: Schematic cross section of a Flash cell. The floating-gate structure is common to all the
nonvolatile memory cells based on the floating-gate MOS transistor. .......................................... 4
Figure 2: Schematic energy band diagram (lower part) as referred to a floating gate MOSFET
structure (upper part). The left side of the figure is related to a neutral cell, while the right side
to a negatively charged cell. ........................................................................................................... 4
Figure 3: Writing mechanism in floating-gate devices. .................................................................. 5
Figure 4: Threshold voltage window closure as a function of program/erase cycles on a single
cell. .................................................................................................................................................. 5
Figure 5: Program and erase time as a function of the cycles number. ......................................... 6

2 Introduction
Complementary metal-oxide-semiconductor (CMOS) memories can be divided into two main
categories: random access memories (RAMs), which are volatile, i.e., they lose the stored
information once the power supply is switched off and read-only memories (ROMs), which are
nonvolatile, i.e, they keep stored information also when the power supply is switched off. Flash
memories (in which a single cell can be electrically programmable and a large number of cells
called a block sector are electrically erasable at the same time) have dominated the (ROM)
market due to their enhanced flexibility against (EPROMs) which are programmable electrically
but can only be erased using ultraviolet radiations. This flexibility, in addition to the advances in
the semiconductor industry, have made flash arrays to be suitable for acting as standard
storage media in computer systems.

As with all ROM memory technologies, the number of times that a flash memory can be
programmed is limited as the flash cell is subject to wear. Despite this fact, this limitation is
usually ignored by embedded systems designers because the number of allowable programing
cycles for current flash technologies is very high (in order of 10,000cycles). However in extreme
cases were the embedded system is subjected to frequent programming/Erase cycles, this
limitation has to be considered. On the other hand for SSD derives and USB flash derives, this
number can have a large effect on life span of these devices especially if subjected to frequent
data operations. In this report, the basic construction of a flash cell is introduced in Section3 ,
the wearing mechanism and the sources of wear are discussed in4 , methods to extend the life
span of flash device and decrease wearing are discussed in5 . Finally a brief conclusion is given
in Section 6.

3 Overview of the flash technology

Flash technology Flash memories store data as charge trapped on a floating gate between the
control gate and the channel of a CMOS transistor. Each gate can store one or more bits of
information depending on whether it is a single-level cell (SLC) or a multi-level cell (MLC).
Commercially available devices store between 1 and 4 bits per cell.
A Flash cell is basically a floating-gate MOS transistor (see Figure 1), i.e., a transistor with a gate
completely surrounded by dielectrics, the floating gate (FG), and electrically governed by a
capacitively coupled control gate (CG). Being electrically isolated, the FG acts as the storing
electrode for the cell device; charge injected in the FG is maintained there, allowing modulation
of the apparent threshold voltage (i.e., seen from the CG) of the cell transistor[1].
Obviously the quality of the dielectrics guarantees the non-volatility, while the thickness allows
the possibility to program or erase the cell by electrical pulses.

Figure 1: Schematic cross section of a Flash cell. The floating-gate structure is common to all the nonvolatile memory cells
based on the floating-gate MOS transistor.

The data stored in a Flash cell can be determined measuring the threshold voltage of the FG
MOS transistor. The best and fastest way to do that is by reading the current driven by the cell
at a fixed gate bias.
Considering Figure 2, the problem of writing an FG cell corresponds to the physical problem of
forcing an electron above or across an energy barrier. The problem can be solved exploiting
different physical effects. In Figure 3, the three main physical mechanisms used to write an FG
memory cell are sketched.

Figure 2: Schematic energy band diagram (lower part) as referred to a floating gate MOSFET structure (upper part). The left
side of the figure is related to a neutral cell, while the right side to a negatively charged cell.

Figure 3: Writing mechanism in floating-gate devices.

4 Wearing Mechanism
The expected lifetime of one block in a flash device is 10,000 program/erase cycles for MLC and
100,000 for SLC Flash products[2]. Cycling is known to cause a fairly uniform wear-out of the
cell performance, mainly due to tunnel oxide degradation, which eventually limits the
endurance characteristics[2] . A typical result of an endurance test on a single cell is shown in
Figure 4. As the experiment was performed applying constant pulses, the variations of program
and erase threshold voltage levels are described as program/erase threshold voltage window
closure and give a measure of the tunnel oxide aging. In real Flash devices, where intelligent
algorithms are used to prevent window closing, this effect corresponds to a program and erase
times increase (see Figure 5). In particular, the reduction of the programmed threshold with
cycling is due to trap generation in the oxide and to interface state generation at the drain side
of the channel, which are mechanisms specific to hot-electron degradation[1].

Figure 4: Threshold voltage window closure as a function of program/erase cycles on a single cell.

Figure 5: Program and erase time as a function of the cycles number.

5 Wear Mitigation
5.1 Wear leveling
The lifetime of flash memory storage can be prolonged if each block in flash memory is updated
uniformly. In real systems, however, there is locality in storage access patterns, revealing
frequently updated hot data and rarely updated cold data. Uneven distribution of erase cycles
caused by hot data shortens the lifetime of flash-based storage system. To make matters
worse, the new generation of NAND flash memory architecture, MLC (Multi-Level Cell) NAND,
has higher density, but the endurance cycle is degraded by an order of magnitude compared to
the SLC NAND architecture.
Many researchers have proposed various wear-leveling algorithms to address this problem[3]
[5]. The goal of the wear-leveling algorithm is to expand the lifetime of flash memory by
distributing erase operations evenly across the whole flash memory media.

5.2 Anealing
To overcome the deterioration of the oxide layer, this damage could be treated by annealing,
but the problem that it could be done only by heating the whole chip for hours at around 250
C. A redesigned flash memory chip is suggested to address the problem by including tiny
onboard heaters that could anneal small groups of memory cells. This type of self-healing NAND
flash memory is reported to survive more than 100 million cycles[6].

6 Conclusion
This report gave a very brief overview of the flash memory technology and the factors that
limits the number of Program/erase cycles. This was attributed to mainly a deterioration of the
oxide layer in the separates the floating gate from the device. The mitigation methods for such
deterioration was suggested and they mainly include annealing of the NAND cells and using
computer algorithms to distribute the level on all the cells increasing the life span of the flash
array.

7 References
[1] R. Bez, E. Camerlenghi, A. Modelli, and A. Visconti, Introduction to flash memory, Proc.
IEEE, vol. 91, no. 4, pp. 489502, Apr. 2003.
[2] L. M. Grupp, A. M. Caulfield, J. Coburn, S. Swanson, E. Yaakobi, P. H. Siegel, and J. K. Wolf,
Characterizing flash memory: anomalies, observations, and applications, in
Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on,
2009, pp. 2433.
[3] Y.-H. Chang, J.-W. Hsieh, and T.-W. Kuo, Improving Flash Wear-Leveling by Proactively
Moving Static Data, IEEE Trans. Comput., vol. 59, no. 1, pp. 5365, Jan. 2010.
[4] D. Jung, Y.-H. Chae, H. Jo, J.-S. Kim, and J. Lee, A group-based wear-leveling algorithm for
large-capacity flash memory storage systems, in Proceedings of the 2007 international
conference on Compilers, architecture, and synthesis for embedded systems, 2007, pp. 160
164.
[5] K. M. J. Lofgren, R. D. Norman, G. B. Thelin, and A. Gupta, Wear leveling techniques for
flash EEPROM systems, US6230233 B1, 08-May-2001.
[6] J. Kim, A. J. Hong, S. Min Kim, E. B. Song, J. H. Park, J. Han, S. Choi, D. Jang, J.-T. Moon, and
K. L. Wang, Novel Vertical-Stacked-Array-Transistor (VSAT) for ultra-high-density and costeffective NAND Flash memory devices and SSD (Solid State Drive), in 2009 Symposium on
VLSI Technology, 2009, pp. 186187.