Esd Lab Record - 14122014

INDEX
Exp.
No
Date
Title
01
SYSTEM DESIGN USING PIC 16F877A
02
SYSTEM DESIGN USING MSP430
03
SYSTEM DESIGN USING AT89C51

MICROCONTROLLER
04
SYSTEM DESIGN USING ATMEGA32

MICROCONTROLLER
05
SIMULATION OF QMF USING

SIMULATION PACKAGE
06
DESIGN OF SERIAL IN PARALLEL

OUT SHIFT REGISTER
07
DESIGN OF MOD-4 DOWN COUNTER
08
IMPLEMENTATION OF ADAPTIVE
FILTERS IN DSP PROCESSOR
09
IMPLEMENTATION OF
MULTISTAGE MULTIRATE SYSTEM
IN DSP PROCESSOR
10
DESIGN OF DATA ACQUISITION

AND SIGNAL PROCESSING SYSTEM
11
IMPLEMENTATION OF LED
INTERFACING IN DSP PROCESSOR
12
BUILT-IN SELF TEST AND FAULT

DIAGNOSIS
13
DESIGN & SIMULATON OF

TEMPERATURE SENSOR USING PIC
16F877A
Page
No.
Mark
Signature
Ex.No: 01
SYSTEM DESIGN USING PIC 16F877A
Date:
AIM:
To design & implement the PIC 16F877A Microcontroller to interfacing of LED using
Embedded C program in MPLAB IDE.
APPARATUS REQUIRED:
Hardware:
1. VPUT-01 Universal PIC Embedded Trainer
2. VPUT-02 16F877A controller Piggy Back
3. Serial Cable
4. Personal Computer
Software:
1. MPLAB IDE workbench for windows platform
2. CCS C Compiler tool chain
3. PIC Boot plus Downloader
4. Operating System Windows Xp,W7
PROCEDURE:
I.
Developing Procedure
1. Open MPLAB IDE software
2. Creating Project
For Creating C Project; Click project Project Wizard Next
Device (16f877A) and click Next select Active tool suite CCS C
Compiler and Click Next Next Finish
3. Open new source file from, File New
4. Save the source file as .c for C
5. Type the relevant code, save it.
6. Add the file to the project and build the project.
II.
Execution Procedure
1. Connect the power card to the development board.
2. Connect the serial cable between the PC and development board.
3. Switch on the power supply.
4. Open PIC Boot plus GUI for hex file downloading.
5. Make the following settings on the downloader software.
a. Select hex File
: .hex
b. Baud rate
: 38400
c. Com Port
: User Defined
6. Click Write button on GUI and Reset the Controller
THEORY:
The PIC16F Development board is specifically designed to help students to master the
required skills in the area of embedded systems. The kit is designed in such way that all the
possible features of the microcontroller will be easily used by the students. The kit supports
in system programming (ISP) which is done through USB port.
Microchips PIC (PIC16F877A), PIC16F/18F Development Kit is proposed to smooth
the progress of developing and debugging of various designs encompassing of High speed 8bit Microcontrollers.
LED interfacing is the stepping stone for microcontroller development. This is a simple
embedded program for PIC 16F877A to interface LEDs, suitable for beginners who wish to
study basics of embedded microcontroller programming. The program is developed through
Micro C compiler, one of the best solutions for embedded programming in PIC family. It is
compatible for Windows XP and Windows 7 platforms and comes with internal burning tools.
PROGRAM:
//This Program For LED interface
//Data Lines - PORTD
//Latch Line - PB4
#include<16f877A.h>
#use delay(clock=20000000)
#use rs232(baud=19200, xmit=PIN_C6, rcv=PIN_C7)
unsigned int led[]={0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80},i;
void main()
{
output_b(0xff);
while(1)
{
for(i=0;i<5;i++){
output_d(0xff);
output_low(PIN_B4);
output_high(PIN_B4);
delay_ms(500);
output_d(0x0);
output_low(PIN_B4);
delay_ms(500);
}
for(i=0;i<8;i++)
{
output_d(led[i]);
output_low(PIN_B4);
delay_ms(500);
}
}
}
OUTPUT:
For C Code Alternative LEDs are continuously flashed.
RESULT:
Thus the PIC 16F877A Microcontroller to interfacing of LED using Embedded C
program in MPLAB IDE is designed and implemented.
Ex.No: 02
SYSTEM DESIGN USING MSP430
Date:
AIM:
To design & implement the MSP430 Microcontroller to interfacing of LED using
Embedded C program
APPARATUS REQUIRED:
Hardware:
2. VPUT-01 MSP430 controller Piggy Back
3. Serial Cable
Software:
1. IAR MSP430
2. MSP FET
PROCEDURE:
I.
i.
For C Project
1. Open IAR MSP430 Software.
2. For creating project Project Create New Project C Main
then browse the location, gave the name of project and save it.
3. Choose LED-Debug: Options --> General Options:32 Bit
4.
Linker Output Others
5. Debugger Driver FET Debugger

6. Project Rebuild All Led.c
II.
Execution Procedure

4. Open MSP FET.exe GUI for hex file downloading.
5. Go to Tools Setup select BSL
6. File Open Auto Reset
THEORY:
The Texas Instruments MSP430 family of ultralow power microcontrollers consist of
several devices featuring different sets of peripherals targeted for various applications. The
architecture, combined with five low power modes is optimized to achieve extended battery
life in portable measurement applications. The device features a powerful 16-bit RISC CPU,
16-bit registers, and constant generators that contribute to maximum code efficiency. The
digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode
in less than 6 s. The MSP430F15x/16x/161x series are microcontroller configurations with
two built-in 16-bit timers, a fast 12-bit A/D converter, dual 12-bit D/A converter, one or two
universal serial synchronous/asynchronous communication interfaces (USART), I 2C, DMA,
and 48 I/O pins. In addition, the MSP430F161x series offers extended RAM addressing for
memory-intensive applications and large C-stack requirements. Typical applications include
sensor systems, industrial control applications, hand-held meters, etc.
PROGRAM:
#include "msp430x16x.h"
void delay()
{
for(int i=0;i<8;i++)
for( int j=0;j<600;j++);
}
void main()
{
// P2SEL = 0x00;
P2DIR = 0xff;
while(1)
{
P2OUT = 0x55;
delay();
P2OUT = 0xAA;
delay();
}
}
OUTPUT:
For C Code Alternative LEDs are continuously flashed.
RESULT:
Thus the MSP430 Microcontroller to interfacing of LED using Embedded C program
is designed and implemented.
Ex.No: 03
SYSTEM DESIGN USING AT89C51
Date:
MICROCONTROLLER
AIM:
To design & implement the AT89C51 Microcontroller to interfacing of LED using
Embedded C program.
APPARATUS REQUIRED:
Hardware:
2. VPUT-05 AT89C51 controller Piggy Back
3. Serial Cable
Software:
1. RIDE
2. Flash Magic
PROCEDURE:
I.
i.
For C Project
1. Open the RIDE Software.
2. Project New Save the File.
3. File New C Files Write Program Save.
4. Project Add Node/Source/Applications
5. Project Build All.
II.
Execution Procedure
4. Step 1: COM Port: User Defined
Baud Rate: 9600

Device
: 89C51RD2Hxx
Interface : None (ISP)

Osci. Freq: 16 MHz
5. Step 2: Uncheck Erase all Flash + Security
Check Erase Blocks used by Hex File
6. Step 3: Load .Hex File.
7. Step 4: Uncheck All.
8. Step 5: Start Yes.
THEORY:
The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4K
bytes of Flash programmable and erasable read only memory (PEROM). The device is
manufactured using Atmels high-density nonvolatile memory technology and is compatible
with the industry-standard MCS-51 instruction set and pinout. The on-chip Flash allows the
program memory to be reprogrammed in-system or by a conventional nonvolatile memory
programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel
AT89C51 is a powerful microcomputer which provides a highly-flexible and cost-effective
solution to many embedded control applications.
The AT89C51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture,
a full duplex serial port, on-chip oscillator and clock circuitry. In addition, the AT89C51 is
designed with static logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port and interrupt system to continue functioning. The Power-down Mode
saves the RAM contents but freezes the oscillator disabling all other chip functions until the
next hardware reset.
PROGRAM:
#include<reg51.h>
#include<stdio.h>
sbit LATCH =P2^4;
void delay();
int i;
void main()
{
while(1)
{
P0
= 0X55;
LATCH = 0;
LATCH = 1;
delay();
P0
= 0Xaa;
LATCH = 0;
LATCH = 1;
delay();
}
}
void delay()
{
long int i,j;
for(i=0;i<2500;i++)
for(j=0;j<0xff;j++);
}
OUTPUT:
For C Code alternative LEDs are continuously flashed.
RESULT:
Thus the AT89C51 Microcontroller to interfacing of LED using Embedded C program
is designed and implemented.
SYSTEM DESIGN USING ATMEGA32

MICROCONTROLLER
Ex.No: 04
Date:
AIM:
To design & implement the ATMEGA32 Microcontroller to interfacing of LED using
Embedded C program.
APPARATUS REQUIRED:
Hardware:
2. VPUT-07 ATMEGA32 controller Piggy Back
3. Serial Cable
Software:
1. Code Vision AVR C Compiler for Windows Platform
2. AVR Studio 4 for windows platform
3. Chip45boot2 GUI V1.12
PROCEDURE:
I.
i.
For C Project
1. Open CodeVision AVR C Compiler.
2. For creating project File New Project OK No, then browse
the location, gave the name of project and save it.
3. To create source file, click File New Source OK.
4. To Configure and select device, go to Project Configure Files
Input Files click Add and choose the C file to add with project.
5. Then in the same Configure window select C Compiler tab choose the chip
ATMEGA32 and select clock as 16 MHz, then click ok.
II.
Execution Procedure
4. Open 45boot2 GUI V1.12 GUI for hex file downloading.
5. Make the following settings on the downloader software.
a. Select hex File
: .hex
b. Baud rate
: 19200
c. Com Port
: User Defined
6. Click Connect to Bootloader, and then wait for status to glow as green.
7. Click Program Flash, wait for some moment.
8. After finishing download click Start application.
THEORY:
The Atmel AVR core combines a rich instruction set with 32 general purpose
working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit
(ALU), allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving throughputs
up to ten times faster than conventional CISC microcontrollers. The ATmega32 provides the
following features: 32Kbytes of In-System Programmable Flash Program memory with ReadWhile-Write capabilities, 1024bytes EEPROM, 2Kbyte SRAM, 32 general purpose I/O lines,
32 general purpose working registers, a JTAG interface for Boundary- scan, On-chip
Debugging support and programming, three flexible Timer/Counters with com- pare modes,
Internal and External Interrupts, a serial programmable USART, a byte oriented Two-wire
Serial Interface, an 8-channel, 10-bit ADC with optional differential input stage with
programmable gain (TQFP package only), a programmable Watchdog Timer with Internal
Oscillator, an SPI serial port, and six software selectable power saving modes. The Idle mode
stops the CPU while allowing the USART, Two-wire interface, A/D Converter, SRAM,
Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode
saves the register contents but freezes the Oscillator, disabling all other chip functions until the
next External Interrupt or Hardware Reset. In Power-save mode, the Asynchronous Timer
continues to run, allowing the user to maintain a timer base while the rest of the device is
sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except
Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator Oscillator is running while the rest of the device is
sleeping. This allows very fast start-up combined with low-power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. The
device is manufactured using Atmels high density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI
serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot
program running on the AVR core.
PROGRAM:
#include<mega32.h>
#include<delay.h>
#define LED
PORTA
#define LED_LATCH
#define CLR
#define SET
PORTB.4
void main()
{
DDRA = 0xFF;
DDRB.4 = 1;
while(1)
{
LED ^= 0XFF;
LED_LATCH = CLR;
LED_LATCH = SET;
delay_ms(2000);
}
}
OUTPUT:
For C Code all the LEDs are continuously toggled.
RESULT:
Thus the ATMEGA32 Microcontroller to interfacing of LED using Embedded C
program is designed and implemented.
FREQUENCY RESPONSE OF QMF FILTER
Ex.No: 05
SIMULATION OF QMF USING SIMULATION
Date:
PACKAGE
AIM:
To simulate QMF design using MATLAB
APPARATUS REQUIRED:
Personal computer.
MATLAB 7.0
PROCEDURE:
Open the MATLAB.
FILE ->New->M-file. Editor window is opened.
Write the program in Editor window.
Save the program with MATLAB extension .m
Debug ->save and run.
Then ,the output is simulated and verified.
THEORY:
In digital signal processing, a quadrature mirror filter is a filter whose magnitude
response is mirror image about
of that of another filter. Together these filters are known
as the Quadrature Mirror Filter pair.

A filter
will be quadrature mirror filter of
The filter responses are symmetric about
if
IMPULSE RESPONSE
In audio/voice codecs, a quadrature mirror filter pair is often used to implement a filter bank
that splits an input signal into two bands. The resulting high-pass and low-pass signals are
often reduced by a factor of 2, giving a critically sampled two-channel representation of the
original signal. The analysis filters are often related by the following formulae in addition to
quadrate mirror property:
where is the frequency, and the sampling rate is
normalized to
This is known as power complementary property. In other words, the power sum of the highpass and low-pass filters is equal to 1.
CODING:
QUADRATURE MIRROR FILTER (QMF) DESIGN
clc; clear;
% clear command & workspace
N = 32;
% number of co-efficients
f = [0 0.5 0.552 1];
% define filter cut-off frequency
m = [1 1 0 0];
% define filter structure
h0 = fir2(N,f,m,hanning(N+1));
h1 = (-1).^(0:N).* h0;
% FIR filter design using hanning window, H(z)

% H(-z)
% impulse response plot for analysis filter

figure;
subplot(2,2,1);
stem(h0);
xlabel('n'); ylabel('constant');
title('Impulse Response, H_0(Z)');
subplot(2,2,2);
stem(h1);
title('Impulse Response, H_1(Z)');
% For Standard QMF Bank
g0 = 2*h0;
% QMF synthesis filter, 2H(z)
g1 = -2*h1;
% -2H(-z)
FILTER ERROR
% impulse response plot for synthesis filter

hold on;
subplot(2,2,3);
stem(g0);
title('Impulse Response, G_0(Z)');
subplot(2,2,4);
stem(g1);
title('Impulse Response, G_1(Z)');
% QMF filter's frequency response plot
figure;
[H,W] = freqz(g0/2,1,512);
% Determine Frequency Response
plot(W/pi,20*log10(abs(H)));grid;
% Plotting radian Vs gain
hold on;
[H1,W] = freqz(g1/2,1,512);
% Determine Frequency Response
plot(W/pi,20*log10(abs(H1)));
% Plotting radian Vs gain
xlabel('\omega/\pi (rad)'); ylabel('Gain (dB)');

title('QMF Filter - Frequency Response');
text(0.115, -10, '|{\itH}_0(\omega)|^2','fontsize',12,'fontweight','demi');
text(0.815, -10, '|{\itH}_1(\omega)|^2','fontsize',12,'fontweight','demi');
% Determine Filter Error
sum = (abs(H)).^2 + (abs(H1)).^2;
% find-out filter error
error = 10*log10(sum);
% error in 'dB'
figure;
plot(W/pi,error); axis([0 1 -0.15 0.13]); grid
xlabel('\omega/\pi (rad)'); ylabel('Error (dB)');
title('Filter Error');
RESULT:
Thus the QMF is simulated using MATLAB and output is verified successfully.
OUT PUT
Ex.No: 06
Date:
DESIGN OF SERIAL IN PARALLEL OUT

SHIFT REGISTER
AIM:
To design a sequential circuit serial in parallel out shift register using VHDL.
APPRATUS REQUIRED:
Personal Computer.
Xilinx software.
PROCEDURE:
Fileopen new projectgive project namenew source
Enter the program
Filesave with .vhd extension
Processsynthesischeck syntax
If the program verified successfully then click on simulation
Processbehavioral checkingsimulate wave form
Verify the operation of designed system with obtained test bench wave form
THEORY:
A serial-in/parallel-out shift register is similar to the serial-in/ serial-out shift register in that it
shifts data into internal storage elements and shifts data out at the serial-out, data-out, pin. It
is different in that it makes all the internal stages available as outputs. Therefore, a serialin/parallel-out shift register converts data from serial format to parallel format. If four data
bits are shifted in by four clock pulses via a single wire at data-in, below, the data becomes
available simultaneously on the four Outputs QA to QD after the fourth clock pulse.
The practical application of the serial-in/parallel-out shift register is to convert data from
serial format on a single wire to parallel format on multiple wires. Perhaps, we will illuminate
four LEDs (Light Emitting Diodes) with the four outputs (QA QB QC QD).
Design of Serial In - Parallel Out Shift Register using Behavior Modeling Style:
Output Waveform : Serial In - Parallel Out Shift Register
PROGRAM:
VERILOG CODE:
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;
wire [3:0] dout ;
input din ;
wire din ;
input clk ;
wire clk ;
input reset ;
wire reset ;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assign dout = s;
endmodule
RESULT
Thus the sequential circuit for serial in parallel out shift register is designed and
output verified successfully.
OUTPUT:
Ex.No: 07
DESIGN OF MOD-4 DOWN COUNTER
Date:
AIM:
To design a sequential circuit mod-4 down counter using VHDL.
APPRATUS REQUIRED:
Personal Computer.
Xilinx software.
PROCEDURE:
Fileopen new projectgive project namenew source
Enter the program
Filesave with .vhd extension
Processsynthesischeck syntax
If the program verified successfully then click on simulation
Processbehavioral checkingsimulate wave form
Verify the operation of designed system with obtained test bench wave form
THEORY:
Counter has a clock input (CLK) and a RESET input. Counter has two output lines, which
take on values of 00, 01, 10, and 11 on subsequent clock cycles.
Thus mod-n counter capable of counting states 0,1,2,.,n-1. For example mod-4 counter
capable of counting states 0,1,2,3(n-1). Hence the states 00,01,10,11,00,01,. Are counted when
the rising edge of clock is detected
PROGRAM:
library IEEE;
use IEEE.std_logic_1164.all; -- supports the data type std_logic
use IEEE.std_logic_unsigned.all; -- supports addition/subtraction of vectors
entity MOD4CTR is
port (U_D,PON,CLK : in BIT;
QOUT: out BIT_VECTOR(1 downto 0);
CU, CD: out BIT); -- carry bits
end MOD4CTR ;
architecture COUNTER of MOD4CTR is
signal QINT: STD_LOGIC_VECTOR(1 downto 0);
begin
SYN_COUNT:process (CLK, PON) -- clock and asynchronous inputs
begin
if pon = '1' then QINT <= "00" after 20 ns;
elsif CLK='1' and CLK'event then
if U_D = '1' then QINT <= QINT + "01" after 20 ns; --addition of bits
else QINT <= QINT - 1 after 20 ns; -- subtraction of integer
end if;
end if;
end process SYN_COUNT;
QOUT <= TO_BITVECTOR(QINT); -- type conversion: casting
CU <= '1' after 20 ns when (U_D = '1' and QINT = 3) else '0' after 20 ns;
CD <= '1' after 20 ns when (U_D = '0' and QINT = 0) else '0' after 20 ns;
end COUNTER;
RESULT
Thus the sequential circuit for mod-3 down counter is designed and output verified
successfully.
Ex.No: 08
IMPLEMENTATION OF ADAPTIVE FILTERS IN DSP
Date:
PROCESSOR
AIM:
To implement the adaptive filters in DSP processor TMS320C6713.
APPARATUS REQUIRED:
TI - TMS320C6713 kit
Code Composer Studio software
CRO -1
FG -2
PROCEDURE:
STEP-1: Setup configuration of DSP processor in Code composer Studio
STEP-2: Select C67XX and Platfom< simulator> and C6713 device cycle
ADD Save quit.
STEP-3: open Code composer Studio
STEP-4: GO to new type Project name adaptive select location finish.
STEP-5: Go to new select Source file Type program save as

adaptive.c.
STEP-6:Go to project add files < CSK6713.cmd> to project
STEP-7: Go to Build option < linker> , Auto initialization model < No auto
initialization>, heap and stack Size<400>
STEP-8: include library rts 6700.lib ok.
STEP-9: Go to project rebuild all
STEP-10: select out file
STEP-11: convert out file to asc file.
THEORY:
An adaptive filter is a filter that self-adjusts its transfer function according to an
optimization algorithm driven by an error signal. Because of the complexity of the
optimization algorithms, most adaptive filters are filters. The adaptive filter uses feedback in
the form of an error signal to refine its transfer function to match the changing parameters.
As the power of digital signal processors has increased, adaptive filters have become
much more common and are now routinely used in devices such as mobile phones and other
communication devices, camcorders and digital cameras, and medical monitoring equipment.
A digital signal processor (DSP) is a specialized microprocessor with an architecture
optimized for the operational needs of digital signal processing.
PROGRAM:
Adaptive Filter Signal:
typedef unsigned int Uint32;
typedefint Int32;
typedef short Int16;
typedef unsigned short Uint16;
int main(void)
{
Int16 outCh1;
Int16 outCh2;
Int16 *origSig;
Int16 *noiseSig;
Int16 alteredSig;
Int16 noiseEst;
double *kern;
Int16 errorSig;
Int32 outValue;
Int32 filtCount;
Uint32 *socValue;
Uint32 socRead;
Uint32 *adcValue;
Uint32 *dacCh1;
Uint16 *dacCh2;
Uint16 adcOut;
socValue = (Uint32 *)0x9004000c;

adcValue = (Uint32 *)0x90040008;
dacCh1 = (Uint32 *)0x90040008;
dacCh2 = (Uint16 *)0x9004000a;
origSig = (Int16 *)0x00013000;

noiseSig = (Int16 *)0x00014000;
kern = (double *)0x00016000;
for(filtCount = 0; filtCount< 32; filtCount++)

{
*(noiseSig + filtCount) = 0x00000000;
*(kern + filtCount) = 0x00000000;
}
while(1)
{
socRead = *socValue;
adcOut = *adcValue;
adcOut&= 0x0fff;
//adcOut ^= 0x0800;
*origSig = adcOut;
adcOut = *adcValue;
adcOut&= 0x0fff;
adcOut ^= 0x0800;
*noiseSig = adcOut;
alteredSig = *origSig + *noiseSig;

outValue = 0;
outValue += *(noiseSig + filtCount) * *(kern + filtCount);
noiseEst =outValue>> 12;
errorSig = alteredSig - noiseEst;
for(filtCount = 31; filtCount>= 0; filtCount--)
{
*(kern + filtCount) = *(kern + filtCount) + (2 * 0.0000001 * errorSig) * *(noiseSig +
filtCount);
*(noiseSig + filtCount + 1) = *(noiseSig + filtCount);
}
outCh1 = alteredSig;
//*dacCh1 = adcOut;
*dacCh1 = outCh1;
outCh2 = errorSig;
//*dacCh2 = adcOut;
*dacCh2 = outCh2;
}
return 0;
}
RESULT
Thus the adaptive filter is implemented in DSP processor and output is verified on
CRO.
Ex.No: 09
IMPLEMENTATION OF MULTISTAGE MULTIRATE
Date:
SYSTEM IN DSP PROCESSOR
AIM:
To implement the multistage multi rate system in DSP processor TMS320C6713.
APPARATUS REQUIRED:
Code composer Studio software
CRO -1
FG -2
PROCEDURE:
STEP-1: setup configuration of DSP processor in Code composer Studio
STEP-2: select C67XX and Platform< simulator> and C6713 device cycle
ADD Save quit.
STEP-4: GO to new type Project name multirate select location finish.
STEP-5: Go to new select Source file Type program save as

multirate.c.
THEORY:
Multirate systems have gained popularity since the early 1980s and they are commonly
used for audio and video processing, communications systems, and transform analysis to name
but a few. In most applications multirate systems are used to improve the performance, or for
increased computational efficiency. The two basic operations in a multirate system are
decreasing (decimation) and increasing (interpolation) the sampling-rate of a signal. Multirate
systems are sometimes used for sampling-rate conversion, which involves both decimation and
interpolation.
A common use of multirate signal processing is for sampling-rate conversion. Suppose
a digital signal x[n] is sampled at an interval T1, and we wish to obtain a signal y[n] sampled
at an interval T2. Then the techniques of decimation and interpolation enable this operation,
providing the ratio T1/T2 is a rational number i.e. L/M. Sampling-rate conversion can be
accomplished by L-fold expansion, followed by low-pass filtering and then M-fold decimation.
A digital signal processor (DSP) is a specialized microprocessor with an architecture
optimized for the operational needs of digital signal processing.
PROGRAM:
Multistage Multirate Processing Signal
#include "deci3.h"
#include "deci4.h"
#include <stdio.h>
/* Specifications for the filters used: fs = 8 KHz, fp1 = fp2 = 700 Hz, fs1 = 3000 Hz, fs2 =
1000 Hz, dp1 = dp2 = 0.005, ds1 = ds2 = 0.001, N1 = 8, N2 = 37, M1 = M2 = L2 = L1 = 2.
For every 4 samples read from the adc the following approximate times apply without using
any additional delays:
samples 1 and 3: 16 us, sample 2: 28 us, sample 4: 0.1 ms
sample 1 = indexSamp 1
This means that without using additional delays the samples are not read at the 8 Khz rate.
Therefore appropriate delays are added for samples 1, 2, 3 and 4 so that each sample would
be read at a rate close to 8 KHz (0.125 ms).
*/
typedef unsigned int Uint32;
typedefint Int32;
typedef short Int16;
typedef unsigned short Uint16;
typedef unsigned char Uchar;
Uint32 *inDeciM1;
Uint32 *inDeciM2;
Uint32 *inInterpL2;
Uint32 *inInterpL1;
Uint32 *storeL1;
Uint32 *outL1;
Int16 *fInterpL2;
Int16 *fInterpL1;
Uint16 adcOut;
Uint32 valueL1;
Int32 outValue;
Int32 filtCount;
Uchar indexL2;
Uchar indexL1;
UcharindexInit;
UcharindexSamp;
int deciM1(void);
int deciM2(void);
int interpL2(void);
int interpL1(void);
int main(void)
{
Uint32 *socValue;
Uint32 *adcValue;
Uint32 *dacValue;
Uint32 socRead;
Uchar *led;
Int32 tCount;
Uint32 countM1;
Uint32 countM2;
Uint32 countL1;
Uint32 countL2;
Uint32 *inTest;
socValue = (Uint32 *)0x9004000c;
adcValue = (Uint32 *)0x90040008;
dacValue = (Uint32 *)0x90040008;
fInterpL2 = (Int16 *)0x0000a000;

fInterpL1 = (Int16 *)0x0000b000;
inDeciM1 = (Uint32 *)0x00011000;

inDeciM2 = (Uint32 *)0x00012000;
inInterpL2 = (Uint32 *)0x00013000;
inInterpL1 = (Uint32 *)0x00014000;
storeL1= (Uint32 *)0x00016000;

outL1 = (Uint32 *)0x00017000;
led = (Uchar *)0x90040016;

inTest = (Uint32 *)0x00015000;
*(inTest + filtCount) = filtCount + 0x300;

*(fInterpL2 + filtCount) = *(fDeciM2 + filtCount) * 2;
*(fInterpL1 + filtCount) = *(fDeciM1 + filtCount) * 2;
{
*(inDeciM1 + filtCount) = 0;
*(inDeciM2 + filtCount) = 0;
*(inInterpL2 + filtCount) = 0;
*(inInterpL1 + filtCount) = 0;
}
indexL2 = 1;
indexL1 = 1;
countM1 = 1;
countM2 = 0;
countL2 = 0;
countL1 = 0;
indexSamp = 1;
while(1)
{
if(indexSamp == 0)
for(tCount = 0; tCount< 200; tCount++);
else if ((indexSamp == 1) || (indexSamp == 3))
else if (indexSamp == 2)
socRead = *socValue;
adcOut = *adcValue;
adcOut&= 0x0fff;
adcOut ^= 0x0800;
*inDeciM1 = adcOut;
if(countM1 == 2)
{
deciM1();
countM1 = 0;
countM2++;
}
if(countM2 == 2)
{
deciM2();
countM2 = 0;
}
if((countM1 == 0) && (countM2 == 0))
{
while(countL2 < 2)
{
interpL2();

*(inInterpL2 + filtCount + 1) = *(inInterpL2 + filtCount);
indexInit = 1;
countL2++;
}
}
storeL1= (Uint32 *)0x00016000;
if((countM1 == 0) && (countM2 == 0) && (countL2 == 2))
{
while(countL1 < 4)
{
if(countL1 == 0)
{
valueL1 = *storeL1;
*inInterpL1 = valueL1;
}
else if(countL1 == 2)
{
valueL1 = *(storeL1 + 1);
*inInterpL1 = valueL1;
}
interpL1();

*(inInterpL1 + filtCount + 1) = *(inInterpL1 + filtCount);
countL1++;
}
}
outL1 = (Uint32 *)0x00017000;
if(indexInit == 0)
outValue = 0x800;
else
outValue = *(outL1 + indexSamp);
*dacValue = outValue;
indexSamp++;
countL1 = 0;
countL2 = 0;
*(inDeciM1 + filtCount + 1) = *(inDeciM1 + filtCount);
countM1++;
if(indexSamp == 4)
indexSamp = 0;
}
return 0;
int deciM1(void)
{

*(inDeciM2 + filtCount + 1) = *(inDeciM2 + filtCount);
outValue = 0;
outValue += *(inDeciM1 + filtCount) * *(fDeciM1 + filtCount);
outValue>>= 14;
*inDeciM2 = outValue;
return 0;
}
int deciM2(void)
{
outValue = 0;
outValue += *(inDeciM2 + filtCount) * *(fDeciM2 + filtCount);
outValue>>= 14;
*inInterpL2 = outValue;
return 0;
}
int interpL2(void)
{
indexL2 ^= 0x01;
if(indexL2 == 0)
filtCount = 0;
else
filtCount = 1;
outValue = 0;
while(filtCount< 37)
{
outValue += *(inInterpL2 + filtCount) * *(fInterpL2 + filtCount);
filtCount += 2;
}
outValue>>= 16;
*storeL1++ = outValue;
return 0;
}
int interpL1(void)
{
indexL1 ^= 0x01;
if(indexL1 == 0)
filtCount = 0;
else
filtCount = 1;
outValue = 0;
while(filtCount< 8)
{
outValue += *(inInterpL1 + filtCount) * *(fInterpL1 + filtCount);
filtCount += 2;
}
outValue>>= 16;
*outL1++ = outValue;
return 0;
}
RESULT:
Thus the multistage multirate system is implemented in DSP processor and output is
verified on CRO.
SIGNAL PROCESSING DESIGN:
Ex.No: 10
Date:
DESIGN OF DATA ACQUISITION AND SIGNAL

PROCESSING SYSTEM
AIM:
To design a model for data acquisition and signal processing using MATLAB
Simulink.
APPRATUS REQUIRED:
Personal Computer
MATLAB Tool
PROCEDURE:
Open MATLAB tool
Click Simulink icon in the MATLAB command window
create a new model by filenewmodel in the Simulink library browser
OUTPUT:
select the sources required and track it in to the new model created and join the blocks
click start simulation icon
double click the scope and output is obtained
THEORY:
Data acquisition is the process of sampling signals that measure real world physical
conditions and converting the resulting samples into digital numeric values that can be
manipulated by a computer. Data acquisition systems (abbreviated with the acronym DAS or
DAQ) typically convert analog waveforms into digital values for processing. The
components of data acquisition systems include:
Sensors that convert physical parameters to electrical signals.
Signal conditioning circuitry to convert sensor signals into a form that can be
converted to digital values.
Analog-to-digital converters, which convert conditioned sensor signals to digital

values.
Signal processing is an area of systems engineering, electrical engineering and applied

mathematics that deals with operations on or analysis of analog as well as digitized signals,
representing time-varying or spatially varying physical quantities. Signals of interest can
include sound, electromagnetic radiation, images, and sensor readings, for example biological
measurements such as electrocardiograms, control system signals, telecommunication
transmission signals, and many others.
RESULT:
Thus the model for data acquisition and signal processing using MATLAB Simulink is
designed and output was verified.
Ex.No: 11
IMPLEMENTATION OF LED INTERFACING IN DSP PROCESSOR
Date:
AIM:
To implement the LED interfacing in DSP processor TMS320C6713.
APPARATUS REQUIRED:
Code composer Studio software
PROCEDURE:
STEP-1: setup configuration of DSP processor in Code composer Studio
STEP-2: select C67XX and Platform< simulator> and C6713 device cycle ADD
Save quit.
STEP-4: GO to new type Project name led select location finish.
STEP-5: Go to new select Source file Type program save as led.c.
PROGRAM:
//LED OUT PROGRAM
//===============
ioport int port0A;
//Led address decleration
void main()
{
int data,i,j;
//Variable declaration
//int *port0A;
//port0A=(int *)0xa000;
while(1)
//infinite loop start heare
{
data=0x0f;
//data to be LED
port0A=data;
//Data send to LED
for(i=0;i<0x5ff;i++)
//Some delay
data=0xf0;
//data to be LED
port0A=data;
//Data send to LED
for(i=0;i<0x5ff;i++)
//Some delay
}
}
RESULT:
Thus the LED Interfacing using DSP Kit is designed and implemented.
Tool on Built-in Self -Test and Fault Diagnosis:
Step 1:
Ex.No: 12
BUILT-IN SELF TEST AND FAULT DIAGNOSIS
Date:
AIM:
To develop & test the built-in self-test and fault diagnosis.
APPARATUS REQUIRED:
1. BISTAD
2. Windows XP
PROCEDURE:
1. Open the Software BISTAD
2. Set the Register Length as 60.
3. Set the Feedbacks and Seed as Random.
4. Set the Clock cycles to run as 10000
5. To Generate & Load the TST and AGM files.
6. Verify the Output in Charts & Diagnozer.
THEORY:
BUILT-IN SELF TEST:
Linear Feedback Shift Registers (LFSR) and other Pseudo-Random Pattern
Generators (PRPG) have become one of the central elements used in test and self test of
contemporary complex electronic systems like processors, controllers, and high-performance
integrated circuits. We have developed a training and research tool BIST Analyzer (BISTA)
for learning basic and advanced issues related to PRPG-based test pattern generation. Unlike
other similar systems, this tool facilitates study of various test optimization problems, allows
fault coverage analysis for different circuits and with different LFSR parameters. The main
didactic aim of the tool is presenting complicated concepts in a comprehensive graphical and
analytical way. The multi-platform JAVA runtime environment allows for easy access and
usage of the tool both in a classroom and at home. The BISTA represents an integrated
simulation, training, and research environment that supports both analytic and synthetic way
of learning.
Step 2:
Step 3:
FAULT DIAGNOSIS
The tool set DIAGNOZER represents a multifunctional remote e-learning environment for
teaching research by learning and investigating the problems of fault diagnosis in electronic
systems. It is a collection of software tools which allow to simulate a system under diagnosis,
emulate a pool of different methods and algorithms of fault location and analyze the
efficiency of different embedded self-diagnosing architectures, and investigate the effect of
real physical defects in electronic circuits. Both, fault model based and fault model free
approaches to fault diagnosis as well as cause-effect and effect-cause techniques of fault
location are supported in the presented environment. Also different embedded BIST and self
diagnosis architectures are emulated to evaluate the efficiency of diagnosis.
Basics of Test and Diagnostics
INTRODUCTION
This applet supports action-based learning via Internet the basics of Digital Test. It offers a
set of tools for understanding the principles of test generation, fault simulation, fault
diagnosis and fault location in digital circuits. A big reservoir of simple combinational
circuits is given to train on the screen in interactive mode the main important techniques and
algorithms. The software provides easy action and reaction (click and watch), the possibility
of distance learning, and learning by doing.
The work window of this program consists of three parts - vector insertion panel, view panel
for design schematics, and view panel for test vectors, fault tables and waveforms. Vector
insertion panel has two sub-panels - one for manually inserting vectors and another one for
automated pseudo random test generation. The boxes at the lines on schematics are clickable
for inserting proper signals directly on the internal lines of the circuits to imitate deterministic
test generation procedures.
SHORT THEORETICAL BASICS
Test Generation
Test generation (TG) is a complex problem with many interacting aspects e.g. the cost of TG
(complexity of the method, test length) and the quality of generated tests (fault coverage).
There are different methods used in test generation: deterministic methods (fault-oriented
TG, fault independent TG), random TG, combined deterministic/random TG, and others.
The complexity of TG methods and algorithms depends on the structure of the gate-level
circuits. In general three fundamental steps are used in generating a test for a fault:
to activate the fault
To activate a fault stuck-at-1

(s-a-1) on the line 9 of the
circuit we have to assign to
the line 9 the value 0. In the
case of the fault s-a-1 the
value 0 on that line will
change to 1.
to propagate the resulting error to a primary output (PO)
To propagate the error signal of a fault stuck-at-1 (s-a-1) on the

line 9 through the OR-gate 11 we have to assign value 0 to the
line 10. In the case of the fault s-a-1 on the line 9 the value 0 on
the line 11 will change to 1.
To
to justify the assigned line values

justify
the
value 0 on the line

9,
we
have
to
assign 0 either to
the line 3 or to the
line 8 or to both
lines.
Fault Diagnosis
A unit under test (UUT) fails when its observed behaviour is different from its expected
Step 4:
behaviour. Diagnosis consists of locating the physical fault(s) in a structural model of the
UUT. The diagnosis process is often hierarchical, carried out as a top-down process (with a
system operating in the field) or bottom-up process (during the fabrication of the system).
Combinational Fault Diagnosis Methods
This approach does most of the work before the testing experiment. It uses fault simulation to
determine the possible responses to a given test in the presence of faults. The database
constructed in this step is called a fault table or a fault dictionary. To locate faults, one tries to
match the actual results of test experiments with one of the pre-computed expected results
stored in the database. The result of the test experiment represents a combination of effects of
the fault to each test pattern.
Fault Table Example
Sequential Fault Diagnosis Methods

In sequential fault diagnosis the process of fault location is carried out step by step, where
each step depends on the result of the diagnostic experiment at the previous step. Such a test
experiment is called adaptive testing. Sequential experiments can be carried out either by
observing only output responses of the UUT or by pinpointing by a special probe also
internal control points of the UUT (guided probing). Sequential diagnosis procedure can be
graphically represented as diagnostic tree.
Example of Fault Location by Edge-Pin Testing

The diagnostic tree in the Figure below corresponds to the fault table example. We can see
that most of the faults are uniquely identified, two faults F1,F4 remain indistinguishable. Not
all test patterns used in the fault table are needed. Different faults need for identifying test
sequences with different lengths. The shortest test contains two patterns the longest four
patterns.
Rather than applying the entire test sequence in a fixed order as in combinational fault
diagnosis, adaptive testing determines the next vector to be applied based on the results
obtained by the preceding vectors. In our example, if T1 fails, the possible faults are {F2,F3}.
At this point applying T2 would be wasteful, because T2does not distinguish among these
faults. The use of adaptive testing may substantially decrease the average number of tests
required to locate a fault.
Guided-Probe Testing
Guided-probe testing extends edge-pin testing process by monitoring internal signals in the
UUT via a probe which is moved (usually by an operator) following the guidance provided
by the test equipment. The principle of guided-probe testing is to backtrace an error from the
primary output where it has been observed during edge-pin testing to its physical location in
the UUT. Probing is carried out step-by-step. In each step an internal signal is probed and
compared to the expected value. The next probing depends on the result of the previous step.
Result:
Thus the built-in self-test and fault diagnosis is verified successfully.
CIRCUIT DESIGN & OUTPUT:
Ex.No: 13
DESIGN & SIMULATON OF TEMPERATURE
Date:
SENSOR USING PIC 16F877A
AIM:
To design & simulation of Temperature Sensor interfacing using PIC16F877A.
APPARATUS REQUIRED:
MPLAB IDE
PROTEUS VSM
PROCEDURE:
I.
Developing Procedure:
Open MPLAB IDEGo to project Wizard next select ICchoose ccs

compiler create a folderfinish
Newfiletype the programsave the document with .c extension
Right click on source fileadd filesselect .x extension file and right click on that
and compile it
Click build all and make project icons
Go to Configure Select device 16f877ok
Go to Configureconfiguration bits(disableenable)ok
Open PIC ISP check whether com1 port is selected or not select .hex fileclick
download.
II. Simulation Procedure:
Open Proteus ISIS 7 Professional Library Pick Device/Symbols
Connect the Components as per Circuit Diagram.
Double click the Microcontroller Browse the Program file (.Hex File).
Debug Execute
Verify the Simulated Output in LCD Display.
PROGRAM:
Program
#include<pic.h>
#include "LCD.h"
#define heart_beat RC0
UWORD temp1;
UBYTE COUNT=0, i=0;
static void hex_ascii(UWORD com)

{
UBYTE a,b,c,d;
temp1=ADRESH<<8;
temp1=(temp1+ADRESL)/2;
a=temp1%10;
b=temp1/10;
c=b%10;
d=b/10;
lcd_data(com+0,c+0x30);
lcd_data(com+1,a+0x30);
lcd_data(com+2,'C');
}
void main()
{
UBYTE b,c,d,e,f;
ADCON1=0X82;
ADCON0=0X00;
TRISE=0X00;
PORTE=0X00;
TRISD=0X00;
PORTD=0X00;
TRISC=0Xff;
PORTC=0X00;
lcd_init();
lcd_condis(0x80,"Health Indicator",16);
for(;;)
{
CHS2=0;//channel selection
CHS1=0;
CHS0=0;
ADON=1;//ADC on
delay(200);
ADCON0=(ADCON0|0X04);//initialize ADC conversion
delay(200);
lcd_condis(0xc0,"Temp:",5);
hex_ascii(0xc5);
lcd_condis(0xc8,"HB:",3);
for(i=0;i<9;i++)
{
TMR1ON=1;
TMR1CS=0;
// TIMER MODE
T1CKPS1=1;
// SETTING PRESCALAR VALUE AS 8
T1CKPS0=1;
TMR1H=0x0B;
TMR1L=0xDB;
while(TMR1IF==0)
{
if(heart_beat==1)
{
COUNT=COUNT+1;
}
else
{
COUNT;
}
}
if(TMR1IF)TMR1IF=0;TMR1ON=0;
}
COUNT=COUNT*6;
b=COUNT%10;//UNIT DIGIT
c=COUNT/10;
d=c%10;
e=c/10;
// tens digit
// hundred digit
lcd_data(0xcb+0,b+0x30);
lcd_data(0xcb+1,d+0x30);
lcd_condis(0xcd,"bpm",3);
COUNT=0;
}
}
RESULT:
Thus the interfacing Temperature Sensor with PIC using Proteus was designed &
simulated.

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INDEX

SYSTEM DESIGN USING PIC 16F877A

SYSTEM DESIGN USING MSP430

SYSTEM DESIGN USING AT89C51

SYSTEM DESIGN USING ATMEGA32

SIMULATION OF QMF USING

DESIGN OF SERIAL IN PARALLEL

DESIGN OF MOD-4 DOWN COUNTER

DESIGN OF DATA ACQUISITION

BUILT-IN SELF TEST AND FAULT

DESIGN & SIMULATON OF

SYSTEM DESIGN USING PIC 16F877A

6. Click Write button on GUI and Reset the Controller

SYSTEM DESIGN USING MSP430

Linker Output Others

5. Debugger Driver FET Debugger

2. Connect the serial cable between the PC and development board.

SYSTEM DESIGN USING AT89C51

Baud Rate: 9600

Interface : None (ISP)

SYSTEM DESIGN USING ATMEGA32

FREQUENCY RESPONSE OF QMF FILTER

SIMULATION OF QMF USING SIMULATION

Open the MATLAB.

FILE ->New->M-file. Editor window is opened.

Write the program in Editor window.

Save the program with MATLAB extension .m

Debug ->save and run.

Then ,the output is simulated and verified.

of that of another filter. Together these filters are known

as the Quadrature Mirror Filter pair.

will be quadrature mirror filter of

The filter responses are symmetric about

% clear command & workspace

f = [0 0.5 0.552 1];

% define filter cut-off frequency

% define filter structure

% FIR filter design using hanning window, H(z)

% impulse response plot for analysis filter

% QMF synthesis filter, 2H(z)

% impulse response plot for synthesis filter

% Determine Frequency Response

% Plotting radian Vs gain

% Determine Frequency Response

% Plotting radian Vs gain

xlabel('\omega/\pi (rad)'); ylabel('Gain (dB)');

% find-out filter error

DESIGN OF SERIAL IN PARALLEL OUT

Fileopen new projectgive project namenew source

Enter the program

Filesave with .vhd extension

If the program verified successfully then click on simulation

Processbehavioral checkingsimulate wave form

Output Waveform : Serial In - Parallel Out Shift Register

DESIGN OF MOD-4 DOWN COUNTER

Fileopen new projectgive project namenew source

Enter the program

Filesave with .vhd extension

If the program verified successfully then click on simulation

Processbehavioral checkingsimulate wave form

IMPLEMENTATION OF ADAPTIVE FILTERS IN DSP

Code Composer Studio software

STEP-1: Setup configuration of DSP processor in Code composer Studio

alteredSig = origSig + noiseSig;