Академический Документы
Профессиональный Документы
Культура Документы
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Welcome to San Francisco and the 35th Design Automation Conference. We wish you
a very productive and fun-filled week.
Basant R. Chawla
General Chair, 35th Design Automation Conference
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Womens
Workshop
Two
Exciting
Keynotes
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program highlights
Womens Workshop - Forget the Ceiling - Break the Glass
This Sunday workshop is designed to help women develop a personal plan for career development.
See details on page 4
TUESDAY KEYNOTE
William J. Spencer
THURSDAY KEYNOTE
George H. Heilmeier
Chairman Emeritus
Bellcore, Morristown, NJ
Thursday, June 18 - 1:00 PM
Gateway Ballroom
See details on page 5
Leaders from the EDA vendor industry, the design community, and universities discuss how EDA can
continue to support rapid innovation in the electronics industry.
See details on page 13
Technical
Program
Over 160 papers, panels, and embedded tutorials in five parallel tracks, covering system design,
advanced verification techniques and issues in deep-submicron design.
See details on pages 7 - 33
35 Years of
Design
Automation
University Design
Contest
6 New
Tutorials
Friday,
June 19
A panel of design automation visionaries presents a retrospective of 35 years of DA, and a lookforward into the coming decade.
See session 49 on page 33
The best in university design and design methodology is presented in a special session and recognized
by a new award.
See session 3 on page 15
Tutorials
1) Design Validation Techniques
2) Design of Complex Mixed-Signal Systems on a Chip
3) CAD for System-Design: Models, Issues, and Some Emerging Tools
4) Interconnect Analysis in High-Frequency, Sub-Micron, Digital VLSI Design
5) Finding Design Errors and Locating Defects: The Same Detective Story
6) High Performance RTL Coding Styles for Synthesis
See details on pages 35 -39
DAC Sponsors
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Silicon Village
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DAC highlights
The newest feature of the exhibit floor. The area features silicon vendors offering ASIC, programmable logic,
foundry and IP solutions.
Exhibit
Information
Exhibitor
Presentations
Monday, June
15
Demo Suites
The newest innovations at your fingertips with exhibitors highlighting their latest products.
Exhibitor Listing
Exhibitor Presentation Abstracts
Exhibitor Product Descriptions
Pages 61 - 62
Pages 67- 88
Pages 90 - 166
A full day of 20-minute exhibitor presentations - choose from 132 presentations; see pages 65-88 for details.
$40 full exhibit-only registration will allow you to attend exhibits Monday through Wednesday.
8:00 AM - 9:00 PM
8:00 AM - 5:00 PM
WWW.DAC.COM
The DAC Web page (http://www.dac.com) provides your connection to the conference and other information of
interest to the DA community.
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conference survey
Again this year we would like you to voice your opinion on various aspects of the conference. DAC is conducting
surveys to determine how to best serve your needs. Please take a few moments to participate if you are
approached by one of our surveyors. Look for interviewers wearing ??? buttons at various locations around
the show. Help make a difference in DAC and receive a Swiss Army-style pocket knife for participating. All survey
participants will also be put in a raffle with a chance to win a Leather Bomber Jacket donated by Compaq.
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Sunday
June 14, 1998
9:00 to 4:00
Moscone Center
San Francisco, CA
Room 301
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Workshop Chair: Penny Herscher - President and CEO, Simplex Solutions, Inc.
Organizing Committee:
Steering Committee:
Barb Acosta - Group Director, Cadence Design Systems, Inc.
Lois DuBois - Communications Consultant
Jody Fast - Corporate Marketing, Simplex Solutions, Inc.
Deirdre Hanford - Vice President, Synopsys, Inc.
Leigh Huang - Director, Avant! Corp.
Jennifer Smith - Vice President, Robertson Stevens
Session 1: Keynote Speech Top 10 Ways Women Shoot Themselves in the Workplace
Nora M. Denzel - Senior Vice President, Legato Systems, Inc.
Nora M. Denzel
eynote Speaker
r. Vice President
Legato
Systems, Inc.
This exciting talk will acquaint you with the ten most common mistakes women make in trying to climb the corporate career
ladder. You will learn first hand what the mistakes are and how to combat them from someone who has been there. Using
a lot of humor and personal experience, Nora will share with you what she learned as she climbed the corporate ladder at
IBM to become one of their youngest executives at 33! She will talk candidly about how she did it, and how you can do it
at an even faster pace.
Penny Herscher
Workshop Chair
President & CEO
Simplex
Solutions, Inc.
The objective of this panel is to share successful habits that others have found work for them, and to create a dialog
through Q&A to address questions you may have about your personal challenges. Each panelist will share with you the
habits they have developed to succeed in the technical world, or have observed in others. They will then be available to
answer your questions during the Q&A session.
Session 4: Workshop
Ceiling
The audience will break up into small work groups to each create a plan of action for their personal career challenges.
Barb is a three time Olympic trialist runner, with world class ranking from 5000 meters through marathon. She also
happens to work in EDA at Cadence! In an inspiring talk, Barb will share techniques to set and break personal records that
you can directly apply to setting and breaking your own career goals.
8:00 AM Registration & Breakfast
10:00 AM BREAK
1:00 PM Tutorial on Mentoring
9:00 AM Welcome by Penny Herscher
10:15 AM Successful Women Panel
1:45 PM BREAK
9:15 AM Keynote Speech, Nora Denzel 12:00 PM LUNCH
2:00 PM Identifying Changes Workshop
The Workshop registration fee includes: a continental breakfast, lunch and the reception.
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Tuesday
Opening
Keynote
Address
9:00 to
10:15
ESPLANADE
BALLROOM
no badge
required to
attend the
Tuesday
Keynote
Thursday
Keynote
Address
1:00 to
1:45
GATEWAY
BALLROOM
no badge
required to
attend the
Thursday
Keynote
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keynote addresses
Design Automation Can Help the Semiconductor
Industry Address Its Many Challenges
William J. Spencer
Chairman of the Board
SEMATECH, Inc.
Austin, TX
Silicon technology has been the economic driver for much of the Information Age, by
providing a 25-30% year-over-year improvement in cost per unit of performance. This
amazing performance has been fueled by constantly improving semiconductor technology,
including major gains in design automation. For the industry to remain on this historic
productivity curve, break-throughs will be required in several aspects of semiconductor
manufacturing technology often linked strongly to design.
Bill Spencer is currently Chairman of SEMATECH, a research and development consortium consisting of sixteen
international corporations involved in semiconductor manufacturing. From 1990-1997, he served as President and
Chief Executive Officer of SEMATECH. Prior to 1990, he was Group Vice President and Senior Technical Officer at
Xerox Corporation in Stamford, Connecticut, as well as Vice President and Manager of the Xerox Palo Alto Research
Center (PARC). He was Director of Systems Development and also Director of Microelectronics at Sandia National
Laboratories from 1973 to 1981, prior to joining Xerox. He began his career at Bell Telephone Laboratories in 1959.
He received his Ph.D. and M.S. from Kansas State University, and an A.B. from William Jewell College in Missouri.
Spencer is also a Research Professor of Medicine at the University of New Mexico, where the first implantable
electronic drug delivery systems were developed jointly with Sandia National Labs. For this work, he received the
Regents Meritorious Service Medal and later a doctor of science degree from William Jewell College. He is currently
a Director of Adobe Systems, Investment Corporation of America, SRI International and the Austin Symphony. He
is also a member of the Board of Trustees of the Computer Museum and William Jewell College.
He has served on several National Research Council studies in the areas of technology, trade, corporation and
competition. In 1998, he will co-chair, with Dick Thornburgh, a NRC workshop on Harnessing Technology for Americas
Future Economic Growth. He will also serve as a Regents Professor at the University of California at Berkeley.
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(badge required)
Monday, June 15
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
10:00 AM to 6:00 PM
10:00 AM to 6:00 PM
10:00 AM to 6:00 PM
8:00
8:00
8:00
8:00
AM
AM
AM
AM
to
to
to
to
9:00
9:00
9:00
5:00
PM
PM
PM
PM
Sunday, June 14
Sunday, June 14
Monday, June 15
8:00 A M to 10:00 A M
4:00 PM to 6:00 PM
8:00 AM to 6:00 PM
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
7:30 AM to 5:00 PM
7:30 AM to 5:00 PM
7:30 AM to 3:00 PM
information desk/messages
The information desk is located in the concourse on the exhibit level. To receive a message at
conference, the DAC Information Desk must be contacted. A message board is located at the information
desk. (Attendees may also send email to one another via DACnet). There are also people available to
answer questions concerning the San Francisco area. For assistance please call (415) 978-3600.
first-aid rooms
The first-aid room for the South Hall is located outside of room 106. The first-aid room for the North Hall
is located outside of room 125. The first-aid room for the Esplanade Ballroom is located next to room 300.
For assistance please call the control room at (415) 974-4021, and ask for the first-aid room. A
nurse will be on duty at all times while meetings and exhibits are open.
business center
Packaging, UPS, photocopy/fax service, computer rental, and office supplies will be in the exhibit
level South Lobby outside Hall C.
Coat and baggage check will be in the South Lobby.
DACnet -98
DACnet workstations will be located in the South Lobby, Esplanade Lobby, the concourse, and the
Press room.
food services
Luncheon service is available Monday through Thursday. Food courts are located in room 206 on
the Mezzanine Level, and room 300 on the Esplanade Level. DAC hosted coffee breaks will be in
the Esplanade Lobby and meeting rooms 302, 309 and 310.
MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
It has been our pleasure to serve you professionally this year. We wish to thank the DAC sponsors, and
the DAC Executive Committee for this opportunity. We also wish to thank the Session Chairs, Speakers,
the Program Committee, and the Exhibitors for their cooperation with MP Associates, Inc.
Marie R. Pistilli, Exhibit Manager & Pat O. Pistilli, Conference Manager
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chedule
tuesday, june 16
9:00
to
10:15
Design Automation Can Help the Semiconductor Industry Address Its Many Challenges
Break
BREAK
William J. Spencer
Chairman of the Board, SEMATECH, Inc., Austin, TX
Opening Remarks Awards Keynote Address (Room: Esplanade Ballroom)
10:30
to
12:00
Lunch
RM #
2:00
to
4:00
RM 102
RM 301
RM 305
RM 304
RM 103
Session 1
Session 2
Session 3
Session 4
Session 5
Interfaces for
Design Reuse
(Tutorial included)
University Design
Contest
Embedded System
Design and
Exploration
Panel: Taming
Noise in DeepSubmicron Digital
Designs
(Tutorial included)
BREAK
Break
4:30
to
6:00
6:00
to
7:00
Session 6
Session 7
Session 8
Session 9
Session 10
Synthesis Flow in
Deep Submicron
Technologies
(Tutorial included)
Environment for
Collaborative
Design
New Methods in
Functional
Verification
Panel: Hardware/
Software Co-Design The Next Embedded
System Design
Challenge
S
RM #
8:30
to
10:00
chedule
wednesday, june 17
RM 102
RM 301
RM 305
RM 304
RM 103
Session 11
Session 12
Session 13
Session 14
Session 15
Extraction and
Modeling for
Interconnect
Processor Design
and Simulation
BREAK
Break
10:30
to
12:00
Session 16
Session 17
Session 18
Session 19
Session 20
Performance
Modeling and
Characterization for
Embedded Systems
Advances in
Placement and
Partitioning
Parasitic Device
Extraction and
Interconnect
Modeling
Design
Optimization for
DSP
Panel: User
Experience With
High Level Formal
Verification
Session 23
Session 24
Session 25
Routing for
Performance and
Crosstalk
Practical
Optimization
Methodologies for
High Performance
Design
RF IC Design
Methodology
(Tutorial included)
Session 29
Session 30
Panel: Technical
Challenges of IP
and Systems-onChip: The ASIC
Vendor Perspective
Lunch
2:00
to
4:00
Session 22
Break
BREAK
Session 26
4:30
to
6:00
Session 27
Session 28
S
RM #
8:30
to
10:00
chedule
thursday, june 18
RM 102
RM 301
RM 305
RM 304
RM 103
Session 31
Session 32
Session 33
Session 34
Session 35
12:00
Lunch
2:00
2:00
to
4:00
Session 36
Session 37
Session 38
Timing Analysis
New Techniques
in State Space
Explorations
Advanced ATPG
Techniques
Session 39
Session 40
From POTS to PANS: Transition in the World of Telecommunications for the Late 90s and Beyond.
Session 42
Session 43
Session 44
Session 45
Fast Functional
Simulation
(Tutorial included)
Power Estimation
and Modeling
Technology
Mapping for
Programmable
Logic
Power Dissipation
and Distribution in
High Performance
Processors
Panel: Challenge
in the Test on
System-on-a-Chip
Era
(Tutorial included)
BREAK
Break
4:30
to
6:00
Interconnect
Panel: Design
Analysis and
Productivity: How to
Reliability in Deep Measure It, How to
Sub-micron
Improve It
BREAK
Break
10:30
to
12:00
Core Test
and BIST
RM 301
RM 305
RM 304
RM 103
Session 46
Session 47
Session 48
Session 49
Controller
Decomposition for
Power and Area
Minimization
IP Protection
Technologies
Case Studies of
New Design
Methods
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Tutorials will be held at the Moscone Center in the Esplanade Ballrooms 301 -306.
8:00 AM - Tutorial Registration Opens (Esplanade Lobby)
8:30 AM - Continental Breakfast
9:00 AM - Tutorials Begin
Tutorial 1
Room 305
Tutorial 2
Room 302
Tutorial 3
Room 303
Tutorial 4
Room 304
Tutorial 5
Room 301
Tutorial 6
Room 306
ac
Silicon Village
Sessions: 1, 7, 24, 30, 33, 35, 39, 43, 45, 47
Design Verification
Sessions: 9, 14, 20, 21, 28, 32, 36, 39, 41, Tutorial 1
Deep Sub-Micron
Sessions: 5, 7, 13, 18, 23, 28, 34, Tutorial 4
Interconnect
Sessions: 13, 18, 23, 28, 34, Tutorial 4
Physical Design
Sessions: 7, 17, 23
11
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If you are interested in the following topics please see the related
sessions listed below.
FPGAs
Sessions: 3, 12, 43
Microprocessors
12
opening session
Opening remarks
9:00 AM
to
10:15 AM
Esplanade
Ballroom
Basant R. Chawla
General Chair
Randal E. Bryant
Design Tools Co-Chair
Jan M. Rabaey
Design Methods Co-Chair
Awards
James Cohoon
ACM Representative
Bing Sheu
Vice President for Conferences IEEE/CAS
10:30 AM
to
12:00 PM
Esplanade
Ballroom
uesday, june 16
SESSION 1
2:00
to
4:00
- denotes
best paper
Room: 102
SESSION 2
Room: 301
uesday, june 16
SESSION 3
Room: 305
UNIVERSITY DESIGN
CONTEST
Chair: Mary Jane Irwin - Penn State
Univ., University Park, PA
Organizer: Jan M. Rabaey
A first for DAC, this session presents original
electronic designs developed at Universities
and resulting in operational implementations.
The designs span a diversity of application
areas
including
wireless,
DSP,
microprocessors and multiprocessors and
use design methodologies and techniques
ranging from custom ICs, to ASICs, to
FPGAs, to PCBs.
SESSION 4
Room: 304
SESSION 5
Room: 103
EMBEDDED SYSTEM
DESIGN AND
EXPLORATION
TAMING NOISE IN
DEEP-SUBMICRON
DIGITAL DESIGNS
PANEL MEMBERS:
Barbara Chappell - Intel Corp.,
Hillsboro, OR
John MacDonald - Sun Microsystems,
Palo Alto, CA
Bob Masleid - IBM Corp., Austin, TX
John McBride - Hewlett-Packard, Fort
Collins, CO
Chris Noughton - Digital Equipment,
Hudson, MA
Kenneth L. Shepard - Columbia Univ.,
New York, NY
Xiaonan Zhang - Metaflow
Technologies, Inc., La Jolla, CA
15
uesday, june 16
SESSION 6
4:30
to
6:00
- denotes
best paper
Room: 102
Room: 301
16
SESSION 7
uesday, june 16
SESSION 8
Room: 305
SESSION 9
Room: 304
ENVIRONMENT FOR
COLLABORATIVE
DESIGN
NEW METHODS IN
FUNCTIONAL
VERIFICATION
SESSION 10
Room: 103
PANEL:
HARDWARE/SOFTWAR
E CO-DESIGN THE
NEXT EMBEDDED
SYSTEM DESIGN
CHALLENGE
Chair: Pete Heller - Collett International,
Inc., Santa Clara, CA
Organizers: Diane Orr, Kristin Hehir Tsantes & Associates,
Campbell, CA
Issues, challenges, tradeoffs and solutions
being employed in the design of systems
with increasing amounts of functionality
implemented in software will be explored in
this panel. Perspectives from system
designers and tool vendors in hardware and
software development domains will be
shared. This panel's goal is to identify
challenges embedded designers face and
determine if design tools offered provide
true hardware/software co-design solutions.
Without an interface to synthesis, can
hardware/software co-design provide
meaningful value? Can automatic hardware
and software partitioning tools replace
humans? Who is responsible for
hardware/software co-design? System
architects? Hardware designers? Software
designers? Can tools optimize system
functionality and performance tradeoff s
between
hardware
and
software
implementation? Are commercial real time
operating systems impacting hardware and
software tradeoff decisions?
PANEL MEMBERS:
17
ednesday, june 17
SESSION 11
Room: 102
SYSTEM-LEVEL POWER
OPTIMIZATION
Chair: Vivek Tiwari - Intel Corp., Santa Clara, CA
Organizers: Rajesh K. Gupta, Sunil D. Sherlekar
Power optimization at the system level must address
a diverse array of issues ranging from choice of
system hardware and software components,
memory system design and appropriate policies for
use of system resources. Papers in this session
report on the progress in methodologies, frameworks
and policy optimization for power reduction at the
system level.
8:30
to
10:00
- denotes
best paper
18
SESSION 12
Room: 301
BOOLEAN METHODS
Chair: Fabio Somenzi - Univ. of Colorado,
Boulder, CO
Organizers: Sharad Malik, Randal E. Bryant
This session examines new an alysis techniques for
Boolean functions. The first paper presents an
innovative instance-specific hardware acceleration
for SAT formulas using configurable logic. The
second paper presents a technique for exact
minimization of BDD representations of functions.
Finally, the last paper presents a canonical NPN
representation of functions for the use in
technology mapping.
ednesday, june 17
SESSION 13
Room: 305
EXTRACTION AND
MODELING FOR
INTERCONNECT
Chair: Hidetoshi Onodera - Kyoto Univ.,
Kyoto, Japan
Organizers: Hidetoshi Onodera,
Alan Mantooth
Fast and accurate analysis of interconnect is
crucial for the performance estimation of
deep sub-micron circuits. This session
discusses methods for interconnect parasitic
extraction using integral equation approaches.
The first paper presents 3-D capacitance
extraction based on a hierarchical algorithm for
the N-body problem. The second paper
proposes a BEM formulation for generating
macromodels used in 2-D hierarchical
capacitance extraction. The last paper
describes a computationally efficient method
for parasitic extraction using a multi layered
3-D Greens function.
SESSION 14
Room: 304
PROCESSOR DESIGN
AND SIMULATION
Chair: Randolph E. Harr - Synopsys,
Inc., Mountain View, CA
Organizers: Anantha Chandrakasan,
Randolph E. Harr
Embedded and single-chip processors are
the core element for all new computing
platforms. Unique design problems inherent
to these processors are finally emerging.
This session covers some recent tool and
methodology developments applied to the
design of DSPs and microprocessors.
SESSION 15
Room: 103
PANEL MEMBERS:
19
ednesday, june 17
SESSION 16
Room: 102
PERFORMANCE MODELING
AND CHARACTERIZATION
FOR EMBEDDED SYSTEMS
Chair: Sunil D. Sherlekar - Silicon Automation
Systems, Bangalore, India
Organizers: Sunil D. Sherlekar, Rajesh K. Gupta
10:30
to
12:00
- denotes
best paper
20
SESSION 17
Room: 301
ADVANCES IN PLACEMENT
AND PARTITIONING
Chair: Antun Domic - Synopsys, Inc., Mountain
View, CA
Organizers: Patrick Groeneveld, Andrew B.
Kahng
This session opens with two powerful advances in
the quadratic placement approach. Next, the novel
application of placement with incomplete netlist
information is introduced. The last two papers
address new multi-way partitioning and clustering
formulations.
ednesday, june 17
SESSION 18
Room: 305
PARASITIC DEVICE
EXTRACTION AND
INTERCONNECT
MODELING
Chair: David D. Ling - IBM Corp.,
Yorktown Heights, NY
Organizers: Alan Mantooth, Hidetoshi
Onodera
This session includes papers focused on
layout extraction. The first paper deals with
the extraction and verification of CMOS I/O
Circuits, which involves the extraction of
SCRs, parasitic bipolar transistors, etc. The
next two papers deal with interconnect
extraction and modeling. One involves
efficient reduced order models for 3-D
interconnects. The other involves extraction
of frequency dependent behavior for timing
analysis.
SESSION 19
Room: 304
DESIGN OPTIMIZATION
FOR DSP
Chair: James A. Rowson - Alta Group
of Cadence Design Systems,
Inc., Sunnyvale, CA
Organizers: Anders Forsen, Ivo Bolsens
Computationally intensive DSP problems
can be optimized early in the design cycle.
These papers show their approaches:
interactive optimization at the behavioral
level, a methodology based on C++, and an
architectural approach for image processing.
SESSION 20
Room: 103
PANEL: USER
EXPERIENCE WITH
HIGH LEVEL FORMAL
VERIFICATION
Chair: Gerry Musgrave - Brunel Univ.,
Uxbridge, UK
Organizers: Gerry Musgrave - Brunel
Univ., Uxbridge, UK
Randal E. Bryant Carnegie Mellon Univ.,
Pittsburgh, PA
Formal verification methods are beginning to
be used by leading edge industries. How
effective are they, how easy it is to embed
them in the design flow and what are the
future requirements are questions the
industry wishes to have answered. The
panel will attempt to answer these and other
aspects of model checking or parameter
validation techniques by sharing their
experience in using a variety of tools. The
emphasis will be on what has been achieved
and how design teams cope with changes in
design flow. They will also describe how they
have been able to transform from using the
tools as a post design checker to be a
proactive design aid in achieving quality
designs in a shorter time.
PANEL MEMBERS:
Pierre Aulagnier - Cisco Systems,
San Jose, CA
Fumiyasu Hirose - Fujitsu Labs., Ltd.,
Kawasaki, Japan
Michael Payer - Siemens AG, Munich,
Germany
Alan Silbert - Nortel, Ottawa,
ON, Canada
John Van Tassel - Texas Instruments,
Inc., Dallas, TX
21
ednesday, june 17
SESSION 21
Room: 102
2:00
to
4:00
SESSION 22
Room: 301
LOGIC OPTIMIZATION
Chair: Albert Wang - Synopsys, Inc., Mountain
View, CA
Organizers: Jason Cong, TingTing Hwang
This session presents recent advances on various
aspects of logic optimization. The first paper presents
a novel method for optimal mapping combined with
forward retiming to guarantee efficient initial state
computation. The second paper presents on-the-fly
technology mapping during logic optimization. The
third paper presents new techniques for efficient
Boolean division. The fourth paper extends efficient
delay-optimal mapping techniques for FPGAs to
library-based designs. The last paper presents an
e fficient solution for fanout optimization.
22
ednesday, june 17
SESSION 23
Room: 305
ROUTING FOR
PERFORMANCE AND
CROSSTALK
Chair: Sachin S. Sapatnekar - Univ. of
Minnesota, Minneapolis, MN
Organizers: Patrick Groenveld,
Andrew B. Kahng
Routing today is more than making all
connections DRC correct in minimum area. In
addition a sub-micron router must maximize
performance and minimize undesired effects
such as crosstalk. This session is dedicated
to new methods for routing that optimize for
these new concerns.
SESSION 24
Room: 304
PRACTICAL OPTIMIZATION
METHODOLOGIES FOR
HIGH PERFORMANCE
DESIGN
Chair: Vivek Tiwari - Intel Corp., Santa
Clara, CA
Organizers: Vivek Tiwari, Kenji Yoshida
The push for high performance design
continues to stress the capabilities of
conventional tools. This motivates the
development
of
innovative
design
methodologies. The first paper describes a
unified methodology for process and circuit
optimization. The other papers present
practical solutions for the problems of timing
improvement of std cell circuits, repeater
insertion and datapath synthesis.
SESSION 25
Room: 103
RF IC DESIGN
METHODOLOGY
Chair: Mojy C. Chian - Harris
Semiconductor, Melbourne, FL
Organizers: Bryan D.Ackland,
Mojy C. Chian
RF design has long been considered a black
art. Historically design tools have been
unable to provide an integrated environment
for RF IC design. This session describes
specific constraints and challenges faced by
RF IC designers and CAD tool developers,
including the strong coupling between signal
integrity and design.
Palo Alto, CA
ednesday, june 17
SESSION 26
Room: 102
24
Room: 301
BDD APPROXIMATION
TECHNIQUES
4:30
to
6:00
SESSION 27
ednesday, june 17
SESSION 28
Room: 305
INTERCONNECT
MODELING AND TIMING
SIMULATION
Chair: Andrew T. Yang - Univ. of
Washington, Seattle, WA
Organizers: Andrew T. Yang, Hidetoshi
Onodera
Non-linear electrical-level circuit and timing
simulation play an important role in the
design and analysis of large scale ICs. The
first three papers in this session address a
variety of interconnect modeling techniques
which can be used in circuit simulation and
timing analysis. The last paper presents a
method for computing adjoint transient
sensitivity in an event-driven PWL simulator.
SESSION 29
Room: 304
SESSION 30
Room: 103
PANEL: TECHNICAL
CHALLENGES OF IP
AND SYSTEM-ON-CHIP:
THE ASIC VENDOR
PERSPECTIVE
Chair: Richard Newton - Univ. of
California, Berkeley, CA
Organizers: Andrew Graham - Si2,
Austin, TX
Andrew B. Kahng - Univ. of
California, Los Angeles, CA
The demand for system-on-chip solutions is
creating
vast
changes
in
reuse
methodology and EDA technology.
Traditional roles of foundries, ASIC
suppliers, and EDA vendors are blurring.
For the end customer, the situation presents
correspondingly
greater
risks
and
opportunities. This panel brings together
today's leading providers of embedded
silicon IP solutions.
The panelists will
discuss practical expectations for systemon-chip design, and the key pieces of
industry infrastructure that must be
addressed to realize the full potential of
system-on-chip. These include: customer
expectations, EDA technology implications;
standards; legal barriers and associated
risks facing ASIC suppliers and EDA
vendors; challenges of incorporating 3rdparty IP; and practical reuse methodologies.
PANEL MEMBERS:
Bruce Beers - IBM Corp., Essex
Junction, VT
Jeffery Hilbert - LSI Logic, Milpitas, CA
Michael Jackson - Motorola, Inc.,
Austin, TX
Anand Naidu - Sand Microelectronics,
Santa Clara, CA
Bob Payne - VLSI Technology,
San Jose, CA
Mark Stibitz - Lucent Technologies,
Allentown, PA
Hitoshi Yoshizawa - NEC Corp.,
Kawasaki, Japan
25
hursday, june 18
SESSION 31
Room: 102
8:30
to
10:00
- denotes
26
SESSION 32
Room: 301
FORMAL METHODS IN
FUNCTIONAL VERIFICATION
Chair: Kunle Olukotun - Stanford Univ.,
Stanford, CA
Organizers: Kunle Olukotun, Andreas
Kuehlmann
This session explores techniques for functional-level
verification. The first paper adds support for bitvector arithmetic to a formal verification environment
that combines theorem proving and model checking.
The second paper presents a new technique for
generating functional test vectors. The last two
papers demonstrate the industrial use of symbolic
trajectory evaluation.
hursday, june 18
SESSION 33
Room: 305
SESSION 34
Room: 304
SESSION 35
Room: 103
INTERCONNECT
ANALYSIS AND
RELIABILITY IN DEEP
SUB-MICRON
PANEL: DESIGN
PRODUCTIVITY: HOW
TO MEASURE IT, HOW
TO IMPROVE IT
PANEL MEMBERS:
Andy Bechtolsheim - Cisco Systems,
San Jose, CA
Ronald E. Collett - Collett International,
Santa Clara, CA
Jeff Hilbert - LSI Logic, Milpitas, CA
Chris Malachowsky - NVidia Corp.,
Sunnyvale, CA
Leif Rosqvist - Cadence Spectrum
Design, San Jose, CA
Jim Thomas - Motorola M-Core
Technology Ctr., Austin, TX
27
hursday, june 18
SESSION 36
Room: 102
Thursday
Keynote
Address
1:00 to 1:45
GATEWAY
BALLROOM
no badge
required to
attend the
Thursday
Keynote
- denotes
28
Room: 301
HIERARCHICAL FUNCTIONAL
TIMING ANALYSIS
10:30
to
12:00
SESSION 37
hursday, june 18
SESSION 38
Room: 305
ADVANCED ATPG
TECHNIQUES
Chair: Yervant Zorian - LogicVision, Inc.,
San Jose, CA
Organizers: Yervant Zorian, Janusz Rajski
Advanced techniques developed for automatic
test pattern generation frequently find
applications in design verification. Papers
presented in this session introduce new
efficient techniques to generate input/output
sequences for functional testing, new highperformance method for sequential learning
of implications and a fault simulation-based
method for diagnosing general design errors
in sequential circuits.
SESSION 39
Room: 304
PRACTICAL
EXPERIENCE OF
FUNCTIONAL
VERIFICATION FOR
COMPLEX ICs
Chair: Rajesh Raina - Motorola, Inc.,
Austin, TX
Organizers: David T. Blaauw, Kenji
Yoshida
Functional verification of large ICs is
consuming an increasingly large portion of
the design resource and design time. This
session examines experiences and results
with functional verification methods of two
high-performance microprocessor designs
and a large ASIC design.
SESSION 40
Room: 103
PANEL MEMBERS:
Rick Carlson - Synplicity, Inc.,
Sunnyvale, CA
Lorne Cooper - Sente, Inc., Acton, MA
Dean Drako - Design Acceleration, Inc.,
San Jose, CA
Rajeev Madhavan - Magma Design
Automation, Inc., Palo Alto, CA
John Sanguinetti - Chronologic, Los
Altos, CA
Curt Widdoes - 0-In Design Automation,
Inc., San Jose, CA
29
hursday, june 18
SESSION 41
Room: 102
Room: 301
FAST FUNCTIONAL
SIMULATION
2:00
to
4:00
SESSION 42
30
hursday, june 18
SESSION 43
Room: 305
TECHNOLOGY MAPPING
FOR PROGRAMMABLE
LOGIC
Chair: Jonathan Rose - Univ. of Toronto,
Toronto, ON, Canada
Organizers: Jason Cong, TingTing Hwang
This session presents new technology mapping
algorithms for complex PLDs and FPGAs. The
first paper presents synthesis and mapping
methods for PLA-style logic blocks. The second
and third papers study the technology mapping
problems for FPGAs with heterogeneous LUTs.
The fourth paper presents a new function
decomposition formulation and solution. The fifth
and sixth papers present post-layout re-synthesis
methods for power reduction in FPGA designs.
SESSION 44
Room: 304
POWER DISSIPATION
AND DISTRIBUTION IN
HIGH PERFORMANCE
PROCESSORS
Chair: David T. Blaauw - Motorola, Inc.,
Austin, T X
Organizers: Anatha Chandrakasan,
Jan M. Rabaey
As feature sizes shrink and clock rates grow,
power dissipation is rapidly becoming a limiting
factor. Sources of power dissipation and power
management techniques for high performance
processors will be discussed. With high power
levels, also comes the challenge of reliably
distributing power on the chip.
SESSION 45
Room: 103
TEST CHALLENGES IN
THE SYSTEM CHIP ERA
Chair: Prab Varma - Duet Technologies,
San Jose, CA
Organizers: Prab Varma - Duet
Technologies Inc.,
San Jose, CA
Takahide Inoue - Sony
Corp., Milpitas, CA
45.1 Embedded Tutorial: System-Chip
Test Strategies
Yervant Zorian - LogicVision, Inc.,
San Jose, CA
PANEL MEMBERS:
Sujit Dey - Univ. of California, San
Diego, CA
Rudy Garcia - Schlumberger
Te c h n o l o g i e s, San Jose, CA
Erik Jan Marinissen - Philips Research
Labs., Eindhoven, The Netherlands
Bruce Mathewson - Advanced RISC
Machines Ltd., Cambridge, UK
Rob Roy - Intel Corp., Hillsboro, OR
Prab Varma - Duet Technologies,
San Jose, CA
Yervant Zorian - LogicVision, Inc.,
San Jose, CA
31
hursday, june 18
SESSION 46
Room: 102
CONTROLLER
DECOMPOSITION FOR
POWER AND AREA
MINIMIZATION
Chair: Fabio Somenzi - Univ. of Colorado,
Boulder, CO
Organizers: Timothy Kam, Luciano Lavagno
4:30
to
6:00
32
SESSION 47
Room: 301
IP PROTECTION
TECHNOLOGIES
Chair: Tom VandenBerge - Texas Instruments,
Dallas, TX
Organizers: Richard Smith, Takahide Inoue
The requirement for the exchange of Intellectual
Property in the design of systems on a chip is well
documented. Protection of IP is needed to support
this exchange. This session presents techniques
for watermarking IP to prove ownership and
encrypting IP to discourage reverse engineering.
hursday, june 18
SESSION 48
Room: 305
SESSION 49
Room: 103
THIRTY-FIVE YEARS OF
DESIGN AUTOMATION, A
RETROSPECTIVE AND A
LOOK-FOWARD
(no badge is required to attend)
Chair: Paul Weil - Intel Corp., Santa Clara, CA
Organizer: Jan M. Rabaey
This session will celebrate thirty five years of design
automation with three presentations by long time
contributors to the field. These presentations will review
the past accomplishments and views of the future. There
will be a panel session after the talks.
33
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New this year DAC has created the University Design Contest. Attend Session 3 to see the top
entries of original electronic designs (circuits or system) that have resulted in operational
implementation. This competition among University researchers was judged on the level of
innovation in the design flow and their use of EDA tools. The top contestants have produced
outstanding work that is detailed in the Session 3 University Design Contest.
Do you have a hot design? Tell the world about it by submitting a proposal to the 36th DAC
University Design Contest. Submissions of original electronic designs (circuit or system) developed
at Universities and research organizations after June, 1997 and resulting in operational
implementations are invited. All entries should provide a complete description of the design and
clarify the originality, distinguishing features and measured performance metrics of the design.
Proof-of-implementation in the form of die or board photographs and measurement data is a must.
See the 36th DAC Call for Papers for complete details on pages 46 - 47.
notes
34
riday, june 19
Tutorials will be held at the Moscone Center in the Esplanade Ballrooms 301 - 306.
8:00 AM - Tutorial Registration Opens (Esplanade Lobby)
8:30 AM - Continental Breakfast
9:00 AM - Tutorials Begin
Tutorial
One
Room 305
Organizer: Gitanjali Swamy - Boston Advanced Development Labs., Mentor Graphics Corp., Boston, MA
Presenters:
Adnan Aziz - Univ. of Texas, Austin, TX
Rajeev Muragi - Fujitsu Labs. of America, Inc., Santa Clara, CA
Amit Narayan - Univ. of California, Berkeley, CA
Gitanjali Swamy - Boston Advanced Development Labs., Mentor Graphics, Boston, MA
Audience: The tutorial will be of interest to the following audiences.
Digital designers, and design project managers: in understanding and choosing validation techniques that are
best suited for different design stages. This will assist evaluation of commercial validation offerings, and help
devise a comprehensive validation strategy in which bugs are caught early in the design cycle.
CAD vendors: in identifying technologies that are relatively mature in the research community and are ready
to be commercialized.
Researchers: in identifying open research problems, where significant advances can be made.
What distinguishes this tutorial from previous ones is that it provides a complete and comprehensive survey
of methods for functional validation, rather than focus on a particular technology alone.
Description: The increasing complexity of VLSI systems has made their functional validation extremely difficult.
Indeed, verification has become the bottleneck in the IC design process today, with validation teams often being
comparable in size to design teams. This tutorial covers state-of-the-art validation techniques. These include the
traditional methods of simulation and emulation, as well as the emerging formal verification technologies. We will
summarize many of the university CAD tools that incorporate these ideas.
Specifically, the tutorial will cover the following topics: Computational models for designs, State-of-the-art
simulation techniques, Emulation technology, Formal equivalence of combinational and sequential gate and
RTL level designs, Formal property verification using model checking, language containment, symbolic
trajectory evaluation and theorem proving. Techniques for advancing the frontiers of verification ranging from
approximation techniques to combining formal verification with simulation for better coverage. Theory will be
reinforced by practice through the use of software demonstrations of public domain tools. Emphasis will be
placed on techniques which can handle large scale designs.
35
Tutorial
Two
riday, june 19
Room 302
Tutorial
Three
36
Room 303
f
Tutorial
Four
riday, june 19
Room 304
37
f
Tutorial
Five
riday, june 19
Room 301
38
f
Tutorial
Six
riday, june 19
Room 306
39
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birds-of-a-feather
DAC will provide conference rooms for informal groups to discuss items of common technical interest.
These very informal non-commercial meetings, held after hours, are referred to as Birds-of-a-Feather.
verilog-AMS
Verilog supports digital event driven simulation. Verilog-A describes analog continuous time
behavior. Verilog-AMS supports mixed-signal hardware description and simulation by specifying how
analog and digital descriptions may be combined and how the analog and digital domains interact.
A summary of the latest version of the Language Reference Manual for Verilog-AMS will be
presented by a member of the OVI technical subcommittee working group. Examples of mixed
signal hardware descriptions will be shown.
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additional meetings
Ph.D forum at DAC - follow-up session
Organizers: Soha Hassoun - Tufts Univ., Medford, MA
Oliver Coudert - Synopsys, Inc., Mountain View, CA
This session will feature a few parallel tracks. In each track, a number of students will present to
academic and industrial researchers a 20-minute overview of their Ph.D thesis work. The goal is to
provide students with detailed feedback on their work. Invitations will be issued at the open poster
session during the SIGDA member meeting, Tuesday, June 16, 7:00PM - 9:00PM. For more
information about the Ph.D Forum at DAC, please visit:
http://www.cs.washington.edu/homes/soha/forum/
CANDE meeting
Wednesday, June 17, 6:00-7:30PM, in room Pacific H, on the 4th floor, at the Marriott hotel.
41
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proceedings
ACM/SIGDA (Association for Computing Machinery/Special Interest Group on Design
Automation) and the Design Automation Conference will jointly publish the proceedings of
DAC98 on CD-ROM. Papers can be accessed using Adobe Acrobat Reader 3.0 (included on
the CD-ROM) or through an HTML browser and PostScript viewer (furnished by the user).
DAC Proceedings will also be available on the World Wide Web after the conference.
A compendium CD-ROM, containing the conference proceedings from the previous year, is
published annually, beginning with Compendium94 (containing DAC, EURO-DAC and ICCAD).
Compendium96 contains ED&TC96, DAC96, EURO-DAC96, ICCAD96, and proceedings from
three symposia (FPGA96, ISLPED96, ISSS96). Compendium97 contains ASP-DAC97
ED&TC97, DAC97, ICCAD97 and proceedings from four symposia (FPGA97, ISLPED97 and
ISPD97, ISSS97.)
SIGDA conference proceedings on CD-ROM and Compendium CD-ROMs are available from
ACM. Stop by the ACM booth for further information.
42
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The lure of historic San Francisco has attracted thousands of visitors every year to experience the
unique charm and beauty of this City by the Bay. No other city in the world can boast of the variety
of attractions that makes San Francisco famous.
By simply crossing a street, you can leave Hong Kong and visit Naples, Chinatown, North Beach,
Japantown, Pacific Heights, and The Mission District all offering enough cultural variety that you will
feel like youve traveled around the world instead of around the city.
Of course there is always the Golden Gate Bridge, Lombard Street, Alcatraz, Fishermans Wharf, Coit
Tower, the Cable Cars and a few hundred other famous attractions to keep you occupied. The Wine
Country (Napa and Sonoma) is only a short drive and Sausalito is an enjoyable ferry ride across the
Bay. If you still have the time and energy, San Francisco provides some of the finest dining and
shopping to be found anywhere. You will find this city a treat for every member of your family.
DAC
DAC
DAC
DAC
DAC
guest/family program
A $45 registration fee will admit each guest or family member to the following:
1.Tuesday night Cocktail Party in the Yerba Buena Ballroom at the San Francisco Marriott.
2. Wednesday night 35 Years of DAC Anniversary Party in the Yerba Buena Ballroom at the
San Francisco Marriott.
3.Use of the complimentary shuttle bus services between all DAC participating hotels and the
Moscone Center.
4. Admission to the exhibit hall when accompanied by an attendee.
REGISTRATION for the Guest/Family Program will be at the Conference Registration desk on Sunday,
June 14 through Wednesday, June 17. A badge will be provided for each registered guest or family
member. This badge must be worn to participate in the above activities. Look for the Guest
Registration sign in the registration area. Children under the age of 14 are not allowed in the
exhibit hall.
43
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busing
rental cars - DAC is not recommending the use of rental cars or cars in general this year due
to the limited space and prohibitive cost of parking in San Francisco. DAC encourages attendees
to leave their cars at home and utilize the excellent transportation system available in San
Francisco and the Bay Area.
busing - Complimentary shuttle bus service is provided by the Design Automation Conference
(DAC) for all registered conference attendees, exhibitors and guest program participants.
conference shuttle bus service - Day & Evening Route busing will be provided to and
from the Moscone Center and all appropriate participating DAC Hotels. Hours will be extended to
accommodate the DAC Demo Suite attendees.
wednesday night party - At 7:00 PM Wednesday night the buses will run from all
appropriate participating hotels to the San Francisco Marriott until 12:00 midnight.
Day route schedule (pick-up every 20 minutes)
Sunday, June 14
Monday, June 15
Tuesday, June 16
Wednesday, June 17
Thursday, June 18
3:45
7:45
7:45
7:15
7:15
PM
AM
AM
AM
AM
6:30 PM
10:00 PM
10:00 PM
12:00 AM
6:30 PM
Drop-Off/Pick-Up
Hilton, Taylor Street
Hilton, Taylor Street
Hilton, Taylor Street
Hilton, Taylor Street
Hilton, Taylor Street
Westin St. Francis, Post
Westin St. Francis, Post
Westin St. Francis, Post
Westin St. Francis, Post
Westin St. Francis, Post
Cyril Magnin
Cyril Magnin
Route B
Grand Hyatt Union Square
Drop-Off/Pick-Up
Stockton Street
Route C
CALTRAIN Train Station
Holiday Inn Civic Center
* Indicates boarding location
Drop-Off/Pick-Up
4th & Townsend
8th
St.
St.
St.
St.
St.
Pickwick Hotel
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45
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topics of interest
Authors are invited to submit original technical papers describing recent and novel research or engineering developments
in all areas of design automation. The DESIGN TOOLS TRACK (T) is devoted to contributions to the research and
development of design tools and the supporting algorithms. The DESIGN METHODS TRACK (M) deals with contributions
to the research and development of design methodologies and applications of design automation tools to designs. Topics
of interest include, but are not limited to:
ac
awards
Michael Lightner
University of Colorado
Jeffrey S. Salowe
Cadence Design Systems, Inc.
DAC $4K: Bryan Neil Ramirez, Crook, CO - attending Colorado School of Mines
DAC $4K: Christine Joyce Mina, Minot, MA - attending Worcester Polytechnic Institute
DAC $4K: Diala William Abboud, Charlotte, NC - attending Univ. of N. Carolina at Charlotte
ac
sponsorship
The 35th Design Automation Conference is sponsored by the ACM/SIGDA (Association for Computing
Machinery/Special Interest Group on Design Automation), IEEE/CAS (Institute of Electrical and
Electronics Engineers/Circuits and Systems Society) and EDAC (Electronic Design Automation
Consortium). Membership information is available at the ACM and IEEE booth.
EDA Consortium
The EDA Consortium is an international association of companies engaged in the development,
manufacture and sale of electronic design automation tools to the electronics engineering
community. Its goal is to promote the EDA industry by increasing awareness of the value of EDA tool
usage and by addressing industry-wide issues.
In addition, the EDA Consortium offers benefits such as:
Maintains a centralized website for all member companies
Develops standardized contracts for EDA tools sales, thereby reducing negotiation time
Drives EDA standards through coordination and implementation
Addresses issues specific to non-US EDA companies
Sponsors and represents the interests of EDA companies at the DAC and DATE (Europe)
conferences
Offers a 10% discount on booth and suites at DAC
Reports on EDA market statistics for market share, industry trends and business forecasts
Bestows the Design Achievement Awards to recognize outstanding integrated circuit and
electronic system development through the use of EDA tools
Sponsors the Phil Kaufman Award to honor individuals for their exceptional innovative
contributions to design tool technology
For more information, contact the EDA Consortium 111 West Saint John Street, Suite 200 San
Jose, CA 95113, USA. Phone: 408-287-3322 email: info@edac.org http://www.edac.org.
49
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sponsorship
ACM / SIGDA
ACM, the Association for Computing Machinery, is an international scientific and educational
organization dedicated to advancing the arts, sciences, and applications of information
technology. With a worldwide membership of 80,000, ACM functions as a focus for computing
professionals and students working in the various fields of Information Technology. ACM
publishes and distributes books, magazines, and peer reviewed journals targeted to particular
computing fields, as well as the monthly magazine Communications of the ACM, the most cited
publication in computing. In late 1997 ACM launched its Digital Library, an invaluable online
resource of over 200,000 fully searchable pages of text from ACM's high quality journals and
proceedings dating back to 1991.
ACM has 37 Special Interest Groups that focus on different computing disciplines. More than half
of all ACM members join one or more of these Special Interest Groups. The SIGs publish
newsletters and sponsor important conferences such as SIGGRAPH, DAC, OOPSLA and CHI, giving
members opportunities to meet experts in their fields of interest and network with other
knowledgeable members.
Become an ACM member today and join thousands of other leading professionals, researchers
and academics who are benefiting from all ACM has to offer.
For further information, visit ACM on the web at http://www.acm.org/.
IEEE
The IEEE Circuits and Systems Society (CAS) is one of the largest societies within IEEE and in the
world devoted to the analysis, design, and applications of circuits, networks, and systems. Its
publication activities span over five archival journals, namely the IEEE Trans. on CAS-Part I
(Fundamentals); Part II (Analog and Digital Signal Processing); Trans. on CAD; Trans. on VLSI; and
Trans. on CAS for Video Technology. A newly formatted Newsletter provides the membership with
short articles on emerging technologies, such as wireless, mixed-mode IC design, and
hardware/software co-design. Also, the Society is cosponsoring with the SP-S, COM-S, and C-S a
new Trans. on Multimedia, expected to appear in early 1999. This periodicals activity of the highest
quality is supplemented by a number of international conferences, sponsored or co-sponsored by
the Society, which include ISCAS, ICCAD, and DAC. A worldwide comprehensive program of
advanced workshops and continuing education short courses, brings to the membership in various
regions the latest developments in cutting-edge technologies of interest to industry and academia
alike. Worthy of special note are the 1st CAS Workshop on Wireless-Communication Circuits &
Systems, to be held in Zurich on June 22-24, 1998 and the CAS 2nd International Workshop on
Design of Mixed-Mode Integrated Circuits and Applications to be held in Guanajuato, Mexico on July
27-29, 1998. For more information please contact the IEEE CAS Society.
50
Phone: 1-219-871-0210
E-mail: b.wehner@ieee.org
Web: http://www.ieee-cas.org
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TECHNICAL PROGRAM
CO-CHAIR, DESIGN METHODS
Jan M. Rabaey
Univ. of California
Dept. of EECS
511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
jan@eecs.berkeley.edu
Anders Forsen
Ericsson Radio Systems AB
RCUR-T/N, Kista
Stockholm, S-16480 Sweden
(46) 8-7572-541
anders.forsen@era.ericsson.se
David Ku
Escalade Corp.
2575 Augustine Dr.
Santa Clara, CA 95054
(408) 654-1617
ku@escalade.com
Patrick Groeneveld
Magma Design Automation
1025A Terra Bella Ave.
Mountain View, CA 94043
(415) 938-6970
patrick@magma-da.com
Andreas Kuehlmann
IBM Corp.
T.J. Watson Research Ctr.
P.O. Box 218
Yorktown Heights, NY 10598
(914) 945-3458
kuehl@watson.ibm.com
Rajesh K. Gupta
Univ. of California
444 Computer Science, 208B IREF
Irvine, CA 92697
(714) 824-8052
gupta@uci.edu
Luciano Lavagno
Cadence Design Systems, Inc.
2001 Addison St., 3rd Fl.
Berkeley, CA 94704-1103
(510) 647-2810
luciano@cadence.com
Randolph E. Harr
Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA 94043-4033
(415) 694-1927
rharr@synopsys.com
Sharad Malik
Princeton Univ.
Dept. of EE
Princeton, NJ 08544
(609) 258-4625
sharad@ee.princeton.edu
TingTing Hwang
Tsing Hua Univ.
Dept. of Computer Science
Hsin-Chu, 30043 Taiwan ROC
(886) 35-715-131
tingting@cs.nthu.edu.tw
Alan Mantooth
Analogy, Inc.
9205 SW Gemini Dr.
Beaverton, OR 97075-1669
(503) 626-9700
alan@analogy.com
Takahide Inoue
Sony Corp.
530 Cottonwood Dr.
Milpitas, CA 95035
(408) 955-4279
inoue@itc.sca.sony.com
Teresa Meng
Stanford Univ.
Gates Computer Science
Bldg. 301
Stanford, CA 94028
(415) 725-3636
meng@mojave.stanford.edu
Andrew B. Kahng
Univ. of California
Dept. of CS, 3713 Boelter Hall
Los Angeles, CA 90024-1596
(310) 206-7073
abk@cs.ucla.edu
Timothy Y. Kam
Intel Corp.
Strategic CAD Labs., JFT-102
5200 NE Elam Young Pkwy.
Hillsboro, OR 97124-6497
(503) 264-7536
tkam@ichips.intel.com
Mike Murray
Acuson
1220 Charleston Rd.
MS L-1, Box 7393
Mountain View, CA 94039
(415) 694-5876
mikem@acuson.com
Farid N. Najm
Univ. of Illinois
1308 W. Main St.
Urbana, IL 61801
(217) 333-7678
najm@uiuc.edu
51
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Kunle Olukotun
Stanford Univ.
Gates Computer Science
Gates 3A, Rm. 302
Stanford, CA 94305-9030
(415) 725 3713
kunle@ogun.stanford.edu
Louis Scheffer
Cadence Design Systems, Inc.
555 River Oaks Pkwy.
Bldg. 2, MS 2B1
San Jose, CA 95134
(408) 944-7114
lou@cadence.com
Kazutoshi Wakabayashi
NEC Corp.
C&C Research Labs.
4-1-1 Miyazaki
Kawasaki, 216 Japan
(81) 44-856-2134
wakaba@sbl.cl.nec.co.jp
Hidetoshi Onodera
Kyoto Univ.
Dept. of Electronics & Comm.
Sakyo-ku
Kyoto, 606-01 Japan
(81) 75-753-5314
onodera@kuee.kyoto-u.ac.jp
Sunil D. Sherlekar
Silicon Automation Systems
3008, 12th B Main, 8th Cross
HAL 2nd Stage, Indiranagar
Bangalore, 560008 India
(91) 80-528-1461
sds@sasi.com
Neil Weste
Macquarie Univ.
Electronics Dept.
Sydney, 2109 Australia
(61) 2-850-9149
new@mpce.mq.edu.au
Janusz Rajski
Mentor Graphics Corp.
8005 SW Boeckman Rd.
Wilsonville, OR 97070-7777
(503) 685-4797
rajski@wv.mentorg.com
Richard Smith
Cadence Design Systems, Inc.
5215 N. O'Connor Rd., Ste. 1000
Irving, TX 75039
(972) 889-0033
dsmith@cadence.com
James A. Rowson
Alta Group of
Cadence Design Systems, Inc.
555 N. Matilda Ave.
Sunnyvale, CA 94086
(408) 523-4157
jimr@altagroup.com
Vivek Tiwari
Intel Corp.
2200 Mission College Blvd.
MS-RN 5-09
Santa Clara, CA 95052-8119
(408) 765-0589
vivek_tiwari@ccm.sc.intel.com
Andrew T. Yang
Univ. of Washington
Dept. of EE, FT-10
Seattle, WA 98195
(206) 543-2932
atyang@uwcad.ee.washington.edu
Kenji Yoshida
Toshiba Corp.
580-1 Horikawa-Cho Saiwai-ku
Kawasaki, 210 Japan
(81) 44 548 2400
kyoshida@eecvun.eec.toshiba.co.jp
Yervant Zorian
LogicVision, Inc.
101 Metro Dr., Third Fl.
San Jose, CA 95110
(408) 453-0146
zorian@lvision.com
panel sub-committee
Nanette Collins
Consultant
37 Symphony Rd., Unit A
Boston, MA 02115
(617) 437-1822
nanette@nvc.com
Takahide Inoue
Sony Corp.
530 Cottonwood Dr.
Milpitas, CA 95035
(408) 955-4279
inoue@itc.sca.sony.com
Andrew B. Kahng
Univ. of California
Dept. of CS, 3713 Boelter Hall
Los Angeles, CA 90024-1596
(310) 206-7073
abk@cs.ucla.edu
Mike Murray
Acuson
1220 Charleston Rd.
MS L-1, Box 7393
Mountain View, CA 94039
(415) 694-5876
mikem@acuson.com
Ivo Bolsens
IMEC
VSDM, Kapeldreef 75
Leuven, BE B-3001 Belgium
(32) 16-281-211
bolsens@imec.be
Mary Jane Irwin
Penn State Univ.
Dept. of CS and Engr.
220 Pond Lab.
University Park, PA
16802-6106
(814) 865-1802
mji@cse.psu.edu
Teresa Meng
Stanford Univ.
Gates Computer Science
Bldg. 301
Stanford, CA 94028
(415) 725-3636
meng@mojave.stanford.edu
Vivek Tiwari
Intel Corp.
2200 Mission College Blvd.
MS-RN 5-09
Santa Clara, CA 95052-8119
(408) 765-0589
vivek_tiwari@ccm.sc.intel.com
ac
VICE CHAIR
Mary Jane Irwin
Penn State Univ.
Dept. of CS and Engr.
220 Pond Lab.
University Park, PA
16802-6106
(814) 865-1802
mji@cse.psu.edu
FINANCE CHAIR
Giovanni De Micheli
Stanford Univ.
Gates Computer
Science Bldg.
Rm. 333
Stanford, CA 94305-9030
(650) 725-3632
nanni@galileo.stanford.edu
TECHNICAL PROGRAM
CO-CHAIR, DESIGN TOOLS
Randal E. Bryant
Carnegie Mellon Univ.
School of CS
Pittsburgh, PA 15213
(412) 268-8821
randy.bryant@cs.cmu.edu
TECHNICAL PROGRAM
CO-CHAIR, DESIGN METHODS
Jan M. Rabaey
Univ. of California
Dept. of EECS
511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
jan@eecs.berkeley.edu
ELECTRONIC MEDIA
CHAIR
Michael Lorenzetti
Mentor Graphics Corp.
8005 SW Boeckman Rd.
Wilsonville, OR 97070-7777
(503) 685-0740
mike_lorenzetti@mentorg.com
TUTORIAL CHAIR
Antun Domic
Synopsys, Inc.
700 E. Middlefield Rd.
Mountain View, CA 940434033
(650) 943-5088
domic@synopsys.com
PUBLICITY CHAIR
Abbie Kendall
OrCAD
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
abbie@orcad.com
ELECTRONIC SYSTEMS
INDUSTRY CHAIR
Bryan D. Ackland
Lucent Technologies
101 Crawfords Corners Rd.
Rm. 4E-508
Holmdel, NJ 07733-1900
(732) 949-7248
bda@lucent.com
PAST CHAIR
Ellen J. Yoffa
IBM Corp.
T.J. Watson Research Ctr.
Rm. 33-109, P.O. Box 218
Yorktown Heights, NY
10598
(914) 945-3270
yoffa@watson.ibm.com
EUROPE/MIDDLE EAST
REPRESENTATIVE
Gerry Musgrave
Brunel Univ.
Dept. of EEE
Uxbridge, UB8 3PH, UK
(44) 1-895-203-251
gerry.musgrave@
brunel.ac.uk
ASIA/INDIA/S. PACIFIC
REPRESENTATIVE
Fumiyasu Hirose
Fujitsu Labs. Ltd.
CAD Lab.
4-1-1 Kamikodanaka
Nakahara-ku
Kawasaki 211, Japan
(81) 44-754-2663
hirose@flab.fujitsu.co.jp
ACM REPRESENTATIVE
James Cohoon
Univ. of Virginia
Dept. of Computer Science
Olsson Hall
Charlottesville, VA 22903
(804) 982-2210
cohoon@virginia.edu
IEEE-CAS REPRESENTATIVE
Michael Lightner
Univ. of Colorado
Dept. of ECE
Campus Box 425
Boulder, CO 80309-0425
(303) 492-5180
lightner@boulder.colorado.edu
EDAC REPRESENTATIVE
Lorie Bowlby
111 W. St. John St.
Ste. 200
San Jose, CA 95123-1104
(408) 226-7240
lorieb@pacbell.net
EXHIBIT MANAGER
Marie R. Pistilli
MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
(303) 530-4562
marie@dac.com
CONFERENCE MANAGER
P.O. Pistilli
MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
(303) 530-4562
pat@dac.com
53
Moscone
Center
Floorplan
54
Moscone
Center
Floorplan
55
Exhibit Floor
Center Map
56
Exhibit Floor
Center Map
57
Exhibit Floor
Center Map
PG 104
58
ACTEL CORP.
ADVANCED RISC MACHINES (ARM)
ALBA CENTRE (THE)
ALPINE MICROSYSTEMS INC.
AMERICAN MICROSYSTEMS, INC.
CHIP EXPRESS CORP.
COREEL MICROSYSTEMS
CYPRESS SEMICONDUCTOR
DESIGN AND REUSE
IBM CORP.
INICORE
INTEGRATED SILICON SYSTEMS LTD.
LATTICE SEMICONDUCTOR CORP.
LIGHTSPEED SEMICONDUCTOR
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, FPGA
LUCENT TECHNOLOGIES, MICROELECTRONICS GROUP, PSS
NEWPORT WAFER-FAB LTD.
PHILIPS SEMICONDUCTORS
PIVOTAL TECHNOLOGIES, INC.
QUICKLOGIC CORP.
RAPID
SEMICONDUCTORES INVESTIGATION Y DISENO (SIDSA)
SIERRA RESEARCH & TECHNOLOGY, INC.
SILICON STRATEGIES
SIMPLE SILICON INC.
TEXAS INSTRUMENTS
TOWER SEMICONDUCTOR LTD.
UNITED MICROELECTRONICS CORP. GROUP
VAUTOMATION INC.
WESTERN DESIGN CENTER, INC. (THE)
XILINX, INC.
SV18
SV28
SV2
SV26
SV27
SV32
SV23
SV38
SV11
SV1
SV15
SV14
SV39
SV8
SV5
SV6
SV12
SV21
SV16
SV22
SV4
SV37
SV36
SV13
SV17
SV25
SV31
SV10
SV20
SV35
SV19
Pacific
Numerix Ad
System
Science Ad
exhibitor listing
ac
The Design Automation Conference continues to combine its outstanding technical program with exhibits
featuring over 200 of the worlds top CAD/CAE companies. Exhibits are located in Halls A, B and C, and room
104 of the Moscone Center. We are pleased to have the following exhibitors this year.
COMPANY NAME
sv
sv
All Companies
in BOLD are
NEW DAC
Exhibitors
sv
sv
sv
sv
denotes
silicon
village
exhibitor
sv
sv
Children under 14
will not be allowed
in the Exhibit Hall.
sv
sv
BOOTH #
sv
sv
sv
sv
sv
COMPANY NAME
BOOTH #
DESIGNSOFT
15
DUET TECHNOLOGIES
1418
DYNACHIP CORP.
21
ECN MAGAZINE/EITD
1538
EDA STANDARDS
438
EE TIMES/EDTN/CMP MEDIA
1518
ELECTRONIC TOOLS CO.
1934
ENGINEERING DATAXPRESS, INC.
825
EONIC SYSTEMS INC.
754
ESCALADE CORP.
128
ESPERAN
252
EVEREST DESIGN AUTOMATION
2538
EXEMPLAR LOGIC
318
FINTRONIC USA, INC.
1524
FORMALIZED DESIGN INC.
78
FREQUENCY TECHNOLOGY, INC.
2200
FRONTIER DESIGN
62
FTL SYSTEMS, INC.
256
FUJITSU/ICL
328
GAMBIT AUTOMATED DESIGN, INC.
544
GATEFIELD CORP.
908
GDA TECHNOLOGIES, INC.
2532
GENESYS TESTWARE
1154
GENIAS SOFTWARE GMBH
154
GLOBETROTTER SOFTWARE, INC.
139
HEWLETT - PACKARD CO.
1530
HYPERLYNX
632
IBM CORP.
1318
IBM CORP.
SV1
IKOS SYSTEMS INC.
1328
INCASES NORTH AMERICA
636
INFOQUICK
88
INICORE
SV15
INTEGRATED INTELLECTUAL PROPERTY INC.
656
INTEGRATED SILICON SYSTEMS LTD.
SV14
INTEGRATED SYSTEM DESIGN
1050
INTELLITECH CORP.
1350
INTELLX
956
INTERACTIVE IMAGE TECHNOLOGIES LTD.
1930
INTERCEPT TECHNOLOGY INC.
1752
INTERHDL, INC.
1918
INTL COMPUTEX INC./INFO. HANDLING SERVICES
64
INTERRA, INC.
1546
INTRINSIX CORP.
2528
INTUSOFT
141
K2 TECHNOLOGIES/SHEARWATER GROUP
2308
KLUWER ACADEMIC PUBLISHERS
926
LATTICE SEMICONDUCTOR CORP.
SV39
LEDA SA
445
LEGEND DESIGN TECHNOLOGY, INC.
752
LIBRARY TECHNOLOGIES, INC.
2150
LIGHTSPEED SEMICONDUCTOR
1156
LIGHTSPEED SEMICONDUCTOR
SV8
LINIUS TECHNOLOGIES
444
LOGICVISION, INC.
218
LSI LOGIC CORP.
536
61
ac
COMPANY NAME
sv
sv
All Companies
in BOLD are
NEW DAC
Exhibitors
sv
sv
sv
sv
sv
sv
denotes
silicon
village
exhibitor
sv
sv
Children under 14
will not be allowed
in the Exhibit Hall.
62
sv
sv
BOOTH #
1008
SV5
SV6
1108
348
93
1824
1830
2530
552
22
2030
SV12
23
1850
96
16
2034
530
1540
338
1522
1018
228
630
20
822
SV21
1846
936
SV16
1700
827
451
84
736
SV22
2108
SV4
448
2000
452
518
1450
2546
349
SV37
208
1622
1654
453
SV36
108
68
918
SV13
1730
127
SV17
644
COMPANY NAME
sv
sv
sv
sv
sv
sv
SIMPOD, INC.
SIMUCAD, INC.
SIMUTEST, INC.
SNAKETECH
SPECTRA LOGIC
STANZA SYSTEMS, INC.
SUMMIT DESIGN, INC.
SUN MICROSYSTEMS
SYCON DESIGN, INC.
SYNAPTICAD INC.
SYNCHRONICITY INC.
SYNOPSYS, INC.
SYNPLICITY, INC.
SYNTEST TECHNOLOGIES, INC.
SYNTYX TECHNOLOGY
SYSTEMS SCIENCE, INC.
TANNER EDA
TAU SIMULATION INC.
TEMENTO SYSTEMS
TERA SYSTEMS, INC.
TERADYNE, INC.
TEXAS INSTRUMENTS
TIMBERWOLF SYSTEMS, INC.
TIME-ROVER INC.
TOPDOWN DESIGN SOLUTIONS, INC.
TOWER SEMICONDUCTOR LTD.
TRANSCENDENT DESIGN TECHNOLOGY, INC.
TRANSEDA, INC.
TRANSLOGIC USA CORP.
TSA
TSSI
ULTIMA INTERCONNECT TECHNOLOGY
UNIFIED DESIGN AUTOMATION, INC.
UNITED MICROELECTRONICS CORP. GROUP
UNIVERSITY BOOTH
VALOR COMPUTERIZED SYSTEMS
VAMP, INC.
VANTIS
VAUTOMATION INC.
VERIBEST, INC.
VERISITY DESIGN, INC.
VERITOOLS, INC.
VERPLEX SYSTEMS, INC.
VERYSYS DESIGN AUTOMATION, INC.
VIEWLOGIC SYSTEMS, INC.
VIRAGE LOGIC
VIRTUAL SILICON TECHNOLOGY, INC.
VSI ALLIANCE
WESTERN DESIGN CENTER, INC. (THE)
X-TEK CORP.
XENTEC INC.
XILINX, INC.
XILINX, INC.
XYNETIX DESIGN SYSTEMS, INC.
YOKOGAWA ELECTRIC CORP.
ZUKEN-REDAC, INC.
ZYCAD TSS CORP.
BOOTH #
2534
1122
1624
1054
1118
19
1808
618
950
90
1800
2130
1742
1646
91
1218
1600
11
94
145
152
SV25
824
13
2350
SV31
86
233
2518
925
2300
144
850
SV10
830
24
87
236
SV20
608
600
1818
151
100
1428
244
1354
115
SV35
2522
153
508
SV19
730
2052
308
77
interHDL Ad
1/2 page
Silicon
Village
1/2 page
Ad
Electronic
Tools
onday, june 15
Time
Rm 102
exhibitor presentations
Rm 103
Rm 301
Rm 304
11:00
11:20
TEMENTO SYSTEMS
ORCAD
CADABRA
11:40
LEDA SA
EXEMPLAR
LOGIC, INC.
EONIC
SYSTEMS INC.
Rm 102
Rm 103
9:00
9:20
9:40
10:00
10:20
10:40
IBM CORP.
GATEFIELD CORP.
INTERHDL, INC.
FREQUENCY
TECHNOLOGY, INC.
VIEWLOGIC
SYSTEMS, INC.
MINC/SYNARIO
Rm 306
PLATFORM
COMPUTING CORP.
XYNETIX DESIGN
SYSTEMS, INC.
ULTIMA
INTERCONNECT
SENTE INC.
CHRYSALIS
SYMBOLIC DESIGN
YOKAGAWA
ELECTRIC CORP.
SYSTEMS
SCIENCE, INC.
VERITOOLS, INC.
VAUTOMATION INC.
EVEREST DESIGN
AUTOMATION
LINIUS
TECHNOLOGIES
0-IN DESIGN
AUTOMATION
TANNER EDA
Rm 305
Rm 306
ATG TECHNOLOGY
3:40
SILVACO
INTERNATIONAL
OMNIVIEW DESIGN,
INC.
LEGEND DESIGN
TECHNOLOGY, INC.
DERIVATION
SYSTEMS, INC.
K2 TECH./
SHEARWATER
4:00
4:20
CAST, INC.
4:40
ALTERA CORP.
5:00
SNAKETECH
5:20
INTRINSIX CORP.
5:40
NU THENA
SYSTEMS, INC.
6:00
MOSCAPE INC.
2:20
2:40
3:00
3:20
Rm 301
Rm 304
CADENCE DESIGN
ARCADIA DESIGN
GENESYS
SUMMIT DESIGN,
APTIX CORP.
SYSTEMS, INC.
SYSTEMS, INC.
TESTWARE
INC.
SILICON INTEGRATION
SEVA
PADS SOFTWARE,
ESPERAN
DYNACHIP CORP.
INITIATIVE, INC. (Si2) TECHNOLOGIES, INC.
INC.
AMBIT DESIGN
TIMBERWOLF
VERYSYS DESIGN
MODEL
SIMUCAD, INC.
SYSTEMS, INC.
SYSTEMS, INC.
AUTOMATION, INC.
TECHNOLOGY, INC.
OPTEM
CAD-MIGOS
CHRONOLOGY
SYNOPSYS, INC.
TRANSEDA, INC.
ENGINEERING INC.
SOFTWARE TOOLS
CORP.
SIMPLEX
NOVAS SOFTWARE,
CYPRESS
HYPERLYNX
SAPIEN DESIGN
SOLUTIONS, INC.
INC.
SEMICONDUCTOR
SILICON VALLEY
ARTISAN
INTERCEPT
SIDSA
ANSOFT CORP.
RESEARCH, INC.
COMPONENTS, INC.
TECHNOLOGY INC.
COMPAQ COMPUTER VERISITY DESIGN,
FINTRONIC USA, INC. LOGICVISION, INC.
FUJITSU/ICL
CORP.
INC.
OEA INTERNATIONAL, TOPDOWN DESIGN
GLOBETROTTER
ABSTRACT INC.
AXIS SYSTEMS
INC.
SOLUTIONS, INC.
SOFTWARE, INC.
LIBRARY
GAMBIT AUTOMATED
ACCEL
ANALOGY, INC.
OPMAXX, INC.
TECHNOLOGIES, INC.
DESIGN, INC.
TECHNOLOGIES, INC.
SUN
INTEG. INTELL.
CIRCUIT
INTERRA, INC.
QUICKLOGIC CORP.
MICROSYSTEMS
PROPERTY INC.
SEMANTICS, INC.
CHIP EXPRESS
VERIBEST, INC.
EDA STANDARDS
SIMPOD, INC.
IKOS SYSTEMS INC.
CORP.
VIRTUAL SILICON
ALTERNATIVE SYS.
SAGANTEC
INTELLITECH CORP.
SPECTRA LOGIC
TECHNOLOGY, INC.
CONCEPTS, INC.
ARISTO
SAND M I C R O TOWER
TRANSLOGIC
COWARE, INC.
TECHNOLOGY
ELECTRONICS, INC.
SEMICONDUCTOR
USA CORP.
These 20-minute presentations by DAC Exhibitors are intended to efficiently introduce you to new product and application information.
Badges are not required for admission to the Exhibitor Presentations.
65
Advance
Tech. Ad
m
9:00
am
onday
exhibitor presentations
Virage Logic
rm. 102
Learn how to rapidly design high quality embedded memories and integrate them into a system on
chip. A new generation of memory compilers create highly optimized low power and high speed
memories, taking full advantage of deep submicron design.
Quickturn Design Systems, Inc.
rm. 103
Quickturn, the leader in design verification, unveils its newest products suite aimed at complex chips
and systems resulting from deep submicron and system-on-chip. These products are based on the
latest emulation and simulation technology, offering unprecedented performance and ease-of-use.
Applied Simulation Technology
rm. 301
Applied Simulation Technology offers leading edge software solutions for high speed digital and analog
circuits and systems. Parasitic extraction and simulation of the physical interconnects for Signal
Integrity and EMI analysis is the company focus.
Morphologic, Inc.
rm. 304
Morphologic will demonstrate Evolution: a multi-device, multi-vendor FPGA design tool set. See how
Evolutions combination of requirements tracking, floorplanning, and data base management yield
deterministic, repeatable results that set the stage for a complete route on the first pass.
IBM Corp.
rm. 305
Exciting solutions ranging from IBM Blue Logic technology to Deep Blue to e-commerce will give you a
competitive advantage.
Platform Computing Corp.
rm. 306
9:20
am
LSF enables design and simulation engineers to fully utilize their computing resources to significantly
shorten design cycles, reduce time to market, and improve product quality by completing more design
iterations in less time. Platforms LSF Suite has helped design engineers derive maximum advantage
from distributed computing environments.
Advanced Technology Center, CoverMeter Division
rm. 102
CoverMeter is a complete Verilog code coverage analysis tool that helps designers determine which
portions of application code have yet to be exercised in simulation test cases. CoverMeter offers
facilities to assure coverage of statements, conditions, toggles and state machines.
Lucent Technologies, Bell Labs Design Automation
rm. 103
Running out of time to verify your systems-on-silicon? We can help you glide through your next design
project with leading-edge standards-based tools and technologies supporting formal verification, mixedsignal design and DSM parasitic extraction. Look to us for solutions to your toughest verification problems.
Phoenix Technologies Ltd., Virtual Chips
rm. 301
At Phoenix our experience is your advantage. We now offer immediate availability on hundreds of
Virtual Components for 1394, USB, AGP, IrDA and PCI standards. Our silicon-proven synthesizable
cores, extensive verification environments, and firmware are 100% compliant with the standards and
backed by over 800 Phoenix employees worldwide.
67
onday
exhibitor presentations
Simutest, Inc.
rm. 304
Simutest presents WaveTools a simulation analysis and test program generation tool used to create
test benches and to display, edit, compare and analyze simulation vectors. WaveTools can also import
simulation vectors and automatically generate and verify test programs for test systems.
GateField Corp.
rm. 305
Looking for the ideal, reprogrammable ASIC solution? GateField is excited to introduce a paradigm
shift in programmable logic technology based on a .25 embedded FLASH process. GateFields
ProASIC capabilities enable reprogrammable system-on-a-chip solutions that set new
price/performance standards in the PLD market.
Xynetix Design Systems, Inc.
rm. 306
9:40
am
...getting signals in the GHz frequency range off-chip and into the system after packaging is perhaps
even greater than the challenge of on-chip performance. (SIARoadmap). Xynetix discusses tools and
techniques for IC packaging and PCB design to optimize overall system performance.
ACEO Technology, Inc.
rm. 102
See the most advanced ASIC design technology featuring One-Pass Hierarchical Synthesis for high
performance single pass synthesis with industry leading gate-count optimization and timing. The next
generation of ASIC design debuts with Layout Driven Synthesis for the most accurate interconnect
modeling.
Avant! Corp.
rm. 103
Avant! will present its newest additions to its suite of TCAD-to-ECAD solutions including, advances in
symbolic layout editing and top level routing, crosstalk analysis, VDSM place and route and its
Milkyway database.
ASPEC Technology, Inc.
rm. 301
Aspecs Semiconductor Intellectual Property (SIP) library services help accelerate design-to-fabrication
time for complex ICs. Aspec provides physical IP, design workflows, design automation tools and
design services to reduce the time and costs for bringing deep sub-micron designs to silicon
fabrication.
SES Inc.
rm. 304
The Intel Portable Simulation Initiative (PSI) is an Intel-led group of companies which share
performance models of components of Intel architecture servers. The PSI uses SES/workbench
technology. This presentation discusses the PSI and another initiative in the Fibre Channel community.
interHDL, Inc.
rm. 305
The leader in HDL analysis presents advanced verification capabilities such as: clock domain analysis,
asynchronous loop detection, power analysis, and code purification. Synopsys and interHDL partnering
to enable automatic verification and compliance to the Design Reuse Methodology as specified in the
Synopsys-Mentor Reuse Methodology Manual.
Ultima Interconnect Technology
rm. 306
To account for coupling noise and power net IR drop/rise, our already best-in-the-class delay calculator
integrated with newly introduced 3D net parasitic extractor provides a critical link in DSM cell-based
IC design flow.
68
m
10:00
am
onday
exhibitor presentations
rm. 102
SynTest provides high performance test and verification tools and services for improving ASIC quality.
Tools include the industrys fastest fault simulation (TurboFault), verify RTL testability analysis, scan
synthesis, ATPG, boundary scan, memory BIST and core test. Services combine these tools with
SynTest engineering, allowing for high level of quality and testability.
Design Acceleration
rm. 103
Discuss product line updates. DAI Signalscan DX, the highest performance/capacity waveform viewing
and source code debugging tool for digital/analog simulators; DAI Coverscan a Verilog verification
coverage analysis tool, DAI Comparescan, a rules-based analysis program, and DAI SST2 Database,
a high-performance simulation database with TurboCompression.
Lattice Semiconductor Corp.
rm. 301
Lattice Semiconductor Corporation, the leader in ISP technology, is driving design tools and CPLD
densities in excess of 1000 macrocells. The focus of this presentation is on high performance ispLSI
devices and Lattices complete ispHDL tools solution.
Tera Systems, Inc.
rm. 304
Tera Systems unveils TeraForm, the revolutionary RTL design-planning system that solves your deepsubmicron-IC timing convergence and complexity problems. TeraForm automates structured-ASIC
design, delivering the density and performance benefits of hierarchical, structured-custom chips while
maintaining the productivity and turn-around-time benefits of traditional ASIC design.
Frequency Technology, Inc.
rm. 305
Frequency Technology blends CAD tools and process physics to help you break the Interconnect
Barrier. Columbus Parasitic Extractor is unsurpassed in accuracy. Our, Interconnect Performance
Characterization service enhances accuracy by creating Verified Interconnect Performance
Parameters, VIPPs, which accurately predict the electrical behavior of interconnects.
Sente Inc.
rm. 306
10:20
am
Sente is the IC Power expert, with tools and consulting to identify power problems, and eliminate
them. Sente technology rapidly analyzes Architectural-level Verilog HDL or VHDL before synthesis and
produces accurate, detailed full-chip power estimates for deep submicron design.
Escalade Corp.
rm. 102
Escalade introduces an IP protection product, IP Guard, that provides unbreakable protection for
popular VHDL and Verilog simulators. IP Guard is the only multi-language input tool that generates
VHDL, Verilog, and C. It complements Escaladess DesignBook and DesignExplorer products to create
a complete IP authoring environment.
Xilinx, Inc.
rm. 103
There is only one answer to the digital design challenge: Software-enabled high-level design flows that yield
high-density, high-performance results for field programmable and ASIC devices. This software, integrated
with sub-micron silicon, is available today. Rich Sevcik will present an overview of the Xilinx solution.
Duet Technologies
rm. 301
Duet provides state-of-the-art semiconductor IP infrastructure components including high performance
IC physical libraries (standard cells, I/O cells, and memory compilers) and comprehensive IP services
including custom library development, library migration, EDA tool integration and validation, IP silicon
verification services, and system-on-chip test services.
69
onday
exhibitor presentations
rm. 304
Focus your attention on having DataXpress solve your interoperability needs. We provide solutions for
schematic, netlist, HDL, PCB/MCM layout design data, EDIF 2 0 0, 3 0 0, 4 0 0, Verilog, VHDL and
most EDA vendors. We offer data translators, translator development environments, conversion
services, outsourcing services, etc.
VIEWlogic Systems, Inc.
rm. 305
Focused on the Systems Designer, providing the industrys hottest engineering tools and solutions for
high-speed system design; system simulation and analog design; language-based FPGA design
environments; and Internet-based enterprise solutions for design re-use. Available on UNIX and NT.
Chrysalis Symbolic Design, Inc.
rm. 306
10:40
am
The Formal Design Company - Design VERIFYer is the industry standard formal equivalence
checking software. Design INSIGHT is the practical model checking solution for design engineers.
Chrysalis delivers a complete family of formal tools, in use by 75 customers at 100+ sites worldwide.
Denali Software, Inc.
rm. 102
With over 1000 licenses sold, Denali Software offers the industry-leading memory simulation solution for
authoring, publishing and verifying memory models of both discrete and embedded memory components.
Denali proudly announces its enhanced technology for verifying memory subsystems and controllers.
Mentor Graphics Corp.
rm. 103
Mentor Graphics is a technology leader in deep submicron design, providing the tools and
methodologies designers need to meet the challenges of system verification and intellectual property.
Synplicity, Inc.
rm. 301
Synplicity will discuss methodologies for high-density FPGA and CPLD design.
SICAN Microelectronics Corp.
rm. 304
Learn about SICANs latest DesignObjects and design service solutions. Synthesizable ASIC cores
combined with SICANs abundant and highly skilled engineering resources enable its customers to meet
todays market requirements and to focus scarce internal resources on areas of highest added-value.
MINC/Synario
rm. 305
MINC/Synario offers a complete line of schematic capture, logic synthesis, and simulation tools for
programmable logic and board design. This tightly integrated tool suite provides a complete design
environment for FPGAs, CPLDs, and PLDs. MINCs broad product line answers the needs of any budget
or environment.
Yokogawa Electric Corp.
rm. 306
11:00
am
70
VirtualICE is a hardware/software co-design tool that reduces development time and ASIC respins.
VirtualICE enables you to solve the problems across the boundaries of hardware and software. VMlink
(Verilog-MATLAB interface) provides new design methodology of digital signal processing system.
Synchronicity Inc.
rm. 102
Synchronicity delivers on the promise of better project management and design reuse with
ProjectSync, a web-based project issue tracking and communications infrastructure. Synchronicity
will present a description of this revolutionary new technology and how it can be used with
Synchronicitys DesignSync product to deliver design reuse infrastructures.
Synplicity, Inc. Ad
onday
exhibitor presentations
Zuken-Redac, Inc.
rm. 103
The challenges of time-to-market, quality expectation, and product complexity require alternative
approaches to electronic design. Through the provision of exciting new solutions, Zuken-Redac is
helping companies change the way they design, and bring innovative new products rapidly into the
market.
RUBICAD Corp.
rm. 301
LACE is the only IC Layout Conversion Environment that allows hierarchical layout migration for design
reuse in systems-on-a-chip in deep-submicron technologies.
Electronic Tools Co.
rm. 304
Learn about our IP exchange solutions. ETC provides solutions for schematic, netlist, PCB/MCM
design data. We use standards like EDIF, Verilog, VHDL, and GENCAM to provide smooth migration,
interoperability, archiving and IP transfer from CAD to CAD and CAD to CAM.
Systems Science, Inc.
rm. 305
INTRODUCING VERA-SV! System Science will present the latest verification and test solutions. VERASV is a powerful solution for complete system verification that offers automated stimulus generation
with dynamic coverage feedback, self-checking tests, and hardware and software coverification in a
single environment.
Veritools, Inc.
rm. 306
11:20
am
Veritools has the most powerful productivity tools in the world. Veritools waveform analysis program,
Undertow, views digital and analog simulation output from Verilog, TIMEMILL, POWERMILL, HSpice,
Anagram and a variety of VHDL simulators.
Temento Systems
rm. 102
Visit Temento Systems exhibit to hear about Diatem, the First ES Design and Test Platform on the
market. From DFT insertion to prototype debug you will learn during the presentation how to reduce
your test time and improve your design methodology.
OrCAD
rm. 103
Make your design process a competitive advantage with OrCAD. Join us for an overview on our new
9.0 Release of NT applications for Internet-enabled component information management; FPGA/CPLD
and PCB system design; analog and mixed-signal design; and PCB layout.
Cadabra
rm. 301
CADABRA provides physical synthesis tools to automate the transistor level layout of standard cell,
gate array cells, and IO cell libraries as well as full and semi-custom macros.
VAutomation Inc.
rm. 304
VAutomation, one of the first companies to recognize the need for re-usable IP when designing
complex ICs, provides synthesizable cores for popular microprocessors (e.g. 8086) and serial
communications controllers (e.g. USB). Its silicon-proven cores shorten development time and enable
system-on-chip integration.
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Rubicad Corp Ad
onday
exhibitor presentations
rm. 305
Come see how Toshiba, NEC, and Motorola are designing their next-generation embedded system-ona-chip ICs using CAE Plus Tools. RTL-accurate C models, automatically synthesized from CAE Plus
ArchGen tool, enable early functional and performance verification of control-intensive system ICs.
Everest Design Automation
rm. 306
11:40
am
Everest Design Automations first product, a gridless, hierarchical routing and floorplanning system,
is more than an order of magnitude faster than current gridless routers. An innovative approach
enables accurate pin assignment and over the block routing, reducing chip area and wire length.
LEDA SA
rm. 102
LEDA offers complete compilation and elaboration solutions for VHDL87/93. VHDL-AMS and Verilog,
and designer tools such as its new VHDL Programmable Design Rule Checker (Proton), a VHDL
source-to-source encryptor (Krypton), and a VHDL/Verilog Source and Library Manager (VHDL*Verilog
Design Studio).
Exemplar Logic
rm. 103
Spectrum blends the industries hottest design creation, simulation, synthesis and implementation
technology into a simple, seamless process designed to do the same job as you - design an FPGA or
ASIC. Come see What FlowTabs PowerTabs, DesignInsight, HDLIntegrator, and much more.
Eonic Systems Inc.
rm. 301
Rapid movement towards flexible, programmable RISC ASIC and DSP cores for embedded applications
means time to market is now dominated by software application development. Eonic Systems
presents the Virtuoso v4.0 real-time operating system (RTOS) and tool set employing innovative
SoftStealth technology to satisfy this challenge.
Linius Technologies
rm. 304
Specialists in wire harness design automation. EMbassy is a 3-D virtual prototyping environment for
correct-by-construction wire harness design and manufacture. EMbassy combines 2-D logical connectivity
and 3-D mechanical data using industry standard file formats, including EDIF, VRML, and IGES.
0-In Design Automation
rm. 305
0-Ins white-box verification zeros-in on corner cases where bugs like to hide. Its fast, efficient, and
extremely thoroughwithout design, testbench, or simulation changes. Find out how 0-In is turning
verification inside-out to find the worlds toughest bugs!
Tanner EDA
rm. 306
2:00
pm
74
Tanner EDA offers feature-rich, easy-to-use physical design and verification tools for analog and mixedsignal ICs. With Windows platforms at Windows prices you can afford to put a powerful tool suite
on the desk of every member of your design team.
ATG Technology
rm. 102
Presenting Designer Friendly Test. INTELLECT, the industrys most powerful sequential ATPG tool,
offers flexible and easy-to-use solutions for full, partial and no-scan design. Consistently outperforms
all others with higher coverage and simpler design integration. Technology, comparisons and results
will be discussed.
Escalade Ad
EE Times Ad
onday
exhibitor presentations
rm. 103
The rapid evolution to system-on-a-chip (SOC) is forcing the convergence of systems, IC, and mixedsignal design. Cadence Design Systems, Inc. will discuss its most recent product announcements in
each of these areas and the resulting impact on SOC methodologies.
Arcadia Design Systems, Inc.
rm. 301
Arcadia Design Systems presents Mustang Datapath Placement Engine with breakthrough technology
for increasing chip performance. An overview of Mustangs innovative approach to optimizing datapath
will be given. The presentation will describe how Mustang integrates into existing design flows and the
key features, functionality and benefits of Mustang.
Genesys Testware
rm. 304
Genesys Testware provides test solutions for systems on chip. TestCores provide BIST of embedded
memories (Memory BistCore), BIST of on-chip logic (Logic BistCore), and board testability and core
test integration (Boundary ScanCore). New features include self-test and repair of embedded DRAMs
and FIFOs.
Summit Design, Inc.
rm. 305
Summit Design will discuss an extensive range of HDL-based solutions for verification, analysis, legacy
code reuse and capture. Supporting ASSP, ASIC and FPGA methodologies, Summits products include
Code Coverage, HW/SW Co-verification, Graphical Capture/Reuse, Legacy Code Management, and
Behavioral Synthesis.
Aptix Corp.
rm. 306
2:20
pm
Reconfigurable prototyping technology enables designers to build and verify entire systems at or near
actual speed. This is key for verification of systems based on audio, video and print quality, requiring
high performance verification that simulation cannot provide.
Silvaco International
rm. 102
Silvaco presents TCAD-Driven-CAD a unique solution for linking process technology to the sub
quarter micron design environment. Presented will be Celebrity - a set of powerful NT-based layout
and verification tools, STORM - technology driven parasitic interconnect extraction and SmartSpice
- a new standard in circuit simulation.
Silicon Integration Initiative, Inc. (Si2)
rm. 103
Si2 provides engineering consultation and services to industry-leading silicon, electronic systems, and
EDA companies for synergistic multi-company efforts focused on improving productivity and costs in
the design and production of integrated silicon systems. Si2 and over 25 companies, including the
EDA Industry Council, will present in-depth interoperability demonstrations.
SEVA Technologies, Inc.
rm. 301
SEVA Technologies now offers an evaluation service to assess new and existing Intellectual Property. Its
IP Evaluation Service helps designers assess which model is appropriate for a given design project
system simulation, design in, synthesis or inclusion in an end product.
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exhibitor presentations
onday
Esperan
rm. 304
Antony Dennis will explain how Esperans VHDL and Verilog training courses can have a major impact
on productivity and design quality, by presenting the real world issues using real engineers who can
really teach.
PADS Software, Inc.
rm. 305
PADS presents PowerBGA, our universal solution for high density interconnect packaging. Power BGA
automates the interconnect process between bare die and its underlying substrate and supports COB,
BGA, CSP, and laminate-based MCM, as well as PCB design based on PADS-PowerPCB technology.
DynaChip Corp.
rm. 306
2:40
pm
DynaChips FPGAs remove the speed barriers from FPGA design. Short, predictable routing delays
enable system-level operation from 66 to 266 MHz. On-chip PLLs allow clock multiplication, division
and latency reduction, 8 ns dual-port RAM enables FIFO performance over 100 MHz and blinding fast
I/O feature selectable LV-TTL/GTL/PECL/LVDS levels.
Omniview Design, Inc.
rm. 102
Omniview Design, Inc. provides solutions to the problems of rapidly increasing design complexity and
shrinking product life cycles. Omniview products focus specifically on the problems of design reuse,
preservation of intellectual property and hardware/software performance analysis at the architectural
level.
Ambit Design Systems, Inc.
rm. 103
Looking for a synthesis alternative? Then look at Ambit. Well show you why our next-generation
synthesis tool has been successful at more than 40 customer sites, gained support from leading ASIC
vendors, and will help you design your next generation of technology.
Simucad, Inc.
rm. 301
SILOS HyperFaults ultra-high performance fault simulation system supports Verilog HDL for fault
simulation at multiple levels of abstraction. HyperFaults architecture incorporates an exclusive set
of performance enhancing utilities coupled with Distributed Multi-Pass Fault Simulation that provides
unsurpassed runtime performance.
TimberWolf Systems, Inc.
rm. 304
TimberWolf is a complete timing driven placement and routing tool that can be used to completely
place and route integrated circuits. See a demonstration of TimberWolf and how its newly completed
detailed routing package can help you with all your IC designs.
Verysys Design Automation, Inc.
rm. 305
The Formal Viewpoint. After a brief introduction to formal verification and its benefits, we will expound
on the ease with which such tools can be integrated into a standard design flow. The most appropriate
and effective use of model and equivalence checking will be then described with illustrative examples.
Model Technology, Inc.
rm. 306
ModelSim - The Ultimate Tool for HDL Simulation. Whether it is VHDL or Verilog, PCs or Unix
workstations, multi-million gate ASICs or mainstream FPGAs - come see why over 18,000 designers
have chosen ModelSim for their HDL simulation needs.
78
m
3:00
pm
onday
exhibitor presentations
rm. 102
To characterize IP designs efficiently, Legend Design Technology, Inc. provides the following EDA products:
GDS-Cut : layout reduction SpiceCut : circuit reduction RC-Cut : AWE-based RC reduction
The products are successfully used for characterizing both timing and power of memory designs.
Synopsys, Inc.
rm. 103
Synopsys CTO will discuss how Synopsys is attacking IC design barriers with state-of-the-art design
flows. These flows include Synopsys comprehensive verification tool suite that spans system-level,
hardware/software, functional, and nanometer IC design, plus advanced design implementation tools.
OptEM Engineering Inc.
rm. 301
OptEM Engineering - a pioneer in developing CAE software and services that focus exclusively on the
fundamentals of interconnect analysis - will present their latest interconnect extraction and analysis
software tools for submicron ICs, advanced IC packages, and cable/connector systems.
CAD-Migos Software Tools, Inc.
rm. 304
SPICE-IT! solves problems. Make it a point to come to this presentation to see a full-featured, mixedmode simulation tool specifically created to solve your design problems. Dont miss this opportunity.
Visit Booth #1638!
Chronology Corp.
rm. 305
Verification Reuse answers the functional challenge posed by the functional verification crisis.
Simulation speed, emulation, and formal verification cannot address the explosion in designs with IP
and design reuse. Chronologys new QuickBench delivers Verification Reuse in easy-to-implement
stages while preserving your functional verification methodology.
TransEDA, Inc.
rm. 306
3:20
pm
TransEDA announces a major breakthrough in logic design verification with a new, unique solution that
is a first in EDA. StateSure is an auto-interactive statemachine verification tool for Verilog/VHDL
designers. StateSure combines static and dynamic analysis and simplifies the verification process for
complex controllers.
Derivation Systems, Inc.
rm. 102
The Formal Synthesis Company. Derivation Systems introduces its DERIVATION technology for
synthesizing formally verified designs from high-level behavioral specifications. Come see DRS Derivational Reasoning System, a design environment that supports system-level codesign in a
formal framework.
Simplex Solutions, Inc.
rm. 103
Have you seen it? With Simplex theres no more waiting for silicon to see the problems. Designers
now have visibility into physical design problems such as interconnect parasitics, clock skew, IR
(voltage) drop, signal coupling, and electromigration. Come see it in Simplex!
HyperLynx
rm. 301
HyperLynx, the leading-supplier of Signal Integrity and EMC tools under $20K, announces the addition
of crosstalk to the HyperSuite, a bundling of their SI and EMC tools. Come see how the HyperSuite
can solve your high-speed design problems.
79
onday
exhibitor presentations
rm. 304
Debussy, The Engineers Desktop - integrated debug & analysis environment for Verilog
HDL/VHDL and mixed-signal designs. Debussy accelerates HDL source code, state machine, and
internal/external IP design debugging. Debussy significantly enhances productivity from architectural
concept, implementation, through tape-out.
Sapien Design
rm. 305
Sapien Design offers IP products including USB-compliant Function and Host Controller macros, and
a USB Test Environment. All are available in Verilog or VHDL. The macros are also available in netlist
for popular FPGAs or synthesizable RTL for ASIC.
Cypress Semiconductor
rm. 306
3:40
pm
Cypress will highlight the industrys fastest In-System Reprogrammable (ISR) CPLD family
Ultra37000, Jam programming support, and Warp VHDL and Verilog development tools that make
designing today a simpler task. Get to market faster with Cypress programmable logic.
K2 Technologies/Shearwater Group
rm. 102
K2s products present a highly automated approach to design finishing including physical verification,
reticle design synthesis, wafer layout, OPC, fracturing, jobdeck generation and the generation of
mask/wafer fab, documentation. Benefits include reduced cost, faster cycle times and elimination of
errors.
Silicon Valley Research, Inc.
rm. 103
Silicon Valley Research, Inc. provides leading-edge IC physical design software for floorplanning,
placement, routing, custom layout and parasitic extraction of deep submicron ASICs, ASSPs, mixed
signal ICs and microprocessors. SVR also provides design consulting services and support to its
customers.
Artisan Components, Inc.
rm. 301
Artisan Components, Inc., a leading physical Intellectual Property (IP) developer, provides ProcessPerfect embedded memories, standard cells, and I/Os to semiconductor, ASIC ASSP and COT
suppliers who need the highest performance, lowest power and highest density, achievable for their
silicon process.
Semiconductores Investigation Y Diseno (SIDSA)
rm. 304
SIDSA offers ASIC design solutions and a variety of reusable IP modules, as well as EDA tools
featuring soft-cores design management and rule checking. SIDSA is also introducing a Field
Programmable System-on-Chip, consisting of a mixed-signal FPGA with on-chip microprocessor.
ANSOFT Corp.
rm. 305
Ansoft Corporation, the leading electromagnetics and wireless EDA company, offers solutions for
parasitic extraction, field solving and signal integrity with an emphasis on IC packages, cables,
connectors, printed circuit boards and on chip interconnects. Recently released features for signal
integrity analysis with enhanced productivity will be displayed.
80
Novas Ad
onday
exhibitor presentations
4:00
pm
rm. 306
Join Steve Klare, President of Intercept Technology Inc., for a detailed presentation on the features of
Pantheon, an integrated PCB/Hybrid/MCM design application. The presentation includes the
Pantheon Database (PDB) native file format, Breakout Router capabilities, and the direct output of
Pantheon design information in Mitrons GenCAD manufacturing file format.
FTL Systems, Inc.
rm. 102
Your high-performance, full-language VHDL and VHDL-AMS simulation is now affordable with Auriga.
Aurigas technology firsts include fully parallel compilation, parallel embedded scheduling combining
event-driven accuracy with cycle-driven performance and optimizing HDL compiler technology.
Compaq Computer Corp.
rm. 103
Todays Pentium II Workstations make a compelling argument to move from proprietary UNIX systems
to industry-standard Windows NT-based environment. This presentation will discuss the performance
benefits of Compaq Professional Workstations over ordinary PCs, and discuss how Wintel
Workstations match and exceed performance levels of RISC/UNIX systems.
Verisity Design, Inc.
rm. 301
Verisity Design offers Specman, high-level verification automation (HLVA) solutions for the functional
verification of electronic systems and chips. Specman, provides a complete solution for functional
verification integrated with todays leading HDL simulators - both VHDL and Verilog, event-driven, and
cycle-based simulators.
Fintronic USA, Inc.
rm. 304
FinSwHw is a co-simulation Verilog-C environment, supported by Super FinSim, the fastest Verilog
simulator. Pure C-code is transformed automatically into code that can be used in Verilog simulations.
Detailed timing information regarding the execution of the C-code is produced.
LogicVision, Inc.
rm. 305
LogicVision will describe icBIST3.0, the most complete suite of test and diagnostic solutions for
complex systems, SOCs and ASICs that depend on very deep sub-micron technology. icBIST3.0
saves engineering time and manufacturing costs by significantly reducing the test development effort
and ATE requirements for at-speed test and diagnostics of leading-edge products. Put us to the Test!
Fujitsu/ICL
rm. 306
4:20
pm
82
Thought about the Silicon Explosion and its impact on current design methods? Come and learn about
SuperVISE, the Fujitsu/ICL solution for SYSTEM design. SuperVISE delivers a proven solutions and
has been shown to reduce time-to-market by at least 25%.
CAST, Inc.
rm. 102
NEW VHDL CORES AND MODELS? From the exciting new synthesizable cores and simulation models
were announcing here to our existing broad libraries of proven devices (www.cast-inc.com), CAST
delivers high-quality, ready-to-use, cost-effective solutions for practical IP-based design.
OEA International, Inc.
rm. 103
OEA is demonstrating the newest, CELL-AN cell SPICE extraction tool, NET-AN critical multi-net
extraction and P-GRID power network analysis tool, all powered by the most accurate and fastest
Cheetah II 3D field solver, and the new SPIRAL inductance design tool.
Verisity Ad
onday
exhibitor presentations
rm. 301
Topdown delivers System-on-Chip design solutions using our core model generation technology.
TopProtect generates protected models for securely distributing Intellectual Property. Cyclops
generates cycle-based models of your designs that run 10 to 50 times faster with your existing
simulator and testbenches.
GLOBEtrotter Software, Inc.
rm. 304
FLEXlm from GLOBEtrotter is used by most all EDA vendors. See how GLOBEtrotters FLEXadmin helps
you get the most out of your software budget, and justify your spending to management. Simplify
license administration efforts while gaining greater understanding of how your organization uses
software. GLOBEtrotter will also discuss the essential Software Asset Management practices for EDA
customers.
Abstract Inc.
rm. 305
Abstract Inc., the worlds technological leader in formal verification tools and methodologies for ASICs
and systems-on-a-chip presents the leading-edge CheckOff tools for complete equivalence and
property checking.
Axis Systems
rm. 306
4:40
pm
The Ultimate Verification Systems Company makes its product debut - Xcite-1000. Using its patented
and revolutionary ReConfigurable Computing (RCC) technology, Xcite-1000 achieves superior
simulation performance while preserving debugging flexibility. Come to our booth for a full description
of the breakthrough in verification technology.
Altera Corp.
rm. 102
Altera will present its comprehensive design solution, including device densities up to 250,000 gates,
the industrys best development software, and the broadest range of megafunctions.
Analogy, Inc.
rm. 103
Analogy extends its simulation offerings with Saber/ModelSim, a mixed-signal product connecting
the powerful Saber mixed-signal simulator with ModelSim PLUS, Model Technology, Inc.s
VHDL/Verilog simulator. Analogy also introduces TESTIFY, the first product to offer mixed-signal fault
simulation for functional test development.
Library Technologies, Inc.
rm. 301
LibChar, UnBlock, IcPower, Verilog, BlockChar and some of their siblings get together for Breakthrough
Dynamic Timing Analysis of custom blocks with full state dependent power and timing models. As
expected no compromise accuracy. A MUST SEE EVENT, DONT MISS IT.
OPMAXX, Inc.
rm. 304
OPMAXX is demonstrating software for yield analysis and improvement, mismatch analysis, analog
fault coverage and testability analysis and introducing Oscilation-based Built-in Self-test (BIST) focused
on solving critical functional and structural test problems of IP and analog design blocks.
Gambit Automated Design, Inc.
rm. 305
84
You Can use any P&R tool to start your VDSM design, but if you want to finish it, you better have
GRANDMASTER. Its advanced algorithms, flexibility, and user-friendliness make it the fastest way
to build VDSM silicon real estate.
Gambit Ad
onday
exhibitor presentations
5:00
pm
rm. 306
Presenting product data management software. Personal PDM promotes collaborative design efforts,
managing project data, providing a single electronic vault. DesignFlow organizes projects, streamlines
communication, facilitates effective design management. ViewCenter allows viewing, storing and
printing of Schematic and PCB files on Intranet or network locations.
Snaketech
rm. 102
Substrate Noise Problems? Following a brief discussion on the basics of substrate noise, Snaketech
will explain how you can quantify and understand substrate noise problems using Layin, a unique
substrate noise modeling program. All technologies and feature sizes are modeled.
Sun Microsystems
rm. 103
Engineering productivity demands more than acquiring the next generation desktop computer to the
engineering environment. Many companies are looking to compute ranches as a tool for engineering
productivity. Suns presentation will examine the implementation of such a compute facility.
Interra, Inc.
rm. 301
Interras EDA-IP toolkit offers customizable software components for EDA tool developers and
semiconductor vendors. Modules are available for VHDL/Verilog analysis, translation, test, debugging
and RTL synthesis. Interra is introducing two new components: Concorde Super Fast RTL Synthesis
and NOM-Netlist Object Model.
Integrated Intellectual Property Inc.
rm. 304
A case study presents how our IP Integration and Consulting Services unit works actively with
customers to follow the IP all the way to tape-out. Our products are dedicated to help customers create
large designs using IP and to take them to silicon very quickly. The SuperCore series and SuperSim
series offers solutions for IEEE-1394, AGP, USB and PCI.
QuickLogic Corp.
rm. 305
QuickLogic designs the fastest FPGAs in the industry along with comprehensive design software. The
companys products provide engineers a low-cost path to rapidly transfer high-performance custom
circuitry into physical silicon at their desktop. This significantly shortens the design cycle times of
electronic systems, accelerating time-to-market.
Circuit Semantics, Inc.
rm. 306
5:20
pm
86
Circuit Semantics, Inc. (CSI) is the industry leading provider of transistor-level characterization tools
for intellectual property cores, custom design, memories and standard cells. CSIs presentation will
highlight our proven Timed-Boolean Extraction technology for characterization of multi-million transistor
designs with pico-second accuracy.
Intrinsix Corp.
rm. 102
Intrinsix is the leading independent provider of design services for ASIC and High Integration
Embedded Systems. At DAC98 Intrinsix is introducing its proprietary microPlatform design paradigm
which combines ASIC design, verification, embedded software, and integration of IP cores.
onday
exhibitor presentations
VeriBest, Inc.
VeriBest,
rm. 103
Windows NT,
5:40
pm
IKOS Systems, the design verification company, will update you on the status of our three businesses:
simulation acceleration, emulation, and verification services. The update will use customer
successes to demonstrate the return that IKOS high performance verification products and services
provide.
Nu Thena Systems, Inc.
rm. 102
Nu Thena introduces its new FORESIGHT FOR CODESIGN product. A significant new product based on
the industry-leading FORESIGHT system design toolset, FORESIGHT FOR CODESIGN is the only proven
systems engineering solution for system-on-a-chip designers.
Sagantec
rm. 103
Come learn how Sagantec enables reuse and optimization of existing silicon intellectual property for
deep submicron design. Its software ensures efficient silicon IP reuse to implement system on
silicon; meet time-to-market and time-to-volume requirements; and take advantage of new process
technology.
Intellitech Corp.
rm. 301
Intellitech will present 3rd generation Scan Tools for silicon debug. The enterprise-wide (Unix &
Windows) solution will reduce your prototype debug time. If youre using BIST, IP CORES or performing
path delay tests, Intellitech Scan Tools can help!
87
onday
exhibitor presentations
rm. 304
Virtual Silicon develops, markets, and supports Silicon Ready libraries and physical design
components for complex integrated circuits in 0.25 and 0.18 micron process technologies. The
companys Diplomat product line offers world-class standard cells, I/Os, and memories that are
manufacturable at multiple foundry partners.
Spectra Logic
rm. 305
Spectra Logic manufactures both reliable, scalable, affordable and widely supported tape libraries,
and a powerful backup and archival software solution. Alexandria Backup and Archive Librarian
software and the Spectra 10000 AIT tape library won Unix Reviews 1997 Outstanding Product award.
Alternative System Concepts, Inc.
rm. 306
6:00
pm
VHDL or Verilog translation tools expand IP market and simplify single-chip design flow. VBIT inserts
boundary and embedded JTAG. ASC announces PowerBuster.
Moscape Inc.
rm. 102
Moscape will be premiering state of the art products aimed at improving performance and reliability of
complex deep submicron IC designs. It performs assertion based analysis of static and dynamic
circuits, tightly integrates logic and physical designs and significantly reduces design iterations.
Aristo Technology
rm. 103
Aristo Technology is a new startup offering block-level interconnect design automation tools for system
ICs. Aristos products help reduce overall design cycle time 20-35% when used within an interconnectcentric flow featuring a novel topology and interconnect hardening methodology.
Sand Microelectronics, Inc.
rm. 301
Accelerate your design with Sands latest silicon-proven synthesizable cores for IEEE 1394, USB, and
PCI connectivity standards.
Tower Semiconductor Ltd.
rm. 304
As a semiconductor foundry with a recently-implemented customer-dedicated design center, Tower
Semiconductor will address the issue of embedded Flash opportunities in todays marketplace.
CoWare, Inc.
rm. 305
CoWare, Inc. provides EDA software and services to meet the growing performance demands of
todays IC designers, by offering tools and methods that provide an entirely new, top-down solution for
system-level design for this new generation of increasingly-complex ICssystems-on-a-chip.
Translogic USA Corp.
rm. 306
Translogics EASE/HDL offers easy graphical entry for complex chip design. It automatically generates
Verilog or VHDL code which inputs to the industrys most popular simulators and synthesis tools. At
DAC, Translogic introduces graphical display of existing Verilog or VHDL code, a key component for
design reuse.
88
Simplex Solutions
Ad
xhibit guide
product descriptions
Abstract Inc.
Booth 1346
46613 Fremont Blvd.
Fremont, CA 94538
(510) 360-2700
http://www.abstract-inc.com
90
DAC Space
Selection Ad
xhibit guide
product descriptions
CoverMeter is the industrys most complete, most flexible and highestthroughput Verilog code coverage analysis tool. Supporting PLIconforming Verilog simulators, CoverMeter is used by designers and
verification engineers to determine which portions of application code
have yet to be exercised in simulation test cases (jumping with just a
mouse click to uncovered code). CoverMeter is a precision calibration
tool, useful at each stage of the design verification process, measuring
code coverage for statements, conditions, toggles and user-specified
expressions, including state machines.
ACEO Ad
xhibit guide
product descriptions
Altera Corp.
Booth 118
ALDEC, Inc.
Booth 1222
2230 Corporate Cr.
Henderson, NV 89014
(800) 487-8743
http://www.aldec.com
ALDEC will be demonstrating its completely integrated, Windows NT/95
based, VHDL and Verilog design environment. The products provide
complete support for VHDL and Verilog and include an HDL editor,
Automatic Test Bench Generation, Design Manager and Language Based
Simulator (Behavioral and Structural). Aldecs innovations in the area of
ready-to-use VHDL/Verilog software solutions for supporting high density
FPGA and CPLD devices will be demonstrated in its booth, stop-by and
receive your Free VHDL Evaluation Kit.
Altera offers the broadest line of CMOS PLDs, including device densities
up to 250,000 gates and system speeds up to 250 MHz. These devices
combine the time-to-market advantages of PLDs with the density, speed,
and cost once associated exclusively with gate arrays. The FLEX 10K
embedded PLD family is optimized for mid- to high-density designs; the
low-cost FLEX 6000 family offers a volume alternative to gate arrays in
the 10,000 to 24,000 gate range. All device families are supported by
Alteras architecture-independent MAX+PLUS II software. Altera also
offers the broadest IP portfolio, including functions from the AMPP and
MegaCore libraries.
92
Altera Ad
xhibit guide
product descriptions
ANSOFT Corp.
Booth 930
ALL ROADS LEAD TO AMI for FPGA to ASIC to ASIC migration services. For
cost-reductions or ASIC second-sourcing, AMIs NETRANS offers fast,
reliable prototyping for all types of digital IC designs. Vectorless FPGA
translations to gate array are now available with AMIs Vectorless
NETRANS. AMI also offers 20+ years of mixed-signal design expertise, a
virtual mixed-signal interface option and flexible CMOS manufacturing
processes making mixed-signal ASIC solutions easy and cost-effective.
Analogy, Inc.
Booth 944
9205 SW Gemini St.
Beaverton, OR 97008
(503) 626-9700
http://www.analogy.com
94
Aptix Corp.
Booth 2042
2880 N. First St.
San Jose, CA 95134
(408) 428-6200
http://www.aptix.com
xhibit guide
product descriptions
Aristo Technology
Booth 80
20111 Stevens Creek Blvd.
Ste. 200
Cupertino, CA 95014
(408) 342-9083
http://www.aristotech.com
Ansoft Ad
Arcadia Ad
xhibit guide
product descriptions
ATG Technology
Booth 1854
EP Time Slot: 3:40 pm
Artisan Components is a leading developer of high-performance, lowpower and high-density physical Intellectual Property (IP) products for the
design and manufacture of System-on-a-Chip ICs. The company offers
highly differentiated Process-Perfect embedded memory, standard cell
and I/O components that meet semiconductor, ASIC, ASSP and COT
suppliers acute performance, power and density needs. Every product is
optimized for each customers manufacturing process and includes
popular and custom design views delivered ready for use with industry
standard and proprietary design tools.
97
xhibit guide
product descriptions
Avant! Corp.
Booth 1308 & 1718
46871 Bayside Pkwy.
Fremont, CA 94538
(510) 413-8697
http://www.avanticorp.com
Axis Systems
Booth 1640
Cadabra
Booth 1442
Axis Systems presents the next generation in design verification - Xcite1000. Using its patented ReConfigurable Computing (RCC) technology,
Xcite-1000 achieves superior simulation performance while preserving
debugging flexibility. Applications for Xcite-1000 range from high-speed
regression runs to software/hardware co-design. Whether the design is
described as either Verilog behavioral, RTL or gate level, Xcite-1000 will
custom configure its computing elements to maximize parallel processing
while minimizing communication. Further, Xcite-1000 directly plugs into
workstations for compactness and high-speed communication. Xcite1000 offers the highest simulation throughput without having to change
design methodology.
98
Avant! Ad
xhibit guide
product descriptions
CAST, Inc.
Booth 1652
EP Time Slot: 4:20 pm
VHDL CORES AND MODELS - Come see why CAST is your best source for
practical IP thats cost-effective, quality-tested, and ready-to-use. Our
synthesizable cores provide the solutions you need when consolidating
designs with ASICs or FPGAs, or creating new systems with off-the-shelf
functions. Our simulation models range from economical standard part
and memory libraries to sophisticated devices and components. Review
our catalog (www.cast-inc.com), then come for a demo and discussion of
how you can best put CAST IP to work.
100
Chronology Corp.
Booth 744
14715 NE 95th St.
Redmond, WA 98052
(425) 869-4227
http://www.chronology.com
Products: Chronology is a leading provider of software for specificationdriven verification. QuickBench is a suite of products for creating
reusable testbenches in Verilog or VHDL. QuickBench Modeler uses
graphical interface specifications and optionally native HDL to generate
reusable bus-functional models. Come to our booth for a demo of our new
QuickBench products. TimingDesigner models and analyzes digital
circuit behavior with timing diagrams. The built in static timing analysis
engine continuously checks for timing/protocol violations. Interface
models and specifications are available through Chronologys Synchrony
program.
Cadabra Ad
xhibit guide
product descriptions
Circuit Semantics, Inc. (CSI) is the industry leading provider of transistorlevel characterization tools for intellectual property cores, multi-million
transistor custom designs, memories and standard cells. DynaBlock is
CSIs proven high-capacity solution for SPICE-accurate characterization of
high-performance designs such as microprocessors, multimedia
accelerators and DSPs. DynaCore generates a reusable timing model for
IP cores. CSIs products plug-and-play with all popular static timing
analyzers and circuit simulators.
Looking for powerful workstations for your EDA applications? Plug into
Compaq. Compaq Professional Workstations combine industry-standard
components with advanced technology, such as an innovative Highly
Parallel System Architecture, to deliver superior performance,
functionality and Unix/NT interoperability. From design to verification,
Compaq Professional Workstations can support your compute intensive
applications, such as those offered by Cadence Design Systems, Mentor
Graphics, Synopsys, and VeriBest. Join us in booth #2118 for powerful
software and hardware demonstrations and highly informative technical
presentations.
102
Computer Design
Booth 1550
10 Tara Blvd., 5th Fl.
Nashua, NH 03062
(603) 891-9125
http://www.computer-design.com
Computer Design magazine is the primary source of why-to information
for engineering managers, senior engineers and engineers responsible
for the design and development of todays computer-based smart
products. Each monthly issue contains in-depth items and features
written by experienced senior editors who concentrate on the critical
technologies, components and tools needed to design microprocessor
and computer-based OEM products and systems.
xhibit guide
product descriptions
CoreEl Microsystems
Booth SV23
46750 Fremont Blvd., Ste. 208
Fremont, CA 94538
(510) 770-2277
http://www.coreel.com
CoreEl MicroSystems Inc. is a leading provider of Silicon Intellectual
Cores for the communication marketplace. A complete range of IP cores
are available in the fields of Ethernet, SONET and ATM for ASIC design.
CoreEl provides cores for the ethernet market namely Gigabit MAC,
10/100 MAC, RMON counters, VLAN support, RMII adapters, etc. In
SONET CoreEl provides framers for OC-3, 12 and 48 and a IP over
Sonet solution. For ATM single chip NIC solutions, SAR-622, ATM switch,
ABR, Utopia, etc. are available.
CoWare, Inc.
Booth 65
2900 Gordon Ave., Ste. 205
Santa Clara, CA 95051
(408) 617-1613
http://www.coware.com
CSELT SpA
Booth 2542
Via G. Reiss Romoli 274
Torino, 10148 Italy
(39) 11 2285220
http://www.cselt.it/cselt/
CSELT is the Telecom Italia Groups centre for research in the field for
Telecommunications and Information Technology. VIP is a
synthesizable Very High Level Intellectual Property Library composed of
customizable system level of soft macros for designing application
oriented integrated circuits. The VIP application areas are: Information
and Communication Technologies, mainly in Fast Packet Switching
(ATM, TCP/IP), Video and Multimedia. A high performance IP Hard
macro library including low power memories, low swing pads, PLLs,
phase aligners, CAMs is also available.
Coware Ad
xhibit guide
product descriptions
Cypress Semiconductor
Booth 344
3901 N. First St.
San Jose, CA 95134
(408) 943-2600
http://www.cypress.com
Cypress Semiconductor
Booth SV38
See Cypress Semiconductor in SV38 and Booth #344. See the product
description in previous listing.
Visit the Denali Software Exhibit to see why designers have adopted
Denali as the preferred solution in VHDL and Verilog for modeling
memories and for the verification of memory controllers. Denalis toolset
enables designers to instantly create models of new memories and
embedded cores. The unique class-based architecture ensures the
reliability and structure necessary for modeling your key memory
specifications. Memory Modeler provides a powerful simulation
environment, accurate models, and interactive debugging features with
all HDL simulators.
104
Design Acceleration
Booth 818
1590 The Alameda
San Jose, CA 95126-2300
(408) 885-1885
http://www.designacc.com
Cypress Ad
xhibit guide
product descriptions
DesignSoft
Booth 15
DynaChip Corp.
Booth 21
Csengery u.53.
Budapest, 1067 Hungary
(36) 1269-1206
http://www.designsoftware.com
Duet Technologies
Booth 1418
2833 Junction Ave., Ste. 100
San Jose, CA 95134
(408) 432-9200
http://www.duettech.com
ECN Magazine/EITD
Booth 1538
201 King of Prussia Rd.
Radnor, PA 19089
(610) 964-4342
http://www.ecnmag.com
ECN provides product news and literature updates for design engineers
and engineering manager, in the electronic OEM. Published monthly, ECN
covers discrete and integrated circuits, components, computer software,
test equipment, power sources, packaging and materials. EITD, The
Electronic Industry Telephone Directory, is the only single volume national
directory for the EOEM. EITD lists over 30,000 sources of electronic
products and services. Check us out on the webwww.ecnmag.com.
EDA Standards
Booth 438
2500 Wilson Blvd.
Arlington, VA 22201
(703) 907-7545
http://www.eia.org/eig
106
Duet Ad
xhibit guide
product descriptions
EE Times/EDTN/CMP Media
Booth 1518
600 Community Dr.
Manhasset, NY 11030
(516) 562-7694
http://www.eet.com
EE Times is the community newspaper for design engineers and technical
and corporate managers in the EOEM industry. Its weekly coverage of
product and technology developments provides its 160,000 readers with
in-depth discussions of the applications and market segments where
these products and technologies are used. The Electronics Design,
Technology & News (EDTN) Network provides a comprehensive
collection of job critical information for electronics professionals. Industry
specific information is categorized into a News Center, EE Design Center,
E-Search, Career Center and includes content from EE Times, EBN, SBN.
108
Engineering
Data Xpress
Ad
xhibit guide
product descriptions
Escalade Corp.
Booth 128
2475 Augustine Dr.
Santa Clara, CA 95054
(408) 654-1605
http://www.escalade.com
Escalade creates powerful products for the authoring, delivery and end
use of IP for systems-on-a-chip designs. IP Guard provides unbreakable
protection and faster simulation for IP modules on all popular VHDL and
Verilog simulators. IP Guard is the only multi-language input tool that
generates VHDL, Verilog, and C. DesignBook offers block diagrams,
state diagrams, truth tables, flow charts and timing diagrams in addition
to HDLs. It is the tool of choice for multi-vendor IP integration. Design
Explorer automates multi-dimensional design space exploration.
Esperan
Booth 252
45 N. First St., Ste. 139
San Jose, CA 95113-1295
(408) 279-1300
http://www.esperan.com
Frequency
Tech. Ad
Fintronic Ad
xhibit guide
product descriptions
EXD Technologies
Exemplar Logic
Booth 318
EP Time Slot: 11:40 am
3 Integrated Formal IC Verification Software Packages; LEQ Equivalency & Property Verification; integrated in one low priced
package for up to 32 million transistor Verilog or VHDL Designs. 10x - 50x
faster than ALL competitors. Labs - Logic Abstraction; input EDIF, Spice,
or Verilog transistors / gates and automatically output RTL Verilog or
VHDL. Layout to RTL Verification or re-target transistors / schematics to
RTL. MC-Check - Multi-Cycle Model Checking; verifies within specified
or infinite cycle periods that design properties, and design behavior are
implemented correctly using a temporal Verilog language called
Assertion Assistant.
With over 1000 licenses sold, and between zero and two outstanding
bugs at any one time over the last twelve months, Fintronics FinSim
family of Verilog simulators is the first choice for people who care about
the quality and performance of the tools they are buying. Fintronics latest
product, FinSwHw, is a co-simulation Verilog-C environment, supported by
Super FinSim, the fastest Verilog simulator, reaching 100 million cycles
per second. Detailed timing information regarding the execution of the Ccode is produced.
Frontier Design
Booth 62
9000 Crow Canyon Rd., Ste. S-221
Danville, CA 94506
(510) 648-2683
http://www.frontierd.com
Frontier Designs A|RT (Algorithm to Register Transfer) EDA tools
provide the ability to drive any HDL-based hardware design flow
directly from a C-code specification of the algorithm, enormously
increasing design productivity. A|RT Library facilitates the
development of fixed-point algorithms required for a silicon
implementation. A|RT Builder directly and automatically converts fixedpoint C-algorithms to VHDL or Verilog. Frontier Design also helps
customers in the wireless telecom, consumer audio and multimedia
areas to implement ASICs and FPGAs using its Algorithm-to-Silicon
design methodology.
111
xhibit guide
product descriptions
GateField Corp.
Booth 908
EP Time Slot: 4:00 pm
Fujitsu/ICL
Booth 328
Wenlock Way West Gorton
Manchester, M12 5DR UK
(44) 161230-5757
http://www.icl.com/da
Fujitsu/ICL displays its leading technology solutions that support Systemlevel design, provide third generation formal verification and offer Highspeed PCB & MCM design tools. Visit our booth, listen to our
presentations and hear how we can accelerate your design time.
SuperVISE with VHDL+ introduces system specification, re-use
capabilities and interface-based design into your current methodology.
ASSURE offers a robust formal verification environment used
throughout Fujitsu. Design Theater offers an integrated PCB & MCM
design tool with its effective analysis of timing, heat and noise
capabilities.
Genesys Testware
Booth 1154
181 Ottawa Way
Fremont, CA 94539
(510) 661-0791
http://www.genesystest.com
Esperan Ad
xhibit guide
product descriptions
IBM Corp.
Booth 1318
EP Time Slot: 4:20 pm
Hewlett-Packard Co.
Booth 1530
IBM Corp.
Booth SV1
Need to solve BIG design problems? NOW YOU CAN at HPs DAC booth
#1530.
See IBM Corp. in SV1 and Booth #1318. See the product description in
previous listing.
HP provides the most powerful UNIX & NT, workstations and servers for
your critical design bottlenecks. Come talk to our system designers. Find
out about HPs technology roadmap for 64-bit HP-UX and learn about
upcoming PA-RISC processors. They are your best path to MERCED and IA64. Stop by and eliminate annoying design flaws by playing our new EDA
game and compete for prizes against your friends! Then take a copy home.
HyperLynx
Booth 632
17641 NE 67th Ct.
Redmond, WA 98052
(425) 869-2320
http://www.hyperlynx.com
FTL
Systems Ad
xhibit guide
product descriptions
Gambord Plaza
1765 Scott Blvd., Ste. 208
Santa Clara, CA 95050
(408) 260-3970
http://www.i2p.com
InfoQuick
Booth 88
2 Executive Cr., Ste. 150
Irvine, CA 92614
(714) 221-0535
http://www.info-quick.com
InfoQuick introduces WebStir for Workgroups, an affordable tool that
hosts an on-line subscription service for obtaining the latest electronic
component information quickly and easily, enabling designers to make
the best component decisions for their designs. Using WebStir in a
Microsoft Windows 95 or NT environment, designers can access
component information from many Websites without having to launch a
Web browser. Talon, the patent-pending backend suite of tools
continually discovers, maintains and relinks specific information on
manufacturers Websites to InfoQuicks Web server.
Inicore
Booth SV15
44350 Grimme Blvd.
Fremont, CA 94528
(510) 445-1529
http://www.inicore.com
Inicore is a system design house that is specialized in the development
and implementation of system-level turnkey projects. It also has
pioneered the concept of easy-to-use, intellectual property cores for FPGA
and ASIC technologies due to its proven design methodology. Cores are
provided for applications such as DSP, CANbus, CPU, UART, VME, I2C,
HDLC, UTOPIA, G704, xDSL. These easy-to-use cores are optimized for
time-to-market sensitive high-level system integration. The company
provides products and services, which support the entire integrated
circuit design process from system analysis to working products.
116
Integrated Intellectual Property, Inc. provides cores for standard bus inter
connectivity market. SuperLINKCore and SuperPHYCore are a Firewire
IEEE 1394 synthesizable cores. Super1394Sim is a Firewire IEEE
1394 verification environment designed for maximum flexibility and can
be used to exhaustively verify your 1394 LINK or PHY design under test.
SuperAGPTargetCore and SuperAGPMasterCore are AGP synthesizable
cores. SuperAGPMasterSim and SuperAGPTargetSim are a fully
compliant AGP simulation model package. SuperPCICore provides the
most comprehensive PCI 2.1 synthesizable core.
IKOS Ad
xhibit guide
product descriptions
Intellitech Corp.
Booth 1350
70 Main St.
Durham, NH 03824
(603) 868-7116
http://www.intellitech.com
Intellitech will demonstrate 3rd generation Scan Tools for silicon debug.
The enterprise-wide (Unix & Windows) solution provides an efficient user
interface, scan vector creation and high-speed vector application to
reduce your prototype debug and development time. If youre using BIST,
designing with IP cores or performing path delay tests, Intellitech Scan
Tools can help!
Intellx
Booth 956
3481 Dayton-Xenia Rd.
Dayton, OH 45432
(937) 426-3111
http://www.intellx.com
MISTIE, a mixed signals design environment developed by the team of
MTL Systems, Inc. and the University of Cincinnati, will be demonstrated.
Funded by the Air Force Research Laboratory and the Defense Advanced
Research Projects Agency (DARPA), MISTIE is a Mixed-Signal Technology
Integration Environment providing the designer an environment for
analog and mixed signal design. MISTIE provides the same design
automation capability VHDL provides for digital systems designers and
meets the need for multi-level abstraction and compliance with the VHDLAMS standard.
118
interHDL, Inc.
Booth 1918
4984 El Camino Real, Ste. 210
Los Altos, CA 94022
(650) 428-4200
http://www.interhdl.com
Hewlett
Packard Ad
Formalized
Design Ad
xhibit guide
product descriptions
Interra, Inc.
Booth 1546
2001 Gateway Pl., Ste. 440W
San Jose, CA 95110
(408) 573-1400
http://www.interrainc.com
Intrinsix Corp.
Booth 2528
33 Lyman St.
Westboro, MA 01581
(508) 836-4100
http://www.intrinsix.com
Intusoft
Booth 141
222 W. Sixth St., Ste. 1070
San Pedro, CA 90731
(310) 833-0710
http://www.intusoft.com
Established in 1985, Intusoft is a leading supplier of circuit simulation
and test synthesis and sequencing software to Fortune 500 Electronics
companies worldwide. Products include: Power Designer (NEW), the most
comprehensive design synthesis and analog/mixed-signal circuit
simulation software package for Power Engineers; Intusofts flagship
product - ICAP/4 Windows, and IsSpice-based simulation program with
separate product options for OrCAD, Intusoft or Protel schematic entry;
Test Designer, a revolution in Test, performs fault diagnostics, fault tree
generation, acceptance test design.
Interra Ad
xhibit guide
product descriptions
K2 Technologies/Shearwater Group
Booth 2308
LEDA SA
Booth 445
35 Avenue Du Granier
Meylan, 38240 France
(33) 47641-9243
http://www.leda.com
122
Integrated
System
Design Ad
xhibit guide
product descriptions
LightSpeed Semiconductor
Booth 1156
LogicVision, Inc.
Booth 218
LightSpeed Semiconductor
Booth SV8
1151 Sonora Ct.
Sunnyvale, CA 94086
(408) 616-3200
http://www.lss-asic.com
Linius Technologies
Booth 444
276 Turnpike Rd.
Westborough, MA 01581
(508) 616-9360
http://www.linius.com
Bell Labs Design Automation is a provider of a complete line of leadingedge verification products for systems-on-silicon and other advanced
applications. FormalCheck, a formal verification product, makes modelchecking of complex designs a reality. ATTSIM, our single-process
mixed signal simulator, utilizes a unique architecture and an efficient
partitioning scheme to tackle your most troublesome mixed signal
designs. We also offer a comprehensive set of DSM parasitic extraction
tools. Look to BLDA to continue to harness tomorrows technologies to
solve todays problems.
124
EDAC Ad
xhibit guide
product descriptions
126
MicroSim Corp.
Its A Whole New World of EDA with the merger of OrCAD and MicroSim.
Join us to learn how to make your design process a competitive
advantage for your company with the new 9.0 Release of OrCAD and
PSpice brand products.
MINC/Synario
Booth 1824
Mechtronix, Inc.
Mentor Ad
xhibit guide
product descriptions
Moscape Inc.
Booth 22
EP Time Slot: 2:40 pm
Morphologic, Inc.
Booth 552
131 D.W. Hwy., Ste. 470
Nashua, NH 03060
(603) 880-4263
http://www.morphologic.com
128
Box 360260
Milpitas, CA 95036
(408) 946-2850
http://www.moscape.com
MyCAD, Inc.
Booth 2030
574 Weddell Dr., Ste. 6
Sunnyvale, CA 94089
(408) 745-6785
http://www.mycad.com
MyCAD, Inc. is well known for the MyChip Station, a powerful full custombased IC layout and verification package in windows. This year we are
very excited to show a preview of MyChip Station V3.5 and also a
schematic entry of SPICE generation package, MyLogic Station V3.5.
The last but not least, VHDL modeling and simulator which supports IEEE
1076-1987 standard, MyVHDL Station V3.5 will be introduced.
Model Tech
Ad
xhibit guide
product descriptions
ACM Ad
xhibit guide
product descriptions
OEA offers the industrys fastest 2D/3D field simulators for accurate
parasitic extraction and a consulting service for IC and packaging
designers. The latest NET-AN, CELL-AN & P-GRID utilize the new Cheetah
II solver technology to deliver the only true full 3D field solutions
available for accurate 3D critical multi-net extraction, full 3D cell SPICE
extraction, and 3D power distribution network analysis. For the analog
and mixed signal designers, the latest SPIRAL inductor design tool, will
make its premiere release showing.
DAC Survey
Ad
xhibit guide
product descriptions
OPMAXX, Inc.
Booth 338
8209 SW Cirrus Dr.
Beaverton, OR 97008
(503) 520-9200
http://www.opmaxx.com
Interconnects play a significant role in the design of todays highperformance digital systems. OptEM Engineering is a pioneer in
developing CAE software and services that focus on the fundamentals of
interconnect analysis - fundamentals that include RLCG parasitic
extraction, signal interaction between interconnects, design rule
definition, and SPICE model generation and analysis. OptEM offers a
comprehensive suite of software tools for submicron ICs, advanced IC
packages, and cable/connector systems. Stop by and find out how we
can provide solutions to your design challenges.
OrCAD
Booth 1018
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
http://www.orcad.com
Visit OrCAD and well show you how your design process can become a
real competitive advantage for your company. Youll see our new,
integrated 9.0 Release of design applications for the Windows NT
enterprise. These powerful products are ideal for designing FPGAs,
CPLDs, and PCB systems; analog and mixed-signal design and
simulation; PCB layout, including options for high-speed design; and, for
Internet-enabled design with OrCADs unique Component Information
System products.
132
Palmchip Corp.
Booth 20
2055 Gateway Pl., Ste. 240
San Jose, CA 95110
(408) 487-8690
http://www.palmchip.com
Palmchip Corporation is a developer and supplier of System-on-Chip
(SOC) solutions, including synthesizable IP cores, embedded software,
and design services. Plamchips CoreFrame Architecture provides a highperformance on-chip bus scheme allowing quick and easy integration of
silicon IP blocks. Combined with our extensive IP portfolio, CoreFrame
dramatically reduces SOC design and verification time. Palmchip also
offers a range of silicon and software design services specialized in the
design of high-integration SOC devices using the ARM RISC processor
core family. Palmchips web site is at www.palmchip.com.
OPMAXX Ad
xhibit guide
product descriptions
Penton Publishing
Booth 822
Philips Semiconductors
Booth SV21
811 E. Arques Ave.
Sunnyvale, CA 94088
(505) 822-7629
http://www.coolpld.com
Prentice Hall-PTR
Booth 827
1 Lake St.
Upper Saddle River, NJ 07458
(201) 236-7238
http://www.prenhall.com
ORCAD Ad
xhibit guide
product descriptions
Provis Corp.
Booth 84
5251 Program Ave., Ste. 100
Mounds View, MN 55112
(612) 785-2000
http://www.provis.com
Provis ensures that your designs are functionally verified and have highquality manufacturing tests. Within our framework are advanced tools for
functional test coverage, network distributed simulation, process
automation, and high-speed fault coverage analysis. At the framework
core are software and accelerated hardware simulators that cover the
complete spectrum of simulation needs. Provis has many new products
at DAC: the ProLog and ProGrade software simulators, the new XPrime
environment, Fault Manager 2.0, and ...our revolutionary new
simulator...Construct.
136
Pinebush Ad
xhibit guide
product descriptions
QuickLogic Corp.
Booth 736 & SV22
1277 Orleans Dr.
Sunnyvale, CA 94089
(408) 990-4000
http://www.quicklogic.com
pASIC 3 is QuickLogics latest family, manufactured on a 0.35 micron 4layer metal. There are five devices in the family, ranging from 12,000 to
100,000 usable gates, from 84 to 456 package pins, and feature 3.3
volt operation with 5 volt compatibility. In 1998, QuickLogic will add
embedded blocks of RAM to the family. QuickLogics QuickWorks design
tools provides designers with a very low cost schematic-entry based tool,
and the free QuickChip tools enable engineers to use third party
environments such as Synopsys, Cadence, Mentor Graphics, Viewlogic,
Veribest, Synario, and many others, to generate QuickLogic designs.
RAPID
Booth SV4
P.O. Box 779003-299
Dallas, TX 75379
(972) 503-0066
http://www.rapid.org
RAPID is an industry trade association chartered with meeting the needs
of companies and organizations that develop and sell IP. The
associations primary function is to promote the acceptance and use of
third party IP products within the electronics industry. Additional
objectives include establishing guidelines and promoting the use of good
business and design practices among members. RAPID works with EDA,
semiconductor companies and industry standard organizations to make
IP easier and more accessible to designers.
IEEE Ad
xhibit guide
product descriptions
Sagantec
Booth 518
RUBICAD Corp.
Booth 2000
1150 N. First St., Ste. 130
San Jose, CA 95112
(408) 995-3334
http://www.edac.org/Rubicad
Macros, cores and libraries are being reused and resized for different
fabs and as part of complex systems-on-silicon. To address this, Rubicad
offers LACE 3.0, the world leading LAyout Conversion Environment. LACE
3.0 facilitates system-level integration (SLI) and hierarchical compaction
of existing system-level macros (SLMs) and cores for use with various
submicron technologies. A major breakthrough in compaction technology
now enables designers to maintain the original hierarchy of RAMs, ROMS,
SRAM, DRAM, datapath, etc. during the compaction process.
Sand Microelectronics
Booth 1450
2121 Ringwood Ave.
San Jose, CA 95131
(408) 321-8200
http://www.sandmicro.com
SANDSTROM Engineering
Booth 2546
3611 Vista Dr.
Manhattan Beach, CA 90266
(310) 545-7108
http://www.sandstrom.org
Write better hardware NOW! Youve got a pretty good design, but you
suspect there are some problems. Dont settle for pretty good. Have
a design that is going to synthesize without the problems that you will
have to solve farther down the line. Sanstrom Engineerings PreSynth.vhd
makes VHDL synthesizable and checks for nonsense constructs, the
dreaded reset problem, registered outputs, and much more.
138
Rubicad Ad
xhibit guide
product descriptions
Sapien Design
Booth 349
45335 Potawatami Dr.
Fremont, CA 94539
(510) 668-0200
http://www.sapiendesign.com
SES Inc.
Booth 1622
EP Time Slot: 3:20 pm
Visit SEVA Technologies Exhibit during DAC to learn about its consulting
services, innovative training and design solutions, hardware and software
benchmarking, and tool and methodology assessment. Its IP Evaluation
Service helps designers assess which model is appropriate for a given
design project system simulation, design in, synthesis or inclusion in
an end product. Through its experience using IP from various third-party
sources, SEVA Technologies has developed the expertise to evaluate IP
models from PCI and USB to IEEE 1394 Firewire and MPEG.
Sente Inc.
Booth 208
31 Nagog Pk.
Acton, MA 01720
(978) 635-9080
http://www.senteinc.com
140
PADS
Software Ad
xhibit guide
product descriptions
142
Silicon Strategies
Booth SV13
954 San Rafael Ave.
Mountain View, CA 94043
(650) 988-9677
http://www.isdmag.com
Silicon Strategies magazine is the premier information source for
technical, project, and corporate management on the strategies, issues,
and products relating to the use of virtual components and intellectual
property in creating systems on a chip. This unique trade journal reports
on the markets evolving technical and business trends, including legal
issues surrounding the use and abuse of IP, pricing strategies, IP design
management, and standardization efforts. It also provides product
coverage on cores of all types, tools for IP integration, and foundry and
design services.
Sagantec Ad
xhibit guide
product descriptions
Silvaco International
Booth 127
4701 Patrick Henry Dr., Bldg. 2
Santa Clara, CA 95054
(408) 654-4376
http://www.silvaco.com
Simpod, Inc.
Booth 2534
EP Time Slot: 2:20 pm
Simucad, Inc.
Booth 1122
Simple Silicon provides digital and mixed signal IPs which enable you to
design for high speed connectivity between PCs, Consumer Electronic
devices, Networking Equipment and Home Appliances. Using our silicon
proven USB, IEEE1394 (firewire) and Low Power Analog Cores can save
the user several months of ASIC design time, enabling them to get to the
market quicker. Our drag and drop silicon components are available as
ASIC-HDL, PLD functions and Physical Layout.
Simutest, Inc.
Booth 1624
521 Almanor
Sunnyvale, CA 94086
(408) 617-6100
http://www.simplex.com
144
Simucad Ad
xhibit guide
product descriptions
Snaketech
Booth 1054
Place de la Chaffardiere
St. Geoire en Valdaine, F-38620 France
(33) 476-071408
http://www.snaketech.com
Substrate Noise Problems? Layin will aid you in analyzing substrate noise
concerns and help ensure first silicon success. Layin can be used to
model designs in all technologies and all feature sizes. Our new Cadence
interface and SPICE netlist integration make the program easy to
integrate into any design flow. High end place and route has become
affordable for both PC and UNIX platforms with cellSnake and gateSnake
V1.4, which include zero-skew clocktree synthesis and path-based timing
constraints.
Spectra Logic
Booth 1118
1700 N. 55th St.
Boulder, CO 80301
(303) 449-6400
http://www.spectralogic.com
146
Sun Microsystems
Booth 618
901 San Antonio Rd.
Palo Alto, CA 94303
(650) 786-3744
http://www.sun.com
Summit
Design Ad
xhibit guide
product descriptions
SynaptiCAD Inc.
Booth 90
Synplicity, Inc.
Booth 1742
Synchronicity Inc.
Booth 1800
Synopsys, Inc.
Booth 2130
700 E. Middlefield Rd.
Mountain View, CA 94043-4033
(650) 694-4418
http://www.synopsys.com
148
Synopsys Ad
Simpod Ad
xhibit guide
product descriptions
Tanner EDA
Booth 1600
2650 Foothill Blvd.
Pasadena, CA 91107
(626) 792-3000
http://www.tanner.com/eda
Temento Systems
Booth 94
EP Time Slot: 11:40 am
151
xhibit guide
product descriptions
Teradyne, Inc.
Booth 152
Time-Rover Inc.
Booth 13
Texas Instruments
Booth SV25
P.O. Box 660199, MS 8678
Dallas, TX 75266
(972) 480-7963
152
Temento Ad
xhibit guide
product descriptions
TSA
Booth 925
TransEDA, Inc.
Booth 233
16795 Lark Ave., Ste. 125
Los Gatos, CA 95032
(408) 395-5014
http://www.transeda.com
Chip designers play to win. So, dont gamble with your tools! Translogics
EASE/HDL offers easy graphical entry and automatic Verilog or VHDL
code generation. EASE/HDL also interfaces to the industrys most
popular simulators and synthesis tools, so it fits easily into your existing
design flow. And, EASE/HDL now offers graphical representation of
existing Verilog or VHDL code. Save time and money through design
reuse. Translogic is your wild card to success! See for yourself at booth
#2518.
154
TSSI
Booth 2300
525 Almanor
Sunnyvale, CA 94086
(408) 328-9149
http://www.ultimatech.com
To achieve first pass silicon success, Ultima-DC, integrated with UltimaPE, a 3D net parasitic extractor, is the first delay calculator taking into
account for coupling noise and power net IR drop/rise in DSM cell-based
IC design flow. Ultima-PE achieves accuracy close to 3D solver and speed
approaching to 2D extraction. Being the leading supplier of the standardalone parasitic reduction tool, Ultima-PR provides best solution for large
digital circuits as well as complex memory and mixed signal circuits.
Silicon
Valley
Research Ad
xhibit guide
product descriptions
University Booth
Booth 830
Univ. of Colorado at Denver
Campus Box 110
Denver, CO 80217-3364
(303) 556-2357
http://www.acm.org/sigda
The University Booth features state-of-the-art demonstrations of research
projects by university researchers and DAC authors. Both EDA, as well as
design and instructional demonstrations are featured at the University
Booth. In addition, at the University Booths program corner DAC
exhibitors provide brochures on their discounted university hardware and
software programs.
156
Vamp, Inc.
Booth 87
Vantis
Booth 236
995 Stewart Dr.
Sunnyvale, CA 94088
(888) Vantis2
http://www.vantis.com
The Vantis VF1 Family offers designers a new level of FPGA
performance. The VF1 Variable-Grain-Architecture delivers the best
performance in a cost-effective 12K to 36K gate FPGA solution.
Developed concurrently with the VF1 FPGA Family, the VF1 DesignDirect
software ensures successful design implementation with its Ease-ofSuccess timing driven tools and graphical interfaces. In addition, Vantis
is setting higher standards in the CPLD industry with its MACH 4 and
MACH 5 families with features such as SpeedLocking, 3-Volt, ISP and
high performance. Stop by booth #236 to receive a copy of the VantisSynario Starter software CD.
Vantis Ad
xhibit guide
product descriptions
VAutomation Inc.
Booth SV20
20 Trafalgar Sq., Ste. 443
Nashua, NH 03063
(603) 882-2282
http://www.vautomation.com
Veritools, Inc.
Booth 1818
EP Time Slot: 11:20 am
VAutomation
provides,
high-quality,
technology-independent
synthesizable cores based on VHDL and Verilog HDL for true system-ona-chip design. Its reusable, silicon-proven cores offer high performance
through increased integration, faster time-to-market and reduced
development costs. Cores are available for the industry-standard 8086,
80186, Z80, and 65C02 microprocessors and VAutomations own ultralow gate count, 8-bit RISC microprocessor, the V8-uRISC. Serial
communication cores are available for USB host, hub and device
controllers, a High-Level Data Link Controller (HDLC) and an Ethernet LAN
controller.
VeriBest, Inc.
Booth 608
6101 Lookout Rd.
Boulder, CO 80301
(303) 581-2432
http://www.veribest.com
158
Veritools Ad
xhibit guide
product descriptions
Virage Logic
Booth 244
1641A S. Main St.
Milpitas, CA 95035
(408) 263-0160
http://www.virlog.com
160
Summit/
Dasys Ad
xhibit guide
product descriptions
VSI Alliance
Booth 115
15495 Los Gatos Blvd., Ste. 3
Los Gatos, CA 95032
(408) 356-8800
http://www.vsi.org
The VSI Alliance is an open organization comprised of all segments of the
system-chip industry segments: Electronic Design Automation (EDA), IP
providers, semiconductor vendors and system companies. (Meet the
member companies in our booth: http://www.vsi.org/. VSIs goal is
accelerated growth of the system-chip market by developing open
technical standards, enabling the mix-and-match of IP exchanged on an
intra-and inter-company basis. Industry-wide participation is sought with
membership open to any corporation interested in development and
promotion of standards for system chip design.
X-Tek Corp.
Booth 2522
4439 W. Fallen Leaf Ln.
Glendale, AZ 85301
(602) 879-6731
http://www.x-tekcorp.com
X-Tek unveils X-CDE, the radically new Comprehensive Design
Environment. Exceed your limitations, break away from dead-end HDLbased methodologies, and blast into the millennium with the state of the
art technology. X-CDE offers development of language independent
models using either stochastic or deterministic techniques. Intuitive
graphical design entry, coupled with simulation and formal verification
capabilities, allows fast paced engineers to successfully perform design
and analysis with ease. Succeed with X-CDE, stop at Booth 2522, get
your diploma, and let X-Tek blow you away!
Western
Design
Center Ad
xhibit guide
product descriptions
Xentec Inc.
Booth 153
Xilinx, Inc.
Booth 508
Xilinx, Inc.
Booth SV19
2100 Logic Dr.
San Jose, CA 95124
(408) 559-7778
http://www.xilinx.com
Xilinx builds performance and technology leadership in all areas of
programmable logic including fast software runtimes, increased turns-perday, performance-optimized architectures, and predictable highperformance for IP implementation. On display in the Silicon Village booth
is evidence of the Xilinx process, density, and performance leadership
through devices built on leading-edge 0.25 processes, industry-leading
densities to half-million gates, and robust and cost-optimized FPGA and
CPLD architectures. Drop by and see how Xilinx complete programmable
logic solutions will build your future successes.
162
Zuken-Redac, Inc.
Booth 308
2041 Mission College Blvd., Ste. 260
Santa Clara, CA 95054
(888) 332-7227
http://www.redac.co.uk
Xilinx Ad
xhibit guide
product descriptions
Zycad Corp.
See GateField Corp. in Booth #908.
164
Verplex Ad
xhibit guide
Actel Corp.
Booth SV18
MicroMagic, Inc.
Booth 93
Compilogic Corp.
Booth 67
SyntyX Technology
Booth 91
SyntyX Technology develops and markets System Level Design Tools for
HW/SW co-design and IP Creation and Reuse, characterized by the
following features:
Standard SDL, behavioral VHDL and C entry.
Unique solution for SDL to VHDL+C interactive system architecture
synthesis.
High performance behavioral synthesis (from standard B-VHDL to
standard RT-VHDL).
Inter-module interface synthesis.
Multilanguage co-simulation back-plane.
SyntyX tools output results are both human readable and compatible with
most logic synthesis tools available on the market.
166
supplemental listing
ac
COMPANY NAME
BOOTH #
4750
4510
4435
4272
4320
4840
4625
4710
4245
4065
4050
4548
4620
4755
4705
4005
4525
4730
4280
4735
4260
4230
4405
4310
4830
4712
4265
4714
4042
4075
4665
4810
4540
4765
4080
4410
4035
4415
4085
4645
4430
4605
4030
4825
4835
4650
4720
4120
4052
4555
4040
4530
4325
COMPANY NAME
MENTOR GRAPHICS CORP.
MEROPA, INC.
MODEL TECHNOLOGY, INC.
MONTEREY DESIGN SYSTEMS, INC.
MOSCAPE INC.
NOVAS SOFTWARE, INC.
NURLOGIC DESIGN, INC.
OMNIVIEW DESIGN, INC.
OPC TECHNOLOGY INC.
OPMAXX, INC.
ORCAD
PADS SOFTWARE, INC.
PROVIS CORP.
QUICKTURN DESIGN SYSTEMS, INC.
RELAY DESIGN AUTOMATION
RUBICAD CORP.
SAGANTEC
SENTE INC.
SILICON INTEGRATION INITIATIVE, INC. (SI2)
SILICON RESOURCES
SILVACO INTERNATIONAL
SIMPLEX SOLUTIONS, INC.
SIMPOD, INC.
SUMMIT DESIGN, INC.
SUN MICROSYSTEMS
SUREFIRE VERIFICATION INC.
SYCON DESIGN, INC.
SYNCHRONICITY INC.
SYNOPSYS, INC.
SYNPLICITY, INC.
SYNTYX TECHNOLOGY
SYSTEMS SCIENCE, INC.
TARGET COMPILER TECHNOLOGIES N.V.
TAVEREN TECHNOLOGY, INC.
TERA SYSTEMS, INC.
TOPDOWN DESIGN SOLUTIONS, INC.
TRANGATE TECHNOLOGY, INC.
TRANSCENDENT DESIGN TECHNOLOGY, INC.
TRANSLOGIC USA CORP.
ULTIMA INTERCONNECT TECHNOLOGY
VANTIS
VERIBEST, INC.
VERISITY DESIGN, INC.
VERITOOLS, INC.
VERPLEX SYSTEMS, INC.
VERYSYS DESIGN AUTOMATION, INC.
VIEWLOGIC SYSTEMS, INC.
VIRAGE LOGIC
VIRTUAL SILICON TECHNOLOGY, INC.
VISUAL SOFTWARE SOLUTIONS
XILINX, INC.
XYNETIX DESIGN SYSTEMS, INC.
Y EXPLORATIONS, INC.
BOOTH #
4090
4740
4670
4640
4820
4250
4815
4425
4125
4210
4685
4330
4805
4205
4675
4560
4315
4715
4255
4760
4420
4450
4130
4285
4615
4235
4565
4745
4305
4505
4445
4550
4215
4070
4660
4105
4220
4290
4845
4270
4025
4725
4060
4225
4275
4045
4015
4135
4545
4240
4010
4020
4055
16
Demo Suite
Map
168
Demo Suite
Map
169
ac
Chair
Thomas P. Pennino
Lucent Technologies, Bell Labs.
101 Crawfords Corner Rd.
Rm. 1M-415
Holmdel, NJ 07733
(732) 949-7340
tpennino@lucent.com
Lorie Bowlby
111 W. St. John St., Ste. 200
San Jose, CA 95113-1104
(408) 226-7240
lorieb@pacbell.net
Randal E. Bryant
Carnegie Mellon Univ.
School of CS
Pittsburgh, PA 15213
(412) 268-8821
randy.bryant@cs.cmu.edu
Basant R. Chawla
Lucent Technologies
283 King George Rd.
Rm. E4D43
Warren, NJ 07059
(908) 559-4070
bchawla@lucent.com
Ronald E. Collett
Collett International, Inc.
5201 Great America Pkwy.
Ste. 3238
Santa Clara, CA 95054
(408) 562-6167
ronc@collett.com
Nanette Collins
Consultant
37 Symphony Rd., Unit A
Boston, MA 02115
(617) 437-1822
nanette@nvc.com
170
Denise Dres
OrCAD
16275 Laguna Canyon Rd.
Irvine, CA 92618
(714) 788-6080
denise.dres@orcad.com
Marie R. Pistilli
MP Associates, Inc.
5305 Spine Rd., Ste. A
Boulder, CO 80301
(303) 530-4562
marie@dac.com
Dave Guinther
Chrysalis Symbolic Design, Inc.
101 Billerica Ave., Bldg. 5
North Billerica, MA 01862
(508) 436-9909
daveg@chrysalis.com
Jan M. Rabaey
Univ. of California
Dept. of EECS - 511 Cory Hall
Berkeley, CA 94720
(510) 643-8206
jan@eecs.berkeley.edu
Abbie Kendall
OrCAD
9300 SW Nimbus Ave.
Beaverton, OR 97008
(503) 671-9500
abbie@orcad.com
Dottie Wanat
Sun Microsystems
3060 N. First St.
San Jose, CA 95134
(408) 544-0417
dottie.wanat@eng.sun.com
Jim Lochmiller
Cadence Design Systems, Inc.
2655 Seely Rd.
San Jose, CA 95134
(408) 944-8095
jiml@cadence.com
Dave Orecchio
VIEWlogic Systems, Inc.
293 Boston Post Rd. West
Marlboro, MA 01752-4615
(508) 480-0881
dorecchio@viewlogic.com
ac
notes page
171
ac
index
About the Conference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Awards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Birds-of-A-Feather/Additional Meetings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40-41
Busing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Call for Papers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46-47
Conference Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Convention Center / Hotel Key Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Convention Center Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54-55
DAC Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
DAC on the WWW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
DACnet-98 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Demo Suite Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Demo Suite Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170
Demo Suite Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168-169
Electronic Design Automation Industry Committee (EIC) . . . . . . . . . . . . . . . . . . . . . . . . . . .171
Executive Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Exhibit-Only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
Exhibit Floor Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56-58
Exhibit Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Exhibitor Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61-62
Exhibitor Presentation Matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Exhibitor Presentations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67-88
Exhibitor Product Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90-164
Exhibitor Supplemental Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .166
First Aid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Food Services . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
General Chairs Message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .inside front cover
Guest Program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Important Information at a Glance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Information Desk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
New to the Conference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Opening Keynote Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Proceedings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Program Highlights . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Program Session Matrices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-9
Registration Hours . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
San Francisco Attractions/Weather . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
SIGDA Meeting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
Sponsorship . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49-50
Technical Program Committee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51-52
Technical Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13-33
Thursday Keynote Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Topics and Related Sessions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11-12
Tutorial Descriptions/Schedule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10, 35-39
University Design Contest . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
Wednesday Night 35 Years of DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Workshop for Women in Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
172