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Experiment -5

Aim- Write programs to implement 2:4 and 3:8 Decoders using


Behavioral modeling , data Flow and Structural modeling and verify
their simulations through waveforms..

Tools Required- Mentor Graphics HDL Designer(TM) 2012.1 (Build 6)


and Model Sim.

Theory- A decoder is a circuit that changes a code into a set of


signals. It is called a decoder because it does the reverse of encoding,
Decoders are simpler to design. A common type of decoder is the line
decoder which takes an n-digit binary number and decodes it into
2n data lines. A 2:4 Decoder has two input lines and four output lines
while 3:8 has three input lines and eight output lines.

5.1 Behavioral Modeling


A VHDL Process statement is used for all behavioral descriptions. The
process is the key structure in behavioral VHDL modeling. A process is
the only means by which the executable functionality of a component
is defined. In fact, for a model to be capable of being simulated, all
components in the model must be defined using one or more
processes.

5.1.1 2:4 Decoder ( Program)


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Behavioral2_4 IS
port(
A : in STD_LOGIC_VECTOR(1 downto 0);
B : out STD_LOGIC_VECTOR(3 downto 0)
);
END ENTITY Behavioral2_4;

ARCHITECTURE data2_4 OF Behavioral2_4 IS


BEGIN
encoder : process (A) is
begin
if (A="00") then
B <= "0001";
elsif (A ="01") then
B <= "0010";
elsif (A="10") then
B <= "0100";
else
B <= "1000";
end if;
end process encoder;
END ARCHITECTURE data2_4;

Image 1 Screenshot of the waveform ( 2:4 Decoder using


behavioral modeling)

5.1.2 3:8 Decoder ( Program)


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Behavioral3_8 IS
port(
A : in STD_LOGIC_VECTOR(2 downto 0);
B : out STD_LOGIC_VECTOR(7 downto 0)
);
END ENTITY Behavioral3_8;
ARCHITECTURE Behavioral3_8_data OF Behavioral3_8 IS
BEGIN
encoder : process (A) is
begin
if (A="000") then
B <= "00000001";
elsif (A ="001") then
B <= "00000010";
elsif (A="010") then
B <= "00000100";
elsif (A ="011") then
B <= "00001000";
elsif (A="100") then
B <= "00010000";

elsif (A ="101") then


B <= "00100000";
elsif (A="110") then
B <= "01000000";
else
B <= "10000000";
end if;
end process encoder;
END ARCHITECTURE Behavioral3_8_data;

Image 2- Screenshot of the waveform ( 3:8 Decoder using


behavioral modeling)

5.2 Structural Modeling


Structural Modeling describes how the components are connected.
Behavioral models are assumed to exist in local working directory or in
a library. Structural modeling facilitate the use of hierarchy and
abstraction in modeling complex systems. Structural models can be
integrated into models that also use processes

5.2.1 2:4 Decoder (Program)

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Structural2_4 IS
port (A0, A1: in bit;
B0, B1,B2,B3:out bit);
END ENTITY Structural2_4;
ARCHITECTURE data2_4 OF Structural2_4 IS
Component AND2 is
port (A,B : in bit;
Y: out bit);
end component;
Component NOT2 is
port ( A:in bit;
Y: out bit);
end component;
Signal S1,S2: bit;
BEGIN
N1: NOT2 port map (A0, S1);
N2: NOT2 port map (A1, S2);
AD1: AND2 port map (S1, S2,B0);
AD2: AND2 port map (A0, S2, B1);
AD3: AND2 port map (S1,A1,B2);
AD4: AND2 port map (A0, A1, B3);
END ARCHITECTURE data2_4;

Image 3- Screenshot of the waveform ( 2:4 Decoder using


Structural Modeling)

5.2.2 3:8 Decoder (Program)


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Structural3_8 IS
port (A0, A1, A2: in bit;
B0, B1,B2,B3, B4,B5, B6,B7:out bit);
END ENTITY Structural3_8;
ARCHITECTURE data3_8 OF Structural3_8 IS
Component AND3 is
port (A,B,C : in bit;
Y: out bit);
end component;
Component NOT2 is

port ( A:in bit;


Y: out bit);
end component;
Signal S1,S2,S3: bit;
BEGIN
N1: NOT2 port map (A0, S1);
N2: NOT2 port map (A1, S2);
N3: NOT2 port map (A2, S3);
AD1: AND3 port map (S3, S2,S1,B0);
AD2: AND3 port map (S3, S2,A0,B1);
AD3: AND3 port map (S3,A1,S1,B2);
AD4: AND3 port map (S3, A1,A0, B3);
AD5: AND3 port map (A2, S2,S1,B4);
AD6: AND3 port map (A2, S2, A0 ,B5);
AD7: AND3 port map (A2,A1,S1,B6);
AD8: AND3 port map (A2,A1,A0,B7);
END ARCHITECTURE data3_8;

Image 4 Screenshot of the waveform ( 3:8 Decoder using


Structural modeling)

5.3 Data Flow


Over here the programs are implemented using simple logic functions
like AND, OR, NOR, NOT and NAND. The logic gates are used to
describe the output in a simple manner.

5.3.1 2:4 Decoder (Program)


VHDL Architecture Shaleen_lib.Normal2_4.data2_4
Created:
by - Administrator.UNKNOWN (E1-2LA1-04)
at - 09:46:27 08/ 6/2014
using Mentor Graphics HDL Designer(TM) 2012.1 (Build 6)
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Normal2_4 IS

port (A0, A1 : in bit;


B0,B1,B2,B3 : out bit);
END ENTITY Normal2_4;
ARCHITECTURE data2_4 OF Normal2_4 IS
BEGIN
B0 <= Not A0 AND NOT A1;
B1 <= A0 AND NOT A1;
B2 <= NOT A0 AND A1;
B3<= A0 AND A1;
END ARCHITECTURE data2_4;

Image 5 Screenshot of the waveform ( 2:4 decoder


using data flow)

5.3.2 3:8 Decoder (Program)


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY dataflow3_8 IS
port (A0, A1,A2 : in bit;
B0,B1,B2,B3,B4,B5,B6,B7 : out bit);
END ENTITY dataflow3_8;
ARCHITECTURE data3_8 OF dataflow3_8 IS
BEGIN
B0 <= NOT A2 AND NOT A1 AND NOT A0;
B1 <= NOT A2 AND NOT A1 AND A0;
B2 <= NOT A2 AND A1 AND NOT A0;
B3 <= NOT A2 AND A1 AND A0;
B4 <= A2 AND NOT A1 AND NOT A0;
B5 <= A2 AND NOT A1 AND A0;
B6 <= A2 AND A1 AND NOT A0;
B7 <= A2 AND A1 AND A0;
END ARCHITECTURE data3_8;

Image 6- Screenshot of the waveform ( 3:8 Decoder


using Data flow)

RESULT- 2:4 And 3:8 Decoders are implemented using behavioral


modeling, structural modeling and data flow. Hence simulations are
verified using waveforms generated.