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LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Structural2_4 IS
port (A0, A1: in bit;
B0, B1,B2,B3:out bit);
END ENTITY Structural2_4;
ARCHITECTURE data2_4 OF Structural2_4 IS
Component AND2 is
port (A,B : in bit;
Y: out bit);
end component;
Component NOT2 is
port ( A:in bit;
Y: out bit);
end component;
Signal S1,S2: bit;
BEGIN
N1: NOT2 port map (A0, S1);
N2: NOT2 port map (A1, S2);
AD1: AND2 port map (S1, S2,B0);
AD2: AND2 port map (A0, S2, B1);
AD3: AND2 port map (S1,A1,B2);
AD4: AND2 port map (A0, A1, B3);
END ARCHITECTURE data2_4;
ENTITY dataflow3_8 IS
port (A0, A1,A2 : in bit;
B0,B1,B2,B3,B4,B5,B6,B7 : out bit);
END ENTITY dataflow3_8;
ARCHITECTURE data3_8 OF dataflow3_8 IS
BEGIN
B0 <= NOT A2 AND NOT A1 AND NOT A0;
B1 <= NOT A2 AND NOT A1 AND A0;
B2 <= NOT A2 AND A1 AND NOT A0;
B3 <= NOT A2 AND A1 AND A0;
B4 <= A2 AND NOT A1 AND NOT A0;
B5 <= A2 AND NOT A1 AND A0;
B6 <= A2 AND A1 AND NOT A0;
B7 <= A2 AND A1 AND A0;
END ARCHITECTURE data3_8;