Ceferino Kevin A.

Tan
EE 177.1
Simulation 3 Carry-Ripple Adder

Objectives
1. To simulate a Carry-Ripple Adder using any HDL (Hardware Description
Language) development software by coding and simulation.
Basic Concept
Previously, we have worked with the basic logic gates, namely, the AND, OR,
NOR, NAND, XOR, XNOR, and the NOT(Inverter) gates.
We now begin to make use of the knowledge of these gates to devise what is
called an adder. Now, there are two types of adders the half adder, and the full
adder.
At the very least, most people expect computers to do some kind of
arithmetic computation, and thus, they expect computers to add. Computers do not
perform decimal operations at the base or the machine level, instead, they utilize a
number system that can be translated or modeled in terms of logical gates, which
use one of the most basic electronic components, the transistor.
To do these binary calculations, developers devised the carry-ripple adder. It
utilizes multiple full adders arranged in an array, made to accept some carry input
from the former, each of which in turn, utilizes a half-adder.

Materials
Hardware Description Language (HDL) development software such as:
1. Altera ModelSim
2. Xilink Simulation
3. EDA Playgound Freeware, online-based
Procedure
1. Familiarize yourself with the Verilog Hardware Description Language.
2. First, we will need to establish a code that utilizes functions that can be
reused with different values. This gives us the ability to recreate the
concept of a carry-ripple adder.
We may choose to use the method which utilizes a half-adder module
linked to a full-adder module, until finally, we use this full-adder module in
our carry-ripple adder module.
3. We begin by writing:
module half_adder(output S,C,input A,B);
xor(S,A,B);

and(C,A,B);
endmodule //This is to establish the base unit of operation: the halfadder.

4. Next, we write:
module full_adder(output S,Cout,input A,B,Cin);
wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);
endmodule

5. Finally, we add our last operating module:

module ripple_adder_4bit(output [3:0] Sum,output Cout,input [3:0]
A,B,input Cin);
wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),
FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2),
FA4(Sum[3],Cout,A[3],B[3],c3);
endmodule

6. Compile the code

7. Finally, simulate the code

8.
9.

8. You will then have to add the output to the grapher. (Waveform window will
show up after your code is simulated)

9. Set each input.

10.Eventually, you will end up with this. Set values including the input carry,
then you will find the results (Shown in following pages).

Output
Code:

module half_adder(output S,C,input A,B);

xor(S,A,B);
and(C,A,B);
endmodule

module full_adder(output S,Cout,input A,B,Cin);

wire s1,c1,c2;
half_adder HA1(s1,c1,A,B);
half_adder HA2(S,c2,s1,Cin);
or OG1(Cout,c1,c2);
endmodule

module ripple_adder_4bit(output [3:0] Sum,output Cout,input [3:0] A,B,input Cin);

wire c1,c2,c3;
full_adder FA1(Sum[0],c1,A[0],B[0],Cin),
FA2(Sum[1],c2,A[1],B[1],c1),
FA3(Sum[2],c3,A[2],B[2],c2),
FA4(Sum[3],Cout,A[3],B[3],c3);
endmodule

Graph

Notice that from top to bottom: Cinput, SUM, Cout, A, B, c1, c2, c3. C1 is the output
of the first full-adder block, c2 is for the 2 nd, c3 for the 3rd, and finally, Cout is for the
4th and last full-adder block.

Conclusion
We have seen how the carry-ripple adder works. We have known how it operates on
a base-level, using the full-adder, and finally, the half-adder.

References

Circuits Today, March 29, 2012 - http://www.circuitstoday.com/half-adder

Digital Logic and Design, 3rd, 4th, and 5th Editions, M. Morris Mano
Computer Architecture, 3rd Edition, M. Morris Mano

Learning Verilog:
Numato Lab, December 29, 2014 - http://numato.com/tutorials/learning-fpga-andverilog-a-beginners-guide-part-1-introduction
VOL - http://vol.verilog.com/