Memory Management (Interrupt Priority Approach) Report

MEMORY MANAGEMENT
(INTERRUPT PRIORITY APPROACH)
2006-2007
PROJECT REPORT
SUBMITTED TO THE FACULTY OF

ELECTRONICS AND COMMUNICATION ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY, WARANGAL (A.P)

(DEEMED UNIVERSITY)
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
SUBMITTED BY
AMIT KUMAR KARNA (04403)

DEVENDER BUDHWAR (04411)
DINESH KUMAR (04412)
Under the Guidance of
Mr. P. Murlidhar
DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING
NATIONAL INSTITUTE OF TECHNOLOGY
(DEEMED UNIVERSITY)
WARANGAL-506004(A.P)
1
Acknowledgements
We would like to express our sincere thanks to our

faculty, P. Murlidhar, Department of Electronics and
Communication Engineering, National Institute of
Technology, Warangal for his constant encouragement,
splendid and gracious guidance throughout our work. He
has been a constant source of inspiration and helped us
in each stage. We express our deep gratitude to him for
such encouragement and kindly cooperation.
Amit Kumar Karna (4403)

Devender Budhwar (4411)
Dinesh Kumar (4412)
2
CONTENTS
Abstract
Introduction
Priority Interrupt Algorithm
VHDL Implementation
The Memory Management Unit
Components
Synchronous RAM
Address and Data Bus Multiplexer
Conclusions
References
ABSTRACT
An MMU is a controller that allows a common resource memory to be
shared by two or more processors depending on various input control
signals. It provides the access to memory to one of the processor according
to priority. Being an Interrupt service procedure, time of processor is
managed efficiently. We have used the fixed priority algorithm. This
approach allows a wide design exploration through automatic
generation/selection of arbitration schemes.
INTRODUCTION
For our EDA-II project we developed a “Memory Management Controller”

where we implemented the ‘priority interrupt’ algorithm.
An exclusion device is a controller that allows a common resource such as

memory to be time shared by two or more processors depending on various
input control signals. The purpose of this project was an implementation of
one of the conventional algorithm for memory management control. We
developed the algorithm, and implemented in VHDL language. The program
was simulated using Altera Quartus-II. The net-list and .sof and .pof files
have been obtained to dump the code onto FPGA.
We chose this project because it is an ambitious project aimed to challenge

us as well as provide a level of sophistication that would allow this project to
be applicable not only as a semester project but to potentially be used in
future projects.
1
Problem statement:
Three processors are required to time share a Synchronous RAM

of size 1024*16.The address bus is 10 bits wide and the data bus is
16 bits wide. There is a r/w signal which allows the processors to
read data from the memory or write data into the memory. The
controller is supposed to control access to the common memory
depending on the request signals received by the three processors
depending on the following algorithms.
Overall Goal: Memory Management Control
Goal: Produce a successful realization of memory management

controller.
Sub Goal 1: Develop individual components

Sub Goal 2: Integrate the components to form a
complete module
Sub Goal 3: Implement on FPGA kit
We successfully reached sub goal 3 except that we did not

demonstrate in hardware due to the limited time and limited
number of accessible pins available on FPGA - EP1C6Q240C8 kit,
we could not actually implement in hardware.
2
PRIORITY INTERRUPT ALGORITHM
Each processor is assigned a priority and depending on the priority a CPU is
given access. When a lower priority processor is active and the controller
receives the request signal from a higher priority processor, the latter is
given access until its job is finished after which the lower priority processor
is given access. Nested interrupts should be allowed.
STATE DIAGRAM:
3
VHDL IMPLEMENTATION
VHDL:
VHSIC Hardware Definition Language.

Common language for designers.
High level language.
Simulation synthesis and analysis tools are available.
Softwares: Quartus-II/Xlinix
DESIGN Unit Names
¾ Entity
Meaningful name describing the purpose of the circuit.
¾ Architecture
According to the modeling style used (i.e., Behavioral,
Procedural, Dataflow, or Structural) or to some specific
architecture property.
¾ Configuration
Name of the corresponding entity with suffix "Cfg“.
¾ Package
Name of the design (i.e., top-level entity) with suffix
"Pkg“.
¾ Testbench (entity, architecture, package)
Name of corresponding entity with suffix "Tb“.
¾ Library (package)
Library name with suffix "Lib".
FPGA
Benefits of using FPGA

¾ Programmed by user at their site using programming hardware.
¾ Can implement tens of thousands of gates on logic on a single
IC.
¾ Can be programmed many times.
¾ Short development time.
¾ Low cost.
¾ FPGA kit in lab: EP1C6Q240C8
Hierarchy ‘n’ fpga occupancy
4
COMPONENTS:-
• Synchronous RAM
• Address and Data Bus Multiplexer
FPGA Occupancy:-
Project navigator
5
State Diagram Simulation:
Conditions:
6
MEMORY MANAGEMENT UNIT:
PRIORITY INTERRUPT MMU:
Entity:
In this algorithm, A is having the highest

priority among A, B and C. If B is having
the access of the memory and A requests for
the access, then the memory is allocated to
A until A stops sending its request and is
true in case of B and C also in which B is
having a high priority…..!
RTL:
7
TECHNOLOGY VIEW:
m u l ti p l e x:m u l t
a d d A [0 ] addA[0]
a d d B [0 ] addB[0]
m e m o r y:m e m
a d d B [8 ] addB[8] c lk
a d d B [9 ] addB[9] data_out_mux[0]~ 688 data_out_mux[0]~ 688
a d d C [0 ] addC [0] data_out_mux[1]~ 689 data_out_mux[1]~ 689
a d d C [4 ] addC [4] data_out_mux[5]~ 693 data_out_mux[5]~ 693 q _b[0] d a ta _ r d _ o u t[0 ]
d a ta A [0 ] dataA[0] data_out_mux[11]~ 699 data_out_mux[11]~ 699 q _b[6] d a ta _ r d _ o u t[6 ]
d a ta A [4 ] dataA[4] data_out_mux[15]~ 703 data_out_mux[15]~ 703 q _b[10] d a ta _ r d _ o u t[1 0 ]
d a ta A [5 ] dataA[5] M ux0~ 131 M ux0~ 131 q _b[11] d a ta _ r d _ o u t[1 1 ]
d a ta A[1 0 ] dataA[10] M ux5~ 132 M ux5~ 132
d a ta A[1 5 ] dataA[15] M ux10~ 139 rw
d a ta B [0 ] dataB[0] M ux11~ 139
d a ta B [1 ] dataB[1] M ux12~ 139
d a ta B [2 ] dataB[2] M ux13~ 139 d a ta _ w r _ o u t[1 5 ]
d a ta B [3 ] dataB[3] M ux14~ 139
D AT AIN
d a ta B [4 ] dataB[4] M ux15~ 139 PAD O U T d a ta _ w r _ o u t[1 5 ]
! OE
d a ta B [5 ] dataB[5] M ux16~ 139
d a ta B [6 ] dataB[6] M ux17~ 139 O U T PU T
d a ta B [7 ] dataB[7] M ux18~ 139
d a ta _ w r _ o u t[1 4 ]
d a ta B [8 ] dataB[8] M ux19~ 139
d a ta B [9 ] dataB[9] M ux20~ 139 D AT AIN
PAD O U T d a ta _ w r _ o u t[1 4 ]
d a ta B [1 0 ] dataB[10] M ux21~ 139 ! OE
d a ta B [1 1 ] dataB[11] M ux22~ 139
O U T PU T
d a ta B [1 2 ] dataB[12] M ux23~ 139
d a ta B [1 3 ] dataB[13] M ux24~ 139 d a ta _ w r _ o u t[1 3 ]
d a ta B [1 4 ] dataB[14] M ux25~ 139
D AT AIN
d a ta B [1 5 ] dataB[15] M ux26~ 180 PAD O U T d a ta _ w r _ o u t[1 3 ]
! OE
d a ta C [0 ] dataC [0]
d a ta C [1 ] dataC [1] O U T PU T
d a ta _ w r _ o u t[1 2 ]
d a ta C [4 ] dataC [4] D AT AIN
PAD O U T d a ta _ w r _ o u t[1 2 ]
d a ta C [5 ] dataC [5] ! OE
O U T PU T
d a ta C [8 ] dataC [8] d a ta _ w r _ o u t[1 1 ]
D AT AIN
d a ta C [1 0 ] dataC [10] PAD O U T d a ta _ w r _ o u t[1 1 ]
! OE
s ta r t dataC [11]
c u r r _ s ta te .s 2
rw B dataC [12] O U T PU T
! AC LR
rw C dataC [13]
co m b~3 1 3 C LK d a ta _ w r _ o u t[1 0 ]
c u r r _ s ta te .s 3 C OM BO U T p e n a b le A dataC [14]
D AT AA D AT AB
re s e t ! AC LR R EG O U T D AT AA dataC [15] D AT AIN
D AT AC C O M BO U T D AT AD PAD O U T d a ta _ w r _ o u t[1 0 ]
c lk C LK c u r r _ s ta te .s 4 D AT AB C O M BO U T penableA ! OE
R EG O U T D AT AD SYN C H _D AT A co m b ~3 1 9
re q A D AT AA ! AC LR D AT AD penableB
LC ELL (AAF 0) LC ELL ( C F C 0) co m b ~3 2 0 D AT AA O U T PU T
re q B D AT AC C LK LC ELL ( 3322) penableC
D AT AA D AT AB
LC ELL ( 5050) D AT AA C O M BO U T d a ta _ w r _ o u t[9 ]
D AT AB R EG O U T D AT AC
C O M BO U T D AT AB
c u r r _ s ta te .s 1 D AT AC D AT AD D AT AIN
rw A D AT AC PAD O U T d a ta _ w r _ o u t[9 ]
! AC LR D AT AD LC ELL ( 32F F ) ! OE
D AT AD
C LK LC ELL (0100)
LC ELL ( 0100) co m b ~3 1 6 O U T PU T
D AT AA
R EG O U T D AT AA
D AT AB p e n a b le B d a ta _ w r _ o u t[8 ]
D AT AB
D AT AC C O M BO U T D AT AA
D AT AC D AT AIN
re q C D AT AD D AT AB C O M BO U T PAD O U T d a ta _ w r _ o u t[8 ]
D AT AD ! OE
LC ELL ( F F F E) D AT AD
LC ELL ( 5455)
LC ELL ( 5544) O U T PU T
co m b ~3 1 8
d a ta _ w r _ o u t[7 ]
D AT AA
co m b ~3 1 7 p e n a b le C
D AT AB D AT AIN
D AT AA C O M BO U T D AT AB PAD O U T d a ta _ w r _ o u t[7 ]
D AT AC ! OE
D AT AC C O M BO U T D AT AC C O M BO U T
D AT AD
D AT AD D AT AD O U T PU T
LC ELL ( 1044)
LC ELL ( F F A5) LC ELL ( 0F 0C )
d a ta _ w r _ o u t[6 ]
co m b ~3 1 5 D AT AIN
rw PAD O U T d a ta _ w r _ o u t[6 ]
D AT AA ! OE
D AT AA
D AT AB
C O M BO U T D AT AC C O M BO U T O U T PU T
D AT AC
D AT AD
D AT AD d a ta _ w r _ o u t[5 ]
LC ELL ( F A0A)
LC ELL ( F E00)
D AT AIN
PAD O U T d a ta _ w r _ o u t[5 ]
! OE
O U T PU T
d a ta _ w r _ o u t[4 ]
d a ta C [1 1 ]
d a ta C [1 2 ] D AT AIN
d a ta C [1 3 ] ! OE
d a ta C [1 4 ]
O U T PU T
d a ta C [1 5 ]
d a ta _ w r _ o u t[3 ]
D AT AIN
! OE
O U T PU T
d a ta _ w r _ o u t[2 ]
D AT AIN
! OE
O U T PU T
d a ta _ w r _ o u t[1 ]
D AT AIN
! OE
O U T PU T
d a ta _ w r _ o u t[0 ]
D AT AIN
! OE
O U T PU T
p r e s e n t~ 1 4
p r e s e n t[2 ]
D AT AB
C O M BO U T D AT AIN
D AT AD PAD O U T p r e s e n t[2 ]
! OE
LC ELL ( 0033)
O U T PU T
p r e s e n t[1 ]
D AT AIN
PAD O U T p r e s e n t[1 ]
! OE
O U T PU T
p r e s e n t[0 ]
D AT AIN
PAD O U T p r e s e n t[0 ]
! OE
O U T PU T
Flow Summary:
8
Simulation results:
Fig. Simulation output of priority interrupt memory management controller
9
COMPONENTS of MMU
MEMORY:
Entity:
Here we have taken 1 kb (1024

bytes) depth of 16 bit vectors. The
memory is accessed by only one
processor at a time which is ensured
by the multiplexer used...
RTL:
10
Technology view:
Flow Summary:
11
Simulation:
MUTLIPLEXER:
ENTITY:
The multiplexer selects the address

bus and the data bus depending on the
condition, i.e , among which of the
processors ,A B or C are enabled and
then it gives selects any one of the
processor depending on the previous
conditions and give it the excess to
memory…At a time only one
processors can get memory excess...
12
RTL:
Technology view:
13
Flow Summary:
Simulation:
14
VHDL CODE:
VHDL code of Main Programme – PRIORITY INTERRUPT MEMORY

MANAGEMENT
<MAIN.VHD>
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity main is
port( reqA,reqB,reqC:in std_logic;
clk,reset:in std_logic;
dataA,dataB,dataC:in std_logic_vector(15 downto 0);
addA,addB,addC:in std_logic_vector(9 downto 0);
data_rd_out:out std_logic_vector(15 downto 0);
--out from memory
present:out std_logic_vector(2 downto 0);
data_wr_out:out std_logic_vector(15 downto 0);
--out from mux
rwA,rwB,rwC:in std_logic;
start:in std_logic
);
end main;
architecture Behavioral of main is

component counter is
port(req:in std_logic;
enable:in std_logic;
finish:out std_logic; clk:in std_logic --cnt:out
integer
);
end component counter;
component memory is
port(r_w:in std_logic ;
data_in:in std_logic_vector(15 downto 0);
data_out:out std_logic_vector(15 downto 0);
addr_bus:in std_logic_vector(9 downto 0);
clk:in std_logic
);
end component memory;
component multiplex is
port(s:in std_logic_vector(2 downto 0);
data_busA:in std_logic_vector(15 downto 0);
data_busB:in std_logic_vector(15 downto 0);
data_busC:in std_logic_vector(15 downto 0);
15
addr_busA:in std_logic_vector(9 downto 0);
addr_busB:in std_logic_vector(9 downto 0);
addr_busC:in std_logic_vector(9 downto 0);
data_out_mux:out std_logic_vector(15 downto 0);
addr_out_mux:out std_logic_vector(9 downto 0));
end component multiplex;
signal data_out:std_logic_vector(15 downto 0);

signal add_out:std_logic_vector(9 downto 0);
type states is (s0,s1,s2,s3,s4);
signal next_state,curr_state:states;
signal
ackA,ackB,ackC,nenableA,nenableB,nenableC,penableA,penableB,penab
leC:std_logic :='0';
signal ll:std_logic_vector( 2 downto 0);
signal rw,preqA,preqB,preqC:std_logic;
begin
--combine bits to form sel line for mux
ll<=(penableA & penableB & penableC);
mult:multiplex port
map(ll,dataA,dataB,dataC,addA,addB,addC,data_out,add_out);
-- data_out and add_out from mux is feed to memory
-- data_rd_out is o/p from memory depending on rw
signal
mem:memory port
map(rw,data_out,data_rd_out,add_out,clk);
rr1:
process(clk,reset)
begin
if reset='1' then
curr_state <= s1;
elsif( clk='1' and clk'event) then
curr_state<=next_state;
end if;
end process rr1;
control_path:
process(curr_state,reqA,reqB,reqC)
variable temp : std_logic_vector(2 downto 0);
begin
temp := (reqA & reqB & reqC);
case curr_state is
when s0 =>
present<="ZZZ";
if( start='1')then
next_state<=s1;
else next_state<=s0;
end if;
when s1 =>
present<="ZZZ";
16
if(temp(2)='1')then --reqA
next_state<=s2;
elsif(temp(1)='1')then --reqB
next_state<=s3;
elsif(temp(0)='1')then --reqC
next_state<=s4;
else
next_state<=s1;
end if;
when s2 =>
present<="100";
if(( reqA='0')and temp(1)='1')then
next_state<=s3;
elsif(( reqA='0')and temp(0)='1')then
next_state<=s4;
elsif temp="000" then
next_state<=s1;
else
next_state<=s2;
end if;
when s3 =>
present<="010";
if(reqA='1') then
next_state <= s2;
elsif((reqB='0')and temp(0)='1')then
next_state<=s4;
next_state<=s1;
else
next_state<=s3;
end if;
when s4=>
present<="001";
if(reqA='1') then
next_state <= s2;
elsif (reqB ='1' and reqA = '0') then
next_state <= s3;
next_state<=s1;
else
next_state<=s4;
end if;
end case;
end process control_path;
data_path:process(curr_state,rwA,rwB,rwC,data_out)
begin
if(curr_state=s1)then
penableA<='0';
penableB<='0';
penableC<='0';
elsif(curr_state=s2)then
17
penableA<='1';
penableB<='0';
penableC<='0';
rw<=rwA;
penableA<='0';
penableB<='1';
penableC<='0';
rw<=rwB;
penableA<='0';
penableB<='0';
penableC<='1';
rw<=rwC;
end if;
data_wr_out<=data_out;
end process data_path;
end Behavioral;
VHDL code of MEMORY:
<MEMORY.VHD>
library IEEE;
entity memory is
port(r_w:in std_logic ;
data_in:in std_logic_vector(15 downto 0);
data_out:out std_logic_vector(15 downto 0);
addr_bus:in std_logic_vector(9 downto 0);
clk:in std_logic);
end memory;
architecture Behavioral of memory is

type mem is array (2**10-1 downto 0) of std_logic_vector
(15 downto 0);
--signal ram_output:std_logic_vector(15 downto 0);
signal RAM : mem:=(others=>(others=>'0'));
begin
p1: process(clk,r_w)
begin
if(clk'event and clk='1')then
if(r_w='1') then
--read from address
data_out<=RAM(conv_integer(addr_bus));
elsif(r_w='0')then
RAM(conv_integer(addr_bus))<=data_in; --
write at given address
18
end if;
end if;
end process p1;
end Behavioral;
VHDL CODE of MUNLTIPLEXER:
<MULTIPLEX.VHD>
library IEEE;
entity multiplex is
port(s:in std_logic_vector(2 downto 0);
data_busA:in std_logic_vector(15 downto 0);
data_busB:in std_logic_vector(15 downto 0);
data_busC:in std_logic_vector(15 downto 0);
addr_busA:in std_logic_vector(9 downto 0);
addr_busB:in std_logic_vector(9 downto 0);
addr_busC:in std_logic_vector(9 downto 0);
data_out_mux:out std_logic_vector(15 downto 0);
addr_out_mux:out std_logic_vector(9 downto 0));
end multiplex;
architecture Behavioral of multiplex is

begin
with s select
data_out_mux <= data_busA when "100",
data_busB when "010", data_busC when "001",
(others=>'Z') when others;
with s select
addr_out_mux <= addr_busA when "100",
addr_busB when "010",
addr_busC when "001",
(others=>'Z') when others;
end Behavioral;
19
CONCLUSIONS
I. Memory can be simultaneously serviced to multi processes.
II. Being an Interrupt service procedure, time of processor is

managed efficiently.
III. FPGA/VHDL combination is a very powerful design tool.

-- Versatile, Adaptable, Efficient, Economic
IV. The given algorithm can be used to implement process

scheduling.
References
1. A VHDL Primer, 3rd edition : J. Bhasker
2. Computer Organization and Architecture: William Stallings
20

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MEMORY MANAGEMENT

(INTERRUPT PRIORITY APPROACH)

SUBMITTED TO THE FACULTY OF

NATIONAL INSTITUTE OF TECHNOLOGY, WARANGAL (A.P)

AMIT KUMAR KARNA (04403)

Under the Guidance of

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

We would like to express our sincere thanks to our

Amit Kumar Karna (4403)

For our EDA-II project we developed a “Memory Management Controller”

An exclusion device is a controller that allows a common resource such as

We chose this project because it is an ambitious project aimed to challenge

Three processors are required to time share a Synchronous RAM

Overall Goal: Memory Management Control

Goal: Produce a successful realization of memory management

Sub Goal 1: Develop individual components

We successfully reached sub goal 3 except that we did not

 VHSIC Hardware Definition Language.

DESIGN Unit Names

 Benefits of using FPGA

Hierarchy ‘n’ fpga occupancy

In this algorithm, A is having the highest

Fig. Simulation output of priority interrupt memory management controller

Here we have taken 1 kb (1024

The multiplexer selects the address

VHDL code of Main Programme – PRIORITY INTERRUPT MEMORY

architecture Behavioral of main is

signal data_out:std_logic_vector(15 downto 0);

VHDL code of MEMORY:

architecture Behavioral of memory is

VHDL CODE of MUNLTIPLEXER:

architecture Behavioral of multiplex is

II. Being an Interrupt service procedure, time of processor is

III. FPGA/VHDL combination is a very powerful design tool.

IV. The given algorithm can be used to implement process

2. Computer Organization and Architecture: William Stallings

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