LESSION PLAN 2-1

Topics in each unit as per

JNTU syllabus

Lecture
No.

Modules & sub modules for

session plan for each topic

Text Books/
Reference Books

UNIT I: NUMBER SYSTEMS AND CODES

1

Discussion of the overall syllabus,

books to be referred and various
competitive exams related to the
subject

Decimal, Binary numbers, number

base conversion

T1 : 1.1
T2 : 1.2, 1.3
R2 : 1.1, 1.2
R3 : 1.7
R5 : 2.1, 2.3

Octal, hexadecimal numbers and

conversions

T2 : 1.4
R3 : 1.8
R4 : 2.4, 2.5
R5 : 2.7, 2.8

Complement representation
of negative numbers

1s and 2s complements with

examples

T2 : 1.5
R2 : 1.4
R5 : 2.6

Tutorial

Problems on above topics

(r-1)s and rs complement with

examples

2
Philosophy of number
systems

Complement representation
of negative numbers
(contd.)

T2 : 1.5
R4 : 2.8

Binary arithmetic

Binary codes

Error detecting

10

Addition, subtraction of binary

numbers: arithmetic and using
complements, signed binary
numbers

T2 : 1.6, 1.7
R2 : 1.3
R3 : 1.10
R4 : 2.3, 2.9

Decimal codes, binary codes:

weighted and non-weighted codes

T1 : 1.2
T2 : 1.7
R2 : 7.5
R3 : 1.9
R4 : 2.10
R5 : 2.9

Error detecting codes: concept of

parity bits, Gray code, ASCII code

T1 : 1.3
T2 : 1.7
R4 : 2.11
R5 : 2.10.1

Tutorial

UNIT II: BOOLEAN ALGEBRA AND SWITCHING FUNCTTIONS

Error correcting codesHamming code

11

Hamming code

Fundamental postulates of
Boolean Algebra

12

Definition of Binary logic,

Switching circuits and binary
signals and postulates

Basic theorems and

properties

13

Duality, basic theorems and

De Morgans laws

14

NOT, AND, OR, NAND, NOR

gates

15

Universal gates, EX-OR, EX-NOR

gates, odd function

16

Discussion on the earlier topics

17

Implementation of Other gates using

NAND, NOR gates

18

Multilevel NAND, NOR realization

Canonical and standard

forms

19

Min-terms and max-terms, sum of

min-terms, product of max-terms,
Conversion between canonical
forms, standard forms

Algebraic simplification

20

Logic operations

21

Tutorial

Switching functions

Tutorial

Switching functions (contd.)

T1 : 1.3
R4 : 2.12
R5 : 2.10.2
T1 : 3.1
T2 : 1.9
R2 : 2.1-2.3
R3 : 2.2.1-2.2.8
R4 : 3.1
T2 : 2.1,2.3
R2 : 2.4-2.8
R3 : 2.2.12
R4 : 3.2
R5 : 1.6
T1 : 3.2
T2 : 2.7, 4.9
R4 : 3.9.6, 3.9.7
R5 : 1.3-1.5

T1 : 5.3
T2 : 2.7, 3.6, 3.7,
4.7, 4.8
R2 : 7.1-7.4
R3 : 2.5
R4 : 3.9
T1 : 3.2
T2 : 2.5
R3 : 3.2
R4 : 3.5
T2 : 2.6
R4 : 3.6

UNIT III: MINIMIZATION OF SWITCHING FUNCTIONS

Map method

22

Representation of functions: Two

variable k map and its examples

23

Three variable k map and its

examples

T1 : 4.2
T2 : 3.1
R2 : 5.2
R3 : 3.4
R4 : 4.4.1
R5 : 5.3, 5.4
R3 : 3.4.1
R4 : 4.4.2

24

Four variable k map and its

examples

T2 : 3.3
R2 : 5.3

25

Five variable k map and its

examples

T1 : 4.1
T2 : 3.4
R3 : 3.4.2
R4 : 4.7.1
R5 : 5.10

26

Tutorial

Prime implicants

Definition and significance

27
Significance and examples on dont
care condition

Dont care combinations

Minimal SOP and POS

forms

28

Sum of products simplification

29

Product of sum simplification

30

Tutorial

Tabular method

Need of the method

31

Prime implicants chart and

Determination of prime implicants
Simplification rules
UNIT IV: COMBINATIONAL LOGIC DESIGN

Design using conventional

logic gates

32

Design of half and full adder

33

Design of subtractor, Code

converter

Encoder

34

Basic need, working and types of

encoders

Decoder

35

Basic need, working and types of

decoders

Tutorial

36

Discussion on the above topics

T2 : 3.3
R2 : 5.4, 6.1
T1 : 4.2
T2 : 3.8
R3 : 3.4.5
R4 : 3.8
R5 : 5.7
T2 : 3.5
R3 : 3.4.6
R4 : 4.5.3, 4.5.4
R5 : 5.5, 5.6
T1 : 4.4, 4.5
T2 : 3.9, 3.11
R3 : 3.5
R4 : 4.8
R5 : 5.11
R2 : 6.2
R4 : 4.10
T1 : 5.1, 5.4
T2 : 4.1-4.4
R3 : 4.6
R5 : 6.5
T2 : 4.5, 5.2, 5.3
T2 : 5.5
R2 : 9.4
R3 : 4.4
R4 : 5.5
R5 : 6.10
R3 : 4.3
R4 : 5.4
R5 : 6.11

T2 : 5.6
R2 : 9.2
R3 : 4.5
R4 : 5.6
R5 : 6.2.1
T2 : 5.5
R5 : 6.3
T1 : 5.2
R3 : 4.6

Multiplexer

37

Study of various multiplexers: 2x1,

4x1, 8x1, 16x1

De-Multiplexer

38

Study of various de-multiplexers

Modular design using IC

chips

39

Design of various digital circuits

using Ics

40

Implementation of Boolean
functions using mux

41

Tutorial

Parity bit generator

42

Basic need and study of parity bit

generator

T2 : 4.9
R5 : 16.8

Code converters

43

Implementation of various code

converters

T2 : 4.5
R5 : 6.9

44

Hazards to digital circuits, Faults

and fault detection

T1 : 8.1, 8.2, 8.5,

8.8
R2 : 8.1-8.5
R3 : 4.11

45

Tutorial

MUX realization of
switching functions

Hazards and hazard free

realizations

T2 : 8.5
R3 : 4.5.1
R4 : 5.6.1
R5 : 6.2.2

UNIT V: PROGRAMMABLE LOGIC DEVICES, THRESHOLD LOGIC

T2 : 5.7
R2 : 9.5, 9.6
R3 : 9.1
Basic PLDs- ROMs
46
Basic structure of ROM and PROM
R4 : 5.7, 5.8
R5 : 11.5-11.6,
12.2
T2 : 5.8
Basic structure of programmable
R3 : 9.3.1
PLA
47
logic array
R4 : 5.9
R5 : 12.3
R3 : 9.3.2
PAL
48
Programmable logic array structure R4 : 5.10
R5 : 12.4
Realization of Switching
Use of Programmable logic devices R2 : 16.4
49
R3 : 9.3.3, 9.5
functions using PLDs
for designing of various circuits
Tutorial
Capabilities and limitations
of threshold gates
Synthesis of threshold
functions
Multigate synthesis

50

Discussion on the above topics

T1 : 7.1, 7.2

51

Introducing concept of threshold

gates and synthesis of threshold
function

UNIT VI: SEQUENTIAL LOGIC DESIGN I

Synchronous
Classification of Sequential
52
circuits
Asynchronous

T2 : 6.1
R2 : 11.1
R3 : 5.1
R4 : 6.1, 6.2

Pulse mode (flip flop)

Level mode (latch)

Basic flip flops- Triggering

and excitation tables

Steps in Synchronous
sequential design
Design of Modulo-N Ring
and shift counters

53

RS latch, RS flip flop, JK FF

D, T FF and conversion of FFs

54

Triggering of FF, master slave FF

55

Tutorial

56

Shift registers, steps in designing of

sequential circuits

57
58

Designing of various counters (using

FFs and shift registers)

Serial binary adder

Sequence detector

59

Designing of serial binary adder and

sequence detector

60

Tutorial

T1 : 9.2, 9.3
T2 : 6.2, 6.3
R2 : 11.2-11.7
R3 : 5.2R4: 6.4,
6.5
R5 : 7.1-7.9
T2 : 6.4, 6.7
R2 : 12.2
T2 : 6.8
R2 : 12.3-12.5
R4 : 6.8, 6.9
R5 : 8.2-8.4
R3 : 4.6.1, 4.6.2
T1 : 9.4
R2 : 14.1
R3 : 6.4.2
R4 : 7.3.3

UNIT VII: SEQUENTIAL LOGIC DESIGN II

Finite state machine
Capabilities and limitations.
Mealy and Moore models

Minimization of completely
and incompletely specified
sequential machines

61

State machine notations, present

state, next state, Mealy, Moore state
machine, state diagram

62

State tables, transition and excitation

tables, analysis of sequential circuits

63

Design example of sequential circuit

64

Elimination of redundant states

65

Tutorial

Partition techniques and

Merger graphs, equivalent state
66
merger chart methodsassignments
concept of minimal cover
67
State assignment techniques
table
UNIT VIII: ALGORITHMIC STATE MACHINES
Salient features of ASM
chart

68

ASM chart, various blocks in ASM

chart, register operations

Simple examples

69

Timing considerations and examples

of ASM chart

70

Tutorial

71

State assignments, ASM tables

72

State tables, logic diagrams with flip

flops, ASM realizations

73

Tutorial

System design using data

path and control subsystems
Control implementationsexamples of Weighing
machine and binary
multiplier

T1 : 9.2, 10.2
T2 : 6.4
R2 : 13.3
R3 : 6.1, 6.2.1,
6.2.2
R4 : 7.1
T1 : 10.3, 10.4
R2 : 14.3, 15.115.5
R3 : 6.2.3, 6.2.4,
6.2.5, 6.3
R4 : 7.4
R2 : 15.7, 15.8
R3 : 7.3.1, 7.4

T2 : 8.1, 8.2
R3 : 7.5.1
R4 : 8.1, 8.2
T2 : 8.3
R3 : 7.5.2
R4 : 8.3
R4 : 8.4, 8.5
T2 : 8.4
R4 : 8.6

REFERRED BOOKS:
TEXT BOOKS:
T1: Zvi Kohavi, Switching and Finite Automata Theory, 2nd Edition, Tata Mc Graw Hill
Publications, 2003.
T2: M.Morris Mano, Digital Design, 2nd Edition, Pearson Education/PHP, 2001.
REFERENCE BOOKS:
R2: Roth, Fundamentals of logic design, 5th Edition, Thomson Publications, 2004
R3: John M. Yarbrough, Digital Logic Applications and Design, 1st Edition, Thomson
Publications, 2006
R4: Donald D Givone, Digital Principles and Design, 1st Edition, Tata Mc graw Hill, 2002
R5: R.P. Jain, Modern Digital Electronics, 3rd Edition, Tata Mc Graw Hill Publications, 2005