485

A Fully Differential Switched-Current

Delta-Sigma Modulator Using a Single
3.347 Power-Supply Voltage
Nianxiong Tan and Sven Erilrsson
Dept. of Electrical Engineering
Linkming University
S-581 83 Link6ping

Sweden
ABSTRACT

This paper presents the design of a fully differential secondorder delta-sigma modulator using a single 3.3-V powersupply voltage. At the system level, we tailor the modulator
structure considering the similarity and difference of
switched-capacitorand switched-current realizations.At the
circuit level, we propose a new switchedcurrent memory cell
and integrator with improved common mode feedback,
without which low power-supply-voltage operation would
not be possible. Other building blocks such as 1-bit A/D and
D/A converters are presented as well. The whole modulator
has been implemented in AMs 0.8-pm double-metal digital
CMOS process. It occupies an active area of 0.53 x 0.48
mm2 and consumes a current of 0.6 mA.
I. INTRODUCTION

Delta-sigma modulation has been employed in oversampling

A D converters. It has been dominantly realized by using the
switched-capacitor (SC) technique [ll. However, when the
power-supply voltage is decreased to 3.3 V or ever lower, the
design of SC delta-sigma modu18tots is a difficult task due to
the reduced voltage swings that are limited by the powersupply voltage. The charging and discharging of large
capacitors become even more painfur with reduced powersupply voltage, which in turn makes high-frequency
operation suffer. The current-mode technique by contrast
features inherent high-frequency operation capability. In
current-mode technique, the swing of signals represented by
currents is not limited by the power-supply voltage. And
floating linear capacitors are not needed, which makes
current-mode circuits more compatible with standard digital
process [2].

A transistor-only current-mode &A modulator has been

proposed [3]. But the circuits utilized high-gain stages like
in SC circuits, thereby losing the power and area advantages
sought possible with switchedcurrent (SI) circuits. An SI
sigma-delta modulator has also been proposed 141. Since
there were not delays in both integrators, the settling of the
two integrators and the comparator coupled with each other.
They had to settle within their final values during the same
clock phase and thus the high-freqwncy operation degraded.

Another drawback was that a fdZy differential structure was

not employed. The differential realization was achieved only
by hardware replica without common mode feedback
(CMFB). The rejection of common-mode signals was poor.
Modem digital CMOS processes usually use a heavily doped
substrate upon which an epitaxial layer is grown. Switching
noise generated by the digital circuits on the same chip can
directly couple into the analog circuits via the low-resistance
substrate. And protection of guard rings is much less
effective [5]. The coupled switching noise is a commonmode signal to the analog circuits. Without efficient
common-mode rejection. any analog circuits in a mixedmode system are almost doomed to fail. Integrating both
analog and digital circuits on the same chip makes the fully
differential structure the only choice for analog circuits, even
though the price that has to be paid is the increased chip area
and power consumption compared with the single-ended
structure.

In this paper, we present the design of a fully differential

second-order SI delta-sigma modulator using a single 3.3-V
power-supply voltage. Following this introduction, Section
11describes the modulator structure tailored for SI realization.
Section 111 presents the fully differential SI integrator with
CMFB. Section IV outlines other modulator subcircuits
including the 1-bit current quantizer and 1-bit D/A converter.
Section V presents the complete modulator circuit. Then
conclusionsarrive.

II. MODULATOR STRUCTURE

The architecture of this delta-sigma modulator is based on
former works [l, 61 that have documented the favorable
stability and component t o l m c e characteristics of a secondorder modulator. It consists of two discrete time integrators,
a current quantization circuit, and a pair of current output
D/A converters, as shown in Fig. 1. The integrator transfer
function in this structure differs f those used in [4] by
having delays from input to output. Thus. the two
integrators and comparator do not settle during the same
clock phase.
With the modulator described here, the input signal of Fig.
1 , 4 r ) is a current and the output y(kT) is a voltage having
CMOS logic levels. The quantizer produces the 1-bit signal

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486

by sensing the direction of current flow from the second

integrator. To feedback the quantized signal, y(kT) is used as
an input to a pair 1-bit D/A converters, one feeding the first
integ" and the other feeding the second integralor.

common-mode range larger, but reduce the gain of GGAs and

thus reduce the input conductance of the memory cell. A
badeoffsbwldbemade.

g5 I
I

Fig. 1. Modulator structure.

In an SC integrator. the scaling factor is directly realized by

changing the ratio of the integration capacitor and the
sampling capacitor. However, in an SI integrator, integration
and scaling are done separately. Scaling can either precede or
follow integration, but it makes a difference conceming
dynamic amplitude range. Unlike the reportedmodulator in
[3], the feedback to the fmt integrator is not scaled down and
thus higher input amplitude range is achievable, because the
input amplitude range is limited by the feedback level fed to
the first integrator. Before feeding to the second integrator,
we scaled down the signal and distribute it to both input
paths. (One is from the output of the first integrator, and the
other is from the feedback.) System level simulation
indicates that the modulator gives a good performance
concerning the dynamic amplitude range and the SNR.

III. SI INTEGRATOR
Fully differential circuits have well-known advantages in
signal processing. Where signal inversion is required, it is
achieved by a simple crossconnection of the signals. More
important, common-mode signals, such as crosstalk from
digital circuits on the same chip, are rejected. In SI memory
cells, fully differential circuits bring the added advantage of
reducing charge injection mrs. All these advantagesjustify
the use of differential circuits in spite of the fact that more
chip area and power consumption are needed compared with
single-ended circuits. A new fully differential memory cell
with CMFB is shown in Fig. 2.

To decrease the transmission error, we use grounded-gate

amplifiers (GGAs) 171 to increase the cell's input
conductance rather than use cascode [8] or regulated cascode
circuits 191to reduce the cell's output conductance.
The memory cell comprises two memory transistors,current
sources for the memory transistors, two GGAs, and a level
shifter. The GGA comprises the grounded-gate transistor TG
and cascoded current bias transistors Tc and
If the gain
of the GGAs is high then the voltages at the summing nodes
are close to a constant value V , = Vfi+ V,, where VgsG is
the quiescent gate-source voltage of transistor TG. This
arrangement creates a "virtual earth" at the input nodes. The
voltages of the output nodes are fixed at the input voltages
of the driven cell. The biasing currents for the GGAs
& m i n e the common-mode range. Larger currents make the

m.

Fig. 2.Full differential memory cell with CMFB

The level shifter comprises the transistor TL and its biasing

transim. The CMFB is accomplished via the level shifter.
Any common-mode component (including clock
feedthrough) present at the input signals is detected at the
common source node of the memory transistors M by the
gate of the
The source voltage of
follows its gate
voltage and a voltage level shifting is realized. Thus the gate
voltage of TN is changed to adjust the biasing current to
reduce the common-mode signals. The main difference
between this new fully differential memory cell and the one
published in [lo] is the use of the level shifter. In [lo], the
voltage of the common source node of the memory
rransistors was larger than necessary in order to make the
biasing transistors for GGAs in saturation. This made low
power-supply-voltage operation impossible given the
threshold voltages around 1 V. In the new cell, the voltage
of the common source node can be much lower than the
threshold voltage (It must be larger than the saturation
voltage of the biasing transistor TZJ) due to the use of the
level shifter. Now low power-supply-voltage operation is
achievable.

n.

With reduced power-supply voltage, switches should be paid

special attention. In SI circuits, potential changes are very
small compared with SC circuits. Transmission gates should
not be used, since under no circumstances can both the p and
n transistors open. Instead, we use n-typepass transistor for
switches where the DC operating voltage is low, p-type pass
transistor for switches where the DC operating voltage is
high. (In the memory cell, no switched node has DC
operating voltage in the vicinity of Vd@) The sizes of the
switch transistors are dimensioned considering the operating
frequency and parasitic capacitances at the switched nodes.
Dummy switches are also used to reduce clock feedthrough.
Note that the switches S, Si and S' should be phased to
ensure that S (and S+)opens momentarily before Si opens.

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487

To guarantee proper opedon, all the transistors should be

in saturation region. DC operation points are optimized to
make the sourcedrain voltage of every @a"l
arge than
its saturation voltage plus a design margin. To reduce mise
introduced by transistors, tbe SatUraMn voltages of memory
transistors and biasing transistorS should be designed to be as
large as possible. The input current range is limited by the
biasing currents. With careful optimization, the differential
inputs can be as large as 95% of the biasing currents without
significant distortion.
The lossless integrator is straightforward. cascading two
memory cells and feeding back the output of the second
memory cell to the input of the first memory cell result in a
lossless integrator. The GGAs and the level shifter are shared
by the two memory cells. We show the lossless integrator in
Fig. 3.

of the other input tnursistor. The voltages at the differential

nodes ramp in inverse direction towards Vdd or zero,
respectively. The differential voltage at the comparator
inputs thus change according to the direction of the current
flows and the outputisproducedaccordiag to thedifTerential
voltage.
1

vaa

Fig. 4. 1-bit current qkntizer with differential input.

4.2. DIA converter

The D/A Coavemrs generate two equal current outputs with
different flowing direction according to the 1-bit digital
input. Current sources are the choice. Considering the
structure of the integrators, the 1-bit D/A converter is
proposed as shown in Fig. 5.

Vdd

1: a Current Mirror

Fig. 3. Fully differential lossless inkpator with CMFB.

With clock phases indicated in the figure, the transfer

function in the z-domain is given by
1

-m

IV. OTHER MODULATOR SUBCIRCUITS

4.1.1-bit current quantizer

With 1-bit quantization as used in this modulator, only the

direction of current flow from the second integrator needs to
be determinedby the quantize. A Simple inverter can be used
to detect the current flow direction as proposed in [41. For
fully differential current inputs, we use a two-stage voltage
comparator with differential input as shown in Fig. 4.
The currents from the second integrator charge or discbarge
the gate parasitic capacitance of the input transistors of the
comparator depending on the direction of the currents. When
one branch of the differential outputs from the second
integrator charges the gate parasitic capacitance of one input
transistor, the other discharges the gate parasitic capacitance

Fig. 5. 1-bit D/A convertg &I differential output.

The two output currents change flowing direction according

to the 1-bit digital input. Since the currents are fed to the
integrators, the nodal voltages at the outputs are fixed due to
the GGAs in the integrators. Thus the output currents are
quite stable. Small DC offset current may exist due to
process variation, but this offset does not present any
problem for 1-bit delta-sigmamodulatars111.

V. COMPLETE MODULATOR
With the system configuration and all the building blocks
available, it is easy to construct the modulator. According to
system-level simulation, the dynamic range for both
integrators should be at least two times the feedback
currents. (Notice that scaling and integration are done
separately as contrast to the SC realization.) We choose the

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488

feedback current 10 pA and the biasing current for the

memory transistor pairs 50 pA to have some design margin.
Attention must be paid to the output mirrors of the
integrators. The voltage change at the output node will
introduce transmission error not only due to the resulting
variation in biasing currents, but also due to the variation in
the gate voltage of the memory transistors owing to the
presence of the gate-drain parasitic capacitance of the mirror
transistors (see Fig. 3). Thus, for the first integrator, a load
should be provided on the phase when the first integrator
output is not fed to the second integrator. For the second
integrator, the output can never drive the current quantizer
directly. It would introduce excessive error in the integration
(not just in scaling). Therefore, an extra mirror is employed
to drive the current quantizer. On the phase when the current
quantizer is activated, this current mirror is disconnected
from the integrator to avoid introducing error in the
integrator via the gate-drain parasitic capacitance of mirror
transistors.
The microphoto of the test chip is shown in Fig. 6. The
whole modulator occupies an active area of 0.53 x 0.48
mm2 and consumes a current of 0.6 mA.

The whole modulator has been implemented in AMS0.8pm double-metal digital CMOS process. It occupies an
active area of 0.53 x 0.48 mm2 and consumes a current of
0.6 mA. We are currently constructing a PCB of
measurement for the test chip. Measurement results will be
presented at the conference talk.
ACKNOWLEDGMENTS

This work was financially supported by the Swedish

National Board for Industrial and Technical Development
(NUTEK).The valuable discussions with H. Triiff and B.
Jonsson are highly appreciated.
REFERENCES

J. C. Candy and G. C. Temes, Oversampling DeltaSigma Data Converters: Theory, Design and
Simulation. IEEE Press, 1992.

C. Toumazou. F. J. Lidgey, and D. G. Haigh,

Analogue IC Design: the current-mode approach. Peter
Peregrinus Ltd., 1990.
S . J. Daubert and D. Vallancourt, A transistor-only
current-mode C-A modulator, IEEE J. Solid-State
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P. J. Crawley and G. W. Roberts, Switched-current
sigma-delta modulation for A D conversion, in IEEE

Proc. ISCASP2, pp. 1320-1323, May 1992.

D. K. Su, M. J. Loinaz, S . Masui, and B. A. Wooley,

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D. Groeneveld, et al., Self-calibrated technique for

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Circuits, vol. 24, pp. 1517-1522. Dec. 1989.
Fig. 6. The microphoto of the test chip.

VI. CONCLUSIONS

In this paper, we have presented the design of a fully

differential SI modulator with a single 3.3-V power-supply
voltage. Considering the specialty of SI realization, we have
tailored the modulator structure. To make low power-supplyvoltage operation possible, we have proposed a fully
differential SI memory cell (and SI integrator) with CMFB
containing a level shifter. Other building blocks such as 1bit current quantizer with differential input and l-bit A/D
converter with differentialoutput have also been proposed.

G. Wegmann and E. A. Vittoz, Very accurate dynamic

current mirrors, Electron. Lett. vol. 25, pp. 644-646,
1989.
C. Toumazou, J. B. Hughes, and D. M. Pattullo.
regulated cascode switched-current memory cell,
Electron. Lett. vol. 26, pp. 303-304, 1990.
J. B. Hughes and K. W.Moulding, Switched-current
signal processing for video frequencies and beyond,
IEEE J. Solid-state Circuits, vol. 28, pp. 314-322,
Mar. 1993.

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