ASSIGNMENT ON CADANCE TRAING NIT SILCHAR

SUBMITTED BY
RAHUL CHAHARIA
SUMIT PALIWAL
SAUMEN DEB
MAYURAN PARANIRUPASINGAN

AIM: To design Layout and Post layout inverter.

STEPS:
LAYOUT DESIGN(BACK END DESIGN):
1. Go to the working folder and open in terminal.
$ csh
$Source cadence.cshrc
$ virtouoso &
2. In virtuoso go to the tools-- library manager-----> select own library which schematic
made earilier and open the schematic.
3. For layout design we need schematic of the circuit and we have to remove all VDD and
GND supply and add pin of VDD and GND before going forward to layout.
4. In schematic go to launch ----> Layout XL
One window will arise
Creat new
(automatic
Click Ok.
5. Go to connectivity-Generate--- Alll from source.
Shift F (to view inside the MOS).
We can delete the pins and boundary.
All PMOS and NMOS in same quadratic.
For polly(po1 ingdraw) and metal (me1 drawing).
Options------>display(one window is come).
X snaps =0.01
Y snaps =0.01
Click OK.
6. Select the poly and Press R(only click where you have draw and just left click and move
the mouse).
7. For VDD ME1 selected Press R and Draw VDD.
8. For GND ME1 selected Press R and Draw GND.
9. For create N-well----press O-----> M1_NDDIF or M1_NWEL.
For create P-well --press O----> PM1_PDIFF.
10. For input poly selected and output ME1. Presss R and draw.
11. For via poly and Metal 1.

Press o----> M1- Poly.(Creat a metal in input to give input)

12. Go to create - pins name as *input then pins name as *output.

For vdd create - pins- vdd--- innout draw a rectangle
For gnd create - pins- gnd--- innout draw a rectangle.
13. For level
Create go to level ----> level 1---> vdd.
Create go to level ----> level 1---> gnd.
14 Design finished.
15.Save.
16. For analysis------> Assura-----> run DRC-----> select technology UMC_18_CMOS
*Rule set DRC and press OK.
17. For error checking in window click right arrow.
* Press K for measureing width.
18. Assura------> Run LVS ----> select technology UMC_18_CMOS----> Rule set LVS
Prees OK.
Next go to the schematic and open it it check the mismatch of cicuit.
19. For Paracitic extraction go to assura -- run RCX -----> window will appear
Type RC.
Coupled mode ----> couple.-----> press OK.
Ref Node -- GND.
Click OK.
Setup----> output------>extracted view
Open av_extraced (from libray manager and click the file zoom then see the resistance and
capacitance inside)
NOTE: For connecting Metal 1 and Metal2 or metal to poly alaways use via.

N well selected Press Q give column 10 (You find no of well).

FOR POST LAYOUT SIMULATION :

1. For post layout simulation following files are required and disply in view-------->
Symbol
Layout
Av_extracted
Schematic
2. Go to tools ----> library ---> cell view and check above file.
3. File ---> cell view-----> Give cell name e.g.----> test_inverter-- press OK.
4. New schematic will appear and Prress I (Symbols are called)
5. Two symbols are required(one for layout and one for schematic).
Short the input.
Short the vdd.
Short the gnd of both.
Keep the output terminal individualy.
6. Give pins.
Vl for voltage for layout.
Vs for voltage for schematic.
7. Give pulse(go to analog library).
0v, 1.8v, 20ns, 10ps, 10ps, 10n
8. Go to file----> new---> cellview
Type- config--- press OK.
One window is open and use template.
Name--> spectre.
View-----> schematic.
Press OK.
Another window is come.
9. Go to tree view and select IO(eg inverter_design).----> Right click----> Set instance
view----> av_extracted.
10. Next go to symbol ---> Right click -----> schematic
11. Then save and close window.
12. Library-----> selected open config.
After this you see above one is layout and below one is schematic.
For Simulation:
Repeat the simulation steps------>

Observe the VL and VS (output voltage of layout & schematic)

VL is always lagging than VS.(It is because of RC mainly capacitance)

SCHEMATIC:

LAYOUT:

RCX

POST LAYOUT: