Академический Документы
Профессиональный Документы
Культура Документы
Workpackage WP3
TTU_DOFSIM
Tool destination:
The goal of the tool is to simulate functional faults for logic level
variables and to create the functional fault table.
Tool description:
Tool platform:
Program. language:
Command:
var_analyze
Input:
Output:
test patterns including fault analysis result for each low level block
(.tst).
Syntax:
var_analyze <design>
design:
Tool acronym:
TTU_MAFFAD
Tool destination:
The tool reads the fault table of functional faults of the circuit and the
defect tables of components of the circuit and calculates the defect
coverage (both, probabilistic and enumerative).
Tool description:
The inputs of the program are the fault table of functional faults
created as the result of the functional fault simulation tool
TTU_DOFSIM, and the defect table of components. The defect
tables should be pregenerated. In this project the pregeneration of
defect tables will be done by the partner CO1-WUT for a given set of
selected complex gates or components. The defect tables are stored
as library components. For each component the very costly analysis
of physical defects to create the defect table will be done only once.
The pregenerated results (the library defect table) will be used by the
tool TTU_MAFFAD each time where a component should be
analyzed. Such a hierarchical approach allows tremendously increase
the efficiency of simulation. In fact the complexity of the defect
simulation will be reduced to the complexity of the SAF simulation.
Tool platform:
Program. language:
Command:
deforient
Input:
SSBDD model file (.agm), test pattern file (.tst), defect tables for the
low-level blocks.
Output:
Syntax:
deforient <design>
design:
Tool acronym:
TTU_DOFGEN
Tool destination:
The tool generates test patterns for all the physical defects of the
circuit described in the pregenerated library defect tables.
Tool description:
Tool platform:
Program. language:
Command:
randomgen
Input:
Output:
Syntax:
design:
options:
-length <x>
Tool acronym:
TTU_SIMBIST
Tool destination:
Tool description:
Tool platform:
Program. language:
Command:
bist
Input:
Output:
Syntax:
[-
or
bist gpoly <generator_poly> -ginit <generator_init> [
apoly <analyzer_poly> -ainit <analyzer_init>] [options]
<design>
design:
generator_length:
analyzer_length:
generator_poly:
generator_init:
analyzer_poly:
analyzer_init:
options:
-rand
Tool acronym:
TTU_HYBCAN
Tool destination:
The tool emulates the given BIST architecture, fault simulates the
given circuit for the given sequence of pseudorandom test patterns,
calculates the fault coverage and total costs of hybrid BIST for the
given breakpoints of the test sequence.
Tool description:
Tool platform:
Program. language:
Command:
hybcost.sh
Input:
two test pattern files (.tst) from BIST emulator and deterministic
generator and SSBDD model file (.agm)
Output:
Syntax:
design:
inp1:
inp2:
10
Tool acronym:
TTU_DERRIN
Tool destination:
Tool description:
This tool is based on the EDIF format converter from the Turbo
Tester package. The input of the converter is the design description in
EDIF format. The output is the internal Turbo Tester format a
special kind of decision diagrams. TTU_DERRIN tool is an add-on
to the EDIF converter. It analyzes the structure of the design and
inserts a single design error into. The output of TTU_DERRIN tool is
two files. The first one is the correct design while the second is the
design which contains an error.
Tool platform:
Program. language:
Command:
xtimport
Input:
Output:
Syntax:
options:
-paths
-spec
-read_iscas89
-gate_level
-tool <application>
-gnd <gnd name>
-vdd <vdd name>
11
Tool acronym:
TTU_PREDIA
Tool destination:
Tool description:
Tool platform:
Program. language:
Command:
prediag
Input:
Output:
Syntax:
design:
options:
-f
-n
-g
-v <extension>
-s <extension>
-o <extension>
-scr
12
TTU_TVECIN
Tool destination:
Tool description:
The Turbo Tester system has a special format the test vectors are kept
in. Automatic test pattern generation tools from Turbo Tester
package use this format to store generated tests in files. However, it
is inconvenient to manually compose from scratch these test vectors
files using this format. Therefore for manual test vector generation a
special user-friendly tool is needed to create the interface between the
user and the Turbo Tester. The proposed vector manager tool
includes also some simple test manipulation possibilities, like fault
simulation, logic simulation, random test vectors creation, etc. It can
work in an interactive as well as in a command line modes. In
interactive mode (usage: vecmanager) the program asks for the name
of the design, the name of the test pattern file, and finally gives the
following menu:
S. Show existing test patterns
N. Insert completely New test
A. Add vectors
D. Remove some vectors
R. Automatically generate some Random sequence
F. Perform Fault simulation
X. Save patterns and eXit
In the command line mode you can add only a single test vector.
Tool platform:
Program. language:
Command:
vecmanager
Input:
Output:
Syntax:
design:
options:
-new
-add <vector>
-i <extension>
-o <extension>
-ftable
13
Tool acronym:
TTU_ECRDCR
Tool destination:
The encryption part of the tool encrypts the information about the
design error, which includes the type of inserted error and its precise
location. The decryption part of the tool allows teacher to decrypt the
information about the design error and therefore to verify the
correctness of the diagnosis performed by the student.
Tool description:
Tool platform:
Program. language:
Command:
checkgate
Input:
encrypted name and type of the erroneous gate (can be read from file
<design>.rep).
Output:
Syntax:
InFile:
message:
options:
-o <file>
-s
14
Tool acronym:
TTU_COMLIB
Tool destination:
Tool description:
Tool platform:
Program. language:
15
16
Tool acronym:
TTU_VHDLDD
Tool destination:
Tool description:
Tool platform:
OS platforms: Solaris
Program. language:
Command:
vhdl2dd
Input:
Output:
Syntax:
or
source_file_name:
result_file_name:
17