Device-Circuit Co-Optimization for Mixed-mode Circuit Design via

Geometric Programming
Jintae Kim, Ritesh Jhaveri, Jason Woo, and Chih-Kong Ken Yang
Department of Electrical Engineering,University of Californica, Los Angeles, CA 90025
Email: jintae@ee.ucla.edu
Abstract
Modern processing technologies offer a number of types of
devices such as high-VT , low-VT , thick-oxide, etc. in addition
to the nominal transistor in order to meet system performance
and functional needs. While designers have leveraged these
devices for mixed-signal design, a design framework is needed
to guide designers in selecting the best set of devices. The
same framework can enable device manufacturers decide
which new devices to include in the suite of device offerings.
This paper presents a design methodology that can quickly
guide a designer in selecting the best set of devices for a
given application, specifications, and circuit structure. The
equation-based optimization framework based on geometric
programming (GP) extends upon previous efforts that optimize
sizing, biasing, and supply voltages. The paper first shows
that convex piecewise-linear function fitting can effectively
model for optimization all the types of devices offered by a
90nm CMOS technology. Additionally, we show the potential
to model and include experimental devices such as a Schottky
Tunneling Source MOSFET. Second, the paper applies the
model to an example circuit, a track-and-hold amplifier. The
optimization and subsequent simulation illustrate the importance and amount of benefit from applying device selection.

analog characteristics but are limited in other characteristics.

These devices can supplement the existing set to improve the
overall system performance [3].
The challenge in blending different devices in mixed-mode
circuit design is the increase in design complexity. In principle,
the increase in the number of available devices will result
in exponentially increasing possible combinations of devices
for given circuit topology. In addition, we must evaluate the
circuit performance of using different set of devices by cooptimizing circuit design variables in order to capture the true
performance improvements. Therefore, evaluating the potential benefit of device-blending would be prohibitive without
relying on an efficient optimization method.
This paper presents a design methodology that can quickly
guide a designer in selecting the best set of devices for a
given application, specifications, and circuit structure. Section
2 briefly reviews geometric programming (GP) based circuit
optimization. Section 3 presents the device modeling results
for 90nm CMOS and an experimental device called Schottky
Tunneling Source MOSFET (STSFET). Section 4 describes
and verifies GP description of track-and-hold amplifier design
with specific focus on settling error and output swing. Section
5 illustrates a design methodology that can guide a designer
to quickly explore the performance improvements of devicecircuit co-optimizations. Section 6 concludes the paper with a
brief summary.

1. Introduction

2. GP-based Circuit Optimization

Mixed-mode circuit design for nanometer-scaled devices is

increasingly difficult due to the poor analog characteristics
of the deeply-scaled core device. In particular, two of the
primary challenges are the output resistance degradation and
the reduction of voltage headroom due to supply scaling [1].
The circuit designers solutions have usually been novel circuit
techniques and low-supply friendly circuit topologies. However, many of these techniques result in a net increase in power
dissipation. For many applications, relaxing the headroom by
increasing supply voltage to increase the dynamic range can
often lead to better power-performance tradeoff. In some cases,
higher voltage devices are needed. Most advanced CMOS
technologies already offer a number of flavors of transistors
such as high-threshold or thick-oxide devices primarily to
help with digital design to control leakage and handle I/O
voltages. Incorporating these devices into mixed signal designs
[2] has led to higher performing designs. A second solution is
to introduce novel device structures that have some superior

1-4244-1382-6/07/$25.00 2007 IEEE

GP is an optimization problem that has the following format

minimize

f0 (x)

subject to

fi (x) 1,

i = 1, . . . , m

gi (x) = 1,

i = 1, . . . , p

xi > 0,

i = 1, . . . , n

(1)

where fi are posynomial functions and gi are monomial

functions. A posynomial function is defined as
f (x1 , . . . , xn ) =

K
X

1k 2k
nk
ck x
x
n ,
1 x2

xi > 0.

(2)

k=1

Posynomial functions, or posynomials, are real-valued functions of n real, positive variable xi with nonnegative coefficients ck 0 and any real exponents ij R. When the
posynomial has only a single term, it is known as a monomial,
i.e.,

470

n
1 2
g(x1 , . . . , xn ) = c1 x
1 x2 xn ,

xi > 0.

(3)

3. GP-compatible Device Modeling

Figure 1. Four flavors of devices in this work

Table 1. Variable sweep ranges for GP device modeling

CORE

HVT

I/O

STSFET

L [m]

[80n,5]

[80n,5]

[240n,5]

[50n,130n]

ID [A]

[1,0.7m]

[0.1,0.5m]

[0.04,0.6m]

[30,3m]

VDS [V]

[0.1,1]

[0.1,1]

[0.1,2.5]

[0.1,1.2]

Table 2. Mean/max % modeling errors in NMOS models

1/gm [%]
gDS [%]
VGS [%]
VDSAT [%]
CGS [%]

CORE
5.3/12.1
6.4/23.2
2.4/5.9
1.9/5.4
3.1/10.5

HVT
2.1/10.4
16.4/56.8
0.8/3.4
3.7/11.2
3.7/10.5

I/O
4.2/10.5
17.6/64
3.4/10.5
3.9/13.2
5.6/10.5

STSFET
7.5/16.1
35.6/88.5
1/5.5
21.5/47.8
21.6/39.5

GP can be transformed to convex optimization problem by

a change of variable and a transformation of objective and
constraint function [4].
GP-based circuit optimization has been one of the popular
choices in optimizing both digital and analog circuits [5].
Previous literatures have described wide areas of design problems as GPs, including CMOS OPAMP design [6], pipelined
ADC design [7], CMOS DC-DC buck converter design [8]
and phase-locked loop design [9].
Design constraints for GP-based circuit optimization can
be categorized into several hierarchies from the system level
constraints to the device model constraints. Device model
constraints, or GP-compatible device models, are essential
parts of the GP-based circuit optimization as they define
small signal and bias-related parameters of transistor in either
posynomial or monomial. Several methods therefore have
been proposed to create such GP-compatible device models
[10,11,12].

GP-compatible device models are created for the purpose

of this paper based on a convex piecewise-linear function
fitting [11]. First group of devices are chosen from production
90nm-CMOS technology. Shown in Fig. 1, both NMOS
and PMOS models for core (CORE), high-threshold (HVT),
and thick-oxide (I/O) devices are created as examples of
favors. In addition, this work considers another set of device
called Schottky Tunneling Source MOSFET (STSFET)[3]
as an example of device that specifically improves analog
performance such as output resistance.
The goal of GP-compatible device modeling is to create
either monomial or posynomial functions of small-signal
and bias-related parameters. Target parameters are inverse
of transconductance (1/gm ), output conductance (gds ), gateto-source voltage (VGS ), minimum drain-to-source voltage
for saturation (VDSAT ), gate-to-source capacitor (CGS ),
gate-to-drain capacitor (CGD ) and drain-to-junction (CJD )
capacitor. These parameters are defined as functions of device
variable such as total width (W ), channel length (L), bias
current (ID ), and drain-to-source voltage (VDS ).
Data points for function fitting are generated by simulations.
For devices from 90nm-CMOS process, circuit simulations
whose compact device model is BSIM4 are carried out
using Cadence SPECTRE. Data points for STSFET are
obtained directly from a device simulator, Synopsis DESSIS.
Simulation sweep ranges for single-finger (W = 1m)
devices are summarized in in Table 1. The resulting device
model for each target parameter is defined as a convex piecewise linear function, which is mathematically equivalent to
the posynomial function.
Table 2 summarizes mean/max % fitting error
(|(yGP M ODEL ySIM U L )/ySIM U L | 100) of several
target parameters for different devices. Modeling errors are
evaluated at the same data set used in the model generation.
The mean % errors for 90nm CMOS devices are mostly less
than 5% with the exception of gds model having slightly
larger errors (6 17%). The experimental result shows that
piecewise-linear convex function fitting method that was
originally proposed to create device models in 0.18 m
process can still be used in sub-100nm process. Table 2 also
shows that a reasonably good modeling accuracy is achieved
for new device such as STSFET whose compact model is not
available. This is very useful because it allows the designer
to explore design tradeoff of a circuit and system even before
the actual fabrication of an experimental device

4. Track-and-Hold Amplifier Optimization

As shown in Fig 2, a target sub-system to illustrate
our design framework is a track-and-hold amplifier. A GPdescription of a track-and-hold amplifier has previously been
reported [7]. In this section, we introduce key design variables
and constraints in a slightly different way and demonstrate its
validity and computational efficiency. Actual implementation
is based on telescopic OPAMP shown in Fig. 3 and complete

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Table 3. GP vs SPECTRE simulation

Spec.
minimize
=700f
0.6
0.391
180.3n2

Power [W]
CH , CLOAD [F]
VSW IN G,DIF F [V]
errAV [%]
[s]

GP
0.73m
700f
0.62
0.39
180.3n

Simul.
0.73m
700f
0.614
0.42
166.8n

4.2. Performance metric and design constraints

1) Settling error in hold phase: Settling error in the hold
phase arises from finite gain (errAV ) and time-constant ( ) of
OPAMP. They can be constrained as [13]
errAV =

Figure 2. Operations of track-and-hold amplifier

=

1
CIN
(
+ 1) ,
AV
CH

CL CIN + CL CH + CH CH
.
Gm CH

(4)

(5)

Actual and can be specified from the desired total

settling error for given sampling period T (= 1/fS ).
(4) and (5) are GP-compatible posynomial inequalities because inverse gain (1/AV ), input capacitance (CIN ), inverse
transconductance (1/Gm = 1/gm,M 2 ) of telescopic OPAMP,
and total load capacitance (CL ) are defined as posynomial
functions using the device models described in section 3.
2) Output Swing: Single-ended output swing (VSW IN G )
of track-and-hold amplifier is limited by required headroom
for transistors to remain in saturation region (VHEADROOM )
and supply voltage (VDD ), i.e.
VSW IN G + VHEADROOM VDD .

(6)

In case of telescopic OPAMP in Fig. 3, (6) can be transformed

to
Figure 3. Schematic of telescopic OPAMP

1
(VSW IN G
VDD
+VDSAT,M 3

design constraints for OPAMP that include biasing, phasemargin, slew-rate, and noise [6] will not be repeated here.

4.1. Design Variables

Design variables of track-and-hold amplifier design
can be defined into stage-level and circuit-level variables.
Stage-level variables are independent of specific OPAMP
architecture and we consider sampling capacitor (CH ), signal
swing (VSW IN G ), and supply voltage (VDD ) as design
variables. Circuit-level variables are architecture-dependent
and we consider length (L), width (W ), bias current (ID ),
and drain-to-source voltage (VDS ) of all transistors (M1 ,
M2 M5 ,M2B M5B ) as design variables.

VDS,M 1 + VDS,M 2

VDSAT,M 4 + VDS,M 5 ) < 1, (7)

which is a posynomial inequality given that VDSAT is defined

as a posynomial function and VDD and VDS are design
variables. We can either fix VSW IN G if it is given from the
specification or consider it as design variable as well.
3) Power: Total power consumption is simply given by
P = VDD ID,M 1

(8)

and is a monomial function. We use it as an optimization

object in the following numerical examples.

1 Equivalent
2 Equivalent

fS =400MHz

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to the 0.25 LSB of the settling error in 6-bit resolution

to the 0.25 LSB of the settling error in 6-bit resolution,

Figure 4. vs. fS from GP and simulation

Figure 6. Device-circuit co-optimization for 6-bit resolution

Figure 5. errAV vs. fS from GP and simulation

4.3. Numerical Examples and Verifications

In order to verify the validity of proposed GP-description,
we optimized the track-and-hold amplifier for minimum power
with specification equivalent to total settling error 0.78%
(0.5LSB of 6-bit resolution) and fS =400MHz. All transistors
are assumed as core devices. The optimization problem is
solved by a dedicated GP-solver and solving a problem takes
2.56 sec in our linux machine running on Xeon 2.8GHz CPU
with 2-GB memory. Table 3 compares GP-predicted optimization result with SPECTRE simulations based on obtained
optimal design variables. Bias and common-mode feedback
circuits are assumed as ideal. The comparison shows resonably
good agreements for both minimization object and design
constraints. For further verifications, Fig. 4 and Fig. 5 show the
comparison of settling error due finite OPAMP gain (errAV )
and time constant ( ) while sweeping sampling frequency
from 100MHz to 800MHz. Computation time to perform this
sweep optimizations is a 19.7 sec and simulated value of
errAV and exhibit good agreements with mean errors 7%,
indicating that GP-based optimization has a potential as an
efficient optimization engine with a reasonably good accuracy.

Figure 7. Device-circuit co-optimization for 8-bit resolution

5. Experimental Results and Discussions

In this section, we quantitatively compare the performance
improvement by simultaneously optimizing device and circuit.
Although circuit optimization deals with continuous variable,
device selection is an inherently discrete process. Therefore,
instead of finding a global optimum solution by solving a
single optimization problem, we perform a constrained but
exhaustive search to find the optimum solutions. The approach
leverages the efficiency of GP even for modest sized problems.
Possible device candidates are CORE, HVT, I/O and STSFET for NMOS (M1 ,M2 ,M3 in Fig. 3) and CORE, HVT,
I/O for PMOS (M4 ,M5 in Fig. 3), leading to 576 (=43
32 ) possible device combinations. The total run-time for the
optimization is about 25 minutes. In order to explore how
design specifications affect optimal selections of devices, we

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Table 4. Pmin for 4 device selections with 6-bit resolution

Pmin [W]
M1
M2
M3
M4
M5

CASE 1
0.73m
CORE
CORE
CORE
CORE
CORE

CASE 2
0.66m
CORE
CORE
I/O
CORE
HVT

CASE 3
0.89m
STSFET
STSFET
STSFET
CORE
CORE

CASE 4
0.53m
STSFET
CORE
STSFET
CORE
CORE

Table 5. Pmin for 4 device selections with 8-bit resolution

Pmin [W]
M1
M2
M3
M4
M5

CASE 1
Infeas.
CORE
CORE
CORE
CORE
CORE

CASE 2
1.38m
CORE
CORE
I/O
HVT
HVT

CASE 3
1.82m
STSFET
STSFET
STSFET
CORE
CORE

CASE 4
0.96m
STSFET
CORE
STSFET
HVT
HVT

Figure 8.
resolution

first optimize all device combinations of problem for two

sets of design specifications: total settling error 0.78% (6bit resolution) and 0.195% (8-bit resolution) while other
specifications are identical to those in Table 3. Fig 6 and 7
show histograms of feasible designs out of 576 optimizations,
respectively, along with the best-five device combinations in
the tables. Note that optimal device selection for 6-bit resolution (M1 =STSFET, M2 =CORE, M3 =STSFET, M4 =CORE,
M5 =CORE) and 8-bit resolution (M1 =STSFET, M2 =CORE,
M3 =STSFET, M4 =HVT, M5 =HVT) are slightly different, but
more importantly optimal selections are blended, i.e. mixed
device selections for each M1 M5 . Compared with the
case that does not consider device optimization (Table 3 vs.
Fig. 6), co-optimization brings 27% (0.528mW as opposed
to 0.73mW) smaller power consumption while satisfying the
same design specification. Another useful design implication
that can be drawn is that the best-five combinations choose
CORE for M2 and STSFET for M3 , indicating that choosing
right devices in signal path has more significant impact on
the performance and can be leveraged for larger problems to
reduce the search space and therefore run time.
To more quantitatively compare the benefit of adding
STSFET to the flavors of device in 90nm-CMOS, Table 4
highlights four possible scenarios of device selections and their
corresponding choice of devices along with obtained minimum
power in case of 6-bit resolution. Case 1 uses CORE devices
for all transistors as an example of circuit-only optimization.
Case 2 is a device-circuit co-optimization without STSFET.
Case 3 is when STSFET is used for all NMOS. Case 4
is a device-circuit optimization using all possible devices,
which is the absolute best case. We first note that although
Pcase4 is smaller than Pcase1 and Pcase2 , Pcase3 is higher than
Pcase1 , indicating that using new device such as STSFET does
not necessarily result in smaller power consumption without

Optimal power vs. fS of T/H amplifier for 6-bit

proper device selections. When compared between optimal

selections with and without STSFET, Pcase4 = 0.8 Pcase2
and therefore it can be said that STSFET with optimal device
selection brings 20% power reduction.
We also compare the case for 8-bit resolution as shown
in Table 5. Note that case 3 is feasible while case 1 is not,
implying that using STSFET is particularly more advantageous
when total settling error specification is more stringent. In
addition, Pcase4 is roughly 30% smaller than Pcase2 , therefore
the amount of power reduction by using STSFET increases at
higher resolution.
The sampling speed constraints can also be swept in the
framework to see how increasing fS affects the power consumptions with and without STSFET. Fig 8 and 9 illustrate8
power versus fS for 6-bit and 8-bit resolution, respectively.
Although Pcase4 is universally smaller for all sampling speed,
the amount of power reduction increases with sampling speed
and bit resolution as well. In the extreme case of 8-bit and
fS = 800M Hz, Pcase4 = 0.48(= 2.4/5) Pcase2 and we
can expect that adding STSFET to the flavor of 90nm CMOS
devices could achieve about 50% power reduction.
One interesting question we may be able to answer from
this result is how reliable it is to estimate circuit performance
based on device metrics. For digital circuits, metrics such as
fT or FO4(fanout-of-4) gate delay can reasonably predict the
digital performance of a technology. For analog applications,
metrics such as fT , gm ro , gm /ID , etc. are often list8ed. In
our example, the fT of the STSFET(with VDS = 0.4, and
gm ro = 15 20) is roughly 3 5 larger than the best
90nm CMOS device. The data implies a substantial systemlevel improvement by using STSFET. However, comparison

between Pcase4 and Pcase2

in Fig. 9 reveals that the net speed
improvement for the same power consumption by introducing
STSFET is at best about 800MHz/550MHz=1.45. Therefore,
a simple performance estimation can be misleading in predicting the performance of mixed-mode circuit.

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[10] P. Veselinovic et al., A method for automatic generation of

piecewise linear models, in Proc. of IEEE Intl Symp. on
Circuits and System (ISCAS), 1996, pp. 2427.
[11] J. Kim, et al., Techniques for Improving the Accuracy of
Geometric-Programming Based Analog Circuit Design Optimization, in Proc. ICCAD, pp. 994-998, Nov. 2004.
[12] A. Magnani, and S. Boyd, Convex piecewise-linear fitting,
submitted for publication by authour, 2006.
[13] B. Razavi, Design of Analog CMOS Integrated Circuits.
McGraw-Hill, 2001.

Figure 9.
resolution

Optimal power vs. fS of T/H amplifier for 8-bit

6. Conclusion
This paper shows that GP-based circuit optimization method
can be a useful framework to explore performance improvement of device-circuit co-optimization. We demonstrated the
framework to evaluate the benefit of mixing different type of
devices by co-optimizing device and circuit using a track-andhold amplifier. The efficiency of GP optimization is shown
to be critical in searching through the design space. The
experimental result indicates that the amount of performance
improvement by adding new device is pronounced when
design specification is stringent and identifying a signal path
can be leveraged to reduce the large search space.

7. References
[1] A.-J. Annema, et al., Analog Circuits in Ultra-Deep-Submicron
CMOS, IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 132143, Jan. 2005.
[2] J. Li, et al., A 10b 170MS/s CMOS Pipelined ADC Featuring
84dB SFDR without Calibration, in VLSI Tech. Dig. Papers,
pp. 226-227, Jun. 2006.
[3] R. Jhaveri and J. Woo, Schottky Tunneling Source MOSFET
Design for Mixed Mode and Analog Applications, in Proc. of
ESSDERC, pp. 295-298, Sep. 2006.
[4] S. Boyd and L. Vendenberghe, Convex Optimization. Cambridge University Press, 2003.
[5] S. Boyd, et al., Circuit Optimization via Geometric Programming, Operations Research, vol. 53, no. 6, pp. 899-932, Nov.Dec. 2005.
[6] M. Hershenson et al., Optimal design of a CMOS opamp via
geometric programming, IEEE Trans. Computer-Aided Design,
vol. 20, no. 1, pp. 121, Jan. 2001.
[7] , Design of pipeline analog-to-digital converters via geometric programming, in Proc. of ICCAD, San Jose, CA, Nov.
2002, pp. 317324.
[8] J. Lee et al., Evaluation of fully-integrated switching regulator
for CMOS process technologies, in Proc. of International
Symposium on SOC 2003, Tampere, Finland, pp. 155158, Nov.
2003.
[9] D. Colleran et al., Optimization of phase-locked loop via
geometric programming, in Proc. of CICC, pp. 377380, Sep.
2003. Jan. 2001.

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